radeon_object.c revision 1.1 
1/*	$OpenBSD: radeon_object.c,v 1.1 2013/08/12 04:11:53 jsg Exp $	*/
2/*
3 * Copyright 2009 Jerome Glisse.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 *
26 */
27/*
28 * Authors:
29 *    Jerome Glisse <glisse@freedesktop.org>
30 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
31 *    Dave Airlie
32 */
33#include <dev/pci/drm/drmP.h>
34#include <dev/pci/drm/radeon_drm.h>
35#include "radeon.h"
36#ifdef notyet
37#include "radeon_trace.h"
38#endif
39
40
41int	 radeon_ttm_init(struct radeon_device *);
42void	 radeon_ttm_fini(struct radeon_device *);
43void	 radeon_bo_clear_surface_reg(struct radeon_bo *);
44void	 radeon_bo_clear_va(struct radeon_bo *);
45
46/*
47 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
48 * function are calling it.
49 */
50
51void radeon_bo_clear_va(struct radeon_bo *bo)
52{
53	struct radeon_bo_va *bo_va, *tmp;
54
55	list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
56		/* remove from all vm address space */
57		radeon_vm_bo_rmv(bo->rdev, bo_va);
58	}
59}
60
61static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
62{
63	struct radeon_bo *bo;
64
65	bo = container_of(tbo, struct radeon_bo, tbo);
66	rw_enter_write(&bo->rdev->gem.rwlock);
67	list_del_init(&bo->list);
68	rw_exit_write(&bo->rdev->gem.rwlock);
69	radeon_bo_clear_surface_reg(bo);
70	radeon_bo_clear_va(bo);
71	drm_gem_object_release(&bo->gem_base);
72	pool_put(&bo->rdev->ddev->objpl, bo);
73}
74
75bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
76{
77	if (bo->destroy == &radeon_ttm_bo_destroy)
78		return true;
79	return false;
80}
81
82void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
83{
84	u32 c = 0;
85
86	rbo->placement.fpfn = 0;
87	rbo->placement.lpfn = 0;
88	rbo->placement.placement = rbo->placements;
89	rbo->placement.busy_placement = rbo->placements;
90	if (domain & RADEON_GEM_DOMAIN_VRAM)
91		rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
92					TTM_PL_FLAG_VRAM;
93	if (domain & RADEON_GEM_DOMAIN_GTT) {
94		if (rbo->rdev->flags & RADEON_IS_AGP) {
95			rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
96		} else {
97			rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
98		}
99	}
100	if (domain & RADEON_GEM_DOMAIN_CPU) {
101		if (rbo->rdev->flags & RADEON_IS_AGP) {
102			rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
103		} else {
104			rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
105		}
106	}
107	if (!c)
108		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
109	rbo->placement.num_placement = c;
110	rbo->placement.num_busy_placement = c;
111}
112
113int radeon_bo_create(struct radeon_device *rdev,
114		     unsigned long size, int byte_align, bool kernel, u32 domain,
115		     struct sg_table *sg, struct radeon_bo **bo_ptr)
116{
117	struct radeon_bo *bo;
118	enum ttm_bo_type type;
119	unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
120	size_t acc_size;
121	int r;
122
123	size = PAGE_ALIGN(size);
124
125#ifdef notyet
126	rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
127#endif
128	if (kernel) {
129		type = ttm_bo_type_kernel;
130	} else if (sg) {
131		type = ttm_bo_type_sg;
132	} else {
133		type = ttm_bo_type_device;
134	}
135	*bo_ptr = NULL;
136
137	acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
138				       sizeof(struct radeon_bo));
139
140	bo = pool_get(&rdev->ddev->objpl, PR_WAITOK | PR_ZERO);
141	if (bo == NULL)
142		return -ENOMEM;
143	r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
144	if (unlikely(r)) {
145		pool_put(&rdev->ddev->objpl, bo);
146		return r;
147	}
148	bo->rdev = rdev;
149	bo->surface_reg = -1;
150	INIT_LIST_HEAD(&bo->list);
151	INIT_LIST_HEAD(&bo->va);
152	radeon_ttm_placement_from_domain(bo, domain);
153	/* Kernel allocation are uninterruptible */
154	rw_enter_read(&rdev->pm.mclk_lock);
155	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
156			&bo->placement, page_align, !kernel, NULL,
157			acc_size, sg, &radeon_ttm_bo_destroy);
158	rw_exit_read(&rdev->pm.mclk_lock);
159	if (unlikely(r != 0)) {
160		return r;
161	}
162	*bo_ptr = bo;
163
164#ifdef notyet
165	trace_radeon_bo_create(bo);
166#endif
167
168	return 0;
169}
170
171int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
172{
173	bool is_iomem;
174	int r;
175
176	if (bo->kptr) {
177		if (ptr) {
178			*ptr = bo->kptr;
179		}
180		return 0;
181	}
182	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
183	if (r) {
184		return r;
185	}
186	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
187	if (ptr) {
188		*ptr = bo->kptr;
189	}
190	radeon_bo_check_tiling(bo, 0, 0);
191	return 0;
192}
193
194void radeon_bo_kunmap(struct radeon_bo *bo)
195{
196	if (bo->kptr == NULL)
197		return;
198	bo->kptr = NULL;
199	radeon_bo_check_tiling(bo, 0, 0);
200	ttm_bo_kunmap(&bo->kmap);
201}
202
203void radeon_bo_unref(struct radeon_bo **bo)
204{
205	struct ttm_buffer_object *tbo;
206	struct radeon_device *rdev;
207
208	if ((*bo) == NULL)
209		return;
210	rdev = (*bo)->rdev;
211	tbo = &((*bo)->tbo);
212	rw_enter_read(&rdev->pm.mclk_lock);
213	ttm_bo_unref(&tbo);
214	rw_exit_read(&rdev->pm.mclk_lock);
215	if (tbo == NULL)
216		*bo = NULL;
217}
218
219int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
220			     u64 *gpu_addr)
221{
222	int r, i;
223
224	if (bo->pin_count) {
225		bo->pin_count++;
226		if (gpu_addr)
227			*gpu_addr = radeon_bo_gpu_offset(bo);
228
229		if (max_offset != 0) {
230			u64 domain_start;
231
232			if (domain == RADEON_GEM_DOMAIN_VRAM)
233				domain_start = bo->rdev->mc.vram_start;
234			else
235				domain_start = bo->rdev->mc.gtt_start;
236#ifdef notyet
237			WARN_ON_ONCE(max_offset <
238				     (radeon_bo_gpu_offset(bo) - domain_start));
239#endif
240		}
241
242		return 0;
243	}
244	radeon_ttm_placement_from_domain(bo, domain);
245	if (domain == RADEON_GEM_DOMAIN_VRAM) {
246		/* force to pin into visible video ram */
247		bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
248	}
249	if (max_offset) {
250		u64 lpfn = max_offset >> PAGE_SHIFT;
251
252		if (!bo->placement.lpfn)
253			bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
254
255		if (lpfn < bo->placement.lpfn)
256			bo->placement.lpfn = lpfn;
257	}
258	for (i = 0; i < bo->placement.num_placement; i++)
259		bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
260	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
261	if (likely(r == 0)) {
262		bo->pin_count = 1;
263		if (gpu_addr != NULL)
264			*gpu_addr = radeon_bo_gpu_offset(bo);
265	}
266	if (unlikely(r != 0))
267		DRM_ERROR("%p pin failed\n", bo);
268	return r;
269}
270
271int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
272{
273	return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
274}
275
276int radeon_bo_unpin(struct radeon_bo *bo)
277{
278	int r, i;
279
280	if (!bo->pin_count) {
281		DRM_ERROR("%p unpin not necessary\n", bo);
282		return 0;
283	}
284	bo->pin_count--;
285	if (bo->pin_count)
286		return 0;
287	for (i = 0; i < bo->placement.num_placement; i++)
288		bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
289	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
290	if (unlikely(r != 0))
291		DRM_ERROR("%p validate failed for unpin\n", bo);
292	return r;
293}
294
295int radeon_bo_evict_vram(struct radeon_device *rdev)
296{
297	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
298	if (0 && (rdev->flags & RADEON_IS_IGP)) {
299		if (rdev->mc.igp_sideport_enabled == false)
300			/* Useless to evict on IGP chips */
301			return 0;
302	}
303	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
304}
305
306void radeon_bo_force_delete(struct radeon_device *rdev)
307{
308	struct drm_device *dev = rdev->ddev;
309	struct radeon_bo *bo, *n;
310
311	if (list_empty(&rdev->gem.objects)) {
312		return;
313	}
314	DRM_ERROR("Userspace still has active objects !\n");
315	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
316		DRM_LOCK();
317#ifdef notyet
318		DRM_ERROR("%p %p %lu %lu force free\n",
319			&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
320			*((unsigned long *)&bo->gem_base.refcount));
321#endif
322		rw_enter_write(&bo->rdev->gem.rwlock);
323		list_del_init(&bo->list);
324		rw_exit_write(&bo->rdev->gem.rwlock);
325		/* this should unref the ttm bo */
326		drm_gem_object_unreference(&bo->gem_base);
327		DRM_UNLOCK();
328	}
329}
330
331int radeon_bo_init(struct radeon_device *rdev)
332{
333	struct drm_local_map	*map;
334	paddr_t start, end;
335
336	/* Add an MTRR for the VRAM */
337	drm_addmap(rdev->ddev, rdev->mc.aper_base, rdev->mc.aper_size,
338	    _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, &map);
339	/* fake a 'cookie', seems to be unused? */
340	rdev->mc.vram_mtrr = 1;
341
342	start = atop(bus_space_mmap(rdev->memt, rdev->mc.aper_base, 0, 0, 0));
343	end = start + atop(rdev->mc.aper_size);
344	uvm_page_physload(start, end, start, end, PHYSLOAD_DEVICE);
345
346#ifdef DRMDEBUG
347	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
348		rdev->mc.mc_vram_size >> 20,
349		(unsigned long long)rdev->mc.aper_size >> 20);
350	DRM_INFO("RAM width %dbits %cDR\n",
351			rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
352#endif
353	return radeon_ttm_init(rdev);
354}
355
356void radeon_bo_fini(struct radeon_device *rdev)
357{
358	radeon_ttm_fini(rdev);
359}
360
361void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
362				struct list_head *head)
363{
364	if (lobj->wdomain) {
365		list_add(&lobj->tv.head, head);
366	} else {
367		list_add_tail(&lobj->tv.head, head);
368	}
369}
370
371int radeon_bo_list_validate(struct list_head *head)
372{
373	struct radeon_bo_list *lobj;
374	struct radeon_bo *bo;
375	u32 domain;
376	int r;
377
378	r = ttm_eu_reserve_buffers(head);
379	if (unlikely(r != 0)) {
380		return r;
381	}
382	list_for_each_entry(lobj, head, tv.head) {
383		bo = lobj->bo;
384		if (!bo->pin_count) {
385			domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
386
387		retry:
388			radeon_ttm_placement_from_domain(bo, domain);
389			r = ttm_bo_validate(&bo->tbo, &bo->placement,
390						true, false);
391			if (unlikely(r)) {
392				if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
393					domain |= RADEON_GEM_DOMAIN_GTT;
394					goto retry;
395				}
396				return r;
397			}
398		}
399		lobj->gpu_offset = radeon_bo_gpu_offset(bo);
400		lobj->tiling_flags = bo->tiling_flags;
401	}
402	return 0;
403}
404
405#ifdef notyet
406int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
407			     struct vm_area_struct *vma)
408{
409	return ttm_fbdev_mmap(vma, &bo->tbo);
410}
411#endif
412
413int radeon_bo_get_surface_reg(struct radeon_bo *bo)
414{
415	struct radeon_device *rdev = bo->rdev;
416	struct radeon_surface_reg *reg;
417	struct radeon_bo *old_object;
418	int steal;
419	int i;
420
421	BUG_ON(!radeon_bo_is_reserved(bo));
422
423	if (!bo->tiling_flags)
424		return 0;
425
426	if (bo->surface_reg >= 0) {
427		reg = &rdev->surface_regs[bo->surface_reg];
428		i = bo->surface_reg;
429		goto out;
430	}
431
432	steal = -1;
433	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
434
435		reg = &rdev->surface_regs[i];
436		if (!reg->bo)
437			break;
438
439		old_object = reg->bo;
440		if (old_object->pin_count == 0)
441			steal = i;
442	}
443
444	/* if we are all out */
445	if (i == RADEON_GEM_MAX_SURFACES) {
446		if (steal == -1)
447			return -ENOMEM;
448		/* find someone with a surface reg and nuke their BO */
449		reg = &rdev->surface_regs[steal];
450		old_object = reg->bo;
451		/* blow away the mapping */
452		DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
453		ttm_bo_unmap_virtual(&old_object->tbo);
454		old_object->surface_reg = -1;
455		i = steal;
456	}
457
458	bo->surface_reg = i;
459	reg->bo = bo;
460
461out:
462	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
463			       bo->tbo.mem.start << PAGE_SHIFT,
464			       bo->tbo.num_pages << PAGE_SHIFT);
465	return 0;
466}
467
468void
469radeon_bo_clear_surface_reg(struct radeon_bo *bo)
470{
471	struct radeon_device *rdev = bo->rdev;
472	struct radeon_surface_reg *reg;
473
474	if (bo->surface_reg == -1)
475		return;
476
477	reg = &rdev->surface_regs[bo->surface_reg];
478	radeon_clear_surface_reg(rdev, bo->surface_reg);
479
480	reg->bo = NULL;
481	bo->surface_reg = -1;
482}
483
484int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
485				uint32_t tiling_flags, uint32_t pitch)
486{
487	struct radeon_device *rdev = bo->rdev;
488	int r;
489
490	if (rdev->family >= CHIP_CEDAR) {
491		unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
492
493		bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
494		bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
495		mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
496		tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
497		stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
498		switch (bankw) {
499		case 0:
500		case 1:
501		case 2:
502		case 4:
503		case 8:
504			break;
505		default:
506			return -EINVAL;
507		}
508		switch (bankh) {
509		case 0:
510		case 1:
511		case 2:
512		case 4:
513		case 8:
514			break;
515		default:
516			return -EINVAL;
517		}
518		switch (mtaspect) {
519		case 0:
520		case 1:
521		case 2:
522		case 4:
523		case 8:
524			break;
525		default:
526			return -EINVAL;
527		}
528		if (tilesplit > 6) {
529			return -EINVAL;
530		}
531		if (stilesplit > 6) {
532			return -EINVAL;
533		}
534	}
535	r = radeon_bo_reserve(bo, false);
536	if (unlikely(r != 0))
537		return r;
538	bo->tiling_flags = tiling_flags;
539	bo->pitch = pitch;
540	radeon_bo_unreserve(bo);
541	return 0;
542}
543
544void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
545				uint32_t *tiling_flags,
546				uint32_t *pitch)
547{
548	BUG_ON(!radeon_bo_is_reserved(bo));
549	if (tiling_flags)
550		*tiling_flags = bo->tiling_flags;
551	if (pitch)
552		*pitch = bo->pitch;
553}
554
555int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
556				bool force_drop)
557{
558	BUG_ON(!radeon_bo_is_reserved(bo) && !force_drop);
559
560	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
561		return 0;
562
563	if (force_drop) {
564		radeon_bo_clear_surface_reg(bo);
565		return 0;
566	}
567
568	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
569		if (!has_moved)
570			return 0;
571
572		if (bo->surface_reg >= 0)
573			radeon_bo_clear_surface_reg(bo);
574		return 0;
575	}
576
577	if ((bo->surface_reg >= 0) && !has_moved)
578		return 0;
579
580	return radeon_bo_get_surface_reg(bo);
581}
582
583void radeon_bo_move_notify(struct ttm_buffer_object *bo,
584			   struct ttm_mem_reg *mem)
585{
586	struct radeon_bo *rbo;
587	if (!radeon_ttm_bo_is_radeon_bo(bo))
588		return;
589	rbo = container_of(bo, struct radeon_bo, tbo);
590	radeon_bo_check_tiling(rbo, 0, 1);
591	radeon_vm_bo_invalidate(rbo->rdev, rbo);
592}
593
594int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
595{
596	struct radeon_device *rdev;
597	struct radeon_bo *rbo;
598	unsigned long offset, size;
599	int r;
600
601	if (!radeon_ttm_bo_is_radeon_bo(bo))
602		return 0;
603	rbo = container_of(bo, struct radeon_bo, tbo);
604	radeon_bo_check_tiling(rbo, 0, 0);
605	rdev = rbo->rdev;
606	if (bo->mem.mem_type == TTM_PL_VRAM) {
607		size = bo->mem.num_pages << PAGE_SHIFT;
608		offset = bo->mem.start << PAGE_SHIFT;
609		if ((offset + size) > rdev->mc.visible_vram_size) {
610			/* hurrah the memory is not visible ! */
611			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
612			rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
613			r = ttm_bo_validate(bo, &rbo->placement, false, false);
614			if (unlikely(r != 0))
615				return r;
616			offset = bo->mem.start << PAGE_SHIFT;
617			/* this should not happen */
618			if ((offset + size) > rdev->mc.visible_vram_size)
619				return -EINVAL;
620		}
621	}
622	return 0;
623}
624
625int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
626{
627	int r;
628
629	r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
630	if (unlikely(r != 0))
631		return r;
632	mtx_enter(&bo->tbo.bdev->fence_lock);
633	if (mem_type)
634		*mem_type = bo->tbo.mem.mem_type;
635	if (bo->tbo.sync_obj)
636		r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
637	mtx_leave(&bo->tbo.bdev->fence_lock);
638	ttm_bo_unreserve(&bo->tbo);
639	return r;
640}
641
642
643/**
644 * radeon_bo_reserve - reserve bo
645 * @bo:		bo structure
646 * @no_intr:	don't return -ERESTARTSYS on pending signal
647 *
648 * Returns:
649 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
650 * a signal. Release all buffer reservations and return to user-space.
651 */
652int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
653{
654	int r;
655
656	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
657	if (unlikely(r != 0)) {
658		if (r != -ERESTARTSYS)
659			DRM_ERROR("%p reserve failed\n", bo);
660		return r;
661	}
662	return 0;
663}
664