1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <linux/console.h> 30#include <linux/efi.h> 31#include <linux/pci.h> 32#include <linux/pm_runtime.h> 33#include <linux/slab.h> 34#include <linux/vga_switcheroo.h> 35#include <linux/vgaarb.h> 36 37#include <drm/drm_cache.h> 38#include <drm/drm_crtc_helper.h> 39#include <drm/drm_device.h> 40#include <drm/drm_file.h> 41#include <drm/drm_framebuffer.h> 42#include <drm/drm_probe_helper.h> 43#include <drm/radeon_drm.h> 44 45#include "radeon_device.h" 46#include "radeon_reg.h" 47#include "radeon.h" 48#include "atom.h" 49 50static const char radeon_family_name[][16] = { 51 "R100", 52 "RV100", 53 "RS100", 54 "RV200", 55 "RS200", 56 "R200", 57 "RV250", 58 "RS300", 59 "RV280", 60 "R300", 61 "R350", 62 "RV350", 63 "RV380", 64 "R420", 65 "R423", 66 "RV410", 67 "RS400", 68 "RS480", 69 "RS600", 70 "RS690", 71 "RS740", 72 "RV515", 73 "R520", 74 "RV530", 75 "RV560", 76 "RV570", 77 "R580", 78 "R600", 79 "RV610", 80 "RV630", 81 "RV670", 82 "RV620", 83 "RV635", 84 "RS780", 85 "RS880", 86 "RV770", 87 "RV730", 88 "RV710", 89 "RV740", 90 "CEDAR", 91 "REDWOOD", 92 "JUNIPER", 93 "CYPRESS", 94 "HEMLOCK", 95 "PALM", 96 "SUMO", 97 "SUMO2", 98 "BARTS", 99 "TURKS", 100 "CAICOS", 101 "CAYMAN", 102 "ARUBA", 103 "TAHITI", 104 "PITCAIRN", 105 "VERDE", 106 "OLAND", 107 "HAINAN", 108 "BONAIRE", 109 "KAVERI", 110 "KABINI", 111 "HAWAII", 112 "MULLINS", 113 "LAST", 114}; 115 116#if defined(CONFIG_VGA_SWITCHEROO) 117bool radeon_has_atpx_dgpu_power_cntl(void); 118bool radeon_is_atpx_hybrid(void); 119#else 120static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 121static inline bool radeon_is_atpx_hybrid(void) { return false; } 122#endif 123 124#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) 125 126struct radeon_px_quirk { 127 u32 chip_vendor; 128 u32 chip_device; 129 u32 subsys_vendor; 130 u32 subsys_device; 131 u32 px_quirk_flags; 132}; 133 134static struct radeon_px_quirk radeon_px_quirk_list[] = { 135 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) 136 * https://bugzilla.kernel.org/show_bug.cgi?id=74551 137 */ 138 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, 139 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU 140 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 141 */ 142 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, 143 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 144 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 145 */ 146 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 147 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 148 * https://bugs.freedesktop.org/show_bug.cgi?id=101491 149 */ 150 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 151 /* Asus K73TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 152 * https://bugzilla.kernel.org/show_bug.cgi?id=51381#c52 153 */ 154 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2123, RADEON_PX_QUIRK_DISABLE_PX }, 155 { 0, 0, 0, 0, 0 }, 156}; 157 158bool radeon_is_px(struct drm_device *dev) 159{ 160 struct radeon_device *rdev = dev->dev_private; 161 162 if (rdev->flags & RADEON_IS_PX) 163 return true; 164 return false; 165} 166 167static void radeon_device_handle_px_quirks(struct radeon_device *rdev) 168{ 169 struct radeon_px_quirk *p = radeon_px_quirk_list; 170 171 /* Apply PX quirks */ 172 while (p && p->chip_device != 0) { 173 if (rdev->pdev->vendor == p->chip_vendor && 174 rdev->pdev->device == p->chip_device && 175 rdev->pdev->subsystem_vendor == p->subsys_vendor && 176 rdev->pdev->subsystem_device == p->subsys_device) { 177 rdev->px_quirk_flags = p->px_quirk_flags; 178 break; 179 } 180 ++p; 181 } 182 183 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) 184 rdev->flags &= ~RADEON_IS_PX; 185 186 /* disable PX is the system doesn't support dGPU power control or hybrid gfx */ 187 if (!radeon_is_atpx_hybrid() && 188 !radeon_has_atpx_dgpu_power_cntl()) 189 rdev->flags &= ~RADEON_IS_PX; 190} 191 192/** 193 * radeon_program_register_sequence - program an array of registers. 194 * 195 * @rdev: radeon_device pointer 196 * @registers: pointer to the register array 197 * @array_size: size of the register array 198 * 199 * Programs an array or registers with and and or masks. 200 * This is a helper for setting golden registers. 201 */ 202void radeon_program_register_sequence(struct radeon_device *rdev, 203 const u32 *registers, 204 const u32 array_size) 205{ 206 u32 tmp, reg, and_mask, or_mask; 207 int i; 208 209 if (array_size % 3) 210 return; 211 212 for (i = 0; i < array_size; i +=3) { 213 reg = registers[i + 0]; 214 and_mask = registers[i + 1]; 215 or_mask = registers[i + 2]; 216 217 if (and_mask == 0xffffffff) { 218 tmp = or_mask; 219 } else { 220 tmp = RREG32(reg); 221 tmp &= ~and_mask; 222 tmp |= or_mask; 223 } 224 WREG32(reg, tmp); 225 } 226} 227 228void radeon_pci_config_reset(struct radeon_device *rdev) 229{ 230 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); 231} 232 233/** 234 * radeon_surface_init - Clear GPU surface registers. 235 * 236 * @rdev: radeon_device pointer 237 * 238 * Clear GPU surface registers (r1xx-r5xx). 239 */ 240void radeon_surface_init(struct radeon_device *rdev) 241{ 242 /* FIXME: check this out */ 243 if (rdev->family < CHIP_R600) { 244 int i; 245 246 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 247 if (rdev->surface_regs[i].bo) 248 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 249 else 250 radeon_clear_surface_reg(rdev, i); 251 } 252 /* enable surfaces */ 253 WREG32(RADEON_SURFACE_CNTL, 0); 254 } 255} 256 257/* 258 * GPU scratch registers helpers function. 259 */ 260/** 261 * radeon_scratch_init - Init scratch register driver information. 262 * 263 * @rdev: radeon_device pointer 264 * 265 * Init CP scratch register driver information (r1xx-r5xx) 266 */ 267void radeon_scratch_init(struct radeon_device *rdev) 268{ 269 int i; 270 271 /* FIXME: check this out */ 272 if (rdev->family < CHIP_R300) { 273 rdev->scratch.num_reg = 5; 274 } else { 275 rdev->scratch.num_reg = 7; 276 } 277 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 278 for (i = 0; i < rdev->scratch.num_reg; i++) { 279 rdev->scratch.free[i] = true; 280 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 281 } 282} 283 284/** 285 * radeon_scratch_get - Allocate a scratch register 286 * 287 * @rdev: radeon_device pointer 288 * @reg: scratch register mmio offset 289 * 290 * Allocate a CP scratch register for use by the driver (all asics). 291 * Returns 0 on success or -EINVAL on failure. 292 */ 293int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 294{ 295 int i; 296 297 for (i = 0; i < rdev->scratch.num_reg; i++) { 298 if (rdev->scratch.free[i]) { 299 rdev->scratch.free[i] = false; 300 *reg = rdev->scratch.reg[i]; 301 return 0; 302 } 303 } 304 return -EINVAL; 305} 306 307/** 308 * radeon_scratch_free - Free a scratch register 309 * 310 * @rdev: radeon_device pointer 311 * @reg: scratch register mmio offset 312 * 313 * Free a CP scratch register allocated for use by the driver (all asics) 314 */ 315void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 316{ 317 int i; 318 319 for (i = 0; i < rdev->scratch.num_reg; i++) { 320 if (rdev->scratch.reg[i] == reg) { 321 rdev->scratch.free[i] = true; 322 return; 323 } 324 } 325} 326 327/* 328 * GPU doorbell aperture helpers function. 329 */ 330/** 331 * radeon_doorbell_init - Init doorbell driver information. 332 * 333 * @rdev: radeon_device pointer 334 * 335 * Init doorbell driver information (CIK) 336 * Returns 0 on success, error on failure. 337 */ 338static int radeon_doorbell_init(struct radeon_device *rdev) 339{ 340 /* doorbell bar mapping */ 341#ifdef __linux__ 342 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); 343 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); 344#endif 345 346 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); 347 if (rdev->doorbell.num_doorbells == 0) 348 return -EINVAL; 349 350#ifdef __linux__ 351 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); 352 if (rdev->doorbell.ptr == NULL) { 353 return -ENOMEM; 354 } 355#endif 356 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); 357 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); 358 359 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); 360 361 return 0; 362} 363 364/** 365 * radeon_doorbell_fini - Tear down doorbell driver information. 366 * 367 * @rdev: radeon_device pointer 368 * 369 * Tear down doorbell driver information (CIK) 370 */ 371static void radeon_doorbell_fini(struct radeon_device *rdev) 372{ 373#ifdef __linux__ 374 iounmap(rdev->doorbell.ptr); 375#else 376 if (rdev->doorbell.size > 0) 377 bus_space_unmap(rdev->memt, rdev->doorbell.bsh, 378 rdev->doorbell.size); 379 rdev->doorbell.size = 0; 380#endif 381 rdev->doorbell.ptr = NULL; 382} 383 384/** 385 * radeon_doorbell_get - Allocate a doorbell entry 386 * 387 * @rdev: radeon_device pointer 388 * @doorbell: doorbell index 389 * 390 * Allocate a doorbell for use by the driver (all asics). 391 * Returns 0 on success or -EINVAL on failure. 392 */ 393int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) 394{ 395 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); 396 if (offset < rdev->doorbell.num_doorbells) { 397 __set_bit(offset, rdev->doorbell.used); 398 *doorbell = offset; 399 return 0; 400 } else { 401 return -EINVAL; 402 } 403} 404 405/** 406 * radeon_doorbell_free - Free a doorbell entry 407 * 408 * @rdev: radeon_device pointer 409 * @doorbell: doorbell index 410 * 411 * Free a doorbell allocated for use by the driver (all asics) 412 */ 413void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) 414{ 415 if (doorbell < rdev->doorbell.num_doorbells) 416 __clear_bit(doorbell, rdev->doorbell.used); 417} 418 419/* 420 * radeon_wb_*() 421 * Writeback is the method by which the GPU updates special pages 422 * in memory with the status of certain GPU events (fences, ring pointers, 423 * etc.). 424 */ 425 426/** 427 * radeon_wb_disable - Disable Writeback 428 * 429 * @rdev: radeon_device pointer 430 * 431 * Disables Writeback (all asics). Used for suspend. 432 */ 433void radeon_wb_disable(struct radeon_device *rdev) 434{ 435 rdev->wb.enabled = false; 436} 437 438/** 439 * radeon_wb_fini - Disable Writeback and free memory 440 * 441 * @rdev: radeon_device pointer 442 * 443 * Disables Writeback and frees the Writeback memory (all asics). 444 * Used at driver shutdown. 445 */ 446void radeon_wb_fini(struct radeon_device *rdev) 447{ 448 radeon_wb_disable(rdev); 449 if (rdev->wb.wb_obj) { 450 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { 451 radeon_bo_kunmap(rdev->wb.wb_obj); 452 radeon_bo_unpin(rdev->wb.wb_obj); 453 radeon_bo_unreserve(rdev->wb.wb_obj); 454 } 455 radeon_bo_unref(&rdev->wb.wb_obj); 456 rdev->wb.wb = NULL; 457 rdev->wb.wb_obj = NULL; 458 } 459} 460 461/** 462 * radeon_wb_init- Init Writeback driver info and allocate memory 463 * 464 * @rdev: radeon_device pointer 465 * 466 * Disables Writeback and frees the Writeback memory (all asics). 467 * Used at driver startup. 468 * Returns 0 on success or an -error on failure. 469 */ 470int radeon_wb_init(struct radeon_device *rdev) 471{ 472 int r; 473 474 if (rdev->wb.wb_obj == NULL) { 475 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 476 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL, 477 &rdev->wb.wb_obj); 478 if (r) { 479 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 480 return r; 481 } 482 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 483 if (unlikely(r != 0)) { 484 radeon_wb_fini(rdev); 485 return r; 486 } 487 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 488 &rdev->wb.gpu_addr); 489 if (r) { 490 radeon_bo_unreserve(rdev->wb.wb_obj); 491 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 492 radeon_wb_fini(rdev); 493 return r; 494 } 495 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 496 radeon_bo_unreserve(rdev->wb.wb_obj); 497 if (r) { 498 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 499 radeon_wb_fini(rdev); 500 return r; 501 } 502 } 503 504 /* clear wb memory */ 505 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); 506 /* disable event_write fences */ 507 rdev->wb.use_event = false; 508 /* disabled via module param */ 509 if (radeon_no_wb == 1) { 510 rdev->wb.enabled = false; 511 } else { 512 if (rdev->flags & RADEON_IS_AGP) { 513 /* often unreliable on AGP */ 514 rdev->wb.enabled = false; 515 } else if (rdev->family < CHIP_R300) { 516 /* often unreliable on pre-r300 */ 517 rdev->wb.enabled = false; 518 } else { 519 rdev->wb.enabled = true; 520 /* event_write fences are only available on r600+ */ 521 if (rdev->family >= CHIP_R600) { 522 rdev->wb.use_event = true; 523 } 524 } 525 } 526 /* always use writeback/events on NI, APUs */ 527 if (rdev->family >= CHIP_PALM) { 528 rdev->wb.enabled = true; 529 rdev->wb.use_event = true; 530 } 531 532 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 533 534 return 0; 535} 536 537/** 538 * radeon_vram_location - try to find VRAM location 539 * @rdev: radeon device structure holding all necessary informations 540 * @mc: memory controller structure holding memory informations 541 * @base: base address at which to put VRAM 542 * 543 * Function will place try to place VRAM at base address provided 544 * as parameter (which is so far either PCI aperture address or 545 * for IGP TOM base address). 546 * 547 * If there is not enough space to fit the unvisible VRAM in the 32bits 548 * address space then we limit the VRAM size to the aperture. 549 * 550 * If we are using AGP and if the AGP aperture doesn't allow us to have 551 * room for all the VRAM than we restrict the VRAM to the PCI aperture 552 * size and print a warning. 553 * 554 * This function will never fails, worst case are limiting VRAM. 555 * 556 * Note: GTT start, end, size should be initialized before calling this 557 * function on AGP platform. 558 * 559 * Note 1: We don't explicitly enforce VRAM start to be aligned on VRAM size, 560 * this shouldn't be a problem as we are using the PCI aperture as a reference. 561 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 562 * not IGP. 563 * 564 * Note 2: we use mc_vram_size as on some board we need to program the mc to 565 * cover the whole aperture even if VRAM size is inferior to aperture size 566 * Novell bug 204882 + along with lots of ubuntu ones 567 * 568 * Note 3: when limiting vram it's safe to overwritte real_vram_size because 569 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 570 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 571 * ones) 572 * 573 * Note 4: IGP TOM addr should be the same as the aperture addr, we don't 574 * explicitly check for that thought. 575 * 576 * FIXME: when reducing VRAM size align new size on power of 2. 577 */ 578void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 579{ 580 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 581 582 mc->vram_start = base; 583 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 584 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 585 mc->real_vram_size = mc->aper_size; 586 mc->mc_vram_size = mc->aper_size; 587 } 588 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 589 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 590 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 591 mc->real_vram_size = mc->aper_size; 592 mc->mc_vram_size = mc->aper_size; 593 } 594 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 595 if (limit && limit < mc->real_vram_size) 596 mc->real_vram_size = limit; 597 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 598 mc->mc_vram_size >> 20, mc->vram_start, 599 mc->vram_end, mc->real_vram_size >> 20); 600} 601 602/** 603 * radeon_gtt_location - try to find GTT location 604 * @rdev: radeon device structure holding all necessary informations 605 * @mc: memory controller structure holding memory informations 606 * 607 * Function will place try to place GTT before or after VRAM. 608 * 609 * If GTT size is bigger than space left then we ajust GTT size. 610 * Thus function will never fails. 611 * 612 * FIXME: when reducing GTT size align new size on power of 2. 613 */ 614void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 615{ 616 u64 size_af, size_bf; 617 618 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 619 size_bf = mc->vram_start & ~mc->gtt_base_align; 620 if (size_bf > size_af) { 621 if (mc->gtt_size > size_bf) { 622 dev_warn(rdev->dev, "limiting GTT\n"); 623 mc->gtt_size = size_bf; 624 } 625 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 626 } else { 627 if (mc->gtt_size > size_af) { 628 dev_warn(rdev->dev, "limiting GTT\n"); 629 mc->gtt_size = size_af; 630 } 631 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 632 } 633 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 634 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 635 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 636} 637 638/* 639 * GPU helpers function. 640 */ 641 642/* 643 * radeon_device_is_virtual - check if we are running is a virtual environment 644 * 645 * Check if the asic has been passed through to a VM (all asics). 646 * Used at driver startup. 647 * Returns true if virtual or false if not. 648 */ 649bool radeon_device_is_virtual(void) 650{ 651#ifdef CONFIG_X86 652 return (cpu_ecxfeature & CPUIDECX_HV); 653#else 654 return false; 655#endif 656} 657 658/** 659 * radeon_card_posted - check if the hw has already been initialized 660 * 661 * @rdev: radeon_device pointer 662 * 663 * Check if the asic has been initialized (all asics). 664 * Used at driver startup. 665 * Returns true if initialized or false if not. 666 */ 667bool radeon_card_posted(struct radeon_device *rdev) 668{ 669 uint32_t reg; 670 671 /* for pass through, always force asic_init for CI */ 672 if (rdev->family >= CHIP_BONAIRE && 673 radeon_device_is_virtual()) 674 return false; 675 676 /* required for EFI mode on macbook2,1 which uses an r5xx asic */ 677#ifdef notyet 678 if (efi_enabled(EFI_BOOT) && 679 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 680 (rdev->family < CHIP_R600)) 681 return false; 682#endif 683 684 if (ASIC_IS_NODCE(rdev)) 685 goto check_memsize; 686 687 /* first check CRTCs */ 688 if (ASIC_IS_DCE4(rdev)) { 689 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 690 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 691 if (rdev->num_crtc >= 4) { 692 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 693 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 694 } 695 if (rdev->num_crtc >= 6) { 696 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 697 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 698 } 699 if (reg & EVERGREEN_CRTC_MASTER_EN) 700 return true; 701 } else if (ASIC_IS_AVIVO(rdev)) { 702 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 703 RREG32(AVIVO_D2CRTC_CONTROL); 704 if (reg & AVIVO_CRTC_EN) { 705 return true; 706 } 707 } else { 708 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 709 RREG32(RADEON_CRTC2_GEN_CNTL); 710 if (reg & RADEON_CRTC_EN) { 711 return true; 712 } 713 } 714 715check_memsize: 716 /* then check MEM_SIZE, in case the crtcs are off */ 717 if (rdev->family >= CHIP_R600) 718 reg = RREG32(R600_CONFIG_MEMSIZE); 719 else 720 reg = RREG32(RADEON_CONFIG_MEMSIZE); 721 722 if (reg) 723 return true; 724 725 return false; 726 727} 728 729/** 730 * radeon_update_bandwidth_info - update display bandwidth params 731 * 732 * @rdev: radeon_device pointer 733 * 734 * Used when sclk/mclk are switched or display modes are set. 735 * params are used to calculate display watermarks (all asics) 736 */ 737void radeon_update_bandwidth_info(struct radeon_device *rdev) 738{ 739 fixed20_12 a; 740 u32 sclk = rdev->pm.current_sclk; 741 u32 mclk = rdev->pm.current_mclk; 742 743 /* sclk/mclk in Mhz */ 744 a.full = dfixed_const(100); 745 rdev->pm.sclk.full = dfixed_const(sclk); 746 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 747 rdev->pm.mclk.full = dfixed_const(mclk); 748 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 749 750 if (rdev->flags & RADEON_IS_IGP) { 751 a.full = dfixed_const(16); 752 /* core_bandwidth = sclk(Mhz) * 16 */ 753 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 754 } 755} 756 757/** 758 * radeon_boot_test_post_card - check and possibly initialize the hw 759 * 760 * @rdev: radeon_device pointer 761 * 762 * Check if the asic is initialized and if not, attempt to initialize 763 * it (all asics). 764 * Returns true if initialized or false if not. 765 */ 766bool radeon_boot_test_post_card(struct radeon_device *rdev) 767{ 768 if (radeon_card_posted(rdev)) 769 return true; 770 771 if (rdev->bios) { 772 DRM_INFO("GPU not posted. posting now...\n"); 773 if (rdev->is_atom_bios) 774 atom_asic_init(rdev->mode_info.atom_context); 775 else 776 radeon_combios_asic_init(rdev->ddev); 777 return true; 778 } else { 779 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 780 return false; 781 } 782} 783 784/** 785 * radeon_dummy_page_init - init dummy page used by the driver 786 * 787 * @rdev: radeon_device pointer 788 * 789 * Allocate the dummy page used by the driver (all asics). 790 * This dummy page is used by the driver as a filler for gart entries 791 * when pages are taken out of the GART 792 * Returns 0 on sucess, -ENOMEM on failure. 793 */ 794int radeon_dummy_page_init(struct radeon_device *rdev) 795{ 796 if (rdev->dummy_page.dmah) 797 return 0; 798 rdev->dummy_page.dmah = drm_dmamem_alloc(rdev->dmat, PAGE_SIZE, PAGE_SIZE, 1, 799 PAGE_SIZE, 0, BUS_DMA_WAITOK); 800 if (!rdev->dummy_page.dmah) 801 return -ENOMEM; 802 rdev->dummy_page.addr = (bus_addr_t)rdev->dummy_page.dmah->map->dm_segs[0].ds_addr; 803 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, 804 RADEON_GART_PAGE_DUMMY); 805 return 0; 806} 807 808/** 809 * radeon_dummy_page_fini - free dummy page used by the driver 810 * 811 * @rdev: radeon_device pointer 812 * 813 * Frees the dummy page used by the driver (all asics). 814 */ 815void radeon_dummy_page_fini(struct radeon_device *rdev) 816{ 817 if (rdev->dummy_page.dmah == NULL) 818 return; 819 820 drm_dmamem_free(rdev->dmat, rdev->dummy_page.dmah); 821 rdev->dummy_page.dmah = NULL; 822 rdev->dummy_page.addr = 0; 823} 824 825 826/* ATOM accessor methods */ 827/* 828 * ATOM is an interpreted byte code stored in tables in the vbios. The 829 * driver registers callbacks to access registers and the interpreter 830 * in the driver parses the tables and executes then to program specific 831 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 832 * atombios.h, and atom.c 833 */ 834 835/** 836 * cail_pll_read - read PLL register 837 * 838 * @info: atom card_info pointer 839 * @reg: PLL register offset 840 * 841 * Provides a PLL register accessor for the atom interpreter (r4xx+). 842 * Returns the value of the PLL register. 843 */ 844static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 845{ 846 struct radeon_device *rdev = info->dev->dev_private; 847 uint32_t r; 848 849 r = rdev->pll_rreg(rdev, reg); 850 return r; 851} 852 853/** 854 * cail_pll_write - write PLL register 855 * 856 * @info: atom card_info pointer 857 * @reg: PLL register offset 858 * @val: value to write to the pll register 859 * 860 * Provides a PLL register accessor for the atom interpreter (r4xx+). 861 */ 862static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 863{ 864 struct radeon_device *rdev = info->dev->dev_private; 865 866 rdev->pll_wreg(rdev, reg, val); 867} 868 869/** 870 * cail_mc_read - read MC (Memory Controller) register 871 * 872 * @info: atom card_info pointer 873 * @reg: MC register offset 874 * 875 * Provides an MC register accessor for the atom interpreter (r4xx+). 876 * Returns the value of the MC register. 877 */ 878static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 879{ 880 struct radeon_device *rdev = info->dev->dev_private; 881 uint32_t r; 882 883 r = rdev->mc_rreg(rdev, reg); 884 return r; 885} 886 887/** 888 * cail_mc_write - write MC (Memory Controller) register 889 * 890 * @info: atom card_info pointer 891 * @reg: MC register offset 892 * @val: value to write to the pll register 893 * 894 * Provides a MC register accessor for the atom interpreter (r4xx+). 895 */ 896static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 897{ 898 struct radeon_device *rdev = info->dev->dev_private; 899 900 rdev->mc_wreg(rdev, reg, val); 901} 902 903/** 904 * cail_reg_write - write MMIO register 905 * 906 * @info: atom card_info pointer 907 * @reg: MMIO register offset 908 * @val: value to write to the pll register 909 * 910 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 911 */ 912static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 913{ 914 struct radeon_device *rdev = info->dev->dev_private; 915 916 WREG32(reg*4, val); 917} 918 919/** 920 * cail_reg_read - read MMIO register 921 * 922 * @info: atom card_info pointer 923 * @reg: MMIO register offset 924 * 925 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 926 * Returns the value of the MMIO register. 927 */ 928static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 929{ 930 struct radeon_device *rdev = info->dev->dev_private; 931 uint32_t r; 932 933 r = RREG32(reg*4); 934 return r; 935} 936 937/** 938 * cail_ioreg_write - write IO register 939 * 940 * @info: atom card_info pointer 941 * @reg: IO register offset 942 * @val: value to write to the pll register 943 * 944 * Provides a IO register accessor for the atom interpreter (r4xx+). 945 */ 946static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 947{ 948 struct radeon_device *rdev = info->dev->dev_private; 949 950 WREG32_IO(reg*4, val); 951} 952 953/** 954 * cail_ioreg_read - read IO register 955 * 956 * @info: atom card_info pointer 957 * @reg: IO register offset 958 * 959 * Provides an IO register accessor for the atom interpreter (r4xx+). 960 * Returns the value of the IO register. 961 */ 962static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 963{ 964 struct radeon_device *rdev = info->dev->dev_private; 965 uint32_t r; 966 967 r = RREG32_IO(reg*4); 968 return r; 969} 970 971/** 972 * radeon_atombios_init - init the driver info and callbacks for atombios 973 * 974 * @rdev: radeon_device pointer 975 * 976 * Initializes the driver info and register access callbacks for the 977 * ATOM interpreter (r4xx+). 978 * Returns 0 on sucess, -ENOMEM on failure. 979 * Called at driver startup. 980 */ 981int radeon_atombios_init(struct radeon_device *rdev) 982{ 983 struct card_info *atom_card_info = 984 kzalloc(sizeof(struct card_info), GFP_KERNEL); 985 986 if (!atom_card_info) 987 return -ENOMEM; 988 989 rdev->mode_info.atom_card_info = atom_card_info; 990 atom_card_info->dev = rdev->ddev; 991 atom_card_info->reg_read = cail_reg_read; 992 atom_card_info->reg_write = cail_reg_write; 993 /* needed for iio ops */ 994 if (rdev->rio_mem_size > 0) { 995 atom_card_info->ioreg_read = cail_ioreg_read; 996 atom_card_info->ioreg_write = cail_ioreg_write; 997 } else { 998#ifndef __powerpc64__ 999 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 1000#endif 1001 atom_card_info->ioreg_read = cail_reg_read; 1002 atom_card_info->ioreg_write = cail_reg_write; 1003 } 1004 atom_card_info->mc_read = cail_mc_read; 1005 atom_card_info->mc_write = cail_mc_write; 1006 atom_card_info->pll_read = cail_pll_read; 1007 atom_card_info->pll_write = cail_pll_write; 1008 1009 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 1010 if (!rdev->mode_info.atom_context) { 1011 radeon_atombios_fini(rdev); 1012 return -ENOMEM; 1013 } 1014 1015 rw_init(&rdev->mode_info.atom_context->mutex, "atomcon"); 1016 rw_init(&rdev->mode_info.atom_context->scratch_mutex, "atomscr"); 1017 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 1018 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 1019 return 0; 1020} 1021 1022/** 1023 * radeon_atombios_fini - free the driver info and callbacks for atombios 1024 * 1025 * @rdev: radeon_device pointer 1026 * 1027 * Frees the driver info and register access callbacks for the ATOM 1028 * interpreter (r4xx+). 1029 * Called at driver shutdown. 1030 */ 1031void radeon_atombios_fini(struct radeon_device *rdev) 1032{ 1033 if (rdev->mode_info.atom_context) { 1034 kfree(rdev->mode_info.atom_context->scratch); 1035 kfree(rdev->mode_info.atom_context->iio); 1036 } 1037 kfree(rdev->mode_info.atom_context); 1038 rdev->mode_info.atom_context = NULL; 1039 kfree(rdev->mode_info.atom_card_info); 1040 rdev->mode_info.atom_card_info = NULL; 1041} 1042 1043/* COMBIOS */ 1044/* 1045 * COMBIOS is the bios format prior to ATOM. It provides 1046 * command tables similar to ATOM, but doesn't have a unified 1047 * parser. See radeon_combios.c 1048 */ 1049 1050/** 1051 * radeon_combios_init - init the driver info for combios 1052 * 1053 * @rdev: radeon_device pointer 1054 * 1055 * Initializes the driver info for combios (r1xx-r3xx). 1056 * Returns 0 on sucess. 1057 * Called at driver startup. 1058 */ 1059int radeon_combios_init(struct radeon_device *rdev) 1060{ 1061 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 1062 return 0; 1063} 1064 1065/** 1066 * radeon_combios_fini - free the driver info for combios 1067 * 1068 * @rdev: radeon_device pointer 1069 * 1070 * Frees the driver info for combios (r1xx-r3xx). 1071 * Called at driver shutdown. 1072 */ 1073void radeon_combios_fini(struct radeon_device *rdev) 1074{ 1075} 1076 1077/* if we get transitioned to only one device, take VGA back */ 1078/** 1079 * radeon_vga_set_decode - enable/disable vga decode 1080 * 1081 * @pdev: PCI device 1082 * @state: enable/disable vga decode 1083 * 1084 * Enable/disable vga decode (all asics). 1085 * Returns VGA resource flags. 1086 */ 1087static unsigned int radeon_vga_set_decode(struct pci_dev *pdev, bool state) 1088{ 1089 STUB(); 1090 return -ENOSYS; 1091#ifdef notyet 1092 struct drm_device *dev = pci_get_drvdata(pdev); 1093 struct radeon_device *rdev = dev->dev_private; 1094 radeon_vga_set_state(rdev, state); 1095 if (state) 1096 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1097 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1098 else 1099 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1100#endif 1101} 1102 1103/** 1104 * radeon_gart_size_auto - Determine a sensible default GART size 1105 * according to ASIC family. 1106 * 1107 * @family: ASIC family name 1108 */ 1109static int radeon_gart_size_auto(enum radeon_family family) 1110{ 1111 /* default to a larger gart size on newer asics */ 1112 if (family >= CHIP_TAHITI) 1113 return 2048; 1114 else if (family >= CHIP_RV770) 1115 return 1024; 1116 else 1117 return 512; 1118} 1119 1120/** 1121 * radeon_check_arguments - validate module params 1122 * 1123 * @rdev: radeon_device pointer 1124 * 1125 * Validates certain module parameters and updates 1126 * the associated values used by the driver (all asics). 1127 */ 1128static void radeon_check_arguments(struct radeon_device *rdev) 1129{ 1130 /* vramlimit must be a power of two */ 1131 if (radeon_vram_limit != 0 && !is_power_of_2(radeon_vram_limit)) { 1132 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 1133 radeon_vram_limit); 1134 radeon_vram_limit = 0; 1135 } 1136 1137 if (radeon_gart_size == -1) { 1138 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1139 } 1140 /* gtt size must be power of two and greater or equal to 32M */ 1141 if (radeon_gart_size < 32) { 1142 dev_warn(rdev->dev, "gart size (%d) too small\n", 1143 radeon_gart_size); 1144 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1145 } else if (!is_power_of_2(radeon_gart_size)) { 1146 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 1147 radeon_gart_size); 1148 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1149 } 1150 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 1151 1152 /* AGP mode can only be -1, 1, 2, 4, 8 */ 1153 switch (radeon_agpmode) { 1154 case -1: 1155 case 0: 1156 case 1: 1157 case 2: 1158 case 4: 1159 case 8: 1160 break; 1161 default: 1162 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 1163 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 1164 radeon_agpmode = 0; 1165 break; 1166 } 1167 1168 if (!is_power_of_2(radeon_vm_size)) { 1169 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", 1170 radeon_vm_size); 1171 radeon_vm_size = 4; 1172 } 1173 1174 if (radeon_vm_size < 1) { 1175 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n", 1176 radeon_vm_size); 1177 radeon_vm_size = 4; 1178 } 1179 1180 /* 1181 * Max GPUVM size for Cayman, SI and CI are 40 bits. 1182 */ 1183 if (radeon_vm_size > 1024) { 1184 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", 1185 radeon_vm_size); 1186 radeon_vm_size = 4; 1187 } 1188 1189 /* defines number of bits in page table versus page directory, 1190 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1191 * page table and the remaining bits are in the page directory */ 1192 if (radeon_vm_block_size == -1) { 1193 1194 /* Total bits covered by PD + PTs */ 1195 unsigned bits = ilog2(radeon_vm_size) + 18; 1196 1197 /* Make sure the PD is 4K in size up to 8GB address space. 1198 Above that split equal between PD and PTs */ 1199 if (radeon_vm_size <= 8) 1200 radeon_vm_block_size = bits - 9; 1201 else 1202 radeon_vm_block_size = (bits + 3) / 2; 1203 1204 } else if (radeon_vm_block_size < 9) { 1205 dev_warn(rdev->dev, "VM page table size (%d) too small\n", 1206 radeon_vm_block_size); 1207 radeon_vm_block_size = 9; 1208 } 1209 1210 if (radeon_vm_block_size > 24 || 1211 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { 1212 dev_warn(rdev->dev, "VM page table size (%d) too large\n", 1213 radeon_vm_block_size); 1214 radeon_vm_block_size = 9; 1215 } 1216} 1217 1218/** 1219 * radeon_switcheroo_set_state - set switcheroo state 1220 * 1221 * @pdev: pci dev pointer 1222 * @state: vga_switcheroo state 1223 * 1224 * Callback for the switcheroo driver. Suspends or resumes 1225 * the asics before or after it is powered up using ACPI methods. 1226 */ 1227#ifdef notyet 1228static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1229{ 1230 struct drm_device *dev = pci_get_drvdata(pdev); 1231 1232 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF) 1233 return; 1234 1235 if (state == VGA_SWITCHEROO_ON) { 1236 pr_info("radeon: switched on\n"); 1237 /* don't suspend or resume card normally */ 1238 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1239 1240 radeon_resume_kms(dev, true, true); 1241 1242 dev->switch_power_state = DRM_SWITCH_POWER_ON; 1243 drm_kms_helper_poll_enable(dev); 1244 } else { 1245 pr_info("radeon: switched off\n"); 1246 drm_kms_helper_poll_disable(dev); 1247 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1248 radeon_suspend_kms(dev, true, true, false); 1249 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 1250 } 1251} 1252 1253/** 1254 * radeon_switcheroo_can_switch - see if switcheroo state can change 1255 * 1256 * @pdev: pci dev pointer 1257 * 1258 * Callback for the switcheroo driver. Check of the switcheroo 1259 * state can be changed. 1260 * Returns true if the state can be changed, false if not. 1261 */ 1262static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1263{ 1264 struct drm_device *dev = pci_get_drvdata(pdev); 1265 1266 /* 1267 * FIXME: open_count is protected by drm_global_mutex but that would lead to 1268 * locking inversion with the driver load path. And the access here is 1269 * completely racy anyway. So don't bother with locking for now. 1270 */ 1271 return atomic_read(&dev->open_count) == 0; 1272} 1273 1274static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1275 .set_gpu_state = radeon_switcheroo_set_state, 1276 .reprobe = NULL, 1277 .can_switch = radeon_switcheroo_can_switch, 1278}; 1279#endif 1280 1281/** 1282 * radeon_device_init - initialize the driver 1283 * 1284 * @rdev: radeon_device pointer 1285 * @ddev: drm dev pointer 1286 * @pdev: pci dev pointer 1287 * @flags: driver flags 1288 * 1289 * Initializes the driver info and hw (all asics). 1290 * Returns 0 for success or an error on failure. 1291 * Called at driver startup. 1292 */ 1293int radeon_device_init(struct radeon_device *rdev, 1294 struct drm_device *ddev, 1295 struct pci_dev *pdev, 1296 uint32_t flags) 1297{ 1298 int r, i; 1299 int dma_bits; 1300 bool runtime = false; 1301 1302 rdev->shutdown = false; 1303 rdev->ddev = ddev; 1304 rdev->pdev = pdev; 1305 rdev->flags = flags; 1306 rdev->family = flags & RADEON_FAMILY_MASK; 1307 rdev->is_atom_bios = false; 1308 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1309 rdev->mc.gtt_size = 512 * 1024 * 1024; 1310 rdev->accel_working = false; 1311 /* set up ring ids */ 1312 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1313 rdev->ring[i].idx = i; 1314 } 1315 rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS); 1316 1317 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", 1318 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1319 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); 1320 printf("%s: %s\n", rdev->self.dv_xname, radeon_family_name[rdev->family]); 1321 1322 /* mutex initialization are all done here so we 1323 * can recall function without having locking issues */ 1324 rw_init(&rdev->ring_lock, "ring"); 1325 rw_init(&rdev->dc_hw_i2c_mutex, "dciic"); 1326 atomic_set(&rdev->ih.lock, 0); 1327 rw_init(&rdev->gem.mutex, "gem"); 1328 rw_init(&rdev->pm.mutex, "pm"); 1329 rw_init(&rdev->gpu_clock_mutex, "gpuclk"); 1330 rw_init(&rdev->srbm_mutex, "srbm"); 1331 rw_init(&rdev->audio.component_mutex, "racm"); 1332 rw_init(&rdev->pm.mclk_lock, "mclk"); 1333 rw_init(&rdev->exclusive_lock, "rdnexc"); 1334 init_waitqueue_head(&rdev->irq.vblank_queue); 1335 r = radeon_gem_init(rdev); 1336 if (r) 1337 return r; 1338 1339 radeon_check_arguments(rdev); 1340 /* Adjust VM size here. 1341 * Max GPUVM size for cayman+ is 40 bits. 1342 */ 1343 rdev->vm_manager.max_pfn = radeon_vm_size << 18; 1344 1345 /* Set asic functions */ 1346 r = radeon_asic_init(rdev); 1347 if (r) 1348 return r; 1349 1350 /* all of the newer IGP chips have an internal gart 1351 * However some rs4xx report as AGP, so remove that here. 1352 */ 1353 if ((rdev->family >= CHIP_RS400) && 1354 (rdev->flags & RADEON_IS_IGP)) { 1355 rdev->flags &= ~RADEON_IS_AGP; 1356 } 1357 1358 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1359 radeon_agp_disable(rdev); 1360 } 1361 1362 /* Set the internal MC address mask 1363 * This is the max address of the GPU's 1364 * internal address space. 1365 */ 1366 if (rdev->family >= CHIP_CAYMAN) 1367 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1368 else if (rdev->family >= CHIP_CEDAR) 1369 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1370 else 1371 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1372 1373 /* set DMA mask. 1374 * PCIE - can handle 40-bits. 1375 * IGP - can handle 40-bits 1376 * AGP - generally dma32 is safest 1377 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1378 */ 1379 dma_bits = 40; 1380 if (rdev->flags & RADEON_IS_AGP) 1381 dma_bits = 32; 1382 if ((rdev->flags & RADEON_IS_PCI) && 1383 (rdev->family <= CHIP_RS740)) 1384 dma_bits = 32; 1385#ifdef CONFIG_PPC64 1386 if (rdev->family == CHIP_CEDAR) 1387 dma_bits = 32; 1388#endif 1389 1390 r = dma_set_mask_and_coherent(&rdev->pdev->dev, DMA_BIT_MASK(dma_bits)); 1391 if (r) { 1392 pr_warn("radeon: No suitable DMA available\n"); 1393 return r; 1394 } 1395 rdev->need_swiotlb = drm_need_swiotlb(dma_bits); 1396 1397 /* Registers mapping */ 1398 /* TODO: block userspace mapping of io register */ 1399 mtx_init(&rdev->mmio_idx_lock, IPL_TTY); 1400 mtx_init(&rdev->smc_idx_lock, IPL_TTY); 1401 mtx_init(&rdev->pll_idx_lock, IPL_TTY); 1402 mtx_init(&rdev->mc_idx_lock, IPL_TTY); 1403 mtx_init(&rdev->pcie_idx_lock, IPL_TTY); 1404 mtx_init(&rdev->pciep_idx_lock, IPL_TTY); 1405 mtx_init(&rdev->pif_idx_lock, IPL_TTY); 1406 mtx_init(&rdev->cg_idx_lock, IPL_TTY); 1407 mtx_init(&rdev->uvd_idx_lock, IPL_TTY); 1408 mtx_init(&rdev->rcu_idx_lock, IPL_TTY); 1409 mtx_init(&rdev->didt_idx_lock, IPL_TTY); 1410 mtx_init(&rdev->end_idx_lock, IPL_TTY); 1411#ifdef __linux__ 1412 if (rdev->family >= CHIP_BONAIRE) { 1413 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); 1414 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); 1415 } else { 1416 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 1417 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 1418 } 1419 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 1420 if (rdev->rmmio == NULL) 1421 return -ENOMEM; 1422#endif 1423 1424 /* doorbell bar mapping */ 1425 if (rdev->family >= CHIP_BONAIRE) 1426 radeon_doorbell_init(rdev); 1427 1428 /* io port mapping */ 1429#ifdef __linux__ 1430 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1431 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { 1432 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 1433 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); 1434 break; 1435 } 1436 } 1437 if (rdev->rio_mem == NULL) 1438 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1439#endif 1440 1441 if (rdev->flags & RADEON_IS_PX) 1442 radeon_device_handle_px_quirks(rdev); 1443 1444 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1445 /* this will fail for cards that aren't VGA class devices, just 1446 * ignore it */ 1447 vga_client_register(rdev->pdev, radeon_vga_set_decode); 1448 1449 if (rdev->flags & RADEON_IS_PX) 1450 runtime = true; 1451#ifdef notyet 1452 if (!pci_is_thunderbolt_attached(rdev->pdev)) 1453 vga_switcheroo_register_client(rdev->pdev, 1454 &radeon_switcheroo_ops, runtime); 1455#endif 1456 if (runtime) 1457 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); 1458 1459 r = radeon_init(rdev); 1460 if (r) 1461 goto failed; 1462 1463 radeon_gem_debugfs_init(rdev); 1464 1465 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1466 /* Acceleration not working on AGP card try again 1467 * with fallback to PCI or PCIE GART 1468 */ 1469 radeon_asic_reset(rdev); 1470 radeon_fini(rdev); 1471 radeon_agp_disable(rdev); 1472 r = radeon_init(rdev); 1473 if (r) 1474 goto failed; 1475 } 1476 1477 radeon_audio_component_init(rdev); 1478 1479 r = radeon_ib_ring_tests(rdev); 1480 if (r) 1481 DRM_ERROR("ib ring test failed (%d).\n", r); 1482 1483 /* 1484 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted 1485 * after the CP ring have chew one packet at least. Hence here we stop 1486 * and restart DPM after the radeon_ib_ring_tests(). 1487 */ 1488 if (rdev->pm.dpm_enabled && 1489 (rdev->pm.pm_method == PM_METHOD_DPM) && 1490 (rdev->family == CHIP_TURKS) && 1491 (rdev->flags & RADEON_IS_MOBILITY)) { 1492 mutex_lock(&rdev->pm.mutex); 1493 radeon_dpm_disable(rdev); 1494 radeon_dpm_enable(rdev); 1495 mutex_unlock(&rdev->pm.mutex); 1496 } 1497 1498 if ((radeon_testing & 1)) { 1499 if (rdev->accel_working) 1500 radeon_test_moves(rdev); 1501 else 1502 DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); 1503 } 1504 if ((radeon_testing & 2)) { 1505 if (rdev->accel_working) 1506 radeon_test_syncing(rdev); 1507 else 1508 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); 1509 } 1510 if (radeon_benchmarking) { 1511 if (rdev->accel_working) 1512 radeon_benchmark(rdev, radeon_benchmarking); 1513 else 1514 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); 1515 } 1516 return 0; 1517 1518failed: 1519 /* balance pm_runtime_get_sync() in radeon_driver_unload_kms() */ 1520 if (radeon_is_px(ddev)) 1521 pm_runtime_put_noidle(ddev->dev); 1522 if (runtime) 1523 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1524 return r; 1525} 1526 1527/** 1528 * radeon_device_fini - tear down the driver 1529 * 1530 * @rdev: radeon_device pointer 1531 * 1532 * Tear down the driver info (all asics). 1533 * Called at driver shutdown. 1534 */ 1535void radeon_device_fini(struct radeon_device *rdev) 1536{ 1537 DRM_INFO("radeon: finishing device.\n"); 1538 rdev->shutdown = true; 1539 /* evict vram memory */ 1540 radeon_bo_evict_vram(rdev); 1541 radeon_audio_component_fini(rdev); 1542 radeon_fini(rdev); 1543 if (!pci_is_thunderbolt_attached(rdev->pdev)) 1544 vga_switcheroo_unregister_client(rdev->pdev); 1545 if (rdev->flags & RADEON_IS_PX) 1546 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1547 vga_client_unregister(rdev->pdev); 1548#ifdef __linux__ 1549 if (rdev->rio_mem) 1550 pci_iounmap(rdev->pdev, rdev->rio_mem); 1551 rdev->rio_mem = NULL; 1552 iounmap(rdev->rmmio); 1553#else 1554 if (rdev->rio_mem_size > 0) 1555 bus_space_unmap(rdev->iot, rdev->rio_mem, rdev->rio_mem_size); 1556 rdev->rio_mem_size = 0; 1557 1558 if (rdev->rmmio_size > 0) 1559 bus_space_unmap(rdev->memt, rdev->rmmio_bsh, rdev->rmmio_size); 1560 rdev->rmmio_size = 0; 1561#endif 1562 rdev->rmmio = NULL; 1563 if (rdev->family >= CHIP_BONAIRE) 1564 radeon_doorbell_fini(rdev); 1565} 1566 1567 1568/* 1569 * Suspend & resume. 1570 */ 1571/* 1572 * radeon_suspend_kms - initiate device suspend 1573 * 1574 * Puts the hw in the suspend state (all asics). 1575 * Returns 0 for success or an error on failure. 1576 * Called at driver suspend. 1577 */ 1578int radeon_suspend_kms(struct drm_device *dev, bool suspend, 1579 bool fbcon, bool freeze) 1580{ 1581 struct radeon_device *rdev; 1582 struct pci_dev *pdev; 1583 struct drm_crtc *crtc; 1584 struct drm_connector *connector; 1585 int i, r; 1586 1587 if (dev == NULL || dev->dev_private == NULL) { 1588 return -ENODEV; 1589 } 1590 1591 rdev = dev->dev_private; 1592#ifdef __linux__ 1593 pdev = to_pci_dev(dev->dev); 1594#else 1595 pdev = dev->pdev; 1596#endif 1597 1598 if (rdev->shutdown) 1599 return 0; 1600 1601#ifdef notyet 1602 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1603 return 0; 1604#endif 1605 1606 drm_kms_helper_poll_disable(dev); 1607 1608 drm_modeset_lock_all(dev); 1609 /* turn off display hw */ 1610 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1611 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1612 } 1613 drm_modeset_unlock_all(dev); 1614 1615 /* unpin the front buffers and cursors */ 1616 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1617 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1618 struct drm_framebuffer *fb = crtc->primary->fb; 1619 struct radeon_bo *robj; 1620 1621 if (radeon_crtc->cursor_bo) { 1622 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1623 r = radeon_bo_reserve(robj, false); 1624 if (r == 0) { 1625 radeon_bo_unpin(robj); 1626 radeon_bo_unreserve(robj); 1627 } 1628 } 1629 1630 if (fb == NULL || fb->obj[0] == NULL) { 1631 continue; 1632 } 1633 robj = gem_to_radeon_bo(fb->obj[0]); 1634 /* don't unpin kernel fb objects */ 1635 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1636 r = radeon_bo_reserve(robj, false); 1637 if (r == 0) { 1638 radeon_bo_unpin(robj); 1639 radeon_bo_unreserve(robj); 1640 } 1641 } 1642 } 1643 /* evict vram memory */ 1644 radeon_bo_evict_vram(rdev); 1645 1646 /* wait for gpu to finish processing current batch */ 1647 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1648 r = radeon_fence_wait_empty(rdev, i); 1649 if (r) { 1650 /* delay GPU reset to resume */ 1651 radeon_fence_driver_force_completion(rdev, i); 1652 } else { 1653 /* finish executing delayed work */ 1654 flush_delayed_work(&rdev->fence_drv[i].lockup_work); 1655 } 1656 } 1657 1658 radeon_save_bios_scratch_regs(rdev); 1659 1660 radeon_suspend(rdev); 1661 radeon_hpd_fini(rdev); 1662 /* evict remaining vram memory 1663 * This second call to evict vram is to evict the gart page table 1664 * using the CPU. 1665 */ 1666 radeon_bo_evict_vram(rdev); 1667 1668 radeon_agp_suspend(rdev); 1669 1670 pci_save_state(pdev); 1671 if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) { 1672 rdev->asic->asic_reset(rdev, true); 1673 pci_restore_state(pdev); 1674 } else if (suspend) { 1675 /* Shut down the device */ 1676 pci_disable_device(pdev); 1677 pci_set_power_state(pdev, PCI_D3hot); 1678 } 1679 1680 if (fbcon) { 1681 console_lock(); 1682 radeon_fbdev_set_suspend(rdev, 1); 1683 console_unlock(); 1684 } 1685 return 0; 1686} 1687 1688/* 1689 * radeon_resume_kms - initiate device resume 1690 * 1691 * Bring the hw back to operating state (all asics). 1692 * Returns 0 for success or an error on failure. 1693 * Called at driver resume. 1694 */ 1695int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) 1696{ 1697 struct drm_connector *connector; 1698 struct radeon_device *rdev = dev->dev_private; 1699#ifdef __linux__ 1700 struct pci_dev *pdev = to_pci_dev(dev->dev); 1701#else 1702 struct pci_dev *pdev = dev->pdev; 1703#endif 1704 struct drm_crtc *crtc; 1705 int r; 1706 1707#ifdef notyet 1708 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1709 return 0; 1710#endif 1711 1712 if (fbcon) { 1713 console_lock(); 1714 } 1715 if (resume) { 1716 pci_set_power_state(pdev, PCI_D0); 1717 pci_restore_state(pdev); 1718 if (pci_enable_device(pdev)) { 1719 if (fbcon) 1720 console_unlock(); 1721 return -1; 1722 } 1723 } 1724 /* resume AGP if in use */ 1725 radeon_agp_resume(rdev); 1726 radeon_resume(rdev); 1727 1728 r = radeon_ib_ring_tests(rdev); 1729 if (r) 1730 DRM_ERROR("ib ring test failed (%d).\n", r); 1731 1732 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1733 /* do dpm late init */ 1734 r = radeon_pm_late_init(rdev); 1735 if (r) { 1736 rdev->pm.dpm_enabled = false; 1737 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1738 } 1739 } else { 1740 /* resume old pm late */ 1741 radeon_pm_resume(rdev); 1742 } 1743 1744 radeon_restore_bios_scratch_regs(rdev); 1745 1746 /* pin cursors */ 1747 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1748 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1749 1750 if (radeon_crtc->cursor_bo) { 1751 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1752 r = radeon_bo_reserve(robj, false); 1753 if (r == 0) { 1754 /* Only 27 bit offset for legacy cursor */ 1755 r = radeon_bo_pin_restricted(robj, 1756 RADEON_GEM_DOMAIN_VRAM, 1757 ASIC_IS_AVIVO(rdev) ? 1758 0 : 1 << 27, 1759 &radeon_crtc->cursor_addr); 1760 if (r != 0) 1761 DRM_ERROR("Failed to pin cursor BO (%d)\n", r); 1762 radeon_bo_unreserve(robj); 1763 } 1764 } 1765 } 1766 1767 /* init dig PHYs, disp eng pll */ 1768 if (rdev->is_atom_bios) { 1769 radeon_atom_encoder_init(rdev); 1770 radeon_atom_disp_eng_pll_init(rdev); 1771 /* turn on the BL */ 1772 if (rdev->mode_info.bl_encoder) { 1773 u8 bl_level = radeon_get_backlight_level(rdev, 1774 rdev->mode_info.bl_encoder); 1775 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1776 bl_level); 1777 } 1778 } 1779 /* reset hpd state */ 1780 radeon_hpd_init(rdev); 1781 /* blat the mode back in */ 1782 if (fbcon) { 1783 drm_helper_resume_force_mode(dev); 1784 /* turn on display hw */ 1785 drm_modeset_lock_all(dev); 1786 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1787 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1788 } 1789 drm_modeset_unlock_all(dev); 1790 } 1791 1792 drm_kms_helper_poll_enable(dev); 1793 1794 /* set the power state here in case we are a PX system or headless */ 1795 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1796 radeon_pm_compute_clocks(rdev); 1797 1798 if (fbcon) { 1799 radeon_fbdev_set_suspend(rdev, 0); 1800 console_unlock(); 1801 } 1802 1803 return 0; 1804} 1805 1806/** 1807 * radeon_gpu_reset - reset the asic 1808 * 1809 * @rdev: radeon device pointer 1810 * 1811 * Attempt the reset the GPU if it has hung (all asics). 1812 * Returns 0 for success or an error on failure. 1813 */ 1814int radeon_gpu_reset(struct radeon_device *rdev) 1815{ 1816 unsigned ring_sizes[RADEON_NUM_RINGS]; 1817 uint32_t *ring_data[RADEON_NUM_RINGS]; 1818 1819 bool saved = false; 1820 1821 int i, r; 1822 1823 down_write(&rdev->exclusive_lock); 1824 1825 if (!rdev->needs_reset) { 1826 up_write(&rdev->exclusive_lock); 1827 return 0; 1828 } 1829 1830 atomic_inc(&rdev->gpu_reset_counter); 1831 1832 radeon_save_bios_scratch_regs(rdev); 1833 radeon_suspend(rdev); 1834 radeon_hpd_fini(rdev); 1835 1836 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1837 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1838 &ring_data[i]); 1839 if (ring_sizes[i]) { 1840 saved = true; 1841 dev_info(rdev->dev, "Saved %d dwords of commands " 1842 "on ring %d.\n", ring_sizes[i], i); 1843 } 1844 } 1845 1846 r = radeon_asic_reset(rdev); 1847 if (!r) { 1848 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1849 radeon_resume(rdev); 1850 } 1851 1852 radeon_restore_bios_scratch_regs(rdev); 1853 1854 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1855 if (!r && ring_data[i]) { 1856 radeon_ring_restore(rdev, &rdev->ring[i], 1857 ring_sizes[i], ring_data[i]); 1858 } else { 1859 radeon_fence_driver_force_completion(rdev, i); 1860 kfree(ring_data[i]); 1861 } 1862 } 1863 1864 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1865 /* do dpm late init */ 1866 r = radeon_pm_late_init(rdev); 1867 if (r) { 1868 rdev->pm.dpm_enabled = false; 1869 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1870 } 1871 } else { 1872 /* resume old pm late */ 1873 radeon_pm_resume(rdev); 1874 } 1875 1876 /* init dig PHYs, disp eng pll */ 1877 if (rdev->is_atom_bios) { 1878 radeon_atom_encoder_init(rdev); 1879 radeon_atom_disp_eng_pll_init(rdev); 1880 /* turn on the BL */ 1881 if (rdev->mode_info.bl_encoder) { 1882 u8 bl_level = radeon_get_backlight_level(rdev, 1883 rdev->mode_info.bl_encoder); 1884 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1885 bl_level); 1886 } 1887 } 1888 /* reset hpd state */ 1889 radeon_hpd_init(rdev); 1890 1891 rdev->in_reset = true; 1892 rdev->needs_reset = false; 1893 1894 downgrade_write(&rdev->exclusive_lock); 1895 1896 drm_helper_resume_force_mode(rdev->ddev); 1897 1898 /* set the power state here in case we are a PX system or headless */ 1899 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1900 radeon_pm_compute_clocks(rdev); 1901 1902 if (!r) { 1903 r = radeon_ib_ring_tests(rdev); 1904 if (r && saved) 1905 r = -EAGAIN; 1906 } else { 1907 /* bad news, how to tell it to userspace ? */ 1908 dev_info(rdev->dev, "GPU reset failed\n"); 1909 } 1910 1911 rdev->needs_reset = r == -EAGAIN; 1912 rdev->in_reset = false; 1913 1914 up_read(&rdev->exclusive_lock); 1915 return r; 1916} 1917