radeon_bios.c revision 1.18
1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <linux/acpi.h> 30#include <linux/pci.h> 31#include <linux/slab.h> 32 33#include <drm/drm_device.h> 34 35#include "atom.h" 36#include "radeon.h" 37#include "radeon_reg.h" 38 39#if defined(__amd64__) || defined(__i386__) 40#include <dev/isa/isareg.h> 41#include <dev/isa/isavar.h> 42#endif 43 44#if defined (__loongson__) 45#include <machine/autoconf.h> 46#endif 47 48/* 49 * BIOS. 50 */ 51 52/* If you boot an IGP board with a discrete card as the primary, 53 * the IGP rom is not accessible via the rom bar as the IGP rom is 54 * part of the system bios. On boot, the system bios puts a 55 * copy of the igp rom at the start of vram if a discrete card is 56 * present. 57 */ 58#ifdef __linux__ 59static bool igp_read_bios_from_vram(struct radeon_device *rdev) 60{ 61 uint8_t __iomem *bios; 62 resource_size_t vram_base; 63 resource_size_t size = 256 * 1024; /* ??? */ 64 65 if (!(rdev->flags & RADEON_IS_IGP)) 66 if (!radeon_card_posted(rdev)) 67 return false; 68 69 rdev->bios = NULL; 70 vram_base = pci_resource_start(rdev->pdev, 0); 71 bios = ioremap(vram_base, size); 72 if (!bios) { 73 return false; 74 } 75 76 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 77 iounmap(bios); 78 return false; 79 } 80 rdev->bios = kmalloc(size, GFP_KERNEL); 81 if (rdev->bios == NULL) { 82 iounmap(bios); 83 return false; 84 } 85 memcpy_fromio(rdev->bios, bios, size); 86 iounmap(bios); 87 return true; 88} 89#else 90static bool igp_read_bios_from_vram(struct radeon_device *rdev) 91{ 92 uint8_t __iomem *bios; 93 bus_size_t size = 256 * 1024; /* ??? */ 94 bus_space_handle_t bsh; 95 bus_space_tag_t bst = rdev->memt; 96 97 if (!(rdev->flags & RADEON_IS_IGP)) 98 if (!radeon_card_posted(rdev)) 99 return false; 100 101 rdev->bios = NULL; 102 103 if (bus_space_map(bst, rdev->fb_aper_offset, size, BUS_SPACE_MAP_LINEAR, &bsh) != 0) 104 return false; 105 106 bios = bus_space_vaddr(rdev->memt, bsh); 107 if (bios == NULL) { 108 bus_space_unmap(bst, bsh, size); 109 return false; 110 } 111 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 112 bus_space_unmap(bst, bsh, size); 113 return false; 114 } 115 116 rdev->bios = kmalloc(size, GFP_KERNEL); 117 if (rdev->bios == NULL) { 118 bus_space_unmap(bst, bsh, size); 119 return false; 120 } 121 memcpy_fromio(rdev->bios, bios, size); 122 bus_space_unmap(bst, bsh, size); 123 return true; 124} 125#endif 126 127#ifdef __linux__ 128static bool radeon_read_bios(struct radeon_device *rdev) 129{ 130 uint8_t __iomem *bios, val1, val2; 131 size_t size; 132 133 rdev->bios = NULL; 134 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 135 bios = pci_map_rom(rdev->pdev, &size); 136 if (!bios) { 137 return false; 138 } 139 140 val1 = readb(&bios[0]); 141 val2 = readb(&bios[1]); 142 143 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 144 pci_unmap_rom(rdev->pdev, bios); 145 return false; 146 } 147 rdev->bios = kzalloc(size, GFP_KERNEL); 148 if (rdev->bios == NULL) { 149 pci_unmap_rom(rdev->pdev, bios); 150 return false; 151 } 152 memcpy_fromio(rdev->bios, bios, size); 153 pci_unmap_rom(rdev->pdev, bios); 154 return true; 155} 156#else 157static bool radeon_read_bios(struct radeon_device *rdev) 158{ 159 uint8_t __iomem *bios; 160 bus_size_t size; 161 pcireg_t address, mask; 162 bus_space_handle_t romh; 163 int rc; 164 165 rdev->bios = NULL; 166 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 167 168 address = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG); 169 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 170 mask = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG); 171 address |= PCI_ROM_ENABLE; 172 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, address); 173 174 size = PCI_ROM_SIZE(mask); 175 if (size == 0) 176 return false; 177 rc = bus_space_map(rdev->memt, PCI_ROM_ADDR(address), size, 178 BUS_SPACE_MAP_LINEAR, &romh); 179 if (rc != 0) { 180 printf(": can't map PCI ROM (%d)\n", rc); 181 return false; 182 } 183 bios = (uint8_t *)bus_space_vaddr(rdev->memt, romh); 184 if (!bios) { 185 printf(": bus_space_vaddr failed\n"); 186 return false; 187 } 188 189 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) 190 goto fail; 191 rdev->bios = kmalloc(size, GFP_KERNEL); 192 memcpy(rdev->bios, bios, size); 193 bus_space_unmap(rdev->memt, romh, size); 194 return true; 195fail: 196 bus_space_unmap(rdev->memt, romh, size); 197 return false; 198} 199 200#endif 201 202#ifdef __linux__ 203static bool radeon_read_platform_bios(struct radeon_device *rdev) 204{ 205 phys_addr_t rom = rdev->pdev->rom; 206 size_t romlen = rdev->pdev->romlen; 207 void __iomem *bios; 208 209 rdev->bios = NULL; 210 211 if (!rom || romlen == 0) 212 return false; 213 214 rdev->bios = kzalloc(romlen, GFP_KERNEL); 215 if (!rdev->bios) 216 return false; 217 218 bios = ioremap(rom, romlen); 219 if (!bios) 220 goto free_bios; 221 222 memcpy_fromio(rdev->bios, bios, romlen); 223 iounmap(bios); 224 225 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) 226 goto free_bios; 227 228 return true; 229free_bios: 230 kfree(rdev->bios); 231 return false; 232} 233#else 234static bool radeon_read_platform_bios(struct radeon_device *rdev) 235{ 236#if defined(__amd64__) || defined(__i386__) || defined(__loongson__) 237 uint8_t __iomem *bios; 238 bus_size_t size = 256 * 1024; /* ??? */ 239 uint8_t *found = NULL; 240 int i; 241 242 if (!(rdev->flags & RADEON_IS_IGP)) 243 if (!radeon_card_posted(rdev)) 244 return false; 245 246 rdev->bios = NULL; 247 248#if defined(__loongson__) 249 if (loongson_videobios == NULL) 250 return false; 251 bios = loongson_videobios; 252#else 253 bios = (u8 *)ISA_HOLE_VADDR(0xc0000); 254#endif 255 256 for (i = 0; i + 2 < size; i++) { 257 if (bios[i] == 0x55 && bios[i + 1] == 0xaa) { 258 found = bios + i; 259 break; 260 } 261 262 } 263 if (found == NULL) { 264 DRM_ERROR("bios size zero or checksum mismatch\n"); 265 return false; 266 } 267 268 rdev->bios = kmalloc(size, GFP_KERNEL); 269 if (rdev->bios == NULL) 270 return false; 271 272 memcpy(rdev->bios, found, size); 273 274 return true; 275#endif 276 return false; 277} 278#endif 279 280#ifdef CONFIG_ACPI 281/* ATRM is used to get the BIOS on the discrete cards in 282 * dual-gpu systems. 283 */ 284/* retrieve the ROM in 4k blocks */ 285#define ATRM_BIOS_PAGE 4096 286/** 287 * radeon_atrm_call - fetch a chunk of the vbios 288 * 289 * @atrm_handle: acpi ATRM handle 290 * @bios: vbios image pointer 291 * @offset: offset of vbios image data to fetch 292 * @len: length of vbios image data to fetch 293 * 294 * Executes ATRM to fetch a chunk of the discrete 295 * vbios image on PX systems (all asics). 296 * Returns the length of the buffer fetched. 297 */ 298static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 299 int offset, int len) 300{ 301 acpi_status status; 302 union acpi_object atrm_arg_elements[2], *obj; 303 struct acpi_object_list atrm_arg; 304 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 305 306 atrm_arg.count = 2; 307 atrm_arg.pointer = &atrm_arg_elements[0]; 308 309 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 310 atrm_arg_elements[0].integer.value = offset; 311 312 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 313 atrm_arg_elements[1].integer.value = len; 314 315 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 316 if (ACPI_FAILURE(status)) { 317 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 318 return -ENODEV; 319 } 320 321 obj = (union acpi_object *)buffer.pointer; 322 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 323 len = obj->buffer.length; 324 kfree(buffer.pointer); 325 return len; 326} 327 328static bool radeon_atrm_get_bios(struct radeon_device *rdev) 329{ 330 int ret; 331 int size = 256 * 1024; 332 int i; 333 struct pci_dev *pdev = NULL; 334 acpi_handle dhandle, atrm_handle; 335 acpi_status status; 336 bool found = false; 337 338 /* ATRM is for the discrete card only */ 339 if (rdev->flags & RADEON_IS_IGP) 340 return false; 341 342 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 343 dhandle = ACPI_HANDLE(&pdev->dev); 344 if (!dhandle) 345 continue; 346 347 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 348 if (!ACPI_FAILURE(status)) { 349 found = true; 350 break; 351 } 352 } 353 354 if (!found) { 355 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 356 dhandle = ACPI_HANDLE(&pdev->dev); 357 if (!dhandle) 358 continue; 359 360 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 361 if (!ACPI_FAILURE(status)) { 362 found = true; 363 break; 364 } 365 } 366 } 367 368 if (!found) 369 return false; 370 371 rdev->bios = kmalloc(size, GFP_KERNEL); 372 if (!rdev->bios) { 373 DRM_ERROR("Unable to allocate bios\n"); 374 return false; 375 } 376 377 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 378 ret = radeon_atrm_call(atrm_handle, 379 rdev->bios, 380 (i * ATRM_BIOS_PAGE), 381 ATRM_BIOS_PAGE); 382 if (ret < ATRM_BIOS_PAGE) 383 break; 384 } 385 386 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 387 kfree(rdev->bios); 388 return false; 389 } 390 return true; 391} 392#else 393static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 394{ 395 return false; 396} 397#endif 398 399static bool ni_read_disabled_bios(struct radeon_device *rdev) 400{ 401 u32 bus_cntl; 402 u32 d1vga_control; 403 u32 d2vga_control; 404 u32 vga_render_control; 405 u32 rom_cntl; 406 bool r; 407 408 bus_cntl = RREG32(R600_BUS_CNTL); 409 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 410 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 411 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 412 rom_cntl = RREG32(R600_ROM_CNTL); 413 414 /* enable the rom */ 415 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 416 if (!ASIC_IS_NODCE(rdev)) { 417 /* Disable VGA mode */ 418 WREG32(AVIVO_D1VGA_CONTROL, 419 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 420 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 421 WREG32(AVIVO_D2VGA_CONTROL, 422 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 423 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 424 WREG32(AVIVO_VGA_RENDER_CONTROL, 425 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 426 } 427 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 428 429 r = radeon_read_bios(rdev); 430 431 /* restore regs */ 432 WREG32(R600_BUS_CNTL, bus_cntl); 433 if (!ASIC_IS_NODCE(rdev)) { 434 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 435 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 436 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 437 } 438 WREG32(R600_ROM_CNTL, rom_cntl); 439 return r; 440} 441 442static bool r700_read_disabled_bios(struct radeon_device *rdev) 443{ 444 uint32_t viph_control; 445 uint32_t bus_cntl; 446 uint32_t d1vga_control; 447 uint32_t d2vga_control; 448 uint32_t vga_render_control; 449 uint32_t rom_cntl; 450 uint32_t cg_spll_func_cntl = 0; 451 uint32_t cg_spll_status; 452 bool r; 453 454 viph_control = RREG32(RADEON_VIPH_CONTROL); 455 bus_cntl = RREG32(R600_BUS_CNTL); 456 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 457 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 458 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 459 rom_cntl = RREG32(R600_ROM_CNTL); 460 461 /* disable VIP */ 462 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 463 /* enable the rom */ 464 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 465 /* Disable VGA mode */ 466 WREG32(AVIVO_D1VGA_CONTROL, 467 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 468 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 469 WREG32(AVIVO_D2VGA_CONTROL, 470 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 471 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 472 WREG32(AVIVO_VGA_RENDER_CONTROL, 473 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 474 475 if (rdev->family == CHIP_RV730) { 476 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 477 478 /* enable bypass mode */ 479 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 480 R600_SPLL_BYPASS_EN)); 481 482 /* wait for SPLL_CHG_STATUS to change to 1 */ 483 cg_spll_status = 0; 484 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 485 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 486 487 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 488 } else 489 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 490 491 r = radeon_read_bios(rdev); 492 493 /* restore regs */ 494 if (rdev->family == CHIP_RV730) { 495 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 496 497 /* wait for SPLL_CHG_STATUS to change to 1 */ 498 cg_spll_status = 0; 499 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 500 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 501 } 502 WREG32(RADEON_VIPH_CONTROL, viph_control); 503 WREG32(R600_BUS_CNTL, bus_cntl); 504 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 505 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 506 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 507 WREG32(R600_ROM_CNTL, rom_cntl); 508 return r; 509} 510 511static bool r600_read_disabled_bios(struct radeon_device *rdev) 512{ 513 uint32_t viph_control; 514 uint32_t bus_cntl; 515 uint32_t d1vga_control; 516 uint32_t d2vga_control; 517 uint32_t vga_render_control; 518 uint32_t rom_cntl; 519 uint32_t general_pwrmgt; 520 uint32_t low_vid_lower_gpio_cntl; 521 uint32_t medium_vid_lower_gpio_cntl; 522 uint32_t high_vid_lower_gpio_cntl; 523 uint32_t ctxsw_vid_lower_gpio_cntl; 524 uint32_t lower_gpio_enable; 525 bool r; 526 527 /* 528 * Some machines with RV610 running amd64 pass initial checks but later 529 * fail atombios specific checks. Return early here so the bios will be 530 * read from 0xc0000 in radeon_read_platform_bios() instead. 531 * RV610 0x1002:0x94C3 0x1028:0x0402 0x00 532 * RV610 0x1002:0x94C1 0x1028:0x0D02 0x00 533 */ 534 if (rdev->family == CHIP_RV610) 535 return false; 536 537 viph_control = RREG32(RADEON_VIPH_CONTROL); 538 bus_cntl = RREG32(R600_BUS_CNTL); 539 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 540 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 541 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 542 rom_cntl = RREG32(R600_ROM_CNTL); 543 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 544 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 545 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 546 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 547 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 548 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 549 550 /* disable VIP */ 551 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 552 /* enable the rom */ 553 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 554 /* Disable VGA mode */ 555 WREG32(AVIVO_D1VGA_CONTROL, 556 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 557 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 558 WREG32(AVIVO_D2VGA_CONTROL, 559 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 560 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 561 WREG32(AVIVO_VGA_RENDER_CONTROL, 562 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 563 564 WREG32(R600_ROM_CNTL, 565 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 566 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 567 R600_SCK_OVERWRITE)); 568 569 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 570 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 571 (low_vid_lower_gpio_cntl & ~0x400)); 572 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 573 (medium_vid_lower_gpio_cntl & ~0x400)); 574 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 575 (high_vid_lower_gpio_cntl & ~0x400)); 576 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 577 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 578 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 579 580 r = radeon_read_bios(rdev); 581 582 /* restore regs */ 583 WREG32(RADEON_VIPH_CONTROL, viph_control); 584 WREG32(R600_BUS_CNTL, bus_cntl); 585 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 586 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 587 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 588 WREG32(R600_ROM_CNTL, rom_cntl); 589 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 590 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 591 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 592 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 593 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 594 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 595 return r; 596} 597 598static bool avivo_read_disabled_bios(struct radeon_device *rdev) 599{ 600 uint32_t seprom_cntl1; 601 uint32_t viph_control; 602 uint32_t bus_cntl; 603 uint32_t d1vga_control; 604 uint32_t d2vga_control; 605 uint32_t vga_render_control; 606 uint32_t gpiopad_a; 607 uint32_t gpiopad_en; 608 uint32_t gpiopad_mask; 609 bool r; 610 611 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 612 viph_control = RREG32(RADEON_VIPH_CONTROL); 613 bus_cntl = RREG32(RV370_BUS_CNTL); 614 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 615 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 616 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 617 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 618 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 619 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 620 621 WREG32(RADEON_SEPROM_CNTL1, 622 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 623 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 624 WREG32(RADEON_GPIOPAD_A, 0); 625 WREG32(RADEON_GPIOPAD_EN, 0); 626 WREG32(RADEON_GPIOPAD_MASK, 0); 627 628 /* disable VIP */ 629 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 630 631 /* enable the rom */ 632 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 633 634 /* Disable VGA mode */ 635 WREG32(AVIVO_D1VGA_CONTROL, 636 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 637 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 638 WREG32(AVIVO_D2VGA_CONTROL, 639 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 640 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 641 WREG32(AVIVO_VGA_RENDER_CONTROL, 642 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 643 644 r = radeon_read_bios(rdev); 645 646 /* restore regs */ 647 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 648 WREG32(RADEON_VIPH_CONTROL, viph_control); 649 WREG32(RV370_BUS_CNTL, bus_cntl); 650 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 651 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 652 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 653 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 654 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 655 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 656 return r; 657} 658 659static bool legacy_read_disabled_bios(struct radeon_device *rdev) 660{ 661 uint32_t seprom_cntl1; 662 uint32_t viph_control; 663 uint32_t bus_cntl; 664 uint32_t crtc_gen_cntl; 665 uint32_t crtc2_gen_cntl; 666 uint32_t crtc_ext_cntl; 667 uint32_t fp2_gen_cntl; 668 bool r; 669 670 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 671 viph_control = RREG32(RADEON_VIPH_CONTROL); 672 if (rdev->flags & RADEON_IS_PCIE) 673 bus_cntl = RREG32(RV370_BUS_CNTL); 674 else 675 bus_cntl = RREG32(RADEON_BUS_CNTL); 676 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 677 crtc2_gen_cntl = 0; 678 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 679 fp2_gen_cntl = 0; 680 681 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 682 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 683 } 684 685 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 686 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 687 } 688 689 WREG32(RADEON_SEPROM_CNTL1, 690 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 691 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 692 693 /* disable VIP */ 694 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 695 696 /* enable the rom */ 697 if (rdev->flags & RADEON_IS_PCIE) 698 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 699 else 700 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 701 702 /* Turn off mem requests and CRTC for both controllers */ 703 WREG32(RADEON_CRTC_GEN_CNTL, 704 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 705 (RADEON_CRTC_DISP_REQ_EN_B | 706 RADEON_CRTC_EXT_DISP_EN))); 707 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 708 WREG32(RADEON_CRTC2_GEN_CNTL, 709 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 710 RADEON_CRTC2_DISP_REQ_EN_B)); 711 } 712 /* Turn off CRTC */ 713 WREG32(RADEON_CRTC_EXT_CNTL, 714 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 715 (RADEON_CRTC_SYNC_TRISTAT | 716 RADEON_CRTC_DISPLAY_DIS))); 717 718 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 719 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 720 } 721 722 r = radeon_read_bios(rdev); 723 724 /* restore regs */ 725 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 726 WREG32(RADEON_VIPH_CONTROL, viph_control); 727 if (rdev->flags & RADEON_IS_PCIE) 728 WREG32(RV370_BUS_CNTL, bus_cntl); 729 else 730 WREG32(RADEON_BUS_CNTL, bus_cntl); 731 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 732 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 733 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 734 } 735 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 736 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 737 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 738 } 739 return r; 740} 741 742static bool radeon_read_disabled_bios(struct radeon_device *rdev) 743{ 744 if (rdev->flags & RADEON_IS_IGP) 745 return igp_read_bios_from_vram(rdev); 746 else if (rdev->family >= CHIP_BARTS) 747 return ni_read_disabled_bios(rdev); 748 else if (rdev->family >= CHIP_RV770) 749 return r700_read_disabled_bios(rdev); 750 else if (rdev->family >= CHIP_R600) 751 return r600_read_disabled_bios(rdev); 752 else if (rdev->family >= CHIP_RS600) 753 return avivo_read_disabled_bios(rdev); 754 else 755 return legacy_read_disabled_bios(rdev); 756} 757 758#ifdef CONFIG_ACPI 759static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 760{ 761 struct acpi_table_header *hdr; 762 acpi_size tbl_size; 763 UEFI_ACPI_VFCT *vfct; 764 unsigned offset; 765 766 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr))) 767 return false; 768 tbl_size = hdr->length; 769 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 770 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 771 return false; 772 } 773 774 vfct = (UEFI_ACPI_VFCT *)hdr; 775 offset = vfct->VBIOSImageOffset; 776 777 while (offset < tbl_size) { 778 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset); 779 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader; 780 781 offset += sizeof(VFCT_IMAGE_HEADER); 782 if (offset > tbl_size) { 783 DRM_ERROR("ACPI VFCT image header truncated\n"); 784 return false; 785 } 786 787 offset += vhdr->ImageLength; 788 if (offset > tbl_size) { 789 DRM_ERROR("ACPI VFCT image truncated\n"); 790 return false; 791 } 792 793 if (vhdr->ImageLength && 794 vhdr->PCIBus == rdev->pdev->bus->number && 795 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) && 796 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) && 797 vhdr->VendorID == rdev->pdev->vendor && 798 vhdr->DeviceID == rdev->pdev->device) { 799 rdev->bios = kmemdup(&vbios->VbiosContent, 800 vhdr->ImageLength, 801 GFP_KERNEL); 802 803 if (!rdev->bios) 804 return false; 805 return true; 806 } 807 } 808 809 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 810 return false; 811} 812#else 813static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 814{ 815 return false; 816} 817#endif 818 819bool radeon_get_bios(struct radeon_device *rdev) 820{ 821 bool r; 822 uint16_t tmp; 823 824 r = radeon_atrm_get_bios(rdev); 825 if (!r) 826 r = radeon_acpi_vfct_bios(rdev); 827 if (!r) 828 r = igp_read_bios_from_vram(rdev); 829 if (!r) 830 r = radeon_read_bios(rdev); 831 if (!r) 832 r = radeon_read_disabled_bios(rdev); 833 if (!r) 834 r = radeon_read_platform_bios(rdev); 835 if (!r || rdev->bios == NULL) { 836 DRM_ERROR("Unable to locate a BIOS ROM\n"); 837 rdev->bios = NULL; 838 return false; 839 } 840 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 841 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 842 goto free_bios; 843 } 844 845 tmp = RBIOS16(0x18); 846 if (RBIOS8(tmp + 0x14) != 0x0) { 847 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 848 goto free_bios; 849 } 850 851 rdev->bios_header_start = RBIOS16(0x48); 852 if (!rdev->bios_header_start) { 853 goto free_bios; 854 } 855 tmp = rdev->bios_header_start + 4; 856 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 857 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 858 rdev->is_atom_bios = true; 859 } else { 860 rdev->is_atom_bios = false; 861 } 862 863 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 864 return true; 865free_bios: 866 kfree(rdev->bios); 867 rdev->bios = NULL; 868 return false; 869} 870