radeon_bios.c revision 1.11
1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include <dev/pci/drm/drmP.h> 29#include "radeon_reg.h" 30#include "radeon.h" 31#include "atom.h" 32 33#if defined(__amd64__) || defined(__i386__) 34#include <dev/isa/isareg.h> 35#include <dev/isa/isavar.h> 36#include "acpi.h" 37#endif 38 39#if defined (__loongson__) 40#include <machine/autoconf.h> 41#endif 42 43/* 44 * BIOS. 45 */ 46 47/* If you boot an IGP board with a discrete card as the primary, 48 * the IGP rom is not accessible via the rom bar as the IGP rom is 49 * part of the system bios. On boot, the system bios puts a 50 * copy of the igp rom at the start of vram if a discrete card is 51 * present. 52 */ 53#ifdef __linux__ 54static bool igp_read_bios_from_vram(struct radeon_device *rdev) 55{ 56 uint8_t __iomem *bios; 57 resource_size_t vram_base; 58 resource_size_t size = 256 * 1024; /* ??? */ 59 60 if (!(rdev->flags & RADEON_IS_IGP)) 61 if (!radeon_card_posted(rdev)) 62 return false; 63 64 rdev->bios = NULL; 65 vram_base = pci_resource_start(rdev->pdev, 0); 66 bios = ioremap(vram_base, size); 67 if (!bios) { 68 return false; 69 } 70 71 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 72 iounmap(bios); 73 return false; 74 } 75 rdev->bios = kmalloc(size, GFP_KERNEL); 76 if (rdev->bios == NULL) { 77 iounmap(bios); 78 return false; 79 } 80 memcpy_fromio(rdev->bios, bios, size); 81 iounmap(bios); 82 return true; 83} 84#else 85static bool igp_read_bios_from_vram(struct radeon_device *rdev) 86{ 87 uint8_t __iomem *bios; 88 bus_size_t size = 256 * 1024; /* ??? */ 89 bus_space_handle_t bsh; 90 bus_space_tag_t bst = rdev->memt; 91 92 if (!(rdev->flags & RADEON_IS_IGP)) 93 if (!radeon_card_posted(rdev)) 94 return false; 95 96 rdev->bios = NULL; 97 98 if (bus_space_map(bst, rdev->fb_aper_offset, size, BUS_SPACE_MAP_LINEAR, &bsh) != 0) 99 return false; 100 101 bios = bus_space_vaddr(rdev->memt, bsh); 102 if (bios == NULL) { 103 bus_space_unmap(bst, bsh, size); 104 return false; 105 } 106 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 107 bus_space_unmap(bst, bsh, size); 108 return false; 109 } 110 111 rdev->bios = kmalloc(size, GFP_KERNEL); 112 if (rdev->bios == NULL) { 113 bus_space_unmap(bst, bsh, size); 114 return false; 115 } 116 memcpy_fromio(rdev->bios, bios, size); 117 bus_space_unmap(bst, bsh, size); 118 return true; 119} 120#endif 121 122#ifdef __linux__ 123static bool radeon_read_bios(struct radeon_device *rdev) 124{ 125 uint8_t __iomem *bios, val1, val2; 126 size_t size; 127 128 rdev->bios = NULL; 129 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 130 bios = pci_map_rom(rdev->pdev, &size); 131 if (!bios) { 132 return false; 133 } 134 135 val1 = readb(&bios[0]); 136 val2 = readb(&bios[1]); 137 138 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 139 pci_unmap_rom(rdev->pdev, bios); 140 return false; 141 } 142 rdev->bios = kzalloc(size, GFP_KERNEL); 143 if (rdev->bios == NULL) { 144 pci_unmap_rom(rdev->pdev, bios); 145 return false; 146 } 147 memcpy_fromio(rdev->bios, bios, size); 148 pci_unmap_rom(rdev->pdev, bios); 149 return true; 150} 151#else 152static bool radeon_read_bios(struct radeon_device *rdev) 153{ 154 uint8_t __iomem *bios; 155 bus_size_t size; 156 pcireg_t address, mask; 157 bus_space_handle_t romh; 158 int rc; 159 160 rdev->bios = NULL; 161 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 162 163 address = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG); 164 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 165 mask = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG); 166 address |= PCI_ROM_ENABLE; 167 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, address); 168 169 size = PCI_ROM_SIZE(mask); 170 if (size == 0) 171 return false; 172 rc = bus_space_map(rdev->memt, PCI_ROM_ADDR(address), size, 173 BUS_SPACE_MAP_LINEAR, &romh); 174 if (rc != 0) { 175 printf(": can't map PCI ROM (%d)\n", rc); 176 return false; 177 } 178 bios = (uint8_t *)bus_space_vaddr(rdev->memt, romh); 179 if (!bios) { 180 printf(": bus_space_vaddr failed\n"); 181 return false; 182 } 183 184 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) 185 goto fail; 186 rdev->bios = kmalloc(size, GFP_KERNEL); 187 memcpy(rdev->bios, bios, size); 188 bus_space_unmap(rdev->memt, romh, size); 189 return true; 190fail: 191 bus_space_unmap(rdev->memt, romh, size); 192 return false; 193} 194 195#endif 196 197#ifdef __linux__ 198static bool radeon_read_platform_bios(struct radeon_device *rdev) 199{ 200 uint8_t __iomem *bios; 201 size_t size; 202 203 rdev->bios = NULL; 204 205 bios = pci_platform_rom(rdev->pdev, &size); 206 if (!bios) { 207 return false; 208 } 209 210 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 211 return false; 212 } 213 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 214 if (rdev->bios == NULL) { 215 return false; 216 } 217 218 return true; 219} 220#else 221static bool radeon_read_platform_bios(struct radeon_device *rdev) 222{ 223#if defined(__amd64__) || defined(__i386__) || defined(__loongson__) 224 uint8_t __iomem *bios; 225 bus_size_t size = 256 * 1024; /* ??? */ 226 uint8_t *found = NULL; 227 int i; 228 229 if (!(rdev->flags & RADEON_IS_IGP)) 230 if (!radeon_card_posted(rdev)) 231 return false; 232 233 rdev->bios = NULL; 234 235#if defined(__loongson__) 236 if (loongson_videobios == NULL) 237 return false; 238 bios = loongson_videobios; 239#else 240 bios = (u8 *)ISA_HOLE_VADDR(0xc0000); 241#endif 242 243 for (i = 0; i + 2 < size; i++) { 244 if (bios[i] == 0x55 && bios[i + 1] == 0xaa) { 245 found = bios + i; 246 break; 247 } 248 249 } 250 if (found == NULL) { 251 DRM_ERROR("bios size zero or checksum mismatch\n"); 252 return false; 253 } 254 255 rdev->bios = kmalloc(size, GFP_KERNEL); 256 if (rdev->bios == NULL) 257 return false; 258 259 memcpy(rdev->bios, found, size); 260 261 return true; 262#endif 263 return false; 264} 265#endif 266 267#ifdef CONFIG_ACPI 268/* ATRM is used to get the BIOS on the discrete cards in 269 * dual-gpu systems. 270 */ 271/* retrieve the ROM in 4k blocks */ 272#define ATRM_BIOS_PAGE 4096 273/** 274 * radeon_atrm_call - fetch a chunk of the vbios 275 * 276 * @atrm_handle: acpi ATRM handle 277 * @bios: vbios image pointer 278 * @offset: offset of vbios image data to fetch 279 * @len: length of vbios image data to fetch 280 * 281 * Executes ATRM to fetch a chunk of the discrete 282 * vbios image on PX systems (all asics). 283 * Returns the length of the buffer fetched. 284 */ 285static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 286 int offset, int len) 287{ 288 acpi_status status; 289 union acpi_object atrm_arg_elements[2], *obj; 290 struct acpi_object_list atrm_arg; 291 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 292 293 atrm_arg.count = 2; 294 atrm_arg.pointer = &atrm_arg_elements[0]; 295 296 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 297 atrm_arg_elements[0].integer.value = offset; 298 299 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 300 atrm_arg_elements[1].integer.value = len; 301 302 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 303 if (ACPI_FAILURE(status)) { 304 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 305 return -ENODEV; 306 } 307 308 obj = (union acpi_object *)buffer.pointer; 309 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 310 len = obj->buffer.length; 311 kfree(buffer.pointer); 312 return len; 313} 314 315static bool radeon_atrm_get_bios(struct radeon_device *rdev) 316{ 317 int ret; 318 int size = 256 * 1024; 319 int i; 320 struct pci_dev *pdev = NULL; 321 acpi_handle dhandle, atrm_handle; 322 acpi_status status; 323 bool found = false; 324 325 /* ATRM is for the discrete card only */ 326 if (rdev->flags & RADEON_IS_IGP) 327 return false; 328 329 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 330 dhandle = ACPI_HANDLE(&pdev->dev); 331 if (!dhandle) 332 continue; 333 334 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 335 if (!ACPI_FAILURE(status)) { 336 found = true; 337 break; 338 } 339 } 340 341 if (!found) { 342 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 343 dhandle = ACPI_HANDLE(&pdev->dev); 344 if (!dhandle) 345 continue; 346 347 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 348 if (!ACPI_FAILURE(status)) { 349 found = true; 350 break; 351 } 352 } 353 } 354 355 if (!found) 356 return false; 357 358 rdev->bios = kmalloc(size, GFP_KERNEL); 359 if (!rdev->bios) { 360 DRM_ERROR("Unable to allocate bios\n"); 361 return false; 362 } 363 364 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 365 ret = radeon_atrm_call(atrm_handle, 366 rdev->bios, 367 (i * ATRM_BIOS_PAGE), 368 ATRM_BIOS_PAGE); 369 if (ret < ATRM_BIOS_PAGE) 370 break; 371 } 372 373 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 374 kfree(rdev->bios); 375 return false; 376 } 377 return true; 378} 379#else 380static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 381{ 382 return false; 383} 384#endif 385 386static bool ni_read_disabled_bios(struct radeon_device *rdev) 387{ 388 u32 bus_cntl; 389 u32 d1vga_control; 390 u32 d2vga_control; 391 u32 vga_render_control; 392 u32 rom_cntl; 393 bool r; 394 395 bus_cntl = RREG32(R600_BUS_CNTL); 396 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 397 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 398 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 399 rom_cntl = RREG32(R600_ROM_CNTL); 400 401 /* enable the rom */ 402 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 403 if (!ASIC_IS_NODCE(rdev)) { 404 /* Disable VGA mode */ 405 WREG32(AVIVO_D1VGA_CONTROL, 406 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 407 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 408 WREG32(AVIVO_D2VGA_CONTROL, 409 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 410 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 411 WREG32(AVIVO_VGA_RENDER_CONTROL, 412 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 413 } 414 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 415 416 r = radeon_read_bios(rdev); 417 418 /* restore regs */ 419 WREG32(R600_BUS_CNTL, bus_cntl); 420 if (!ASIC_IS_NODCE(rdev)) { 421 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 422 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 423 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 424 } 425 WREG32(R600_ROM_CNTL, rom_cntl); 426 return r; 427} 428 429static bool r700_read_disabled_bios(struct radeon_device *rdev) 430{ 431 uint32_t viph_control; 432 uint32_t bus_cntl; 433 uint32_t d1vga_control; 434 uint32_t d2vga_control; 435 uint32_t vga_render_control; 436 uint32_t rom_cntl; 437 uint32_t cg_spll_func_cntl = 0; 438 uint32_t cg_spll_status; 439 bool r; 440 441 viph_control = RREG32(RADEON_VIPH_CONTROL); 442 bus_cntl = RREG32(R600_BUS_CNTL); 443 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 444 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 445 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 446 rom_cntl = RREG32(R600_ROM_CNTL); 447 448 /* disable VIP */ 449 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 450 /* enable the rom */ 451 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 452 /* Disable VGA mode */ 453 WREG32(AVIVO_D1VGA_CONTROL, 454 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 455 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 456 WREG32(AVIVO_D2VGA_CONTROL, 457 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 458 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 459 WREG32(AVIVO_VGA_RENDER_CONTROL, 460 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 461 462 if (rdev->family == CHIP_RV730) { 463 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 464 465 /* enable bypass mode */ 466 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 467 R600_SPLL_BYPASS_EN)); 468 469 /* wait for SPLL_CHG_STATUS to change to 1 */ 470 cg_spll_status = 0; 471 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 472 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 473 474 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 475 } else 476 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 477 478 r = radeon_read_bios(rdev); 479 480 /* restore regs */ 481 if (rdev->family == CHIP_RV730) { 482 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 483 484 /* wait for SPLL_CHG_STATUS to change to 1 */ 485 cg_spll_status = 0; 486 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 487 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 488 } 489 WREG32(RADEON_VIPH_CONTROL, viph_control); 490 WREG32(R600_BUS_CNTL, bus_cntl); 491 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 492 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 493 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 494 WREG32(R600_ROM_CNTL, rom_cntl); 495 return r; 496} 497 498static bool r600_read_disabled_bios(struct radeon_device *rdev) 499{ 500 uint32_t viph_control; 501 uint32_t bus_cntl; 502 uint32_t d1vga_control; 503 uint32_t d2vga_control; 504 uint32_t vga_render_control; 505 uint32_t rom_cntl; 506 uint32_t general_pwrmgt; 507 uint32_t low_vid_lower_gpio_cntl; 508 uint32_t medium_vid_lower_gpio_cntl; 509 uint32_t high_vid_lower_gpio_cntl; 510 uint32_t ctxsw_vid_lower_gpio_cntl; 511 uint32_t lower_gpio_enable; 512 bool r; 513 514 viph_control = RREG32(RADEON_VIPH_CONTROL); 515 bus_cntl = RREG32(R600_BUS_CNTL); 516 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 517 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 518 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 519 rom_cntl = RREG32(R600_ROM_CNTL); 520 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 521 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 522 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 523 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 524 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 525 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 526 527 /* disable VIP */ 528 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 529 /* enable the rom */ 530 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 531 /* Disable VGA mode */ 532 WREG32(AVIVO_D1VGA_CONTROL, 533 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 534 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 535 WREG32(AVIVO_D2VGA_CONTROL, 536 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 537 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 538 WREG32(AVIVO_VGA_RENDER_CONTROL, 539 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 540 541 WREG32(R600_ROM_CNTL, 542 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 543 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 544 R600_SCK_OVERWRITE)); 545 546 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 547 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 548 (low_vid_lower_gpio_cntl & ~0x400)); 549 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 550 (medium_vid_lower_gpio_cntl & ~0x400)); 551 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 552 (high_vid_lower_gpio_cntl & ~0x400)); 553 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 554 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 555 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 556 557 r = radeon_read_bios(rdev); 558 559 /* restore regs */ 560 WREG32(RADEON_VIPH_CONTROL, viph_control); 561 WREG32(R600_BUS_CNTL, bus_cntl); 562 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 563 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 564 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 565 WREG32(R600_ROM_CNTL, rom_cntl); 566 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 567 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 568 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 569 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 570 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 571 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 572 return r; 573} 574 575static bool avivo_read_disabled_bios(struct radeon_device *rdev) 576{ 577 uint32_t seprom_cntl1; 578 uint32_t viph_control; 579 uint32_t bus_cntl; 580 uint32_t d1vga_control; 581 uint32_t d2vga_control; 582 uint32_t vga_render_control; 583 uint32_t gpiopad_a; 584 uint32_t gpiopad_en; 585 uint32_t gpiopad_mask; 586 bool r; 587 588 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 589 viph_control = RREG32(RADEON_VIPH_CONTROL); 590 bus_cntl = RREG32(RV370_BUS_CNTL); 591 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 592 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 593 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 594 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 595 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 596 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 597 598 WREG32(RADEON_SEPROM_CNTL1, 599 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 600 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 601 WREG32(RADEON_GPIOPAD_A, 0); 602 WREG32(RADEON_GPIOPAD_EN, 0); 603 WREG32(RADEON_GPIOPAD_MASK, 0); 604 605 /* disable VIP */ 606 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 607 608 /* enable the rom */ 609 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 610 611 /* Disable VGA mode */ 612 WREG32(AVIVO_D1VGA_CONTROL, 613 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 614 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 615 WREG32(AVIVO_D2VGA_CONTROL, 616 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 617 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 618 WREG32(AVIVO_VGA_RENDER_CONTROL, 619 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 620 621 r = radeon_read_bios(rdev); 622 623 /* restore regs */ 624 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 625 WREG32(RADEON_VIPH_CONTROL, viph_control); 626 WREG32(RV370_BUS_CNTL, bus_cntl); 627 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 628 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 629 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 630 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 631 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 632 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 633 return r; 634} 635 636static bool legacy_read_disabled_bios(struct radeon_device *rdev) 637{ 638 uint32_t seprom_cntl1; 639 uint32_t viph_control; 640 uint32_t bus_cntl; 641 uint32_t crtc_gen_cntl; 642 uint32_t crtc2_gen_cntl; 643 uint32_t crtc_ext_cntl; 644 uint32_t fp2_gen_cntl; 645 bool r; 646 647 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 648 viph_control = RREG32(RADEON_VIPH_CONTROL); 649 if (rdev->flags & RADEON_IS_PCIE) 650 bus_cntl = RREG32(RV370_BUS_CNTL); 651 else 652 bus_cntl = RREG32(RADEON_BUS_CNTL); 653 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 654 crtc2_gen_cntl = 0; 655 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 656 fp2_gen_cntl = 0; 657 658 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 659 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 660 } 661 662 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 663 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 664 } 665 666 WREG32(RADEON_SEPROM_CNTL1, 667 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 668 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 669 670 /* disable VIP */ 671 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 672 673 /* enable the rom */ 674 if (rdev->flags & RADEON_IS_PCIE) 675 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 676 else 677 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 678 679 /* Turn off mem requests and CRTC for both controllers */ 680 WREG32(RADEON_CRTC_GEN_CNTL, 681 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 682 (RADEON_CRTC_DISP_REQ_EN_B | 683 RADEON_CRTC_EXT_DISP_EN))); 684 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 685 WREG32(RADEON_CRTC2_GEN_CNTL, 686 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 687 RADEON_CRTC2_DISP_REQ_EN_B)); 688 } 689 /* Turn off CRTC */ 690 WREG32(RADEON_CRTC_EXT_CNTL, 691 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 692 (RADEON_CRTC_SYNC_TRISTAT | 693 RADEON_CRTC_DISPLAY_DIS))); 694 695 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 696 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 697 } 698 699 r = radeon_read_bios(rdev); 700 701 /* restore regs */ 702 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 703 WREG32(RADEON_VIPH_CONTROL, viph_control); 704 if (rdev->flags & RADEON_IS_PCIE) 705 WREG32(RV370_BUS_CNTL, bus_cntl); 706 else 707 WREG32(RADEON_BUS_CNTL, bus_cntl); 708 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 709 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 710 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 711 } 712 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 713 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 714 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 715 } 716 return r; 717} 718 719static bool radeon_read_disabled_bios(struct radeon_device *rdev) 720{ 721 if (rdev->flags & RADEON_IS_IGP) 722 return igp_read_bios_from_vram(rdev); 723 else if (rdev->family >= CHIP_BARTS) 724 return ni_read_disabled_bios(rdev); 725 else if (rdev->family >= CHIP_RV770) 726 return r700_read_disabled_bios(rdev); 727 else if (rdev->family >= CHIP_R600) 728 return r600_read_disabled_bios(rdev); 729 else if (rdev->family >= CHIP_RS600) 730 return avivo_read_disabled_bios(rdev); 731 else 732 return legacy_read_disabled_bios(rdev); 733} 734 735#if NACPI > 0 736#define CONFIG_ACPI 737#endif 738 739#ifdef CONFIG_ACPI 740static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 741{ 742 bool ret = false; 743 struct acpi_table_header *hdr; 744 acpi_size tbl_size; 745 UEFI_ACPI_VFCT *vfct; 746 GOP_VBIOS_CONTENT *vbios; 747 VFCT_IMAGE_HEADER *vhdr; 748 749 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) 750 return false; 751 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 752 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 753 goto out_unmap; 754 } 755 756 vfct = (UEFI_ACPI_VFCT *)hdr; 757 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 758 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 759 goto out_unmap; 760 } 761 762 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 763 vhdr = &vbios->VbiosHeader; 764 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 765 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 766 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 767 768 if (vhdr->PCIBus != rdev->pdev->bus->number || 769 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || 770 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || 771 vhdr->VendorID != rdev->pdev->vendor || 772 vhdr->DeviceID != rdev->pdev->device) { 773 DRM_INFO("ACPI VFCT table is not for this card\n"); 774 goto out_unmap; 775 } 776 777 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 778 DRM_ERROR("ACPI VFCT image truncated\n"); 779 goto out_unmap; 780 } 781 782 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); 783 ret = !!rdev->bios; 784 785out_unmap: 786 return ret; 787} 788#else 789static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 790{ 791 return false; 792} 793#endif 794 795bool radeon_get_bios(struct radeon_device *rdev) 796{ 797 bool r; 798 uint16_t tmp; 799 800 r = radeon_atrm_get_bios(rdev); 801 if (r == false) 802 r = radeon_acpi_vfct_bios(rdev); 803 if (r == false) 804 r = igp_read_bios_from_vram(rdev); 805 if (r == false) 806 r = radeon_read_bios(rdev); 807 if (r == false) 808 r = radeon_read_disabled_bios(rdev); 809 if (r == false) 810 r = radeon_read_platform_bios(rdev); 811 if (r == false || rdev->bios == NULL) { 812 DRM_ERROR("Unable to locate a BIOS ROM\n"); 813 rdev->bios = NULL; 814 return false; 815 } 816 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 817 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 818 goto free_bios; 819 } 820 821 tmp = RBIOS16(0x18); 822 if (RBIOS8(tmp + 0x14) != 0x0) { 823 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 824 goto free_bios; 825 } 826 827 rdev->bios_header_start = RBIOS16(0x48); 828 if (!rdev->bios_header_start) { 829 goto free_bios; 830 } 831 tmp = rdev->bios_header_start + 4; 832 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 833 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 834 rdev->is_atom_bios = true; 835 } else { 836 rdev->is_atom_bios = false; 837 } 838 839 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 840 return true; 841free_bios: 842 kfree(rdev->bios); 843 rdev->bios = NULL; 844 return false; 845} 846