r600d.h revision 1.5
1/* $OpenBSD: r600d.h,v 1.5 2018/04/20 16:09:37 deraadt Exp $ */ 2/* 3 * Copyright 2009 Advanced Micro Devices, Inc. 4 * Copyright 2009 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#ifndef R600D_H 29#define R600D_H 30 31#define CP_PACKET2 0x80000000 32#define PACKET2_PAD_SHIFT 0 33#define PACKET2_PAD_MASK (0x3fffffff << 0) 34 35#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 36 37#define R6XX_MAX_SH_GPRS 256 38#define R6XX_MAX_TEMP_GPRS 16 39#define R6XX_MAX_SH_THREADS 256 40#define R6XX_MAX_SH_STACK_ENTRIES 4096 41#define R6XX_MAX_BACKENDS 8 42#define R6XX_MAX_BACKENDS_MASK 0xff 43#define R6XX_MAX_SIMDS 8 44#define R6XX_MAX_SIMDS_MASK 0xff 45#define R6XX_MAX_PIPES 8 46#define R6XX_MAX_PIPES_MASK 0xff 47 48/* PTE flags */ 49#define PTE_VALID (1 << 0) 50#define PTE_SYSTEM (1 << 1) 51#define PTE_SNOOPED (1 << 2) 52#define PTE_READABLE (1 << 5) 53#define PTE_WRITEABLE (1 << 6) 54 55/* tiling bits */ 56#define ARRAY_LINEAR_GENERAL 0x00000000 57#define ARRAY_LINEAR_ALIGNED 0x00000001 58#define ARRAY_1D_TILED_THIN1 0x00000002 59#define ARRAY_2D_TILED_THIN1 0x00000004 60 61/* Registers */ 62#define ARB_POP 0x2418 63#define ENABLE_TC128 (1 << 30) 64#define ARB_GDEC_RD_CNTL 0x246C 65 66#define CC_GC_SHADER_PIPE_CONFIG 0x8950 67#define CC_RB_BACKEND_DISABLE 0x98F4 68#define BACKEND_DISABLE(x) ((x) << 16) 69 70#define R_028808_CB_COLOR_CONTROL 0x28808 71#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) 72#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) 73#define C_028808_SPECIAL_OP 0xFFFFFF8F 74#define V_028808_SPECIAL_NORMAL 0x00 75#define V_028808_SPECIAL_DISABLE 0x01 76#define V_028808_SPECIAL_RESOLVE_BOX 0x07 77 78#define CB_COLOR0_BASE 0x28040 79#define CB_COLOR1_BASE 0x28044 80#define CB_COLOR2_BASE 0x28048 81#define CB_COLOR3_BASE 0x2804C 82#define CB_COLOR4_BASE 0x28050 83#define CB_COLOR5_BASE 0x28054 84#define CB_COLOR6_BASE 0x28058 85#define CB_COLOR7_BASE 0x2805C 86#define CB_COLOR7_FRAG 0x280FC 87 88#define CB_COLOR0_SIZE 0x28060 89#define CB_COLOR0_VIEW 0x28080 90#define R_028080_CB_COLOR0_VIEW 0x028080 91#define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) 92#define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) 93#define C_028080_SLICE_START 0xFFFFF800 94#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) 95#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 96#define C_028080_SLICE_MAX 0xFF001FFF 97#define R_028084_CB_COLOR1_VIEW 0x028084 98#define R_028088_CB_COLOR2_VIEW 0x028088 99#define R_02808C_CB_COLOR3_VIEW 0x02808C 100#define R_028090_CB_COLOR4_VIEW 0x028090 101#define R_028094_CB_COLOR5_VIEW 0x028094 102#define R_028098_CB_COLOR6_VIEW 0x028098 103#define R_02809C_CB_COLOR7_VIEW 0x02809C 104#define R_028100_CB_COLOR0_MASK 0x028100 105#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) 106#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) 107#define C_028100_CMASK_BLOCK_MAX 0xFFFFF000 108#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) 109#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF) 110#define C_028100_FMASK_TILE_MAX 0x00000FFF 111#define R_028104_CB_COLOR1_MASK 0x028104 112#define R_028108_CB_COLOR2_MASK 0x028108 113#define R_02810C_CB_COLOR3_MASK 0x02810C 114#define R_028110_CB_COLOR4_MASK 0x028110 115#define R_028114_CB_COLOR5_MASK 0x028114 116#define R_028118_CB_COLOR6_MASK 0x028118 117#define R_02811C_CB_COLOR7_MASK 0x02811C 118#define CB_COLOR0_INFO 0x280a0 119# define CB_FORMAT(x) ((x) << 2) 120# define CB_ARRAY_MODE(x) ((x) << 8) 121# define CB_SOURCE_FORMAT(x) ((x) << 27) 122# define CB_SF_EXPORT_FULL 0 123# define CB_SF_EXPORT_NORM 1 124#define CB_COLOR0_TILE 0x280c0 125#define CB_COLOR0_FRAG 0x280e0 126#define CB_COLOR0_MASK 0x28100 127 128#define SQ_ALU_CONST_CACHE_PS_0 0x28940 129#define SQ_ALU_CONST_CACHE_PS_1 0x28944 130#define SQ_ALU_CONST_CACHE_PS_2 0x28948 131#define SQ_ALU_CONST_CACHE_PS_3 0x2894c 132#define SQ_ALU_CONST_CACHE_PS_4 0x28950 133#define SQ_ALU_CONST_CACHE_PS_5 0x28954 134#define SQ_ALU_CONST_CACHE_PS_6 0x28958 135#define SQ_ALU_CONST_CACHE_PS_7 0x2895c 136#define SQ_ALU_CONST_CACHE_PS_8 0x28960 137#define SQ_ALU_CONST_CACHE_PS_9 0x28964 138#define SQ_ALU_CONST_CACHE_PS_10 0x28968 139#define SQ_ALU_CONST_CACHE_PS_11 0x2896c 140#define SQ_ALU_CONST_CACHE_PS_12 0x28970 141#define SQ_ALU_CONST_CACHE_PS_13 0x28974 142#define SQ_ALU_CONST_CACHE_PS_14 0x28978 143#define SQ_ALU_CONST_CACHE_PS_15 0x2897c 144#define SQ_ALU_CONST_CACHE_VS_0 0x28980 145#define SQ_ALU_CONST_CACHE_VS_1 0x28984 146#define SQ_ALU_CONST_CACHE_VS_2 0x28988 147#define SQ_ALU_CONST_CACHE_VS_3 0x2898c 148#define SQ_ALU_CONST_CACHE_VS_4 0x28990 149#define SQ_ALU_CONST_CACHE_VS_5 0x28994 150#define SQ_ALU_CONST_CACHE_VS_6 0x28998 151#define SQ_ALU_CONST_CACHE_VS_7 0x2899c 152#define SQ_ALU_CONST_CACHE_VS_8 0x289a0 153#define SQ_ALU_CONST_CACHE_VS_9 0x289a4 154#define SQ_ALU_CONST_CACHE_VS_10 0x289a8 155#define SQ_ALU_CONST_CACHE_VS_11 0x289ac 156#define SQ_ALU_CONST_CACHE_VS_12 0x289b0 157#define SQ_ALU_CONST_CACHE_VS_13 0x289b4 158#define SQ_ALU_CONST_CACHE_VS_14 0x289b8 159#define SQ_ALU_CONST_CACHE_VS_15 0x289bc 160#define SQ_ALU_CONST_CACHE_GS_0 0x289c0 161#define SQ_ALU_CONST_CACHE_GS_1 0x289c4 162#define SQ_ALU_CONST_CACHE_GS_2 0x289c8 163#define SQ_ALU_CONST_CACHE_GS_3 0x289cc 164#define SQ_ALU_CONST_CACHE_GS_4 0x289d0 165#define SQ_ALU_CONST_CACHE_GS_5 0x289d4 166#define SQ_ALU_CONST_CACHE_GS_6 0x289d8 167#define SQ_ALU_CONST_CACHE_GS_7 0x289dc 168#define SQ_ALU_CONST_CACHE_GS_8 0x289e0 169#define SQ_ALU_CONST_CACHE_GS_9 0x289e4 170#define SQ_ALU_CONST_CACHE_GS_10 0x289e8 171#define SQ_ALU_CONST_CACHE_GS_11 0x289ec 172#define SQ_ALU_CONST_CACHE_GS_12 0x289f0 173#define SQ_ALU_CONST_CACHE_GS_13 0x289f4 174#define SQ_ALU_CONST_CACHE_GS_14 0x289f8 175#define SQ_ALU_CONST_CACHE_GS_15 0x289fc 176 177#define CONFIG_MEMSIZE 0x5428 178#define CONFIG_CNTL 0x5424 179#define CP_STALLED_STAT1 0x8674 180#define CP_STALLED_STAT2 0x8678 181#define CP_BUSY_STAT 0x867C 182#define CP_STAT 0x8680 183#define CP_COHER_BASE 0x85F8 184#define CP_DEBUG 0xC1FC 185#define R_0086D8_CP_ME_CNTL 0x86D8 186#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 187#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 188#define CP_ME_RAM_DATA 0xC160 189#define CP_ME_RAM_RADDR 0xC158 190#define CP_ME_RAM_WADDR 0xC15C 191#define CP_MEQ_THRESHOLDS 0x8764 192#define MEQ_END(x) ((x) << 16) 193#define ROQ_END(x) ((x) << 24) 194#define CP_PERFMON_CNTL 0x87FC 195#define CP_PFP_UCODE_ADDR 0xC150 196#define CP_PFP_UCODE_DATA 0xC154 197#define CP_QUEUE_THRESHOLDS 0x8760 198#define ROQ_IB1_START(x) ((x) << 0) 199#define ROQ_IB2_START(x) ((x) << 8) 200#define CP_RB_BASE 0xC100 201#define CP_RB_CNTL 0xC104 202#define RB_BUFSZ(x) ((x) << 0) 203#define RB_BLKSZ(x) ((x) << 8) 204#define RB_NO_UPDATE (1 << 27) 205#define RB_RPTR_WR_ENA (1 << 31) 206#define BUF_SWAP_32BIT (2 << 16) 207#define CP_RB_RPTR 0x8700 208#define CP_RB_RPTR_ADDR 0xC10C 209#define RB_RPTR_SWAP(x) ((x) << 0) 210#define CP_RB_RPTR_ADDR_HI 0xC110 211#define CP_RB_RPTR_WR 0xC108 212#define CP_RB_WPTR 0xC114 213#define CP_RB_WPTR_ADDR 0xC118 214#define CP_RB_WPTR_ADDR_HI 0xC11C 215#define CP_RB_WPTR_DELAY 0x8704 216#define CP_ROQ_IB1_STAT 0x8784 217#define CP_ROQ_IB2_STAT 0x8788 218#define CP_SEM_WAIT_TIMER 0x85BC 219 220#define DB_DEBUG 0x9830 221#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 222#define DB_DEPTH_BASE 0x2800C 223#define DB_HTILE_DATA_BASE 0x28014 224#define DB_HTILE_SURFACE 0x28D24 225#define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) 226#define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 227#define C_028D24_HTILE_WIDTH 0xFFFFFFFE 228#define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 229#define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 230#define C_028D24_HTILE_HEIGHT 0xFFFFFFFD 231#define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) 232#define DB_WATERMARKS 0x9838 233#define DEPTH_FREE(x) ((x) << 0) 234#define DEPTH_FLUSH(x) ((x) << 5) 235#define DEPTH_PENDING_FREE(x) ((x) << 15) 236#define DEPTH_CACHELINE_FREE(x) ((x) << 20) 237 238#define DCP_TILING_CONFIG 0x6CA0 239#define PIPE_TILING(x) ((x) << 1) 240#define BANK_TILING(x) ((x) << 4) 241#define GROUP_SIZE(x) ((x) << 6) 242#define ROW_TILING(x) ((x) << 8) 243#define BANK_SWAPS(x) ((x) << 11) 244#define SAMPLE_SPLIT(x) ((x) << 14) 245#define BACKEND_MAP(x) ((x) << 16) 246 247#define GB_TILING_CONFIG 0x98F0 248#define PIPE_TILING__SHIFT 1 249#define PIPE_TILING__MASK 0x0000000e 250 251#define GC_USER_SHADER_PIPE_CONFIG 0x8954 252#define INACTIVE_QD_PIPES(x) ((x) << 8) 253#define INACTIVE_QD_PIPES_MASK 0x0000FF00 254#define INACTIVE_SIMDS(x) ((x) << 16) 255#define INACTIVE_SIMDS_MASK 0x00FF0000 256 257#define SQ_CONFIG 0x8c00 258# define VC_ENABLE (1 << 0) 259# define EXPORT_SRC_C (1 << 1) 260# define DX9_CONSTS (1 << 2) 261# define ALU_INST_PREFER_VECTOR (1 << 3) 262# define DX10_CLAMP (1 << 4) 263# define CLAUSE_SEQ_PRIO(x) ((x) << 8) 264# define PS_PRIO(x) ((x) << 24) 265# define VS_PRIO(x) ((x) << 26) 266# define GS_PRIO(x) ((x) << 28) 267# define ES_PRIO(x) ((x) << 30) 268#define SQ_GPR_RESOURCE_MGMT_1 0x8c04 269# define NUM_PS_GPRS(x) ((x) << 0) 270# define NUM_VS_GPRS(x) ((x) << 16) 271# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 272#define SQ_GPR_RESOURCE_MGMT_2 0x8c08 273# define NUM_GS_GPRS(x) ((x) << 0) 274# define NUM_ES_GPRS(x) ((x) << 16) 275#define SQ_THREAD_RESOURCE_MGMT 0x8c0c 276# define NUM_PS_THREADS(x) ((x) << 0) 277# define NUM_VS_THREADS(x) ((x) << 8) 278# define NUM_GS_THREADS(x) ((x) << 16) 279# define NUM_ES_THREADS(x) ((x) << 24) 280#define SQ_STACK_RESOURCE_MGMT_1 0x8c10 281# define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 282# define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 283#define SQ_STACK_RESOURCE_MGMT_2 0x8c14 284# define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 285# define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 286#define SQ_ESGS_RING_BASE 0x8c40 287#define SQ_GSVS_RING_BASE 0x8c48 288#define SQ_ESTMP_RING_BASE 0x8c50 289#define SQ_GSTMP_RING_BASE 0x8c58 290#define SQ_VSTMP_RING_BASE 0x8c60 291#define SQ_PSTMP_RING_BASE 0x8c68 292#define SQ_FBUF_RING_BASE 0x8c70 293#define SQ_REDUC_RING_BASE 0x8c78 294 295#define GRBM_CNTL 0x8000 296# define GRBM_READ_TIMEOUT(x) ((x) << 0) 297#define GRBM_STATUS 0x8010 298#define CMDFIFO_AVAIL_MASK 0x0000001F 299#define GUI_ACTIVE (1<<31) 300#define GRBM_STATUS2 0x8014 301#define GRBM_SOFT_RESET 0x8020 302#define SOFT_RESET_CP (1<<0) 303 304#define CG_THERMAL_STATUS 0x7F4 305#define ASIC_T(x) ((x) << 0) 306#define ASIC_T_MASK 0x1FF 307#define ASIC_T_SHIFT 0 308 309#define HDP_HOST_PATH_CNTL 0x2C00 310#define HDP_NONSURFACE_BASE 0x2C04 311#define HDP_NONSURFACE_INFO 0x2C08 312#define HDP_NONSURFACE_SIZE 0x2C0C 313#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 314#define HDP_TILING_CONFIG 0x2F3C 315#define HDP_DEBUG1 0x2F34 316 317#define MC_VM_AGP_TOP 0x2184 318#define MC_VM_AGP_BOT 0x2188 319#define MC_VM_AGP_BASE 0x218C 320#define MC_VM_FB_LOCATION 0x2180 321#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C 322#define ENABLE_L1_TLB (1 << 0) 323#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 324#define ENABLE_L1_STRICT_ORDERING (1 << 2) 325#define SYSTEM_ACCESS_MODE_MASK 0x000000C0 326#define SYSTEM_ACCESS_MODE_SHIFT 6 327#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 328#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 329#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 330#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 331#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 332#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 333#define ENABLE_SEMAPHORE_MODE (1 << 10) 334#define ENABLE_WAIT_L2_QUERY (1 << 11) 335#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) 336#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 337#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 338#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) 339#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 340#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 341#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 342#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC 343#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 344#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 345#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C 346#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 347#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 348#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 349#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 350#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 351#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C 352#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 353#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 354#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 355#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 356#define LOGICAL_PAGE_NUMBER_SHIFT 0 357#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 358#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 359 360#define PA_CL_ENHANCE 0x8A14 361#define CLIP_VTX_REORDER_ENA (1 << 0) 362#define NUM_CLIP_SEQ(x) ((x) << 1) 363#define PA_SC_AA_CONFIG 0x28C04 364#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 365#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 366#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 367#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C 368#define S0_X(x) ((x) << 0) 369#define S0_Y(x) ((x) << 4) 370#define S1_X(x) ((x) << 8) 371#define S1_Y(x) ((x) << 12) 372#define S2_X(x) ((x) << 16) 373#define S2_Y(x) ((x) << 20) 374#define S3_X(x) ((x) << 24) 375#define S3_Y(x) ((x) << 28) 376#define S4_X(x) ((x) << 0) 377#define S4_Y(x) ((x) << 4) 378#define S5_X(x) ((x) << 8) 379#define S5_Y(x) ((x) << 12) 380#define S6_X(x) ((x) << 16) 381#define S6_Y(x) ((x) << 20) 382#define S7_X(x) ((x) << 24) 383#define S7_Y(x) ((x) << 28) 384#define PA_SC_CLIPRECT_RULE 0x2820c 385#define PA_SC_ENHANCE 0x8BF0 386#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 387#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 388#define PA_SC_LINE_STIPPLE 0x28A0C 389#define PA_SC_LINE_STIPPLE_STATE 0x8B10 390#define PA_SC_MODE_CNTL 0x28A4C 391#define PA_SC_MULTI_CHIP_CNTL 0x8B20 392 393#define PA_SC_SCREEN_SCISSOR_TL 0x28030 394#define PA_SC_GENERIC_SCISSOR_TL 0x28240 395#define PA_SC_WINDOW_SCISSOR_TL 0x28204 396 397#define PCIE_PORT_INDEX 0x0038 398#define PCIE_PORT_DATA 0x003C 399 400#define CHMAP 0x2004 401#define NOOFCHAN_SHIFT 12 402#define NOOFCHAN_MASK 0x00003000 403 404#define RAMCFG 0x2408 405#define NOOFBANK_SHIFT 0 406#define NOOFBANK_MASK 0x00000001 407#define NOOFRANK_SHIFT 1 408#define NOOFRANK_MASK 0x00000002 409#define NOOFROWS_SHIFT 2 410#define NOOFROWS_MASK 0x0000001C 411#define NOOFCOLS_SHIFT 5 412#define NOOFCOLS_MASK 0x00000060 413#define CHANSIZE_SHIFT 7 414#define CHANSIZE_MASK 0x00000080 415#define BURSTLENGTH_SHIFT 8 416#define BURSTLENGTH_MASK 0x00000100 417#define CHANSIZE_OVERRIDE (1 << 10) 418 419#define SCRATCH_REG0 0x8500 420#define SCRATCH_REG1 0x8504 421#define SCRATCH_REG2 0x8508 422#define SCRATCH_REG3 0x850C 423#define SCRATCH_REG4 0x8510 424#define SCRATCH_REG5 0x8514 425#define SCRATCH_REG6 0x8518 426#define SCRATCH_REG7 0x851C 427#define SCRATCH_UMSK 0x8540 428#define SCRATCH_ADDR 0x8544 429 430#define SPI_CONFIG_CNTL 0x9100 431#define GPR_WRITE_PRIORITY(x) ((x) << 0) 432#define DISABLE_INTERP_1 (1 << 5) 433#define SPI_CONFIG_CNTL_1 0x913C 434#define VTX_DONE_DELAY(x) ((x) << 0) 435#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 436#define SPI_INPUT_Z 0x286D8 437#define SPI_PS_IN_CONTROL_0 0x286CC 438#define NUM_INTERP(x) ((x)<<0) 439#define POSITION_ENA (1<<8) 440#define POSITION_CENTROID (1<<9) 441#define POSITION_ADDR(x) ((x)<<10) 442#define PARAM_GEN(x) ((x)<<15) 443#define PARAM_GEN_ADDR(x) ((x)<<19) 444#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 445#define PERSP_GRADIENT_ENA (1<<28) 446#define LINEAR_GRADIENT_ENA (1<<29) 447#define POSITION_SAMPLE (1<<30) 448#define BARYC_AT_SAMPLE_ENA (1<<31) 449#define SPI_PS_IN_CONTROL_1 0x286D0 450#define GEN_INDEX_PIX (1<<0) 451#define GEN_INDEX_PIX_ADDR(x) ((x)<<1) 452#define FRONT_FACE_ENA (1<<8) 453#define FRONT_FACE_CHAN(x) ((x)<<9) 454#define FRONT_FACE_ALL_BITS (1<<11) 455#define FRONT_FACE_ADDR(x) ((x)<<12) 456#define FOG_ADDR(x) ((x)<<17) 457#define FIXED_PT_POSITION_ENA (1<<24) 458#define FIXED_PT_POSITION_ADDR(x) ((x)<<25) 459 460#define SQ_MS_FIFO_SIZES 0x8CF0 461#define CACHE_FIFO_SIZE(x) ((x) << 0) 462#define FETCH_FIFO_HIWATER(x) ((x) << 8) 463#define DONE_FIFO_HIWATER(x) ((x) << 16) 464#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 465#define SQ_PGM_START_ES 0x28880 466#define SQ_PGM_START_FS 0x28894 467#define SQ_PGM_START_GS 0x2886C 468#define SQ_PGM_START_PS 0x28840 469#define SQ_PGM_RESOURCES_PS 0x28850 470#define SQ_PGM_EXPORTS_PS 0x28854 471#define SQ_PGM_CF_OFFSET_PS 0x288cc 472#define SQ_PGM_START_VS 0x28858 473#define SQ_PGM_RESOURCES_VS 0x28868 474#define SQ_PGM_CF_OFFSET_VS 0x288d0 475 476#define SQ_VTX_CONSTANT_WORD0_0 0x30000 477#define SQ_VTX_CONSTANT_WORD1_0 0x30004 478#define SQ_VTX_CONSTANT_WORD2_0 0x30008 479# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 480# define SQ_VTXC_STRIDE(x) ((x) << 8) 481# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 482# define SQ_ENDIAN_NONE 0 483# define SQ_ENDIAN_8IN16 1 484# define SQ_ENDIAN_8IN32 2 485#define SQ_VTX_CONSTANT_WORD3_0 0x3000c 486#define SQ_VTX_CONSTANT_WORD6_0 0x38018 487#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) 488#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) 489#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 490#define SQ_TEX_VTX_INVALID_BUFFER 0x1 491#define SQ_TEX_VTX_VALID_TEXTURE 0x2 492#define SQ_TEX_VTX_VALID_BUFFER 0x3 493 494 495#define SX_MISC 0x28350 496#define SX_MEMORY_EXPORT_BASE 0x9010 497#define SX_DEBUG_1 0x9054 498#define SMX_EVENT_RELEASE (1 << 0) 499#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 500 501#define TA_CNTL_AUX 0x9508 502#define DISABLE_CUBE_WRAP (1 << 0) 503#define DISABLE_CUBE_ANISO (1 << 1) 504#define SYNC_GRADIENT (1 << 24) 505#define SYNC_WALKER (1 << 25) 506#define SYNC_ALIGNER (1 << 26) 507#define BILINEAR_PRECISION_6_BIT (0 << 31) 508#define BILINEAR_PRECISION_8_BIT (1 << 31) 509 510#define TC_CNTL 0x9608 511#define TC_L2_SIZE(x) ((x)<<5) 512#define L2_DISABLE_LATE_HIT (1<<9) 513 514#define VC_ENHANCE 0x9714 515 516#define VGT_CACHE_INVALIDATION 0x88C4 517#define CACHE_INVALIDATION(x) ((x)<<0) 518#define VC_ONLY 0 519#define TC_ONLY 1 520#define VC_AND_TC 2 521#define VGT_DMA_BASE 0x287E8 522#define VGT_DMA_BASE_HI 0x287E4 523#define VGT_ES_PER_GS 0x88CC 524#define VGT_GS_PER_ES 0x88C8 525#define VGT_GS_PER_VS 0x88E8 526#define VGT_GS_VERTEX_REUSE 0x88D4 527#define VGT_PRIMITIVE_TYPE 0x8958 528#define VGT_NUM_INSTANCES 0x8974 529#define VGT_OUT_DEALLOC_CNTL 0x28C5C 530#define DEALLOC_DIST_MASK 0x0000007F 531#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 532#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 533#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 534#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c 535#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 536#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 537#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c 538#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 539#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 540#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 541#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 542#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 543#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC 544#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC 545#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC 546#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C 547#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 548#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 549#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 550#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 551 552#define VGT_STRMOUT_EN 0x28AB0 553#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 554#define VTX_REUSE_DEPTH_MASK 0x000000FF 555#define VGT_EVENT_INITIATOR 0x28a90 556# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 557# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 558 559#define VM_CONTEXT0_CNTL 0x1410 560#define ENABLE_CONTEXT (1 << 0) 561#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 562#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 563#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 564#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 565#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 566#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 567#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 568#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 569#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 570#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 571#define RESPONSE_TYPE_MASK 0x000000F0 572#define RESPONSE_TYPE_SHIFT 4 573#define VM_L2_CNTL 0x1400 574#define ENABLE_L2_CACHE (1 << 0) 575#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 576#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 577#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) 578#define VM_L2_CNTL2 0x1404 579#define INVALIDATE_ALL_L1_TLBS (1 << 0) 580#define INVALIDATE_L2_CACHE (1 << 1) 581#define VM_L2_CNTL3 0x1408 582#define BANK_SELECT_0(x) (((x) & 0x1f) << 0) 583#define BANK_SELECT_1(x) (((x) & 0x1f) << 5) 584#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) 585#define VM_L2_STATUS 0x140C 586#define L2_BUSY (1 << 0) 587 588#define WAIT_UNTIL 0x8040 589#define WAIT_2D_IDLE_bit (1 << 14) 590#define WAIT_3D_IDLE_bit (1 << 15) 591#define WAIT_2D_IDLECLEAN_bit (1 << 16) 592#define WAIT_3D_IDLECLEAN_bit (1 << 17) 593 594/* async DMA */ 595#define DMA_TILING_CONFIG 0x3ec4 596#define DMA_CONFIG 0x3e4c 597 598#define DMA_RB_CNTL 0xd000 599# define DMA_RB_ENABLE (1 << 0) 600# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 601# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 602# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 603# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 604# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 605#define DMA_RB_BASE 0xd004 606#define DMA_RB_RPTR 0xd008 607#define DMA_RB_WPTR 0xd00c 608 609#define DMA_RB_RPTR_ADDR_HI 0xd01c 610#define DMA_RB_RPTR_ADDR_LO 0xd020 611 612#define DMA_IB_CNTL 0xd024 613# define DMA_IB_ENABLE (1 << 0) 614# define DMA_IB_SWAP_ENABLE (1 << 4) 615#define DMA_IB_RPTR 0xd028 616#define DMA_CNTL 0xd02c 617# define TRAP_ENABLE (1 << 0) 618# define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 619# define SEM_WAIT_INT_ENABLE (1 << 2) 620# define DATA_SWAP_ENABLE (1 << 3) 621# define FENCE_SWAP_ENABLE (1 << 4) 622# define CTXEMPTY_INT_ENABLE (1 << 28) 623#define DMA_STATUS_REG 0xd034 624# define DMA_IDLE (1 << 0) 625#define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 626#define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 627#define DMA_MODE 0xd0bc 628 629/* async DMA packets */ 630#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 631 (((t) & 0x1) << 23) | \ 632 (((s) & 0x1) << 22) | \ 633 (((n) & 0xFFFF) << 0)) 634/* async DMA Packet types */ 635#define DMA_PACKET_WRITE 0x2 636#define DMA_PACKET_COPY 0x3 637#define DMA_PACKET_INDIRECT_BUFFER 0x4 638#define DMA_PACKET_SEMAPHORE 0x5 639#define DMA_PACKET_FENCE 0x6 640#define DMA_PACKET_TRAP 0x7 641#define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */ 642#define DMA_PACKET_NOP 0xf 643 644#define IH_RB_CNTL 0x3e00 645# define IH_RB_ENABLE (1 << 0) 646# define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 647# define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 648# define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 649# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 650# define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 651# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 652#define IH_RB_BASE 0x3e04 653#define IH_RB_RPTR 0x3e08 654#define IH_RB_WPTR 0x3e0c 655# define RB_OVERFLOW (1 << 0) 656# define WPTR_OFFSET_MASK 0x3fffc 657#define IH_RB_WPTR_ADDR_HI 0x3e10 658#define IH_RB_WPTR_ADDR_LO 0x3e14 659#define IH_CNTL 0x3e18 660# define ENABLE_INTR (1 << 0) 661# define IH_MC_SWAP(x) ((x) << 1) 662# define IH_MC_SWAP_NONE 0 663# define IH_MC_SWAP_16BIT 1 664# define IH_MC_SWAP_32BIT 2 665# define IH_MC_SWAP_64BIT 3 666# define RPTR_REARM (1 << 4) 667# define MC_WRREQ_CREDIT(x) ((x) << 15) 668# define MC_WR_CLEAN_CNT(x) ((x) << 20) 669 670#define RLC_CNTL 0x3f00 671# define RLC_ENABLE (1 << 0) 672#define RLC_HB_BASE 0x3f10 673#define RLC_HB_CNTL 0x3f0c 674#define RLC_HB_RPTR 0x3f20 675#define RLC_HB_WPTR 0x3f1c 676#define RLC_HB_WPTR_LSB_ADDR 0x3f14 677#define RLC_HB_WPTR_MSB_ADDR 0x3f18 678#define RLC_GPU_CLOCK_COUNT_LSB 0x3f38 679#define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c 680#define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40 681#define RLC_MC_CNTL 0x3f44 682#define RLC_UCODE_CNTL 0x3f48 683#define RLC_UCODE_ADDR 0x3f2c 684#define RLC_UCODE_DATA 0x3f30 685 686/* new for TN */ 687#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 688#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 689 690#define SRBM_SOFT_RESET 0xe60 691# define SOFT_RESET_DMA (1 << 12) 692# define SOFT_RESET_RLC (1 << 13) 693# define RV770_SOFT_RESET_DMA (1 << 20) 694 695#define CP_INT_CNTL 0xc124 696# define CNTX_BUSY_INT_ENABLE (1 << 19) 697# define CNTX_EMPTY_INT_ENABLE (1 << 20) 698# define SCRATCH_INT_ENABLE (1 << 25) 699# define TIME_STAMP_INT_ENABLE (1 << 26) 700# define IB2_INT_ENABLE (1 << 29) 701# define IB1_INT_ENABLE (1 << 30) 702# define RB_INT_ENABLE (1 << 31) 703#define CP_INT_STATUS 0xc128 704# define SCRATCH_INT_STAT (1 << 25) 705# define TIME_STAMP_INT_STAT (1 << 26) 706# define IB2_INT_STAT (1 << 29) 707# define IB1_INT_STAT (1 << 30) 708# define RB_INT_STAT (1 << 31) 709 710#define GRBM_INT_CNTL 0x8060 711# define RDERR_INT_ENABLE (1 << 0) 712# define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) 713# define GUI_IDLE_INT_ENABLE (1 << 19) 714 715#define INTERRUPT_CNTL 0x5468 716# define IH_DUMMY_RD_OVERRIDE (1 << 0) 717# define IH_DUMMY_RD_EN (1 << 1) 718# define IH_REQ_NONSNOOP_EN (1 << 3) 719# define GEN_IH_INT_EN (1 << 8) 720#define INTERRUPT_CNTL2 0x546c 721 722#define D1MODE_VBLANK_STATUS 0x6534 723#define D2MODE_VBLANK_STATUS 0x6d34 724# define DxMODE_VBLANK_OCCURRED (1 << 0) 725# define DxMODE_VBLANK_ACK (1 << 4) 726# define DxMODE_VBLANK_STAT (1 << 12) 727# define DxMODE_VBLANK_INTERRUPT (1 << 16) 728# define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) 729#define D1MODE_VLINE_STATUS 0x653c 730#define D2MODE_VLINE_STATUS 0x6d3c 731# define DxMODE_VLINE_OCCURRED (1 << 0) 732# define DxMODE_VLINE_ACK (1 << 4) 733# define DxMODE_VLINE_STAT (1 << 12) 734# define DxMODE_VLINE_INTERRUPT (1 << 16) 735# define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) 736#define DxMODE_INT_MASK 0x6540 737# define D1MODE_VBLANK_INT_MASK (1 << 0) 738# define D1MODE_VLINE_INT_MASK (1 << 4) 739# define D2MODE_VBLANK_INT_MASK (1 << 8) 740# define D2MODE_VLINE_INT_MASK (1 << 12) 741#define DCE3_DISP_INTERRUPT_STATUS 0x7ddc 742# define DC_HPD1_INTERRUPT (1 << 18) 743# define DC_HPD2_INTERRUPT (1 << 19) 744#define DISP_INTERRUPT_STATUS 0x7edc 745# define LB_D1_VLINE_INTERRUPT (1 << 2) 746# define LB_D2_VLINE_INTERRUPT (1 << 3) 747# define LB_D1_VBLANK_INTERRUPT (1 << 4) 748# define LB_D2_VBLANK_INTERRUPT (1 << 5) 749# define DACA_AUTODETECT_INTERRUPT (1 << 16) 750# define DACB_AUTODETECT_INTERRUPT (1 << 17) 751# define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) 752# define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) 753# define DC_I2C_SW_DONE_INTERRUPT (1 << 20) 754# define DC_I2C_HW_DONE_INTERRUPT (1 << 21) 755#define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 756#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 757# define DC_HPD4_INTERRUPT (1 << 14) 758# define DC_HPD4_RX_INTERRUPT (1 << 15) 759# define DC_HPD3_INTERRUPT (1 << 28) 760# define DC_HPD1_RX_INTERRUPT (1 << 29) 761# define DC_HPD2_RX_INTERRUPT (1 << 30) 762#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec 763# define DC_HPD3_RX_INTERRUPT (1 << 0) 764# define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) 765# define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) 766# define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) 767# define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) 768# define AUX1_SW_DONE_INTERRUPT (1 << 5) 769# define AUX1_LS_DONE_INTERRUPT (1 << 6) 770# define AUX2_SW_DONE_INTERRUPT (1 << 7) 771# define AUX2_LS_DONE_INTERRUPT (1 << 8) 772# define AUX3_SW_DONE_INTERRUPT (1 << 9) 773# define AUX3_LS_DONE_INTERRUPT (1 << 10) 774# define AUX4_SW_DONE_INTERRUPT (1 << 11) 775# define AUX4_LS_DONE_INTERRUPT (1 << 12) 776# define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) 777# define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) 778/* DCE 3.2 */ 779# define AUX5_SW_DONE_INTERRUPT (1 << 15) 780# define AUX5_LS_DONE_INTERRUPT (1 << 16) 781# define AUX6_SW_DONE_INTERRUPT (1 << 17) 782# define AUX6_LS_DONE_INTERRUPT (1 << 18) 783# define DC_HPD5_INTERRUPT (1 << 19) 784# define DC_HPD5_RX_INTERRUPT (1 << 20) 785# define DC_HPD6_INTERRUPT (1 << 21) 786# define DC_HPD6_RX_INTERRUPT (1 << 22) 787 788#define DACA_AUTO_DETECT_CONTROL 0x7828 789#define DACB_AUTO_DETECT_CONTROL 0x7a28 790#define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 791#define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 792# define DACx_AUTODETECT_MODE(x) ((x) << 0) 793# define DACx_AUTODETECT_MODE_NONE 0 794# define DACx_AUTODETECT_MODE_CONNECT 1 795# define DACx_AUTODETECT_MODE_DISCONNECT 2 796# define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) 797/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ 798# define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) 799 800#define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 801#define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 802#define DACA_AUTODETECT_INT_CONTROL 0x7838 803#define DACB_AUTODETECT_INT_CONTROL 0x7a38 804# define DACx_AUTODETECT_ACK (1 << 0) 805# define DACx_AUTODETECT_INT_ENABLE (1 << 16) 806 807#define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 808#define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 809#define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 810# define DC_HOT_PLUG_DETECTx_EN (1 << 0) 811 812#define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 813#define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 814#define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 815# define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) 816# define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) 817 818/* DCE 3.0 */ 819#define DC_HPD1_INT_STATUS 0x7d00 820#define DC_HPD2_INT_STATUS 0x7d0c 821#define DC_HPD3_INT_STATUS 0x7d18 822#define DC_HPD4_INT_STATUS 0x7d24 823/* DCE 3.2 */ 824#define DC_HPD5_INT_STATUS 0x7dc0 825#define DC_HPD6_INT_STATUS 0x7df4 826# define DC_HPDx_INT_STATUS (1 << 0) 827# define DC_HPDx_SENSE (1 << 1) 828# define DC_HPDx_RX_INT_STATUS (1 << 8) 829 830#define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 831#define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 832#define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c 833# define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) 834# define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) 835# define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) 836/* DCE 3.0 */ 837#define DC_HPD1_INT_CONTROL 0x7d04 838#define DC_HPD2_INT_CONTROL 0x7d10 839#define DC_HPD3_INT_CONTROL 0x7d1c 840#define DC_HPD4_INT_CONTROL 0x7d28 841/* DCE 3.2 */ 842#define DC_HPD5_INT_CONTROL 0x7dc4 843#define DC_HPD6_INT_CONTROL 0x7df8 844# define DC_HPDx_INT_ACK (1 << 0) 845# define DC_HPDx_INT_POLARITY (1 << 8) 846# define DC_HPDx_INT_EN (1 << 16) 847# define DC_HPDx_RX_INT_ACK (1 << 20) 848# define DC_HPDx_RX_INT_EN (1 << 24) 849 850/* DCE 3.0 */ 851#define DC_HPD1_CONTROL 0x7d08 852#define DC_HPD2_CONTROL 0x7d14 853#define DC_HPD3_CONTROL 0x7d20 854#define DC_HPD4_CONTROL 0x7d2c 855/* DCE 3.2 */ 856#define DC_HPD5_CONTROL 0x7dc8 857#define DC_HPD6_CONTROL 0x7dfc 858# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 859# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 860/* DCE 3.2 */ 861# define DC_HPDx_EN (1 << 28) 862 863#define D1GRPH_INTERRUPT_STATUS 0x6158 864#define D2GRPH_INTERRUPT_STATUS 0x6958 865# define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) 866# define DxGRPH_PFLIP_INT_CLEAR (1 << 8) 867#define D1GRPH_INTERRUPT_CONTROL 0x615c 868#define D2GRPH_INTERRUPT_CONTROL 0x695c 869# define DxGRPH_PFLIP_INT_MASK (1 << 0) 870# define DxGRPH_PFLIP_INT_TYPE (1 << 8) 871 872/* PCIE link stuff */ 873#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 874# define LC_POINT_7_PLUS_EN (1 << 6) 875#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 876# define LC_LINK_WIDTH_SHIFT 0 877# define LC_LINK_WIDTH_MASK 0x7 878# define LC_LINK_WIDTH_X0 0 879# define LC_LINK_WIDTH_X1 1 880# define LC_LINK_WIDTH_X2 2 881# define LC_LINK_WIDTH_X4 3 882# define LC_LINK_WIDTH_X8 4 883# define LC_LINK_WIDTH_X16 6 884# define LC_LINK_WIDTH_RD_SHIFT 4 885# define LC_LINK_WIDTH_RD_MASK 0x70 886# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 887# define LC_RECONFIG_NOW (1 << 8) 888# define LC_RENEGOTIATION_SUPPORT (1 << 9) 889# define LC_RENEGOTIATE_EN (1 << 10) 890# define LC_SHORT_RECONFIG_EN (1 << 11) 891# define LC_UPCONFIGURE_SUPPORT (1 << 12) 892# define LC_UPCONFIGURE_DIS (1 << 13) 893#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 894# define LC_GEN2_EN_STRAP (1 << 0) 895# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 896# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 897# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 898# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 899# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 900# define LC_CURRENT_DATA_RATE (1 << 11) 901# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 902# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 903# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 904# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 905#define MM_CFGREGS_CNTL 0x544c 906# define MM_WR_TO_CFG_EN (1 << 3) 907#define LINK_CNTL2 0x88 /* F0 */ 908# define TARGET_LINK_SPEED_MASK (0xf << 0) 909# define SELECTABLE_DEEMPHASIS (1 << 6) 910 911/* Audio clocks */ 912#define DCCG_AUDIO_DTO0_PHASE 0x0514 913#define DCCG_AUDIO_DTO0_MODULE 0x0518 914#define DCCG_AUDIO_DTO0_LOAD 0x051c 915# define DTO_LOAD (1 << 31) 916#define DCCG_AUDIO_DTO0_CNTL 0x0520 917 918#define DCCG_AUDIO_DTO1_PHASE 0x0524 919#define DCCG_AUDIO_DTO1_MODULE 0x0528 920#define DCCG_AUDIO_DTO1_LOAD 0x052c 921#define DCCG_AUDIO_DTO1_CNTL 0x0530 922 923#define DCCG_AUDIO_DTO_SELECT 0x0534 924 925/* digital blocks */ 926#define TMDSA_CNTL 0x7880 927# define TMDSA_HDMI_EN (1 << 2) 928#define LVTMA_CNTL 0x7a80 929# define LVTMA_HDMI_EN (1 << 2) 930#define DDIA_CNTL 0x7200 931# define DDIA_HDMI_EN (1 << 2) 932#define DIG0_CNTL 0x75a0 933# define DIG_MODE(x) (((x) & 7) << 8) 934# define DIG_MODE_DP 0 935# define DIG_MODE_LVDS 1 936# define DIG_MODE_TMDS_DVI 2 937# define DIG_MODE_TMDS_HDMI 3 938# define DIG_MODE_SDVO 4 939#define DIG1_CNTL 0x79a0 940 941/* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one 942 * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly 943 * different due to the new DIG blocks, but also have 2 instances. 944 * DCE 3.0 HDMI blocks are part of each DIG encoder. 945 */ 946 947/* rs6xx/rs740/r6xx/dce3 */ 948#define HDMI0_CONTROL 0x7400 949/* rs6xx/rs740/r6xx */ 950# define HDMI0_ENABLE (1 << 0) 951# define HDMI0_STREAM(x) (((x) & 3) << 2) 952# define HDMI0_STREAM_TMDSA 0 953# define HDMI0_STREAM_LVTMA 1 954# define HDMI0_STREAM_DVOA 2 955# define HDMI0_STREAM_DDIA 3 956/* rs6xx/r6xx/dce3 */ 957# define HDMI0_ERROR_ACK (1 << 8) 958# define HDMI0_ERROR_MASK (1 << 9) 959#define HDMI0_STATUS 0x7404 960# define HDMI0_ACTIVE_AVMUTE (1 << 0) 961# define HDMI0_AUDIO_ENABLE (1 << 4) 962# define HDMI0_AZ_FORMAT_WTRIG (1 << 28) 963# define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) 964#define HDMI0_AUDIO_PACKET_CONTROL 0x7408 965# define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) 966# define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 967# define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) 968# define HDMI0_AUDIO_TEST_EN (1 << 12) 969# define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 970# define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) 971# define HDMI0_60958_CS_UPDATE (1 << 26) 972# define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) 973# define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) 974#define HDMI0_AUDIO_CRC_CONTROL 0x740c 975# define HDMI0_AUDIO_CRC_EN (1 << 0) 976#define HDMI0_VBI_PACKET_CONTROL 0x7410 977# define HDMI0_NULL_SEND (1 << 0) 978# define HDMI0_GC_SEND (1 << 4) 979# define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 980#define HDMI0_INFOFRAME_CONTROL0 0x7414 981# define HDMI0_AVI_INFO_SEND (1 << 0) 982# define HDMI0_AVI_INFO_CONT (1 << 1) 983# define HDMI0_AUDIO_INFO_SEND (1 << 4) 984# define HDMI0_AUDIO_INFO_CONT (1 << 5) 985# define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ 986# define HDMI0_AUDIO_INFO_UPDATE (1 << 7) 987# define HDMI0_MPEG_INFO_SEND (1 << 8) 988# define HDMI0_MPEG_INFO_CONT (1 << 9) 989# define HDMI0_MPEG_INFO_UPDATE (1 << 10) 990#define HDMI0_INFOFRAME_CONTROL1 0x7418 991# define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 992# define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 993# define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 994#define HDMI0_GENERIC_PACKET_CONTROL 0x741c 995# define HDMI0_GENERIC0_SEND (1 << 0) 996# define HDMI0_GENERIC0_CONT (1 << 1) 997# define HDMI0_GENERIC0_UPDATE (1 << 2) 998# define HDMI0_GENERIC1_SEND (1 << 4) 999# define HDMI0_GENERIC1_CONT (1 << 5) 1000# define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 1001# define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 1002#define HDMI0_GC 0x7428 1003# define HDMI0_GC_AVMUTE (1 << 0) 1004#define HDMI0_AVI_INFO0 0x7454 1005# define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1006# define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) 1007# define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10) 1008# define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12) 1009# define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13) 1010# define HDMI0_AVI_INFO_Y_RGB 0 1011# define HDMI0_AVI_INFO_Y_YCBCR422 1 1012# define HDMI0_AVI_INFO_Y_YCBCR444 2 1013# define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 1014# define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16) 1015# define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20) 1016# define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22) 1017# define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 1018# define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24) 1019# define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 1020#define HDMI0_AVI_INFO1 0x7458 1021# define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 1022# define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 1023# define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 1024#define HDMI0_AVI_INFO2 0x745c 1025# define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 1026# define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 1027#define HDMI0_AVI_INFO3 0x7460 1028# define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 1029# define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24) 1030#define HDMI0_MPEG_INFO0 0x7464 1031# define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1032# define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 1033# define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 1034# define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 1035#define HDMI0_MPEG_INFO1 0x7468 1036# define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 1037# define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8) 1038# define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12) 1039#define HDMI0_GENERIC0_HDR 0x746c 1040#define HDMI0_GENERIC0_0 0x7470 1041#define HDMI0_GENERIC0_1 0x7474 1042#define HDMI0_GENERIC0_2 0x7478 1043#define HDMI0_GENERIC0_3 0x747c 1044#define HDMI0_GENERIC0_4 0x7480 1045#define HDMI0_GENERIC0_5 0x7484 1046#define HDMI0_GENERIC0_6 0x7488 1047#define HDMI0_GENERIC1_HDR 0x748c 1048#define HDMI0_GENERIC1_0 0x7490 1049#define HDMI0_GENERIC1_1 0x7494 1050#define HDMI0_GENERIC1_2 0x7498 1051#define HDMI0_GENERIC1_3 0x749c 1052#define HDMI0_GENERIC1_4 0x74a0 1053#define HDMI0_GENERIC1_5 0x74a4 1054#define HDMI0_GENERIC1_6 0x74a8 1055#define HDMI0_ACR_32_0 0x74ac 1056# define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 1057#define HDMI0_ACR_32_1 0x74b0 1058# define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) 1059#define HDMI0_ACR_44_0 0x74b4 1060# define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 1061#define HDMI0_ACR_44_1 0x74b8 1062# define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) 1063#define HDMI0_ACR_48_0 0x74bc 1064# define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 1065#define HDMI0_ACR_48_1 0x74c0 1066# define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) 1067#define HDMI0_ACR_STATUS_0 0x74c4 1068#define HDMI0_ACR_STATUS_1 0x74c8 1069#define HDMI0_AUDIO_INFO0 0x74cc 1070# define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1071# define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) 1072#define HDMI0_AUDIO_INFO1 0x74d0 1073# define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 1074# define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 1075# define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 1076# define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 1077#define HDMI0_60958_0 0x74d4 1078# define HDMI0_60958_CS_A(x) (((x) & 1) << 0) 1079# define HDMI0_60958_CS_B(x) (((x) & 1) << 1) 1080# define HDMI0_60958_CS_C(x) (((x) & 1) << 2) 1081# define HDMI0_60958_CS_D(x) (((x) & 3) << 3) 1082# define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) 1083# define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 1084# define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 1085# define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 1086# define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 1087# define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 1088#define HDMI0_60958_1 0x74d8 1089# define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 1090# define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 1091# define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) 1092# define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) 1093# define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 1094#define HDMI0_ACR_PACKET_CONTROL 0x74dc 1095# define HDMI0_ACR_SEND (1 << 0) 1096# define HDMI0_ACR_CONT (1 << 1) 1097# define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) 1098# define HDMI0_ACR_HW 0 1099# define HDMI0_ACR_32 1 1100# define HDMI0_ACR_44 2 1101# define HDMI0_ACR_48 3 1102# define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 1103# define HDMI0_ACR_AUTO_SEND (1 << 12) 1104#define HDMI0_RAMP_CONTROL0 0x74e0 1105# define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 1106#define HDMI0_RAMP_CONTROL1 0x74e4 1107# define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 1108#define HDMI0_RAMP_CONTROL2 0x74e8 1109# define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 1110#define HDMI0_RAMP_CONTROL3 0x74ec 1111# define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 1112/* HDMI0_60958_2 is r7xx only */ 1113#define HDMI0_60958_2 0x74f0 1114# define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 1115# define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 1116# define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 1117# define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 1118# define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 1119# define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 1120/* r6xx only; second instance starts at 0x7700 */ 1121#define HDMI1_CONTROL 0x7700 1122#define HDMI1_STATUS 0x7704 1123#define HDMI1_AUDIO_PACKET_CONTROL 0x7708 1124/* DCE3; second instance starts at 0x7800 NOT 0x7700 */ 1125#define DCE3_HDMI1_CONTROL 0x7800 1126#define DCE3_HDMI1_STATUS 0x7804 1127#define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808 1128/* DCE3.2 (for interrupts) */ 1129#define AFMT_STATUS 0x7600 1130# define AFMT_AUDIO_ENABLE (1 << 4) 1131# define AFMT_AZ_FORMAT_WTRIG (1 << 28) 1132# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 1133# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 1134#define AFMT_AUDIO_PACKET_CONTROL 0x7604 1135# define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 1136# define AFMT_AUDIO_TEST_EN (1 << 12) 1137# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 1138# define AFMT_60958_CS_UPDATE (1 << 26) 1139# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 1140# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 1141# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 1142# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 1143 1144/* 1145 * PM4 1146 */ 1147#define PACKET_TYPE0 0 1148#define PACKET_TYPE1 1 1149#define PACKET_TYPE2 2 1150#define PACKET_TYPE3 3 1151 1152#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 1153#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 1154#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 1155#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 1156#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 1157 (((reg) >> 2) & 0xFFFF) | \ 1158 ((n) & 0x3FFF) << 16) 1159#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1160 (((op) & 0xFF) << 8) | \ 1161 ((n) & 0x3FFF) << 16) 1162 1163/* Packet 3 types */ 1164#define PACKET3_NOP 0x10 1165#define PACKET3_INDIRECT_BUFFER_END 0x17 1166#define PACKET3_SET_PREDICATION 0x20 1167#define PACKET3_REG_RMW 0x21 1168#define PACKET3_COND_EXEC 0x22 1169#define PACKET3_PRED_EXEC 0x23 1170#define PACKET3_START_3D_CMDBUF 0x24 1171#define PACKET3_DRAW_INDEX_2 0x27 1172#define PACKET3_CONTEXT_CONTROL 0x28 1173#define PACKET3_DRAW_INDEX_IMMD_BE 0x29 1174#define PACKET3_INDEX_TYPE 0x2A 1175#define PACKET3_DRAW_INDEX 0x2B 1176#define PACKET3_DRAW_INDEX_AUTO 0x2D 1177#define PACKET3_DRAW_INDEX_IMMD 0x2E 1178#define PACKET3_NUM_INSTANCES 0x2F 1179#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1180#define PACKET3_INDIRECT_BUFFER_MP 0x38 1181#define PACKET3_MEM_SEMAPHORE 0x39 1182# define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 1183# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 1184# define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1185#define PACKET3_MPEG_INDEX 0x3A 1186#define PACKET3_COPY_DW 0x3B 1187#define PACKET3_WAIT_REG_MEM 0x3C 1188#define PACKET3_MEM_WRITE 0x3D 1189#define PACKET3_INDIRECT_BUFFER 0x32 1190#define PACKET3_CP_DMA 0x41 1191/* 1. header 1192 * 2. SRC_ADDR_LO [31:0] 1193 * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0] 1194 * 4. DST_ADDR_LO [31:0] 1195 * 5. DST_ADDR_HI [7:0] 1196 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1197 */ 1198# define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1199/* COMMAND */ 1200# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1201 /* 0 - none 1202 * 1 - 8 in 16 1203 * 2 - 8 in 32 1204 * 3 - 8 in 64 1205 */ 1206# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1207 /* 0 - none 1208 * 1 - 8 in 16 1209 * 2 - 8 in 32 1210 * 3 - 8 in 64 1211 */ 1212# define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1213 /* 0 - memory 1214 * 1 - register 1215 */ 1216# define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1217 /* 0 - memory 1218 * 1 - register 1219 */ 1220# define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1221# define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1222#define PACKET3_SURFACE_SYNC 0x43 1223# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1224# define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */ 1225# define PACKET3_TC_ACTION_ENA (1 << 23) 1226# define PACKET3_VC_ACTION_ENA (1 << 24) 1227# define PACKET3_CB_ACTION_ENA (1 << 25) 1228# define PACKET3_DB_ACTION_ENA (1 << 26) 1229# define PACKET3_SH_ACTION_ENA (1 << 27) 1230# define PACKET3_SMX_ACTION_ENA (1 << 28) 1231#define PACKET3_ME_INITIALIZE 0x44 1232#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1233#define PACKET3_COND_WRITE 0x45 1234#define PACKET3_EVENT_WRITE 0x46 1235#define EVENT_TYPE(x) ((x) << 0) 1236#define EVENT_INDEX(x) ((x) << 8) 1237 /* 0 - any non-TS event 1238 * 1 - ZPASS_DONE 1239 * 2 - SAMPLE_PIPELINESTAT 1240 * 3 - SAMPLE_STREAMOUTSTAT* 1241 * 4 - *S_PARTIAL_FLUSH 1242 * 5 - TS events 1243 */ 1244#define PACKET3_EVENT_WRITE_EOP 0x47 1245#define DATA_SEL(x) ((x) << 29) 1246 /* 0 - discard 1247 * 1 - send low 32bit data 1248 * 2 - send 64bit data 1249 * 3 - send 64bit counter value 1250 */ 1251#define INT_SEL(x) ((x) << 24) 1252 /* 0 - none 1253 * 1 - interrupt only (DATA_SEL = 0) 1254 * 2 - interrupt when data write is confirmed 1255 */ 1256#define PACKET3_ONE_REG_WRITE 0x57 1257#define PACKET3_SET_CONFIG_REG 0x68 1258#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 1259#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1260#define PACKET3_SET_CONTEXT_REG 0x69 1261#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 1262#define PACKET3_SET_CONTEXT_REG_END 0x00029000 1263#define PACKET3_SET_ALU_CONST 0x6A 1264#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 1265#define PACKET3_SET_ALU_CONST_END 0x00032000 1266#define PACKET3_SET_BOOL_CONST 0x6B 1267#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 1268#define PACKET3_SET_BOOL_CONST_END 0x00040000 1269#define PACKET3_SET_LOOP_CONST 0x6C 1270#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 1271#define PACKET3_SET_LOOP_CONST_END 0x0003e380 1272#define PACKET3_SET_RESOURCE 0x6D 1273#define PACKET3_SET_RESOURCE_OFFSET 0x00038000 1274#define PACKET3_SET_RESOURCE_END 0x0003c000 1275#define PACKET3_SET_SAMPLER 0x6E 1276#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 1277#define PACKET3_SET_SAMPLER_END 0x0003cff0 1278#define PACKET3_SET_CTL_CONST 0x6F 1279#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 1280#define PACKET3_SET_CTL_CONST_END 0x0003e200 1281#define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */ 1282#define PACKET3_SURFACE_BASE_UPDATE 0x73 1283 1284 1285#define R_008020_GRBM_SOFT_RESET 0x8020 1286#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) 1287#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) 1288#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) 1289#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) 1290#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) 1291#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) 1292#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) 1293#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) 1294#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) 1295#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) 1296#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) 1297#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) 1298#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) 1299#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) 1300#define R_008010_GRBM_STATUS 0x8010 1301#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) 1302#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) 1303#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) 1304#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) 1305#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) 1306#define S_008010_VC_BUSY(x) (((x) & 1) << 11) 1307#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) 1308#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) 1309#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) 1310#define S_008010_VGT_BUSY(x) (((x) & 1) << 17) 1311#define S_008010_TA03_BUSY(x) (((x) & 1) << 18) 1312#define S_008010_TC_BUSY(x) (((x) & 1) << 19) 1313#define S_008010_SX_BUSY(x) (((x) & 1) << 20) 1314#define S_008010_SH_BUSY(x) (((x) & 1) << 21) 1315#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) 1316#define S_008010_SMX_BUSY(x) (((x) & 1) << 23) 1317#define S_008010_SC_BUSY(x) (((x) & 1) << 24) 1318#define S_008010_PA_BUSY(x) (((x) & 1) << 25) 1319#define S_008010_DB03_BUSY(x) (((x) & 1) << 26) 1320#define S_008010_CR_BUSY(x) (((x) & 1) << 27) 1321#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) 1322#define S_008010_CP_BUSY(x) (((x) & 1) << 29) 1323#define S_008010_CB03_BUSY(x) (((x) & 1) << 30) 1324#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) 1325#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) 1326#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) 1327#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) 1328#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) 1329#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) 1330#define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 1331#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 1332#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 1333#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 1334#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 1335#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 1336#define G_008010_TC_BUSY(x) (((x) >> 19) & 1) 1337#define G_008010_SX_BUSY(x) (((x) >> 20) & 1) 1338#define G_008010_SH_BUSY(x) (((x) >> 21) & 1) 1339#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) 1340#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) 1341#define G_008010_SC_BUSY(x) (((x) >> 24) & 1) 1342#define G_008010_PA_BUSY(x) (((x) >> 25) & 1) 1343#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) 1344#define G_008010_CR_BUSY(x) (((x) >> 27) & 1) 1345#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) 1346#define G_008010_CP_BUSY(x) (((x) >> 29) & 1) 1347#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) 1348#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) 1349#define R_008014_GRBM_STATUS2 0x8014 1350#define S_008014_CR_CLEAN(x) (((x) & 1) << 0) 1351#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) 1352#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) 1353#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) 1354#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) 1355#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) 1356#define S_008014_TA0_BUSY(x) (((x) & 1) << 12) 1357#define S_008014_TA1_BUSY(x) (((x) & 1) << 13) 1358#define S_008014_TA2_BUSY(x) (((x) & 1) << 14) 1359#define S_008014_TA3_BUSY(x) (((x) & 1) << 15) 1360#define S_008014_DB0_BUSY(x) (((x) & 1) << 16) 1361#define S_008014_DB1_BUSY(x) (((x) & 1) << 17) 1362#define S_008014_DB2_BUSY(x) (((x) & 1) << 18) 1363#define S_008014_DB3_BUSY(x) (((x) & 1) << 19) 1364#define S_008014_CB0_BUSY(x) (((x) & 1) << 20) 1365#define S_008014_CB1_BUSY(x) (((x) & 1) << 21) 1366#define S_008014_CB2_BUSY(x) (((x) & 1) << 22) 1367#define S_008014_CB3_BUSY(x) (((x) & 1) << 23) 1368#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) 1369#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) 1370#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) 1371#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) 1372#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) 1373#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) 1374#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) 1375#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) 1376#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) 1377#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) 1378#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) 1379#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) 1380#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) 1381#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) 1382#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) 1383#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) 1384#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) 1385#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) 1386#define R_000E50_SRBM_STATUS 0x0E50 1387#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) 1388#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) 1389#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) 1390#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) 1391#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) 1392#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) 1393#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) 1394#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) 1395#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) 1396#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) 1397#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 1398#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 1399#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 1400#define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 1401#define R_000E60_SRBM_SOFT_RESET 0x0E60 1402#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 1403#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) 1404#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) 1405#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) 1406#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) 1407#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) 1408#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) 1409#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) 1410#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) 1411#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) 1412#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) 1413#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) 1414#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) 1415#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 1416 1417#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 1418 1419#define R_028C04_PA_SC_AA_CONFIG 0x028C04 1420#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) 1421#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) 1422#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC 1423#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) 1424#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) 1425#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF 1426#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) 1427#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) 1428#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF 1429#define R_0280E0_CB_COLOR0_FRAG 0x0280E0 1430#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1431#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1432#define C_0280E0_BASE_256B 0x00000000 1433#define R_0280E4_CB_COLOR1_FRAG 0x0280E4 1434#define R_0280E8_CB_COLOR2_FRAG 0x0280E8 1435#define R_0280EC_CB_COLOR3_FRAG 0x0280EC 1436#define R_0280F0_CB_COLOR4_FRAG 0x0280F0 1437#define R_0280F4_CB_COLOR5_FRAG 0x0280F4 1438#define R_0280F8_CB_COLOR6_FRAG 0x0280F8 1439#define R_0280FC_CB_COLOR7_FRAG 0x0280FC 1440#define R_0280C0_CB_COLOR0_TILE 0x0280C0 1441#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1442#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1443#define C_0280C0_BASE_256B 0x00000000 1444#define R_0280C4_CB_COLOR1_TILE 0x0280C4 1445#define R_0280C8_CB_COLOR2_TILE 0x0280C8 1446#define R_0280CC_CB_COLOR3_TILE 0x0280CC 1447#define R_0280D0_CB_COLOR4_TILE 0x0280D0 1448#define R_0280D4_CB_COLOR5_TILE 0x0280D4 1449#define R_0280D8_CB_COLOR6_TILE 0x0280D8 1450#define R_0280DC_CB_COLOR7_TILE 0x0280DC 1451#define R_0280A0_CB_COLOR0_INFO 0x0280A0 1452#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) 1453#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) 1454#define C_0280A0_ENDIAN 0xFFFFFFFC 1455#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) 1456#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) 1457#define C_0280A0_FORMAT 0xFFFFFF03 1458#define V_0280A0_COLOR_INVALID 0x00000000 1459#define V_0280A0_COLOR_8 0x00000001 1460#define V_0280A0_COLOR_4_4 0x00000002 1461#define V_0280A0_COLOR_3_3_2 0x00000003 1462#define V_0280A0_COLOR_16 0x00000005 1463#define V_0280A0_COLOR_16_FLOAT 0x00000006 1464#define V_0280A0_COLOR_8_8 0x00000007 1465#define V_0280A0_COLOR_5_6_5 0x00000008 1466#define V_0280A0_COLOR_6_5_5 0x00000009 1467#define V_0280A0_COLOR_1_5_5_5 0x0000000A 1468#define V_0280A0_COLOR_4_4_4_4 0x0000000B 1469#define V_0280A0_COLOR_5_5_5_1 0x0000000C 1470#define V_0280A0_COLOR_32 0x0000000D 1471#define V_0280A0_COLOR_32_FLOAT 0x0000000E 1472#define V_0280A0_COLOR_16_16 0x0000000F 1473#define V_0280A0_COLOR_16_16_FLOAT 0x00000010 1474#define V_0280A0_COLOR_8_24 0x00000011 1475#define V_0280A0_COLOR_8_24_FLOAT 0x00000012 1476#define V_0280A0_COLOR_24_8 0x00000013 1477#define V_0280A0_COLOR_24_8_FLOAT 0x00000014 1478#define V_0280A0_COLOR_10_11_11 0x00000015 1479#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 1480#define V_0280A0_COLOR_11_11_10 0x00000017 1481#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 1482#define V_0280A0_COLOR_2_10_10_10 0x00000019 1483#define V_0280A0_COLOR_8_8_8_8 0x0000001A 1484#define V_0280A0_COLOR_10_10_10_2 0x0000001B 1485#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C 1486#define V_0280A0_COLOR_32_32 0x0000001D 1487#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E 1488#define V_0280A0_COLOR_16_16_16_16 0x0000001F 1489#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 1490#define V_0280A0_COLOR_32_32_32_32 0x00000022 1491#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 1492#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) 1493#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1494#define C_0280A0_ARRAY_MODE 0xFFFFF0FF 1495#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 1496#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 1497#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 1498#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 1499#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1500#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1501#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF 1502#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) 1503#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) 1504#define C_0280A0_READ_SIZE 0xFFFF7FFF 1505#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) 1506#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) 1507#define C_0280A0_COMP_SWAP 0xFFFCFFFF 1508#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1509#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1510#define C_0280A0_TILE_MODE 0xFFF3FFFF 1511#define V_0280A0_TILE_DISABLE 0 1512#define V_0280A0_CLEAR_ENABLE 1 1513#define V_0280A0_FRAG_ENABLE 2 1514#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1515#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1516#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1517#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) 1518#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) 1519#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF 1520#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) 1521#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) 1522#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF 1523#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) 1524#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) 1525#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF 1526#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) 1527#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) 1528#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF 1529#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) 1530#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) 1531#define C_0280A0_ROUND_MODE 0xFDFFFFFF 1532#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) 1533#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1534#define C_0280A0_TILE_COMPACT 0xFBFFFFFF 1535#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) 1536#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) 1537#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF 1538#define R_0280A4_CB_COLOR1_INFO 0x0280A4 1539#define R_0280A8_CB_COLOR2_INFO 0x0280A8 1540#define R_0280AC_CB_COLOR3_INFO 0x0280AC 1541#define R_0280B0_CB_COLOR4_INFO 0x0280B0 1542#define R_0280B4_CB_COLOR5_INFO 0x0280B4 1543#define R_0280B8_CB_COLOR6_INFO 0x0280B8 1544#define R_0280BC_CB_COLOR7_INFO 0x0280BC 1545#define R_028060_CB_COLOR0_SIZE 0x028060 1546#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1547#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1548#define C_028060_PITCH_TILE_MAX 0xFFFFFC00 1549#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1550#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1551#define C_028060_SLICE_TILE_MAX 0xC00003FF 1552#define R_028064_CB_COLOR1_SIZE 0x028064 1553#define R_028068_CB_COLOR2_SIZE 0x028068 1554#define R_02806C_CB_COLOR3_SIZE 0x02806C 1555#define R_028070_CB_COLOR4_SIZE 0x028070 1556#define R_028074_CB_COLOR5_SIZE 0x028074 1557#define R_028078_CB_COLOR6_SIZE 0x028078 1558#define R_02807C_CB_COLOR7_SIZE 0x02807C 1559#define R_028238_CB_TARGET_MASK 0x028238 1560#define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) 1561#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) 1562#define C_028238_TARGET0_ENABLE 0xFFFFFFF0 1563#define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) 1564#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) 1565#define C_028238_TARGET1_ENABLE 0xFFFFFF0F 1566#define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) 1567#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) 1568#define C_028238_TARGET2_ENABLE 0xFFFFF0FF 1569#define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) 1570#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) 1571#define C_028238_TARGET3_ENABLE 0xFFFF0FFF 1572#define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) 1573#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) 1574#define C_028238_TARGET4_ENABLE 0xFFF0FFFF 1575#define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) 1576#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) 1577#define C_028238_TARGET5_ENABLE 0xFF0FFFFF 1578#define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) 1579#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) 1580#define C_028238_TARGET6_ENABLE 0xF0FFFFFF 1581#define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) 1582#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) 1583#define C_028238_TARGET7_ENABLE 0x0FFFFFFF 1584#define R_02823C_CB_SHADER_MASK 0x02823C 1585#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) 1586#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) 1587#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 1588#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) 1589#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) 1590#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F 1591#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) 1592#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) 1593#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF 1594#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) 1595#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) 1596#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF 1597#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) 1598#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) 1599#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF 1600#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) 1601#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) 1602#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF 1603#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) 1604#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) 1605#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF 1606#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) 1607#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) 1608#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF 1609#define R_028AB0_VGT_STRMOUT_EN 0x028AB0 1610#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) 1611#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) 1612#define C_028AB0_STREAMOUT 0xFFFFFFFE 1613#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 1614#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) 1615#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) 1616#define C_028B20_BUFFER_0_EN 0xFFFFFFFE 1617#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) 1618#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) 1619#define C_028B20_BUFFER_1_EN 0xFFFFFFFD 1620#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) 1621#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) 1622#define C_028B20_BUFFER_2_EN 0xFFFFFFFB 1623#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) 1624#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) 1625#define C_028B20_BUFFER_3_EN 0xFFFFFFF7 1626#define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1627#define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1628#define C_028B20_SIZE 0x00000000 1629#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 1630#define S_038000_DIM(x) (((x) & 0x7) << 0) 1631#define G_038000_DIM(x) (((x) >> 0) & 0x7) 1632#define C_038000_DIM 0xFFFFFFF8 1633#define V_038000_SQ_TEX_DIM_1D 0x00000000 1634#define V_038000_SQ_TEX_DIM_2D 0x00000001 1635#define V_038000_SQ_TEX_DIM_3D 0x00000002 1636#define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 1637#define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1638#define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1639#define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 1640#define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1641#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) 1642#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) 1643#define C_038000_TILE_MODE 0xFFFFFF87 1644#define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 1645#define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 1646#define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 1647#define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 1648#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) 1649#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) 1650#define C_038000_TILE_TYPE 0xFFFFFF7F 1651#define S_038000_PITCH(x) (((x) & 0x7FF) << 8) 1652#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) 1653#define C_038000_PITCH 0xFFF800FF 1654#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) 1655#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) 1656#define C_038000_TEX_WIDTH 0x0007FFFF 1657#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 1658#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) 1659#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) 1660#define C_038004_TEX_HEIGHT 0xFFFFE000 1661#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) 1662#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) 1663#define C_038004_TEX_DEPTH 0xFC001FFF 1664#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) 1665#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) 1666#define C_038004_DATA_FORMAT 0x03FFFFFF 1667#define V_038004_COLOR_INVALID 0x00000000 1668#define V_038004_COLOR_8 0x00000001 1669#define V_038004_COLOR_4_4 0x00000002 1670#define V_038004_COLOR_3_3_2 0x00000003 1671#define V_038004_COLOR_16 0x00000005 1672#define V_038004_COLOR_16_FLOAT 0x00000006 1673#define V_038004_COLOR_8_8 0x00000007 1674#define V_038004_COLOR_5_6_5 0x00000008 1675#define V_038004_COLOR_6_5_5 0x00000009 1676#define V_038004_COLOR_1_5_5_5 0x0000000A 1677#define V_038004_COLOR_4_4_4_4 0x0000000B 1678#define V_038004_COLOR_5_5_5_1 0x0000000C 1679#define V_038004_COLOR_32 0x0000000D 1680#define V_038004_COLOR_32_FLOAT 0x0000000E 1681#define V_038004_COLOR_16_16 0x0000000F 1682#define V_038004_COLOR_16_16_FLOAT 0x00000010 1683#define V_038004_COLOR_8_24 0x00000011 1684#define V_038004_COLOR_8_24_FLOAT 0x00000012 1685#define V_038004_COLOR_24_8 0x00000013 1686#define V_038004_COLOR_24_8_FLOAT 0x00000014 1687#define V_038004_COLOR_10_11_11 0x00000015 1688#define V_038004_COLOR_10_11_11_FLOAT 0x00000016 1689#define V_038004_COLOR_11_11_10 0x00000017 1690#define V_038004_COLOR_11_11_10_FLOAT 0x00000018 1691#define V_038004_COLOR_2_10_10_10 0x00000019 1692#define V_038004_COLOR_8_8_8_8 0x0000001A 1693#define V_038004_COLOR_10_10_10_2 0x0000001B 1694#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C 1695#define V_038004_COLOR_32_32 0x0000001D 1696#define V_038004_COLOR_32_32_FLOAT 0x0000001E 1697#define V_038004_COLOR_16_16_16_16 0x0000001F 1698#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 1699#define V_038004_COLOR_32_32_32_32 0x00000022 1700#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 1701#define V_038004_FMT_1 0x00000025 1702#define V_038004_FMT_GB_GR 0x00000027 1703#define V_038004_FMT_BG_RG 0x00000028 1704#define V_038004_FMT_32_AS_8 0x00000029 1705#define V_038004_FMT_32_AS_8_8 0x0000002A 1706#define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B 1707#define V_038004_FMT_8_8_8 0x0000002C 1708#define V_038004_FMT_16_16_16 0x0000002D 1709#define V_038004_FMT_16_16_16_FLOAT 0x0000002E 1710#define V_038004_FMT_32_32_32 0x0000002F 1711#define V_038004_FMT_32_32_32_FLOAT 0x00000030 1712#define V_038004_FMT_BC1 0x00000031 1713#define V_038004_FMT_BC2 0x00000032 1714#define V_038004_FMT_BC3 0x00000033 1715#define V_038004_FMT_BC4 0x00000034 1716#define V_038004_FMT_BC5 0x00000035 1717#define V_038004_FMT_BC6 0x00000036 1718#define V_038004_FMT_BC7 0x00000037 1719#define V_038004_FMT_32_AS_32_32_32_32 0x00000038 1720#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 1721#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1722#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1723#define C_038010_FORMAT_COMP_X 0xFFFFFFFC 1724#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1725#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1726#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 1727#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1728#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1729#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF 1730#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1731#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1732#define C_038010_FORMAT_COMP_W 0xFFFFFF3F 1733#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1734#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1735#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF 1736#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1737#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1738#define C_038010_SRF_MODE_ALL 0xFFFFFBFF 1739#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1740#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1741#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF 1742#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1743#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1744#define C_038010_ENDIAN_SWAP 0xFFFFCFFF 1745#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) 1746#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) 1747#define C_038010_REQUEST_SIZE 0xFFFF3FFF 1748#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) 1749#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1750#define C_038010_DST_SEL_X 0xFFF8FFFF 1751#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1752#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1753#define C_038010_DST_SEL_Y 0xFFC7FFFF 1754#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1755#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1756#define C_038010_DST_SEL_Z 0xFE3FFFFF 1757#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) 1758#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1759#define C_038010_DST_SEL_W 0xF1FFFFFF 1760# define SQ_SEL_X 0 1761# define SQ_SEL_Y 1 1762# define SQ_SEL_Z 2 1763# define SQ_SEL_W 3 1764# define SQ_SEL_0 4 1765# define SQ_SEL_1 5 1766#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1767#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1768#define C_038010_BASE_LEVEL 0x0FFFFFFF 1769#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 1770#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1771#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1772#define C_038014_LAST_LEVEL 0xFFFFFFF0 1773#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1774#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1775#define C_038014_BASE_ARRAY 0xFFFE000F 1776#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1777#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1778#define C_038014_LAST_ARRAY 0xC001FFFF 1779#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 1780#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1781#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1782#define C_0288A8_ITEMSIZE 0xFFFF8000 1783#define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 1784#define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1785#define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1786#define C_008C44_MEM_SIZE 0x00000000 1787#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 1788#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1789#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1790#define C_0288B0_ITEMSIZE 0xFFFF8000 1791#define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 1792#define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1793#define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1794#define C_008C54_MEM_SIZE 0x00000000 1795#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 1796#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1797#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1798#define C_0288C0_ITEMSIZE 0xFFFF8000 1799#define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 1800#define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1801#define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1802#define C_008C74_MEM_SIZE 0x00000000 1803#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 1804#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1805#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1806#define C_0288B4_ITEMSIZE 0xFFFF8000 1807#define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C 1808#define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1809#define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1810#define C_008C5C_MEM_SIZE 0x00000000 1811#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC 1812#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1813#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1814#define C_0288AC_ITEMSIZE 0xFFFF8000 1815#define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C 1816#define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1817#define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1818#define C_008C4C_MEM_SIZE 0x00000000 1819#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC 1820#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1821#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1822#define C_0288BC_ITEMSIZE 0xFFFF8000 1823#define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C 1824#define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1825#define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1826#define C_008C6C_MEM_SIZE 0x00000000 1827#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 1828#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1829#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1830#define C_0288C4_ITEMSIZE 0xFFFF8000 1831#define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C 1832#define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1833#define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1834#define C_008C7C_MEM_SIZE 0x00000000 1835#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 1836#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1837#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1838#define C_0288B8_ITEMSIZE 0xFFFF8000 1839#define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 1840#define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1841#define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1842#define C_008C64_MEM_SIZE 0x00000000 1843#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 1844#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1845#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1846#define C_0288C8_ITEMSIZE 0xFFFF8000 1847#define R_028010_DB_DEPTH_INFO 0x028010 1848#define S_028010_FORMAT(x) (((x) & 0x7) << 0) 1849#define G_028010_FORMAT(x) (((x) >> 0) & 0x7) 1850#define C_028010_FORMAT 0xFFFFFFF8 1851#define V_028010_DEPTH_INVALID 0x00000000 1852#define V_028010_DEPTH_16 0x00000001 1853#define V_028010_DEPTH_X8_24 0x00000002 1854#define V_028010_DEPTH_8_24 0x00000003 1855#define V_028010_DEPTH_X8_24_FLOAT 0x00000004 1856#define V_028010_DEPTH_8_24_FLOAT 0x00000005 1857#define V_028010_DEPTH_32_FLOAT 0x00000006 1858#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 1859#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) 1860#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) 1861#define C_028010_READ_SIZE 0xFFFFFFF7 1862#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) 1863#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) 1864#define C_028010_ARRAY_MODE 0xFFF87FFF 1865#define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 1866#define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 1867#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) 1868#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) 1869#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF 1870#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) 1871#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1872#define C_028010_TILE_COMPACT 0xFBFFFFFF 1873#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1874#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1875#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF 1876#define R_028000_DB_DEPTH_SIZE 0x028000 1877#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1878#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1879#define C_028000_PITCH_TILE_MAX 0xFFFFFC00 1880#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1881#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1882#define C_028000_SLICE_TILE_MAX 0xC00003FF 1883#define R_028004_DB_DEPTH_VIEW 0x028004 1884#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) 1885#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) 1886#define C_028004_SLICE_START 0xFFFFF800 1887#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1888#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1889#define C_028004_SLICE_MAX 0xFF001FFF 1890#define R_028800_DB_DEPTH_CONTROL 0x028800 1891#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1892#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1893#define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1894#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1895#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1896#define C_028800_Z_ENABLE 0xFFFFFFFD 1897#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1898#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1899#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1900#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1901#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1902#define C_028800_ZFUNC 0xFFFFFF8F 1903#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1904#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1905#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1906#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1907#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1908#define C_028800_STENCILFUNC 0xFFFFF8FF 1909#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1910#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1911#define C_028800_STENCILFAIL 0xFFFFC7FF 1912#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1913#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1914#define C_028800_STENCILZPASS 0xFFFE3FFF 1915#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1916#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1917#define C_028800_STENCILZFAIL 0xFFF1FFFF 1918#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1919#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1920#define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1921#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1922#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1923#define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1924#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1925#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1926#define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1927#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1928#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1929#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1930 1931#endif 1932