i915_pci.c revision 1.19
1/* 2 * Copyright �� 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25#include <drm/drm_color_mgmt.h> 26#include <drm/drm_drv.h> 27#include <drm/i915_pciids.h> 28 29#include "gt/intel_gt_regs.h" 30#include "gt/intel_sa_media.h" 31 32#include "i915_driver.h" 33#include "i915_drv.h" 34#include "i915_pci.h" 35#include "i915_reg.h" 36#include "intel_pci_config.h" 37 38#define PLATFORM(x) .platform = (x) 39#define GEN(x) \ 40 .__runtime.graphics.ip.ver = (x), \ 41 .__runtime.media.ip.ver = (x), \ 42 .__runtime.display.ip.ver = (x) 43 44#define NO_DISPLAY .__runtime.pipe_mask = 0 45 46#define I845_PIPE_OFFSETS \ 47 .display.pipe_offsets = { \ 48 [TRANSCODER_A] = PIPE_A_OFFSET, \ 49 }, \ 50 .display.trans_offsets = { \ 51 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 52 } 53 54#define I9XX_PIPE_OFFSETS \ 55 .display.pipe_offsets = { \ 56 [TRANSCODER_A] = PIPE_A_OFFSET, \ 57 [TRANSCODER_B] = PIPE_B_OFFSET, \ 58 }, \ 59 .display.trans_offsets = { \ 60 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 61 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 62 } 63 64#define IVB_PIPE_OFFSETS \ 65 .display.pipe_offsets = { \ 66 [TRANSCODER_A] = PIPE_A_OFFSET, \ 67 [TRANSCODER_B] = PIPE_B_OFFSET, \ 68 [TRANSCODER_C] = PIPE_C_OFFSET, \ 69 }, \ 70 .display.trans_offsets = { \ 71 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 72 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 73 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 74 } 75 76#define HSW_PIPE_OFFSETS \ 77 .display.pipe_offsets = { \ 78 [TRANSCODER_A] = PIPE_A_OFFSET, \ 79 [TRANSCODER_B] = PIPE_B_OFFSET, \ 80 [TRANSCODER_C] = PIPE_C_OFFSET, \ 81 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 82 }, \ 83 .display.trans_offsets = { \ 84 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 85 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 86 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 87 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 88 } 89 90#define CHV_PIPE_OFFSETS \ 91 .display.pipe_offsets = { \ 92 [TRANSCODER_A] = PIPE_A_OFFSET, \ 93 [TRANSCODER_B] = PIPE_B_OFFSET, \ 94 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 95 }, \ 96 .display.trans_offsets = { \ 97 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 98 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 99 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 100 } 101 102#define I845_CURSOR_OFFSETS \ 103 .display.cursor_offsets = { \ 104 [PIPE_A] = CURSOR_A_OFFSET, \ 105 } 106 107#define I9XX_CURSOR_OFFSETS \ 108 .display.cursor_offsets = { \ 109 [PIPE_A] = CURSOR_A_OFFSET, \ 110 [PIPE_B] = CURSOR_B_OFFSET, \ 111 } 112 113#define CHV_CURSOR_OFFSETS \ 114 .display.cursor_offsets = { \ 115 [PIPE_A] = CURSOR_A_OFFSET, \ 116 [PIPE_B] = CURSOR_B_OFFSET, \ 117 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 118 } 119 120#define IVB_CURSOR_OFFSETS \ 121 .display.cursor_offsets = { \ 122 [PIPE_A] = CURSOR_A_OFFSET, \ 123 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 124 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 125 } 126 127#define TGL_CURSOR_OFFSETS \ 128 .display.cursor_offsets = { \ 129 [PIPE_A] = CURSOR_A_OFFSET, \ 130 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 131 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 132 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 133 } 134 135#define I9XX_COLORS \ 136 .display.color = { .gamma_lut_size = 256 } 137#define I965_COLORS \ 138 .display.color = { .gamma_lut_size = 129, \ 139 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 140 } 141#define ILK_COLORS \ 142 .display.color = { .gamma_lut_size = 1024 } 143#define IVB_COLORS \ 144 .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 145#define CHV_COLORS \ 146 .display.color = { \ 147 .degamma_lut_size = 65, .gamma_lut_size = 257, \ 148 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 149 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 150 } 151#define GLK_COLORS \ 152 .display.color = { \ 153 .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 154 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 155 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 156 } 157#define ICL_COLORS \ 158 .display.color = { \ 159 .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 160 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 161 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 162 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 163 } 164 165/* Keep in gen based order, and chronological order within a gen */ 166 167#define GEN_DEFAULT_PAGE_SIZES \ 168 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K 169 170#define GEN_DEFAULT_REGIONS \ 171 .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM 172 173#define I830_FEATURES \ 174 GEN(2), \ 175 .is_mobile = 1, \ 176 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 177 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 178 .display.has_overlay = 1, \ 179 .display.cursor_needs_physical = 1, \ 180 .display.overlay_needs_physical = 1, \ 181 .display.has_gmch = 1, \ 182 .gpu_reset_clobbers_display = true, \ 183 .has_3d_pipeline = 1, \ 184 .hws_needs_physical = 1, \ 185 .unfenced_needs_alignment = 1, \ 186 .__runtime.platform_engine_mask = BIT(RCS0), \ 187 .has_snoop = true, \ 188 .has_coherent_ggtt = false, \ 189 .dma_mask_size = 32, \ 190 I9XX_PIPE_OFFSETS, \ 191 I9XX_CURSOR_OFFSETS, \ 192 I9XX_COLORS, \ 193 GEN_DEFAULT_PAGE_SIZES, \ 194 GEN_DEFAULT_REGIONS 195 196#define I845_FEATURES \ 197 GEN(2), \ 198 .__runtime.pipe_mask = BIT(PIPE_A), \ 199 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \ 200 .display.has_overlay = 1, \ 201 .display.overlay_needs_physical = 1, \ 202 .display.has_gmch = 1, \ 203 .has_3d_pipeline = 1, \ 204 .gpu_reset_clobbers_display = true, \ 205 .hws_needs_physical = 1, \ 206 .unfenced_needs_alignment = 1, \ 207 .__runtime.platform_engine_mask = BIT(RCS0), \ 208 .has_snoop = true, \ 209 .has_coherent_ggtt = false, \ 210 .dma_mask_size = 32, \ 211 I845_PIPE_OFFSETS, \ 212 I845_CURSOR_OFFSETS, \ 213 I9XX_COLORS, \ 214 GEN_DEFAULT_PAGE_SIZES, \ 215 GEN_DEFAULT_REGIONS 216 217static const struct intel_device_info i830_info = { 218 I830_FEATURES, 219 PLATFORM(INTEL_I830), 220}; 221 222static const struct intel_device_info i845g_info = { 223 I845_FEATURES, 224 PLATFORM(INTEL_I845G), 225}; 226 227static const struct intel_device_info i85x_info = { 228 I830_FEATURES, 229 PLATFORM(INTEL_I85X), 230 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 231}; 232 233static const struct intel_device_info i865g_info = { 234 I845_FEATURES, 235 PLATFORM(INTEL_I865G), 236 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 237}; 238 239#define GEN3_FEATURES \ 240 GEN(3), \ 241 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 242 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 243 .display.has_gmch = 1, \ 244 .gpu_reset_clobbers_display = true, \ 245 .__runtime.platform_engine_mask = BIT(RCS0), \ 246 .has_3d_pipeline = 1, \ 247 .has_snoop = true, \ 248 .has_coherent_ggtt = true, \ 249 .dma_mask_size = 32, \ 250 I9XX_PIPE_OFFSETS, \ 251 I9XX_CURSOR_OFFSETS, \ 252 I9XX_COLORS, \ 253 GEN_DEFAULT_PAGE_SIZES, \ 254 GEN_DEFAULT_REGIONS 255 256static const struct intel_device_info i915g_info = { 257 GEN3_FEATURES, 258 PLATFORM(INTEL_I915G), 259 .has_coherent_ggtt = false, 260 .display.cursor_needs_physical = 1, 261 .display.has_overlay = 1, 262 .display.overlay_needs_physical = 1, 263 .hws_needs_physical = 1, 264 .unfenced_needs_alignment = 1, 265}; 266 267static const struct intel_device_info i915gm_info = { 268 GEN3_FEATURES, 269 PLATFORM(INTEL_I915GM), 270 .is_mobile = 1, 271 .display.cursor_needs_physical = 1, 272 .display.has_overlay = 1, 273 .display.overlay_needs_physical = 1, 274 .display.supports_tv = 1, 275 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 276 .hws_needs_physical = 1, 277 .unfenced_needs_alignment = 1, 278}; 279 280static const struct intel_device_info i945g_info = { 281 GEN3_FEATURES, 282 PLATFORM(INTEL_I945G), 283 .display.has_hotplug = 1, 284 .display.cursor_needs_physical = 1, 285 .display.has_overlay = 1, 286 .display.overlay_needs_physical = 1, 287 .hws_needs_physical = 1, 288 .unfenced_needs_alignment = 1, 289}; 290 291static const struct intel_device_info i945gm_info = { 292 GEN3_FEATURES, 293 PLATFORM(INTEL_I945GM), 294 .is_mobile = 1, 295 .display.has_hotplug = 1, 296 .display.cursor_needs_physical = 1, 297 .display.has_overlay = 1, 298 .display.overlay_needs_physical = 1, 299 .display.supports_tv = 1, 300 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 301 .hws_needs_physical = 1, 302 .unfenced_needs_alignment = 1, 303}; 304 305static const struct intel_device_info g33_info = { 306 GEN3_FEATURES, 307 PLATFORM(INTEL_G33), 308 .display.has_hotplug = 1, 309 .display.has_overlay = 1, 310 .dma_mask_size = 36, 311}; 312 313static const struct intel_device_info pnv_g_info = { 314 GEN3_FEATURES, 315 PLATFORM(INTEL_PINEVIEW), 316 .display.has_hotplug = 1, 317 .display.has_overlay = 1, 318 .dma_mask_size = 36, 319}; 320 321static const struct intel_device_info pnv_m_info = { 322 GEN3_FEATURES, 323 PLATFORM(INTEL_PINEVIEW), 324 .is_mobile = 1, 325 .display.has_hotplug = 1, 326 .display.has_overlay = 1, 327 .dma_mask_size = 36, 328}; 329 330#define GEN4_FEATURES \ 331 GEN(4), \ 332 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 333 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 334 .display.has_hotplug = 1, \ 335 .display.has_gmch = 1, \ 336 .gpu_reset_clobbers_display = true, \ 337 .__runtime.platform_engine_mask = BIT(RCS0), \ 338 .has_3d_pipeline = 1, \ 339 .has_snoop = true, \ 340 .has_coherent_ggtt = true, \ 341 .dma_mask_size = 36, \ 342 I9XX_PIPE_OFFSETS, \ 343 I9XX_CURSOR_OFFSETS, \ 344 I965_COLORS, \ 345 GEN_DEFAULT_PAGE_SIZES, \ 346 GEN_DEFAULT_REGIONS 347 348static const struct intel_device_info i965g_info = { 349 GEN4_FEATURES, 350 PLATFORM(INTEL_I965G), 351 .display.has_overlay = 1, 352 .hws_needs_physical = 1, 353 .has_snoop = false, 354}; 355 356static const struct intel_device_info i965gm_info = { 357 GEN4_FEATURES, 358 PLATFORM(INTEL_I965GM), 359 .is_mobile = 1, 360 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 361 .display.has_overlay = 1, 362 .display.supports_tv = 1, 363 .hws_needs_physical = 1, 364 .has_snoop = false, 365}; 366 367static const struct intel_device_info g45_info = { 368 GEN4_FEATURES, 369 PLATFORM(INTEL_G45), 370 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), 371 .gpu_reset_clobbers_display = false, 372}; 373 374static const struct intel_device_info gm45_info = { 375 GEN4_FEATURES, 376 PLATFORM(INTEL_GM45), 377 .is_mobile = 1, 378 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 379 .display.supports_tv = 1, 380 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), 381 .gpu_reset_clobbers_display = false, 382}; 383 384#define GEN5_FEATURES \ 385 GEN(5), \ 386 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 387 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 388 .display.has_hotplug = 1, \ 389 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 390 .has_3d_pipeline = 1, \ 391 .has_snoop = true, \ 392 .has_coherent_ggtt = true, \ 393 /* ilk does support rc6, but we do not implement [power] contexts */ \ 394 .has_rc6 = 0, \ 395 .dma_mask_size = 36, \ 396 I9XX_PIPE_OFFSETS, \ 397 I9XX_CURSOR_OFFSETS, \ 398 ILK_COLORS, \ 399 GEN_DEFAULT_PAGE_SIZES, \ 400 GEN_DEFAULT_REGIONS 401 402static const struct intel_device_info ilk_d_info = { 403 GEN5_FEATURES, 404 PLATFORM(INTEL_IRONLAKE), 405}; 406 407static const struct intel_device_info ilk_m_info = { 408 GEN5_FEATURES, 409 PLATFORM(INTEL_IRONLAKE), 410 .is_mobile = 1, 411 .has_rps = true, 412 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 413}; 414 415#define GEN6_FEATURES \ 416 GEN(6), \ 417 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 418 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 419 .display.has_hotplug = 1, \ 420 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 421 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 422 .has_3d_pipeline = 1, \ 423 .has_coherent_ggtt = true, \ 424 .has_llc = 1, \ 425 .has_rc6 = 1, \ 426 /* snb does support rc6p, but enabling it causes various issues */ \ 427 .has_rc6p = 0, \ 428 .has_rps = true, \ 429 .dma_mask_size = 40, \ 430 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 431 .__runtime.ppgtt_size = 31, \ 432 I9XX_PIPE_OFFSETS, \ 433 I9XX_CURSOR_OFFSETS, \ 434 ILK_COLORS, \ 435 GEN_DEFAULT_PAGE_SIZES, \ 436 GEN_DEFAULT_REGIONS 437 438#define SNB_D_PLATFORM \ 439 GEN6_FEATURES, \ 440 PLATFORM(INTEL_SANDYBRIDGE) 441 442static const struct intel_device_info snb_d_gt1_info = { 443 SNB_D_PLATFORM, 444 .gt = 1, 445}; 446 447static const struct intel_device_info snb_d_gt2_info = { 448 SNB_D_PLATFORM, 449 .gt = 2, 450}; 451 452#define SNB_M_PLATFORM \ 453 GEN6_FEATURES, \ 454 PLATFORM(INTEL_SANDYBRIDGE), \ 455 .is_mobile = 1 456 457 458static const struct intel_device_info snb_m_gt1_info = { 459 SNB_M_PLATFORM, 460 .gt = 1, 461}; 462 463static const struct intel_device_info snb_m_gt2_info = { 464 SNB_M_PLATFORM, 465 .gt = 2, 466}; 467 468#define GEN7_FEATURES \ 469 GEN(7), \ 470 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 471 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ 472 .display.has_hotplug = 1, \ 473 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 474 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 475 .has_3d_pipeline = 1, \ 476 .has_coherent_ggtt = true, \ 477 .has_llc = 1, \ 478 .has_rc6 = 1, \ 479 .has_rc6p = 1, \ 480 .has_reset_engine = true, \ 481 .has_rps = true, \ 482 .dma_mask_size = 40, \ 483 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 484 .__runtime.ppgtt_size = 31, \ 485 IVB_PIPE_OFFSETS, \ 486 IVB_CURSOR_OFFSETS, \ 487 IVB_COLORS, \ 488 GEN_DEFAULT_PAGE_SIZES, \ 489 GEN_DEFAULT_REGIONS 490 491#define IVB_D_PLATFORM \ 492 GEN7_FEATURES, \ 493 PLATFORM(INTEL_IVYBRIDGE), \ 494 .has_l3_dpf = 1 495 496static const struct intel_device_info ivb_d_gt1_info = { 497 IVB_D_PLATFORM, 498 .gt = 1, 499}; 500 501static const struct intel_device_info ivb_d_gt2_info = { 502 IVB_D_PLATFORM, 503 .gt = 2, 504}; 505 506#define IVB_M_PLATFORM \ 507 GEN7_FEATURES, \ 508 PLATFORM(INTEL_IVYBRIDGE), \ 509 .is_mobile = 1, \ 510 .has_l3_dpf = 1 511 512static const struct intel_device_info ivb_m_gt1_info = { 513 IVB_M_PLATFORM, 514 .gt = 1, 515}; 516 517static const struct intel_device_info ivb_m_gt2_info = { 518 IVB_M_PLATFORM, 519 .gt = 2, 520}; 521 522static const struct intel_device_info ivb_q_info = { 523 GEN7_FEATURES, 524 PLATFORM(INTEL_IVYBRIDGE), 525 NO_DISPLAY, 526 .gt = 2, 527 .has_l3_dpf = 1, 528}; 529 530static const struct intel_device_info vlv_info = { 531 PLATFORM(INTEL_VALLEYVIEW), 532 GEN(7), 533 .is_lp = 1, 534 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 535 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 536 .has_runtime_pm = 1, 537 .has_rc6 = 1, 538 .has_reset_engine = true, 539 .has_rps = true, 540 .display.has_gmch = 1, 541 .display.has_hotplug = 1, 542 .dma_mask_size = 40, 543 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, 544 .__runtime.ppgtt_size = 31, 545 .has_snoop = true, 546 .has_coherent_ggtt = false, 547 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 548 .display.mmio_offset = VLV_DISPLAY_BASE, 549 I9XX_PIPE_OFFSETS, 550 I9XX_CURSOR_OFFSETS, 551 I965_COLORS, 552 GEN_DEFAULT_PAGE_SIZES, 553 GEN_DEFAULT_REGIONS, 554}; 555 556#define G75_FEATURES \ 557 GEN7_FEATURES, \ 558 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 559 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 560 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ 561 .display.has_ddi = 1, \ 562 .display.has_fpga_dbg = 1, \ 563 .display.has_dp_mst = 1, \ 564 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 565 HSW_PIPE_OFFSETS, \ 566 .has_runtime_pm = 1 567 568#define HSW_PLATFORM \ 569 G75_FEATURES, \ 570 PLATFORM(INTEL_HASWELL), \ 571 .has_l3_dpf = 1 572 573static const struct intel_device_info hsw_gt1_info = { 574 HSW_PLATFORM, 575 .gt = 1, 576}; 577 578static const struct intel_device_info hsw_gt2_info = { 579 HSW_PLATFORM, 580 .gt = 2, 581}; 582 583static const struct intel_device_info hsw_gt3_info = { 584 HSW_PLATFORM, 585 .gt = 3, 586}; 587 588#define GEN8_FEATURES \ 589 G75_FEATURES, \ 590 GEN(8), \ 591 .has_logical_ring_contexts = 1, \ 592 .dma_mask_size = 39, \ 593 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 594 .__runtime.ppgtt_size = 48, \ 595 .has_64bit_reloc = 1 596 597#define BDW_PLATFORM \ 598 GEN8_FEATURES, \ 599 PLATFORM(INTEL_BROADWELL) 600 601static const struct intel_device_info bdw_gt1_info = { 602 BDW_PLATFORM, 603 .gt = 1, 604}; 605 606static const struct intel_device_info bdw_gt2_info = { 607 BDW_PLATFORM, 608 .gt = 2, 609}; 610 611static const struct intel_device_info bdw_rsvd_info = { 612 BDW_PLATFORM, 613 .gt = 3, 614 /* According to the device ID those devices are GT3, they were 615 * previously treated as not GT3, keep it like that. 616 */ 617}; 618 619static const struct intel_device_info bdw_gt3_info = { 620 BDW_PLATFORM, 621 .gt = 3, 622 .__runtime.platform_engine_mask = 623 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 624}; 625 626static const struct intel_device_info chv_info = { 627 PLATFORM(INTEL_CHERRYVIEW), 628 GEN(8), 629 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 630 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 631 .display.has_hotplug = 1, 632 .is_lp = 1, 633 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 634 .has_64bit_reloc = 1, 635 .has_runtime_pm = 1, 636 .has_rc6 = 1, 637 .has_rps = true, 638 .has_logical_ring_contexts = 1, 639 .display.has_gmch = 1, 640 .dma_mask_size = 39, 641 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, 642 .__runtime.ppgtt_size = 32, 643 .has_reset_engine = 1, 644 .has_snoop = true, 645 .has_coherent_ggtt = false, 646 .display.mmio_offset = VLV_DISPLAY_BASE, 647 CHV_PIPE_OFFSETS, 648 CHV_CURSOR_OFFSETS, 649 CHV_COLORS, 650 GEN_DEFAULT_PAGE_SIZES, 651 GEN_DEFAULT_REGIONS, 652}; 653 654#define GEN9_DEFAULT_PAGE_SIZES \ 655 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 656 I915_GTT_PAGE_SIZE_64K 657 658#define GEN9_FEATURES \ 659 GEN8_FEATURES, \ 660 GEN(9), \ 661 GEN9_DEFAULT_PAGE_SIZES, \ 662 .__runtime.has_dmc = 1, \ 663 .has_gt_uc = 1, \ 664 .__runtime.has_hdcp = 1, \ 665 .display.has_ipc = 1, \ 666 .display.has_psr = 1, \ 667 .display.has_psr_hw_tracking = 1, \ 668 .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ 669 .display.dbuf.slice_mask = BIT(DBUF_S1) 670 671#define SKL_PLATFORM \ 672 GEN9_FEATURES, \ 673 PLATFORM(INTEL_SKYLAKE) 674 675static const struct intel_device_info skl_gt1_info = { 676 SKL_PLATFORM, 677 .gt = 1, 678}; 679 680static const struct intel_device_info skl_gt2_info = { 681 SKL_PLATFORM, 682 .gt = 2, 683}; 684 685#define SKL_GT3_PLUS_PLATFORM \ 686 SKL_PLATFORM, \ 687 .__runtime.platform_engine_mask = \ 688 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 689 690 691static const struct intel_device_info skl_gt3_info = { 692 SKL_GT3_PLUS_PLATFORM, 693 .gt = 3, 694}; 695 696static const struct intel_device_info skl_gt4_info = { 697 SKL_GT3_PLUS_PLATFORM, 698 .gt = 4, 699}; 700 701#define GEN9_LP_FEATURES \ 702 GEN(9), \ 703 .is_lp = 1, \ 704 .display.dbuf.slice_mask = BIT(DBUF_S1), \ 705 .display.has_hotplug = 1, \ 706 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 707 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 708 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 709 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 710 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 711 .has_3d_pipeline = 1, \ 712 .has_64bit_reloc = 1, \ 713 .display.has_ddi = 1, \ 714 .display.has_fpga_dbg = 1, \ 715 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 716 .__runtime.has_hdcp = 1, \ 717 .display.has_psr = 1, \ 718 .display.has_psr_hw_tracking = 1, \ 719 .has_runtime_pm = 1, \ 720 .__runtime.has_dmc = 1, \ 721 .has_rc6 = 1, \ 722 .has_rps = true, \ 723 .display.has_dp_mst = 1, \ 724 .has_logical_ring_contexts = 1, \ 725 .has_gt_uc = 1, \ 726 .dma_mask_size = 39, \ 727 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 728 .__runtime.ppgtt_size = 48, \ 729 .has_reset_engine = 1, \ 730 .has_snoop = true, \ 731 .has_coherent_ggtt = false, \ 732 .display.has_ipc = 1, \ 733 HSW_PIPE_OFFSETS, \ 734 IVB_CURSOR_OFFSETS, \ 735 IVB_COLORS, \ 736 GEN9_DEFAULT_PAGE_SIZES, \ 737 GEN_DEFAULT_REGIONS 738 739static const struct intel_device_info bxt_info = { 740 GEN9_LP_FEATURES, 741 PLATFORM(INTEL_BROXTON), 742 .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 743}; 744 745static const struct intel_device_info glk_info = { 746 GEN9_LP_FEATURES, 747 PLATFORM(INTEL_GEMINILAKE), 748 .__runtime.display.ip.ver = 10, 749 .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 750 GLK_COLORS, 751}; 752 753#define KBL_PLATFORM \ 754 GEN9_FEATURES, \ 755 PLATFORM(INTEL_KABYLAKE) 756 757static const struct intel_device_info kbl_gt1_info = { 758 KBL_PLATFORM, 759 .gt = 1, 760}; 761 762static const struct intel_device_info kbl_gt2_info = { 763 KBL_PLATFORM, 764 .gt = 2, 765}; 766 767static const struct intel_device_info kbl_gt3_info = { 768 KBL_PLATFORM, 769 .gt = 3, 770 .__runtime.platform_engine_mask = 771 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 772}; 773 774#define CFL_PLATFORM \ 775 GEN9_FEATURES, \ 776 PLATFORM(INTEL_COFFEELAKE) 777 778static const struct intel_device_info cfl_gt1_info = { 779 CFL_PLATFORM, 780 .gt = 1, 781}; 782 783static const struct intel_device_info cfl_gt2_info = { 784 CFL_PLATFORM, 785 .gt = 2, 786}; 787 788static const struct intel_device_info cfl_gt3_info = { 789 CFL_PLATFORM, 790 .gt = 3, 791 .__runtime.platform_engine_mask = 792 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 793}; 794 795#define CML_PLATFORM \ 796 GEN9_FEATURES, \ 797 PLATFORM(INTEL_COMETLAKE) 798 799static const struct intel_device_info cml_gt1_info = { 800 CML_PLATFORM, 801 .gt = 1, 802}; 803 804static const struct intel_device_info cml_gt2_info = { 805 CML_PLATFORM, 806 .gt = 2, 807}; 808 809#define GEN11_DEFAULT_PAGE_SIZES \ 810 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 811 I915_GTT_PAGE_SIZE_64K | \ 812 I915_GTT_PAGE_SIZE_2M 813 814#define GEN11_FEATURES \ 815 GEN9_FEATURES, \ 816 GEN11_DEFAULT_PAGE_SIZES, \ 817 .display.abox_mask = BIT(0), \ 818 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 819 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 820 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 821 .display.pipe_offsets = { \ 822 [TRANSCODER_A] = PIPE_A_OFFSET, \ 823 [TRANSCODER_B] = PIPE_B_OFFSET, \ 824 [TRANSCODER_C] = PIPE_C_OFFSET, \ 825 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 826 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 827 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 828 }, \ 829 .display.trans_offsets = { \ 830 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 831 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 832 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 833 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 834 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 835 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 836 }, \ 837 GEN(11), \ 838 ICL_COLORS, \ 839 .display.dbuf.size = 2048, \ 840 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 841 .__runtime.has_dsc = 1, \ 842 .has_coherent_ggtt = false, \ 843 .has_logical_ring_elsq = 1 844 845static const struct intel_device_info icl_info = { 846 GEN11_FEATURES, 847 PLATFORM(INTEL_ICELAKE), 848 .__runtime.platform_engine_mask = 849 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 850}; 851 852static const struct intel_device_info ehl_info = { 853 GEN11_FEATURES, 854 PLATFORM(INTEL_ELKHARTLAKE), 855 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 856 .__runtime.ppgtt_size = 36, 857}; 858 859static const struct intel_device_info jsl_info = { 860 GEN11_FEATURES, 861 PLATFORM(INTEL_JASPERLAKE), 862 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 863 .__runtime.ppgtt_size = 36, 864}; 865 866#define GEN12_FEATURES \ 867 GEN11_FEATURES, \ 868 GEN(12), \ 869 .display.abox_mask = GENMASK(2, 1), \ 870 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 871 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 872 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 873 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 874 .display.pipe_offsets = { \ 875 [TRANSCODER_A] = PIPE_A_OFFSET, \ 876 [TRANSCODER_B] = PIPE_B_OFFSET, \ 877 [TRANSCODER_C] = PIPE_C_OFFSET, \ 878 [TRANSCODER_D] = PIPE_D_OFFSET, \ 879 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 880 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 881 }, \ 882 .display.trans_offsets = { \ 883 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 884 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 885 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 886 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 887 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 888 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 889 }, \ 890 TGL_CURSOR_OFFSETS, \ 891 .has_global_mocs = 1, \ 892 .has_pxp = 1, \ 893 .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */ 894 895static const struct intel_device_info tgl_info = { 896 GEN12_FEATURES, 897 PLATFORM(INTEL_TIGERLAKE), 898 .display.has_modular_fia = 1, 899 .__runtime.platform_engine_mask = 900 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 901}; 902 903static const struct intel_device_info rkl_info = { 904 GEN12_FEATURES, 905 PLATFORM(INTEL_ROCKETLAKE), 906 .display.abox_mask = BIT(0), 907 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 908 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 909 BIT(TRANSCODER_C), 910 .display.has_hti = 1, 911 .display.has_psr_hw_tracking = 0, 912 .__runtime.platform_engine_mask = 913 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 914}; 915 916#define DGFX_FEATURES \ 917 .__runtime.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \ 918 .has_llc = 0, \ 919 .has_pxp = 0, \ 920 .has_snoop = 1, \ 921 .is_dgfx = 1, \ 922 .has_heci_gscfi = 1 923 924static const struct intel_device_info dg1_info = { 925 GEN12_FEATURES, 926 DGFX_FEATURES, 927 .__runtime.graphics.ip.rel = 10, 928 PLATFORM(INTEL_DG1), 929 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 930 .require_force_probe = 1, 931 .__runtime.platform_engine_mask = 932 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | 933 BIT(VCS0) | BIT(VCS2), 934 /* Wa_16011227922 */ 935 .__runtime.ppgtt_size = 47, 936}; 937 938static const struct intel_device_info adl_s_info = { 939 GEN12_FEATURES, 940 PLATFORM(INTEL_ALDERLAKE_S), 941 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 942 .display.has_hti = 1, 943 .display.has_psr_hw_tracking = 0, 944 .__runtime.platform_engine_mask = 945 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 946 .dma_mask_size = 39, 947}; 948 949#define XE_LPD_FEATURES \ 950 .display.abox_mask = GENMASK(1, 0), \ 951 .display.color = { \ 952 .degamma_lut_size = 128, .gamma_lut_size = 1024, \ 953 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 954 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 955 }, \ 956 .display.dbuf.size = 4096, \ 957 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 958 BIT(DBUF_S4), \ 959 .display.has_ddi = 1, \ 960 .__runtime.has_dmc = 1, \ 961 .display.has_dp_mst = 1, \ 962 .display.has_dsb = 1, \ 963 .__runtime.has_dsc = 1, \ 964 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 965 .display.has_fpga_dbg = 1, \ 966 .__runtime.has_hdcp = 1, \ 967 .display.has_hotplug = 1, \ 968 .display.has_ipc = 1, \ 969 .display.has_psr = 1, \ 970 .__runtime.display.ip.ver = 13, \ 971 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 972 .display.pipe_offsets = { \ 973 [TRANSCODER_A] = PIPE_A_OFFSET, \ 974 [TRANSCODER_B] = PIPE_B_OFFSET, \ 975 [TRANSCODER_C] = PIPE_C_OFFSET, \ 976 [TRANSCODER_D] = PIPE_D_OFFSET, \ 977 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 978 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 979 }, \ 980 .display.trans_offsets = { \ 981 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 982 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 983 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 984 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 985 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 986 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 987 }, \ 988 TGL_CURSOR_OFFSETS 989 990static const struct intel_device_info adl_p_info = { 991 GEN12_FEATURES, 992 XE_LPD_FEATURES, 993 PLATFORM(INTEL_ALDERLAKE_P), 994 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 995 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 996 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 997 .display.has_cdclk_crawl = 1, 998 .display.has_modular_fia = 1, 999 .display.has_psr_hw_tracking = 0, 1000 .__runtime.platform_engine_mask = 1001 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 1002 .__runtime.ppgtt_size = 48, 1003 .dma_mask_size = 39, 1004}; 1005 1006#undef GEN 1007 1008#define XE_HP_PAGE_SIZES \ 1009 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 1010 I915_GTT_PAGE_SIZE_64K | \ 1011 I915_GTT_PAGE_SIZE_2M 1012 1013#define XE_HP_FEATURES \ 1014 .__runtime.graphics.ip.ver = 12, \ 1015 .__runtime.graphics.ip.rel = 50, \ 1016 XE_HP_PAGE_SIZES, \ 1017 .dma_mask_size = 46, \ 1018 .has_3d_pipeline = 1, \ 1019 .has_64bit_reloc = 1, \ 1020 .has_flat_ccs = 1, \ 1021 .has_global_mocs = 1, \ 1022 .has_gt_uc = 1, \ 1023 .has_llc = 1, \ 1024 .has_logical_ring_contexts = 1, \ 1025 .has_logical_ring_elsq = 1, \ 1026 .has_mslice_steering = 1, \ 1027 .has_rc6 = 1, \ 1028 .has_reset_engine = 1, \ 1029 .has_rps = 1, \ 1030 .has_runtime_pm = 1, \ 1031 .__runtime.ppgtt_size = 48, \ 1032 .__runtime.ppgtt_type = INTEL_PPGTT_FULL 1033 1034#define XE_HPM_FEATURES \ 1035 .__runtime.media.ip.ver = 12, \ 1036 .__runtime.media.ip.rel = 50 1037 1038__maybe_unused 1039static const struct intel_device_info xehpsdv_info = { 1040 XE_HP_FEATURES, 1041 XE_HPM_FEATURES, 1042 DGFX_FEATURES, 1043 PLATFORM(INTEL_XEHPSDV), 1044 NO_DISPLAY, 1045 .has_64k_pages = 1, 1046 .needs_compact_pt = 1, 1047 .has_media_ratio_mode = 1, 1048 .__runtime.platform_engine_mask = 1049 BIT(RCS0) | BIT(BCS0) | 1050 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | 1051 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | 1052 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) | 1053 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), 1054 .require_force_probe = 1, 1055}; 1056 1057#define DG2_FEATURES \ 1058 XE_HP_FEATURES, \ 1059 XE_HPM_FEATURES, \ 1060 DGFX_FEATURES, \ 1061 .__runtime.graphics.ip.rel = 55, \ 1062 .__runtime.media.ip.rel = 55, \ 1063 PLATFORM(INTEL_DG2), \ 1064 .has_4tile = 1, \ 1065 .has_64k_pages = 1, \ 1066 .has_guc_deprivilege = 1, \ 1067 .has_heci_pxp = 1, \ 1068 .needs_compact_pt = 1, \ 1069 .has_media_ratio_mode = 1, \ 1070 .__runtime.platform_engine_mask = \ 1071 BIT(RCS0) | BIT(BCS0) | \ 1072 BIT(VECS0) | BIT(VECS1) | \ 1073 BIT(VCS0) | BIT(VCS2) | \ 1074 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3) 1075 1076static const struct intel_device_info dg2_info = { 1077 DG2_FEATURES, 1078 XE_LPD_FEATURES, 1079 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1080 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1081 .require_force_probe = 1, 1082}; 1083 1084static const struct intel_device_info ats_m_info = { 1085 DG2_FEATURES, 1086 NO_DISPLAY, 1087 .require_force_probe = 1, 1088 .tuning_thread_rr_after_dep = 1, 1089}; 1090 1091#define XE_HPC_FEATURES \ 1092 XE_HP_FEATURES, \ 1093 .dma_mask_size = 52, \ 1094 .has_3d_pipeline = 0, \ 1095 .has_guc_deprivilege = 1, \ 1096 .has_l3_ccs_read = 1, \ 1097 .has_mslice_steering = 0, \ 1098 .has_one_eu_per_fuse_bit = 1 1099 1100__maybe_unused 1101static const struct intel_device_info pvc_info = { 1102 XE_HPC_FEATURES, 1103 XE_HPM_FEATURES, 1104 DGFX_FEATURES, 1105 .__runtime.graphics.ip.rel = 60, 1106 .__runtime.media.ip.rel = 60, 1107 PLATFORM(INTEL_PONTEVECCHIO), 1108 NO_DISPLAY, 1109 .has_flat_ccs = 0, 1110 .__runtime.platform_engine_mask = 1111 BIT(BCS0) | 1112 BIT(VCS0) | 1113 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), 1114 .require_force_probe = 1, 1115}; 1116 1117#define XE_LPDP_FEATURES \ 1118 XE_LPD_FEATURES, \ 1119 .__runtime.display.ip.ver = 14, \ 1120 .display.has_cdclk_crawl = 1, \ 1121 .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) 1122 1123static const struct intel_gt_definition xelpmp_extra_gt[] = { 1124 { 1125 .type = GT_MEDIA, 1126 .name = "Standalone Media GT", 1127 .gsi_offset = MTL_MEDIA_GSI_BASE, 1128 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 1129 }, 1130 {} 1131}; 1132 1133static const struct intel_device_info mtl_info = { 1134 XE_HP_FEATURES, 1135 XE_LPDP_FEATURES, 1136 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1137 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1138 /* 1139 * Real graphics IP version will be obtained from hardware GMD_ID 1140 * register. Value provided here is just for sanity checking. 1141 */ 1142 .__runtime.graphics.ip.ver = 12, 1143 .__runtime.graphics.ip.rel = 70, 1144 .__runtime.media.ip.ver = 13, 1145 PLATFORM(INTEL_METEORLAKE), 1146 .display.has_modular_fia = 1, 1147 .extra_gt_list = xelpmp_extra_gt, 1148 .has_flat_ccs = 0, 1149 .has_snoop = 1, 1150 .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, 1151 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), 1152 .require_force_probe = 1, 1153}; 1154 1155#undef PLATFORM 1156 1157/* 1158 * Make sure any device matches here are from most specific to most 1159 * general. For example, since the Quanta match is based on the subsystem 1160 * and subvendor IDs, we need it to come before the more general IVB 1161 * PCI ID matches, otherwise we'll use the wrong info struct above. 1162 */ 1163const struct pci_device_id pciidlist[] = { 1164 INTEL_I830_IDS(&i830_info), 1165 INTEL_I845G_IDS(&i845g_info), 1166 INTEL_I85X_IDS(&i85x_info), 1167 INTEL_I865G_IDS(&i865g_info), 1168 INTEL_I915G_IDS(&i915g_info), 1169 INTEL_I915GM_IDS(&i915gm_info), 1170 INTEL_I945G_IDS(&i945g_info), 1171 INTEL_I945GM_IDS(&i945gm_info), 1172 INTEL_I965G_IDS(&i965g_info), 1173 INTEL_G33_IDS(&g33_info), 1174 INTEL_I965GM_IDS(&i965gm_info), 1175 INTEL_GM45_IDS(&gm45_info), 1176 INTEL_G45_IDS(&g45_info), 1177 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 1178 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 1179 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 1180 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 1181 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 1182 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 1183 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 1184 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 1185 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 1186 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 1187 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 1188 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 1189 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 1190 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 1191 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 1192 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 1193 INTEL_VLV_IDS(&vlv_info), 1194 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 1195 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 1196 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 1197 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 1198 INTEL_CHV_IDS(&chv_info), 1199 INTEL_SKL_GT1_IDS(&skl_gt1_info), 1200 INTEL_SKL_GT2_IDS(&skl_gt2_info), 1201 INTEL_SKL_GT3_IDS(&skl_gt3_info), 1202 INTEL_SKL_GT4_IDS(&skl_gt4_info), 1203 INTEL_BXT_IDS(&bxt_info), 1204 INTEL_GLK_IDS(&glk_info), 1205 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 1206 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 1207 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 1208 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 1209 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 1210 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 1211 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 1212 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 1213 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 1214 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 1215 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 1216 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 1217 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 1218 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 1219 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 1220 INTEL_CML_GT1_IDS(&cml_gt1_info), 1221 INTEL_CML_GT2_IDS(&cml_gt2_info), 1222 INTEL_CML_U_GT1_IDS(&cml_gt1_info), 1223 INTEL_CML_U_GT2_IDS(&cml_gt2_info), 1224 INTEL_ICL_11_IDS(&icl_info), 1225 INTEL_EHL_IDS(&ehl_info), 1226 INTEL_JSL_IDS(&jsl_info), 1227 INTEL_TGL_12_IDS(&tgl_info), 1228 INTEL_RKL_IDS(&rkl_info), 1229 INTEL_ADLS_IDS(&adl_s_info), 1230 INTEL_ADLP_IDS(&adl_p_info), 1231 INTEL_ADLN_IDS(&adl_p_info), 1232 INTEL_DG1_IDS(&dg1_info), 1233 INTEL_RPLS_IDS(&adl_s_info), 1234 INTEL_RPLP_IDS(&adl_p_info), 1235 INTEL_DG2_IDS(&dg2_info), 1236 INTEL_ATS_M_IDS(&ats_m_info), 1237 INTEL_MTL_IDS(&mtl_info), 1238 {0, 0, 0} 1239}; 1240MODULE_DEVICE_TABLE(pci, pciidlist); 1241 1242#ifdef __linux__ 1243static void i915_pci_remove(struct pci_dev *pdev) 1244{ 1245 struct drm_i915_private *i915; 1246 1247 i915 = pci_get_drvdata(pdev); 1248 if (!i915) /* driver load aborted, nothing to cleanup */ 1249 return; 1250 1251 i915_driver_remove(i915); 1252 pci_set_drvdata(pdev, NULL); 1253} 1254 1255/* is device_id present in comma separated list of ids */ 1256static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 1257{ 1258 char *s, *p, *tok; 1259 bool ret; 1260 1261 if (!devices || !*devices) 1262 return false; 1263 1264 /* match everything */ 1265 if (negative && strcmp(devices, "!*") == 0) 1266 return true; 1267 if (!negative && strcmp(devices, "*") == 0) 1268 return true; 1269 1270 s = kstrdup(devices, GFP_KERNEL); 1271 if (!s) 1272 return false; 1273 1274 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 1275 u16 val; 1276 1277 if (negative && tok[0] == '!') 1278 tok++; 1279 else if ((negative && tok[0] != '!') || 1280 (!negative && tok[0] == '!')) 1281 continue; 1282 1283 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 1284 ret = true; 1285 break; 1286 } 1287 } 1288 1289 kfree(s); 1290 1291 return ret; 1292} 1293 1294static bool id_forced(u16 device_id) 1295{ 1296 return device_id_in_list(device_id, i915_modparams.force_probe, false); 1297} 1298 1299static bool id_blocked(u16 device_id) 1300{ 1301 return device_id_in_list(device_id, i915_modparams.force_probe, true); 1302} 1303 1304bool i915_pci_resource_valid(struct pci_dev *pdev, int bar) 1305{ 1306 if (!pci_resource_flags(pdev, bar)) 1307 return false; 1308 1309 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 1310 return false; 1311 1312 if (!pci_resource_len(pdev, bar)) 1313 return false; 1314 1315 return true; 1316} 1317 1318static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info) 1319{ 1320 int gttmmaddr_bar = intel_info->__runtime.graphics.ip.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR; 1321 1322 return i915_pci_resource_valid(pdev, gttmmaddr_bar); 1323} 1324 1325static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1326{ 1327 struct intel_device_info *intel_info = 1328 (struct intel_device_info *) ent->driver_data; 1329 int err; 1330 1331 if (intel_info->require_force_probe && !id_forced(pdev->device)) { 1332 dev_info(&pdev->dev, 1333 "Your graphics device %04x is not properly supported by i915 in this\n" 1334 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 1335 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 1336 "or (recommended) check for kernel updates.\n", 1337 pdev->device, pdev->device, pdev->device); 1338 return -ENODEV; 1339 } 1340 1341 if (id_blocked(pdev->device)) { 1342 dev_info(&pdev->dev, "I915 probe blocked for Device ID %04x.\n", 1343 pdev->device); 1344 return -ENODEV; 1345 } 1346 1347 if (intel_info->require_force_probe) { 1348 dev_info(&pdev->dev, "Force probing unsupported Device ID %04x, tainting kernel\n", 1349 pdev->device); 1350 add_taint(TAINT_USER, LOCKDEP_STILL_OK); 1351 } 1352 1353 /* Only bind to function 0 of the device. Early generations 1354 * used function 1 as a placeholder for multi-head. This causes 1355 * us confusion instead, especially on the systems where both 1356 * functions have the same PCI-ID! 1357 */ 1358 if (PCI_FUNC(pdev->devfn)) 1359 return -ENODEV; 1360 1361 if (!intel_mmio_bar_valid(pdev, intel_info)) 1362 return -ENXIO; 1363 1364 /* Detect if we need to wait for other drivers early on */ 1365 if (intel_modeset_probe_defer(pdev)) 1366 return -EPROBE_DEFER; 1367 1368 err = i915_driver_probe(pdev, ent); 1369 if (err) 1370 return err; 1371 1372 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1373 i915_pci_remove(pdev); 1374 return -ENODEV; 1375 } 1376 1377 err = i915_live_selftests(pdev); 1378 if (err) { 1379 i915_pci_remove(pdev); 1380 return err > 0 ? -ENOTTY : err; 1381 } 1382 1383 err = i915_perf_selftests(pdev); 1384 if (err) { 1385 i915_pci_remove(pdev); 1386 return err > 0 ? -ENOTTY : err; 1387 } 1388 1389 return 0; 1390} 1391 1392static void i915_pci_shutdown(struct pci_dev *pdev) 1393{ 1394 struct drm_i915_private *i915 = pci_get_drvdata(pdev); 1395 1396 i915_driver_shutdown(i915); 1397} 1398 1399static struct pci_driver i915_pci_driver = { 1400 .name = DRIVER_NAME, 1401 .id_table = pciidlist, 1402 .probe = i915_pci_probe, 1403 .remove = i915_pci_remove, 1404 .shutdown = i915_pci_shutdown, 1405 .driver.pm = &i915_pm_ops, 1406}; 1407 1408int i915_pci_register_driver(void) 1409{ 1410 return pci_register_driver(&i915_pci_driver); 1411} 1412 1413void i915_pci_unregister_driver(void) 1414{ 1415 pci_unregister_driver(&i915_pci_driver); 1416} 1417 1418#else 1419 1420int i915_pci_register_driver(void) 1421{ 1422 return 0; 1423} 1424 1425void i915_pci_unregister_driver(void) 1426{ 1427} 1428#endif 1429