1// SPDX-License-Identifier: MIT
2/*
3 * Copyright �� 2019 Intel Corporation
4 */
5
6#include <asm/tsc.h>
7#include <linux/cpufreq.h>
8
9#include "i915_drv.h"
10#include "i915_reg.h"
11#include "intel_gt.h"
12#include "intel_llc.h"
13#include "intel_mchbar_regs.h"
14#include "intel_pcode.h"
15#include "intel_rps.h"
16
17struct ia_constants {
18	unsigned int min_gpu_freq;
19	unsigned int max_gpu_freq;
20
21	unsigned int min_ring_freq;
22	unsigned int max_ia_freq;
23};
24
25static struct intel_gt *llc_to_gt(struct intel_llc *llc)
26{
27	return container_of(llc, struct intel_gt, llc);
28}
29
30static unsigned int cpu_max_MHz(void)
31{
32	struct cpufreq_policy *policy;
33	unsigned int max_khz;
34
35#ifdef notyet
36	policy = cpufreq_cpu_get(0);
37	if (policy) {
38		max_khz = policy->cpuinfo.max_freq;
39		cpufreq_cpu_put(policy);
40	} else {
41		/*
42		 * Default to measured freq if none found, PCU will ensure we
43		 * don't go over
44		 */
45		max_khz = tsc_khz;
46	}
47#else
48	/* XXX we ideally want the max not cpuspeed... */
49	max_khz = cpuspeed;
50#endif
51
52	return max_khz / 1000;
53}
54
55static bool get_ia_constants(struct intel_llc *llc,
56			     struct ia_constants *consts)
57{
58	struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
59	struct intel_rps *rps = &llc_to_gt(llc)->rps;
60
61	if (!HAS_LLC(i915) || IS_DGFX(i915))
62		return false;
63
64	consts->max_ia_freq = cpu_max_MHz();
65
66	consts->min_ring_freq =
67		intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf;
68	/* convert DDR frequency from units of 266.6MHz to bandwidth */
69	consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
70
71	consts->min_gpu_freq = intel_rps_get_min_raw_freq(rps);
72	consts->max_gpu_freq = intel_rps_get_max_raw_freq(rps);
73
74	return true;
75}
76
77static void calc_ia_freq(struct intel_llc *llc,
78			 unsigned int gpu_freq,
79			 const struct ia_constants *consts,
80			 unsigned int *out_ia_freq,
81			 unsigned int *out_ring_freq)
82{
83	struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
84	const int diff = consts->max_gpu_freq - gpu_freq;
85	unsigned int ia_freq = 0, ring_freq = 0;
86
87	if (GRAPHICS_VER(i915) >= 9) {
88		/*
89		 * ring_freq = 2 * GT. ring_freq is in 100MHz units
90		 * No floor required for ring frequency on SKL.
91		 */
92		ring_freq = gpu_freq;
93	} else if (GRAPHICS_VER(i915) >= 8) {
94		/* max(2 * GT, DDR). NB: GT is 50MHz units */
95		ring_freq = max(consts->min_ring_freq, gpu_freq);
96	} else if (IS_HASWELL(i915)) {
97		ring_freq = mult_frac(gpu_freq, 5, 4);
98		ring_freq = max(consts->min_ring_freq, ring_freq);
99		/* leave ia_freq as the default, chosen by cpufreq */
100	} else {
101		const int min_freq = 15;
102		const int scale = 180;
103
104		/*
105		 * On older processors, there is no separate ring
106		 * clock domain, so in order to boost the bandwidth
107		 * of the ring, we need to upclock the CPU (ia_freq).
108		 *
109		 * For GPU frequencies less than 750MHz,
110		 * just use the lowest ring freq.
111		 */
112		if (gpu_freq < min_freq)
113			ia_freq = 800;
114		else
115			ia_freq = consts->max_ia_freq - diff * scale / 2;
116		ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
117	}
118
119	*out_ia_freq = ia_freq;
120	*out_ring_freq = ring_freq;
121}
122
123static void gen6_update_ring_freq(struct intel_llc *llc)
124{
125	struct ia_constants consts;
126	unsigned int gpu_freq;
127
128	if (!get_ia_constants(llc, &consts))
129		return;
130
131	/*
132	 * Although this is unlikely on any platform during initialization,
133	 * let's ensure we don't get accidentally into infinite loop
134	 */
135	if (consts.max_gpu_freq <= consts.min_gpu_freq)
136		return;
137	/*
138	 * For each potential GPU frequency, load a ring frequency we'd like
139	 * to use for memory access.  We do this by specifying the IA frequency
140	 * the PCU should use as a reference to determine the ring frequency.
141	 */
142	for (gpu_freq = consts.max_gpu_freq;
143	     gpu_freq >= consts.min_gpu_freq;
144	     gpu_freq--) {
145		unsigned int ia_freq, ring_freq;
146
147		calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
148		snb_pcode_write(llc_to_gt(llc)->uncore, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
149				ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
150				ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
151				gpu_freq);
152	}
153}
154
155void intel_llc_enable(struct intel_llc *llc)
156{
157	gen6_update_ring_freq(llc);
158}
159
160void intel_llc_disable(struct intel_llc *llc)
161{
162	/* Currently there is no HW configuration to be done to disable. */
163}
164
165#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
166#include "selftest_llc.c"
167#endif
168