intel_gt_irq.c revision 1.3
1// SPDX-License-Identifier: MIT 2/* 3 * Copyright �� 2019 Intel Corporation 4 */ 5 6#include <linux/sched/clock.h> 7 8#include "i915_drv.h" 9#include "i915_irq.h" 10#include "intel_breadcrumbs.h" 11#include "intel_gt.h" 12#include "intel_gt_irq.h" 13#include "intel_lrc_reg.h" 14#include "intel_uncore.h" 15#include "intel_rps.h" 16 17static void guc_irq_handler(struct intel_guc *guc, u16 iir) 18{ 19 if (iir & GUC_INTR_GUC2HOST) 20 intel_guc_to_host_event_handler(guc); 21} 22 23static u32 24gen11_gt_engine_identity(struct intel_gt *gt, 25 const unsigned int bank, const unsigned int bit) 26{ 27 void __iomem * const regs = gt->uncore->regs; 28 u32 timeout_ts; 29 u32 ident; 30 31 lockdep_assert_held(>->irq_lock); 32 33 raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit)); 34 35 /* 36 * NB: Specs do not specify how long to spin wait, 37 * so we do ~100us as an educated guess. 38 */ 39 timeout_ts = (local_clock() >> 10) + 100; 40 do { 41 ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank)); 42 } while (!(ident & GEN11_INTR_DATA_VALID) && 43 !time_after32(local_clock() >> 10, timeout_ts)); 44 45 if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) { 46 DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n", 47 bank, bit, ident); 48 return 0; 49 } 50 51 raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank), 52 GEN11_INTR_DATA_VALID); 53 54 return ident; 55} 56 57static void 58gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, 59 const u16 iir) 60{ 61 if (instance == OTHER_GUC_INSTANCE) 62 return guc_irq_handler(>->uc.guc, iir); 63 64 if (instance == OTHER_GTPM_INSTANCE) 65 return gen11_rps_irq_handler(>->rps, iir); 66 67 WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n", 68 instance, iir); 69} 70 71static void 72gen11_engine_irq_handler(struct intel_gt *gt, const u8 class, 73 const u8 instance, const u16 iir) 74{ 75 struct intel_engine_cs *engine; 76 77 if (instance <= MAX_ENGINE_INSTANCE) 78 engine = gt->engine_class[class][instance]; 79 else 80 engine = NULL; 81 82 if (likely(engine)) 83 return intel_engine_cs_irq(engine, iir); 84 85 WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n", 86 class, instance); 87} 88 89static void 90gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity) 91{ 92 const u8 class = GEN11_INTR_ENGINE_CLASS(identity); 93 const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity); 94 const u16 intr = GEN11_INTR_ENGINE_INTR(identity); 95 96 if (unlikely(!intr)) 97 return; 98 99 if (class <= COPY_ENGINE_CLASS) 100 return gen11_engine_irq_handler(gt, class, instance, intr); 101 102 if (class == OTHER_CLASS) 103 return gen11_other_irq_handler(gt, instance, intr); 104 105 WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n", 106 class, instance, intr); 107} 108 109static void 110gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank) 111{ 112 void __iomem * const regs = gt->uncore->regs; 113 unsigned long intr_dw; 114 unsigned int bit; 115 116 lockdep_assert_held(>->irq_lock); 117 118 intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); 119 120 for_each_set_bit(bit, &intr_dw, 32) { 121 const u32 ident = gen11_gt_engine_identity(gt, bank, bit); 122 123 gen11_gt_identity_handler(gt, ident); 124 } 125 126 /* Clear must be after shared has been served for engine */ 127 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw); 128} 129 130void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl) 131{ 132 unsigned int bank; 133 134 spin_lock(>->irq_lock); 135 136 for (bank = 0; bank < 2; bank++) { 137 if (master_ctl & GEN11_GT_DW_IRQ(bank)) 138 gen11_gt_bank_handler(gt, bank); 139 } 140 141 spin_unlock(>->irq_lock); 142} 143 144bool gen11_gt_reset_one_iir(struct intel_gt *gt, 145 const unsigned int bank, const unsigned int bit) 146{ 147 void __iomem * const regs = gt->uncore->regs; 148 u32 dw; 149 150 lockdep_assert_held(>->irq_lock); 151 152 dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); 153 if (dw & BIT(bit)) { 154 /* 155 * According to the BSpec, DW_IIR bits cannot be cleared without 156 * first servicing the Selector & Shared IIR registers. 157 */ 158 gen11_gt_engine_identity(gt, bank, bit); 159 160 /* 161 * We locked GT INT DW by reading it. If we want to (try 162 * to) recover from this successfully, we need to clear 163 * our bit, otherwise we are locking the register for 164 * everybody. 165 */ 166 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit)); 167 168 return true; 169 } 170 171 return false; 172} 173 174void gen11_gt_irq_reset(struct intel_gt *gt) 175{ 176 struct intel_uncore *uncore = gt->uncore; 177 178 /* Disable RCS, BCS, VCS and VECS class engines. */ 179 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0); 180 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); 181 182 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ 183 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); 184 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0); 185 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0); 186 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0); 187 if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) 188 intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~0); 189 if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) 190 intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~0); 191 intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0); 192 if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) 193 intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0); 194 195 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); 196 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); 197 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0); 198 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0); 199} 200 201void gen11_gt_irq_postinstall(struct intel_gt *gt) 202{ 203 struct intel_uncore *uncore = gt->uncore; 204 u32 irqs = GT_RENDER_USER_INTERRUPT; 205 u32 dmask; 206 u32 smask; 207 208 if (!intel_uc_wants_guc_submission(>->uc)) 209 irqs |= GT_CS_MASTER_ERROR_INTERRUPT | 210 GT_CONTEXT_SWITCH_INTERRUPT | 211 GT_WAIT_SEMAPHORE_INTERRUPT; 212 213 dmask = irqs << 16 | irqs; 214 smask = irqs << 16; 215 216#ifdef notyet 217 BUILD_BUG_ON(irqs & 0xffff0000); 218#endif 219 220 /* Enable RCS, BCS, VCS and VECS class interrupts. */ 221 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask); 222 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask); 223 224 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ 225 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); 226 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask); 227 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask); 228 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask); 229 if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) 230 intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~dmask); 231 if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) 232 intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~dmask); 233 intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask); 234 if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) 235 intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask); 236 /* 237 * RPS interrupts will get enabled/disabled on demand when RPS itself 238 * is enabled/disabled. 239 */ 240 gt->pm_ier = 0x0; 241 gt->pm_imr = ~gt->pm_ier; 242 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); 243 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); 244 245 /* Same thing for GuC interrupts */ 246 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0); 247 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0); 248} 249 250void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) 251{ 252 if (gt_iir & GT_RENDER_USER_INTERRUPT) 253 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 254 gt_iir); 255 256 if (gt_iir & ILK_BSD_USER_INTERRUPT) 257 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 258 gt_iir); 259} 260 261static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) 262{ 263 if (!HAS_L3_DPF(gt->i915)) 264 return; 265 266 spin_lock(>->irq_lock); 267 gen5_gt_disable_irq(gt, GT_PARITY_ERROR(gt->i915)); 268 spin_unlock(>->irq_lock); 269 270 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) 271 gt->i915->l3_parity.which_slice |= 1 << 1; 272 273 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) 274 gt->i915->l3_parity.which_slice |= 1 << 0; 275 276 schedule_work(>->i915->l3_parity.error_work); 277} 278 279void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) 280{ 281 if (gt_iir & GT_RENDER_USER_INTERRUPT) 282 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 283 gt_iir); 284 285 if (gt_iir & GT_BSD_USER_INTERRUPT) 286 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 287 gt_iir >> 12); 288 289 if (gt_iir & GT_BLT_USER_INTERRUPT) 290 intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], 291 gt_iir >> 22); 292 293 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | 294 GT_BSD_CS_ERROR_INTERRUPT | 295 GT_CS_MASTER_ERROR_INTERRUPT)) 296 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); 297 298 if (gt_iir & GT_PARITY_ERROR(gt->i915)) 299 gen7_parity_error_irq_handler(gt, gt_iir); 300} 301 302void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl) 303{ 304 void __iomem * const regs = gt->uncore->regs; 305 u32 iir; 306 307 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { 308 iir = raw_reg_read(regs, GEN8_GT_IIR(0)); 309 if (likely(iir)) { 310 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 311 iir >> GEN8_RCS_IRQ_SHIFT); 312 intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], 313 iir >> GEN8_BCS_IRQ_SHIFT); 314 raw_reg_write(regs, GEN8_GT_IIR(0), iir); 315 } 316 } 317 318 if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) { 319 iir = raw_reg_read(regs, GEN8_GT_IIR(1)); 320 if (likely(iir)) { 321 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 322 iir >> GEN8_VCS0_IRQ_SHIFT); 323 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][1], 324 iir >> GEN8_VCS1_IRQ_SHIFT); 325 raw_reg_write(regs, GEN8_GT_IIR(1), iir); 326 } 327 } 328 329 if (master_ctl & GEN8_GT_VECS_IRQ) { 330 iir = raw_reg_read(regs, GEN8_GT_IIR(3)); 331 if (likely(iir)) { 332 intel_engine_cs_irq(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0], 333 iir >> GEN8_VECS_IRQ_SHIFT); 334 raw_reg_write(regs, GEN8_GT_IIR(3), iir); 335 } 336 } 337 338 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { 339 iir = raw_reg_read(regs, GEN8_GT_IIR(2)); 340 if (likely(iir)) { 341 gen6_rps_irq_handler(>->rps, iir); 342 guc_irq_handler(>->uc.guc, iir >> 16); 343 raw_reg_write(regs, GEN8_GT_IIR(2), iir); 344 } 345 } 346} 347 348void gen8_gt_irq_reset(struct intel_gt *gt) 349{ 350 struct intel_uncore *uncore = gt->uncore; 351 352 GEN8_IRQ_RESET_NDX(uncore, GT, 0); 353 GEN8_IRQ_RESET_NDX(uncore, GT, 1); 354 GEN8_IRQ_RESET_NDX(uncore, GT, 2); 355 GEN8_IRQ_RESET_NDX(uncore, GT, 3); 356} 357 358void gen8_gt_irq_postinstall(struct intel_gt *gt) 359{ 360 /* These are interrupts we'll toggle with the ring mask register */ 361 const u32 irqs = 362 GT_CS_MASTER_ERROR_INTERRUPT | 363 GT_RENDER_USER_INTERRUPT | 364 GT_CONTEXT_SWITCH_INTERRUPT | 365 GT_WAIT_SEMAPHORE_INTERRUPT; 366 const u32 gt_interrupts[] = { 367 irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT, 368 irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT, 369 0, 370 irqs << GEN8_VECS_IRQ_SHIFT, 371 }; 372 struct intel_uncore *uncore = gt->uncore; 373 374 gt->pm_ier = 0x0; 375 gt->pm_imr = ~gt->pm_ier; 376 GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]); 377 GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]); 378 /* 379 * RPS interrupts will get enabled/disabled on demand when RPS itself 380 * is enabled/disabled. Same wil be the case for GuC interrupts. 381 */ 382 GEN8_IRQ_INIT_NDX(uncore, GT, 2, gt->pm_imr, gt->pm_ier); 383 GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]); 384} 385 386static void gen5_gt_update_irq(struct intel_gt *gt, 387 u32 interrupt_mask, 388 u32 enabled_irq_mask) 389{ 390 lockdep_assert_held(>->irq_lock); 391 392 GEM_BUG_ON(enabled_irq_mask & ~interrupt_mask); 393 394 gt->gt_imr &= ~interrupt_mask; 395 gt->gt_imr |= (~enabled_irq_mask & interrupt_mask); 396 intel_uncore_write(gt->uncore, GTIMR, gt->gt_imr); 397} 398 399void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask) 400{ 401 gen5_gt_update_irq(gt, mask, mask); 402 intel_uncore_posting_read_fw(gt->uncore, GTIMR); 403} 404 405void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask) 406{ 407 gen5_gt_update_irq(gt, mask, 0); 408} 409 410void gen5_gt_irq_reset(struct intel_gt *gt) 411{ 412 struct intel_uncore *uncore = gt->uncore; 413 414 GEN3_IRQ_RESET(uncore, GT); 415 if (GRAPHICS_VER(gt->i915) >= 6) 416 GEN3_IRQ_RESET(uncore, GEN6_PM); 417} 418 419void gen5_gt_irq_postinstall(struct intel_gt *gt) 420{ 421 struct intel_uncore *uncore = gt->uncore; 422 u32 pm_irqs = 0; 423 u32 gt_irqs = 0; 424 425 gt->gt_imr = ~0; 426 if (HAS_L3_DPF(gt->i915)) { 427 /* L3 parity interrupt is always unmasked. */ 428 gt->gt_imr = ~GT_PARITY_ERROR(gt->i915); 429 gt_irqs |= GT_PARITY_ERROR(gt->i915); 430 } 431 432 gt_irqs |= GT_RENDER_USER_INTERRUPT; 433 if (GRAPHICS_VER(gt->i915) == 5) 434 gt_irqs |= ILK_BSD_USER_INTERRUPT; 435 else 436 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; 437 438 GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs); 439 440 if (GRAPHICS_VER(gt->i915) >= 6) { 441 /* 442 * RPS interrupts will get enabled/disabled on demand when RPS 443 * itself is enabled/disabled. 444 */ 445 if (HAS_ENGINE(gt, VECS0)) { 446 pm_irqs |= PM_VEBOX_USER_INTERRUPT; 447 gt->pm_ier |= PM_VEBOX_USER_INTERRUPT; 448 } 449 450 gt->pm_imr = 0xffffffff; 451 GEN3_IRQ_INIT(uncore, GEN6_PM, gt->pm_imr, pm_irqs); 452 } 453} 454