intel_psr.c revision 1.4
1/* 2 * Copyright �� 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24#include <drm/drm_atomic_helper.h> 25 26#include "display/intel_dp.h" 27 28#include "i915_drv.h" 29#include "intel_atomic.h" 30#include "intel_de.h" 31#include "intel_display_types.h" 32#include "intel_dp_aux.h" 33#include "intel_hdmi.h" 34#include "intel_psr.h" 35#include "intel_snps_phy.h" 36#include "intel_sprite.h" 37#include "skl_universal_plane.h" 38 39/** 40 * DOC: Panel Self Refresh (PSR/SRD) 41 * 42 * Since Haswell Display controller supports Panel Self-Refresh on display 43 * panels witch have a remote frame buffer (RFB) implemented according to PSR 44 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 45 * when system is idle but display is on as it eliminates display refresh 46 * request to DDR memory completely as long as the frame buffer for that 47 * display is unchanged. 48 * 49 * Panel Self Refresh must be supported by both Hardware (source) and 50 * Panel (sink). 51 * 52 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 53 * to power down the link and memory controller. For DSI panels the same idea 54 * is called "manual mode". 55 * 56 * The implementation uses the hardware-based PSR support which automatically 57 * enters/exits self-refresh mode. The hardware takes care of sending the 58 * required DP aux message and could even retrain the link (that part isn't 59 * enabled yet though). The hardware also keeps track of any frontbuffer 60 * changes to know when to exit self-refresh mode again. Unfortunately that 61 * part doesn't work too well, hence why the i915 PSR support uses the 62 * software frontbuffer tracking to make sure it doesn't miss a screen 63 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 64 * get called by the frontbuffer tracking code. Note that because of locking 65 * issues the self-refresh re-enable code is done from a work queue, which 66 * must be correctly synchronized/cancelled when shutting down the pipe." 67 * 68 * DC3CO (DC3 clock off) 69 * 70 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 71 * clock off automatically during PSR2 idle state. 72 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 73 * entry/exit allows the HW to enter a low-power state even when page flipping 74 * periodically (for instance a 30fps video playback scenario). 75 * 76 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 77 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 78 * frames, if no other flip occurs and the function above is executed, DC3CO is 79 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 80 * of another flip. 81 * Front buffer modifications do not trigger DC3CO activation on purpose as it 82 * would bring a lot of complexity and most of the moderns systems will only 83 * use page flips. 84 */ 85 86static bool psr_global_enabled(struct intel_dp *intel_dp) 87{ 88 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 89 90 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 91 case I915_PSR_DEBUG_DEFAULT: 92 return i915->params.enable_psr; 93 case I915_PSR_DEBUG_DISABLE: 94 return false; 95 default: 96 return true; 97 } 98} 99 100static bool psr2_global_enabled(struct intel_dp *intel_dp) 101{ 102 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 103 case I915_PSR_DEBUG_DISABLE: 104 case I915_PSR_DEBUG_FORCE_PSR1: 105 return false; 106 default: 107 return true; 108 } 109} 110 111static void psr_irq_control(struct intel_dp *intel_dp) 112{ 113 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 114 enum transcoder trans_shift; 115 i915_reg_t imr_reg; 116 u32 mask, val; 117 118 /* 119 * gen12+ has registers relative to transcoder and one per transcoder 120 * using the same bit definition: handle it as TRANSCODER_EDP to force 121 * 0 shift in bit definition 122 */ 123 if (DISPLAY_VER(dev_priv) >= 12) { 124 trans_shift = 0; 125 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 126 } else { 127 trans_shift = intel_dp->psr.transcoder; 128 imr_reg = EDP_PSR_IMR; 129 } 130 131 mask = EDP_PSR_ERROR(trans_shift); 132 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 133 mask |= EDP_PSR_POST_EXIT(trans_shift) | 134 EDP_PSR_PRE_ENTRY(trans_shift); 135 136 /* Warning: it is masking/setting reserved bits too */ 137 val = intel_de_read(dev_priv, imr_reg); 138 val &= ~EDP_PSR_TRANS_MASK(trans_shift); 139 val |= ~mask; 140 intel_de_write(dev_priv, imr_reg, val); 141} 142 143static void psr_event_print(struct drm_i915_private *i915, 144 u32 val, bool psr2_enabled) 145{ 146 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 147 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 148 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 149 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 150 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 151 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 152 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 153 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 154 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 155 if (val & PSR_EVENT_GRAPHICS_RESET) 156 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 157 if (val & PSR_EVENT_PCH_INTERRUPT) 158 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 159 if (val & PSR_EVENT_MEMORY_UP) 160 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 161 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 162 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 163 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 164 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 165 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 166 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 167 if (val & PSR_EVENT_REGISTER_UPDATE) 168 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 169 if (val & PSR_EVENT_HDCP_ENABLE) 170 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 171 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 172 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 173 if (val & PSR_EVENT_VBI_ENABLE) 174 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 175 if (val & PSR_EVENT_LPSP_MODE_EXIT) 176 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 177 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 178 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 179} 180 181void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 182{ 183 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 184 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 185 ktime_t time_ns = ktime_get(); 186 enum transcoder trans_shift; 187 i915_reg_t imr_reg; 188 189 if (DISPLAY_VER(dev_priv) >= 12) { 190 trans_shift = 0; 191 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 192 } else { 193 trans_shift = intel_dp->psr.transcoder; 194 imr_reg = EDP_PSR_IMR; 195 } 196 197 if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { 198 intel_dp->psr.last_entry_attempt = time_ns; 199 drm_dbg_kms(&dev_priv->drm, 200 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 201 transcoder_name(cpu_transcoder)); 202 } 203 204 if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { 205 intel_dp->psr.last_exit = time_ns; 206 drm_dbg_kms(&dev_priv->drm, 207 "[transcoder %s] PSR exit completed\n", 208 transcoder_name(cpu_transcoder)); 209 210 if (DISPLAY_VER(dev_priv) >= 9) { 211 u32 val = intel_de_read(dev_priv, 212 PSR_EVENT(cpu_transcoder)); 213 bool psr2_enabled = intel_dp->psr.psr2_enabled; 214 215 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 216 val); 217 psr_event_print(dev_priv, val, psr2_enabled); 218 } 219 } 220 221 if (psr_iir & EDP_PSR_ERROR(trans_shift)) { 222 u32 val; 223 224 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 225 transcoder_name(cpu_transcoder)); 226 227 intel_dp->psr.irq_aux_error = true; 228 229 /* 230 * If this interruption is not masked it will keep 231 * interrupting so fast that it prevents the scheduled 232 * work to run. 233 * Also after a PSR error, we don't want to arm PSR 234 * again so we don't care about unmask the interruption 235 * or unset irq_aux_error. 236 */ 237 val = intel_de_read(dev_priv, imr_reg); 238 val |= EDP_PSR_ERROR(trans_shift); 239 intel_de_write(dev_priv, imr_reg, val); 240 241 schedule_work(&intel_dp->psr.work); 242 } 243} 244 245static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 246{ 247 u8 alpm_caps = 0; 248 249 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 250 &alpm_caps) != 1) 251 return false; 252 return alpm_caps & DP_ALPM_CAP; 253} 254 255static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 256{ 257 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 258 u8 val = 8; /* assume the worst if we can't read the value */ 259 260 if (drm_dp_dpcd_readb(&intel_dp->aux, 261 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 262 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 263 else 264 drm_dbg_kms(&i915->drm, 265 "Unable to get sink synchronization latency, assuming 8 frames\n"); 266 return val; 267} 268 269static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 270{ 271 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 272 ssize_t r; 273 u16 w; 274 u8 y; 275 276 /* If sink don't have specific granularity requirements set legacy ones */ 277 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 278 /* As PSR2 HW sends full lines, we do not care about x granularity */ 279 w = 4; 280 y = 4; 281 goto exit; 282 } 283 284 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); 285 if (r != 2) 286 drm_dbg_kms(&i915->drm, 287 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 288 /* 289 * Spec says that if the value read is 0 the default granularity should 290 * be used instead. 291 */ 292 if (r != 2 || w == 0) 293 w = 4; 294 295 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 296 if (r != 1) { 297 drm_dbg_kms(&i915->drm, 298 "Unable to read DP_PSR2_SU_Y_GRANULARITY\n"); 299 y = 4; 300 } 301 if (y == 0) 302 y = 1; 303 304exit: 305 intel_dp->psr.su_w_granularity = w; 306 intel_dp->psr.su_y_granularity = y; 307} 308 309void intel_psr_init_dpcd(struct intel_dp *intel_dp) 310{ 311 struct drm_i915_private *dev_priv = 312 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 313 314 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 315 sizeof(intel_dp->psr_dpcd)); 316 317 if (!intel_dp->psr_dpcd[0]) 318 return; 319 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 320 intel_dp->psr_dpcd[0]); 321 322 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 323 drm_dbg_kms(&dev_priv->drm, 324 "PSR support not currently available for this panel\n"); 325 return; 326 } 327 328 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 329 drm_dbg_kms(&dev_priv->drm, 330 "Panel lacks power state control, PSR cannot be enabled\n"); 331 return; 332 } 333 334 intel_dp->psr.sink_support = true; 335 intel_dp->psr.sink_sync_latency = 336 intel_dp_get_sink_sync_latency(intel_dp); 337 338 if (DISPLAY_VER(dev_priv) >= 9 && 339 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 340 bool y_req = intel_dp->psr_dpcd[1] & 341 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 342 bool alpm = intel_dp_get_alpm_status(intel_dp); 343 344 /* 345 * All panels that supports PSR version 03h (PSR2 + 346 * Y-coordinate) can handle Y-coordinates in VSC but we are 347 * only sure that it is going to be used when required by the 348 * panel. This way panel is capable to do selective update 349 * without a aux frame sync. 350 * 351 * To support PSR version 02h and PSR version 03h without 352 * Y-coordinate requirement panels we would need to enable 353 * GTC first. 354 */ 355 intel_dp->psr.sink_psr2_support = y_req && alpm; 356 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 357 intel_dp->psr.sink_psr2_support ? "" : "not "); 358 359 if (intel_dp->psr.sink_psr2_support) { 360 intel_dp->psr.colorimetry_support = 361 intel_dp_get_colorimetry_status(intel_dp); 362 intel_dp_get_su_granularity(intel_dp); 363 } 364 } 365} 366 367static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 368{ 369 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 370 u32 aux_clock_divider, aux_ctl; 371 int i; 372 static const u8 aux_msg[] = { 373 [0] = DP_AUX_NATIVE_WRITE << 4, 374 [1] = DP_SET_POWER >> 8, 375 [2] = DP_SET_POWER & 0xff, 376 [3] = 1 - 1, 377 [4] = DP_SET_POWER_D0, 378 }; 379 u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | 380 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 381 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 382 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 383 384 BUILD_BUG_ON(sizeof(aux_msg) > 20); 385 for (i = 0; i < sizeof(aux_msg); i += 4) 386 intel_de_write(dev_priv, 387 EDP_PSR_AUX_DATA(intel_dp->psr.transcoder, i >> 2), 388 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); 389 390 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 391 392 /* Start with bits set for DDI_AUX_CTL register */ 393 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 394 aux_clock_divider); 395 396 /* Select only valid bits for SRD_AUX_CTL */ 397 aux_ctl &= psr_aux_mask; 398 intel_de_write(dev_priv, EDP_PSR_AUX_CTL(intel_dp->psr.transcoder), 399 aux_ctl); 400} 401 402static void intel_psr_enable_sink(struct intel_dp *intel_dp) 403{ 404 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 405 u8 dpcd_val = DP_PSR_ENABLE; 406 407 /* Enable ALPM at sink for psr2 */ 408 if (intel_dp->psr.psr2_enabled) { 409 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 410 DP_ALPM_ENABLE | 411 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 412 413 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 414 } else { 415 if (intel_dp->psr.link_standby) 416 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 417 418 if (DISPLAY_VER(dev_priv) >= 8) 419 dpcd_val |= DP_PSR_CRC_VERIFICATION; 420 } 421 422 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 423 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 424 425 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 426 427 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 428} 429 430static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 431{ 432 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 433 u32 val = 0; 434 435 if (DISPLAY_VER(dev_priv) >= 11) 436 val |= EDP_PSR_TP4_TIME_0US; 437 438 if (dev_priv->params.psr_safest_params) { 439 val |= EDP_PSR_TP1_TIME_2500us; 440 val |= EDP_PSR_TP2_TP3_TIME_2500us; 441 goto check_tp3_sel; 442 } 443 444 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) 445 val |= EDP_PSR_TP1_TIME_0us; 446 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) 447 val |= EDP_PSR_TP1_TIME_100us; 448 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) 449 val |= EDP_PSR_TP1_TIME_500us; 450 else 451 val |= EDP_PSR_TP1_TIME_2500us; 452 453 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) 454 val |= EDP_PSR_TP2_TP3_TIME_0us; 455 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) 456 val |= EDP_PSR_TP2_TP3_TIME_100us; 457 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) 458 val |= EDP_PSR_TP2_TP3_TIME_500us; 459 else 460 val |= EDP_PSR_TP2_TP3_TIME_2500us; 461 462check_tp3_sel: 463 if (intel_dp_source_supports_hbr2(intel_dp) && 464 drm_dp_tps3_supported(intel_dp->dpcd)) 465 val |= EDP_PSR_TP1_TP3_SEL; 466 else 467 val |= EDP_PSR_TP1_TP2_SEL; 468 469 return val; 470} 471 472static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 473{ 474 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 475 int idle_frames; 476 477 /* Let's use 6 as the minimum to cover all known cases including the 478 * off-by-one issue that HW has in some cases. 479 */ 480 idle_frames = max(6, dev_priv->vbt.psr.idle_frames); 481 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 482 483 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 484 idle_frames = 0xf; 485 486 return idle_frames; 487} 488 489static void hsw_activate_psr1(struct intel_dp *intel_dp) 490{ 491 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 492 u32 max_sleep_time = 0x1f; 493 u32 val = EDP_PSR_ENABLE; 494 495 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 496 497 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 498 if (IS_HASWELL(dev_priv)) 499 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 500 501 if (intel_dp->psr.link_standby) 502 val |= EDP_PSR_LINK_STANDBY; 503 504 val |= intel_psr1_get_tp_time(intel_dp); 505 506 if (DISPLAY_VER(dev_priv) >= 8) 507 val |= EDP_PSR_CRC_ENABLE; 508 509 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & 510 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 511 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); 512} 513 514static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 515{ 516 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 517 u32 val = 0; 518 519 if (dev_priv->params.psr_safest_params) 520 return EDP_PSR2_TP2_TIME_2500us; 521 522 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 523 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 524 val |= EDP_PSR2_TP2_TIME_50us; 525 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 526 val |= EDP_PSR2_TP2_TIME_100us; 527 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 528 val |= EDP_PSR2_TP2_TIME_500us; 529 else 530 val |= EDP_PSR2_TP2_TIME_2500us; 531 532 return val; 533} 534 535static void hsw_activate_psr2(struct intel_dp *intel_dp) 536{ 537 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 538 u32 val = EDP_PSR2_ENABLE; 539 540 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 541 542 if (!IS_ALDERLAKE_P(dev_priv)) 543 val |= EDP_SU_TRACK_ENABLE; 544 545 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) 546 val |= EDP_Y_COORDINATE_ENABLE; 547 548 val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1); 549 val |= intel_psr2_get_tp_time(intel_dp); 550 551 /* Wa_22012278275:adl-p */ 552 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { 553 static const u8 map[] = { 554 2, /* 5 lines */ 555 1, /* 6 lines */ 556 0, /* 7 lines */ 557 3, /* 8 lines */ 558 6, /* 9 lines */ 559 5, /* 10 lines */ 560 4, /* 11 lines */ 561 7, /* 12 lines */ 562 }; 563 /* 564 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 565 * comments bellow for more information 566 */ 567 u32 tmp, lines = 7; 568 569 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 570 571 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 572 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT; 573 val |= tmp; 574 575 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 576 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT; 577 val |= tmp; 578 } else if (DISPLAY_VER(dev_priv) >= 12) { 579 /* 580 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default 581 * values from BSpec. In order to setting an optimal power 582 * consumption, lower than 4k resoluition mode needs to decrese 583 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution 584 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. 585 */ 586 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 587 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); 588 val |= TGL_EDP_PSR2_FAST_WAKE(7); 589 } else if (DISPLAY_VER(dev_priv) >= 9) { 590 val |= EDP_PSR2_IO_BUFFER_WAKE(7); 591 val |= EDP_PSR2_FAST_WAKE(7); 592 } 593 594 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 595 val |= EDP_PSR2_SU_SDP_SCANLINE; 596 597 if (intel_dp->psr.psr2_sel_fetch_enabled) { 598 /* Wa_1408330847 */ 599 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 600 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 601 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 602 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 603 604 intel_de_write(dev_priv, 605 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 606 PSR2_MAN_TRK_CTL_ENABLE); 607 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 608 intel_de_write(dev_priv, 609 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); 610 } 611 612 /* 613 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 614 * recommending keep this bit unset while PSR2 is enabled. 615 */ 616 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); 617 618 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 619} 620 621static bool 622transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 623{ 624 if (DISPLAY_VER(dev_priv) < 9) 625 return false; 626 else if (DISPLAY_VER(dev_priv) >= 12) 627 return trans == TRANSCODER_A; 628 else 629 return trans == TRANSCODER_EDP; 630} 631 632static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 633{ 634 if (!cstate || !cstate->hw.active) 635 return 0; 636 637 return DIV_ROUND_UP(1000 * 1000, 638 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 639} 640 641static void psr2_program_idle_frames(struct intel_dp *intel_dp, 642 u32 idle_frames) 643{ 644 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 645 u32 val; 646 647 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 648 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); 649 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 650 val |= idle_frames; 651 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 652} 653 654static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 655{ 656 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 657 658 psr2_program_idle_frames(intel_dp, 0); 659 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 660} 661 662static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 663{ 664 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 665 666 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 667 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 668} 669 670static void tgl_dc3co_disable_work(struct work_struct *work) 671{ 672 struct intel_dp *intel_dp = 673 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 674 675 mutex_lock(&intel_dp->psr.lock); 676 /* If delayed work is pending, it is not idle */ 677 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 678 goto unlock; 679 680 tgl_psr2_disable_dc3co(intel_dp); 681unlock: 682 mutex_unlock(&intel_dp->psr.lock); 683} 684 685static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 686{ 687 if (!intel_dp->psr.dc3co_exitline) 688 return; 689 690 cancel_delayed_work(&intel_dp->psr.dc3co_work); 691 /* Before PSR2 exit disallow dc3co*/ 692 tgl_psr2_disable_dc3co(intel_dp); 693} 694 695static bool 696dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 697 struct intel_crtc_state *crtc_state) 698{ 699 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 700 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 701 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 702 enum port port = dig_port->base.port; 703 704 if (IS_ALDERLAKE_P(dev_priv)) 705 return pipe <= PIPE_B && port <= PORT_B; 706 else 707 return pipe == PIPE_A && port == PORT_A; 708} 709 710static void 711tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 712 struct intel_crtc_state *crtc_state) 713{ 714 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 715 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 716 u32 exit_scanlines; 717 718 /* 719 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 720 * disable DC3CO until the changed dc3co activating/deactivating sequence 721 * is applied. B.Specs:49196 722 */ 723 return; 724 725 /* 726 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 727 * TODO: when the issue is addressed, this restriction should be removed. 728 */ 729 if (crtc_state->enable_psr2_sel_fetch) 730 return; 731 732 if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO)) 733 return; 734 735 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 736 return; 737 738 /* Wa_16011303918:adl-p */ 739 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 740 return; 741 742 /* 743 * DC3CO Exit time 200us B.Spec 49196 744 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 745 */ 746 exit_scanlines = 747 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 748 749 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 750 return; 751 752 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 753} 754 755static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 756 struct intel_crtc_state *crtc_state) 757{ 758 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 759 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 760 struct intel_plane_state *plane_state; 761 struct intel_plane *plane; 762 int i; 763 764 if (!dev_priv->params.enable_psr2_sel_fetch && 765 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 766 drm_dbg_kms(&dev_priv->drm, 767 "PSR2 sel fetch not enabled, disabled by parameter\n"); 768 return false; 769 } 770 771 if (crtc_state->uapi.async_flip) { 772 drm_dbg_kms(&dev_priv->drm, 773 "PSR2 sel fetch not enabled, async flip enabled\n"); 774 return false; 775 } 776 777 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 778 if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) { 779 drm_dbg_kms(&dev_priv->drm, 780 "PSR2 sel fetch not enabled, plane rotated\n"); 781 return false; 782 } 783 } 784 785 /* Wa_14010254185 Wa_14010103792 */ 786 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 787 drm_dbg_kms(&dev_priv->drm, 788 "PSR2 sel fetch not enabled, missing the implementation of WAs\n"); 789 return false; 790 } 791 792 return crtc_state->enable_psr2_sel_fetch = true; 793} 794 795static bool psr2_granularity_check(struct intel_dp *intel_dp, 796 struct intel_crtc_state *crtc_state) 797{ 798 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 799 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 800 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 801 u16 y_granularity = 0; 802 803 /* PSR2 HW only send full lines so we only need to validate the width */ 804 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) 805 return false; 806 807 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) 808 return false; 809 810 /* HW tracking is only aligned to 4 lines */ 811 if (!crtc_state->enable_psr2_sel_fetch) 812 return intel_dp->psr.su_y_granularity == 4; 813 814 /* 815 * adl_p has 1 line granularity. For other platforms with SW tracking we 816 * can adjust the y coordinates to match sink requirement if multiple of 817 * 4. 818 */ 819 if (IS_ALDERLAKE_P(dev_priv)) 820 y_granularity = intel_dp->psr.su_y_granularity; 821 else if (intel_dp->psr.su_y_granularity <= 2) 822 y_granularity = 4; 823 else if ((intel_dp->psr.su_y_granularity % 4) == 0) 824 y_granularity = intel_dp->psr.su_y_granularity; 825 826 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 827 return false; 828 829 crtc_state->su_y_granularity = y_granularity; 830 return true; 831} 832 833static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 834 struct intel_crtc_state *crtc_state) 835{ 836 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 837 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 838 u32 hblank_total, hblank_ns, req_ns; 839 840 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 841 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 842 843 /* From spec: (72 / number of lanes) * 1000 / symbol clock frequency MHz */ 844 req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000); 845 846 if ((hblank_ns - req_ns) > 100) 847 return true; 848 849 if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 850 return false; 851 852 crtc_state->req_psr2_sdp_prior_scanline = true; 853 return true; 854} 855 856static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 857 struct intel_crtc_state *crtc_state) 858{ 859 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 860 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 861 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 862 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 863 864 if (!intel_dp->psr.sink_psr2_support) 865 return false; 866 867 /* JSL and EHL only supports eDP 1.3 */ 868 if (IS_JSL_EHL(dev_priv)) { 869 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); 870 return false; 871 } 872 873 /* Wa_16011181250 */ 874 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) || 875 IS_DG2(dev_priv)) { 876 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); 877 return false; 878 } 879 880 /* 881 * We are missing the implementation of some workarounds to enabled PSR2 882 * in Alderlake_P, until ready PSR2 should be kept disabled. 883 */ 884 if (IS_ALDERLAKE_P(dev_priv)) { 885 drm_dbg_kms(&dev_priv->drm, "PSR2 is missing the implementation of workarounds\n"); 886 return false; 887 } 888 889 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 890 drm_dbg_kms(&dev_priv->drm, 891 "PSR2 not supported in transcoder %s\n", 892 transcoder_name(crtc_state->cpu_transcoder)); 893 return false; 894 } 895 896 if (!psr2_global_enabled(intel_dp)) { 897 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 898 return false; 899 } 900 901 /* 902 * DSC and PSR2 cannot be enabled simultaneously. If a requested 903 * resolution requires DSC to be enabled, priority is given to DSC 904 * over PSR2. 905 */ 906 if (crtc_state->dsc.compression_enable) { 907 drm_dbg_kms(&dev_priv->drm, 908 "PSR2 cannot be enabled since DSC is enabled\n"); 909 return false; 910 } 911 912 if (crtc_state->crc_enabled) { 913 drm_dbg_kms(&dev_priv->drm, 914 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 915 return false; 916 } 917 918 if (DISPLAY_VER(dev_priv) >= 12) { 919 psr_max_h = 5120; 920 psr_max_v = 3200; 921 max_bpp = 30; 922 } else if (DISPLAY_VER(dev_priv) >= 10) { 923 psr_max_h = 4096; 924 psr_max_v = 2304; 925 max_bpp = 24; 926 } else if (DISPLAY_VER(dev_priv) == 9) { 927 psr_max_h = 3640; 928 psr_max_v = 2304; 929 max_bpp = 24; 930 } 931 932 if (crtc_state->pipe_bpp > max_bpp) { 933 drm_dbg_kms(&dev_priv->drm, 934 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 935 crtc_state->pipe_bpp, max_bpp); 936 return false; 937 } 938 939 /* Wa_16011303918:adl-p */ 940 if (crtc_state->vrr.enable && 941 IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 942 drm_dbg_kms(&dev_priv->drm, 943 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 944 return false; 945 } 946 947 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 948 drm_dbg_kms(&dev_priv->drm, 949 "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n"); 950 return false; 951 } 952 953 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 954 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 955 !HAS_PSR_HW_TRACKING(dev_priv)) { 956 drm_dbg_kms(&dev_priv->drm, 957 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 958 return false; 959 } 960 } 961 962 /* Wa_2209313811 */ 963 if (!crtc_state->enable_psr2_sel_fetch && 964 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 965 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n"); 966 goto unsupported; 967 } 968 969 if (!psr2_granularity_check(intel_dp, crtc_state)) { 970 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); 971 goto unsupported; 972 } 973 974 if (!crtc_state->enable_psr2_sel_fetch && 975 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 976 drm_dbg_kms(&dev_priv->drm, 977 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 978 crtc_hdisplay, crtc_vdisplay, 979 psr_max_h, psr_max_v); 980 goto unsupported; 981 } 982 983 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 984 return true; 985 986unsupported: 987 crtc_state->enable_psr2_sel_fetch = false; 988 return false; 989} 990 991void intel_psr_compute_config(struct intel_dp *intel_dp, 992 struct intel_crtc_state *crtc_state) 993{ 994 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 995 const struct drm_display_mode *adjusted_mode = 996 &crtc_state->hw.adjusted_mode; 997 int psr_setup_time; 998 999 /* 1000 * Current PSR panels dont work reliably with VRR enabled 1001 * So if VRR is enabled, do not enable PSR. 1002 */ 1003 if (crtc_state->vrr.enable) 1004 return; 1005 1006 if (!CAN_PSR(intel_dp)) 1007 return; 1008 1009 if (!psr_global_enabled(intel_dp)) { 1010 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 1011 return; 1012 } 1013 1014 if (intel_dp->psr.sink_not_reliable) { 1015 drm_dbg_kms(&dev_priv->drm, 1016 "PSR sink implementation is not reliable\n"); 1017 return; 1018 } 1019 1020 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1021 drm_dbg_kms(&dev_priv->drm, 1022 "PSR condition failed: Interlaced mode enabled\n"); 1023 return; 1024 } 1025 1026 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 1027 if (psr_setup_time < 0) { 1028 drm_dbg_kms(&dev_priv->drm, 1029 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1030 intel_dp->psr_dpcd[1]); 1031 return; 1032 } 1033 1034 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1035 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1036 drm_dbg_kms(&dev_priv->drm, 1037 "PSR condition failed: PSR setup time (%d us) too long\n", 1038 psr_setup_time); 1039 return; 1040 } 1041 1042 crtc_state->has_psr = true; 1043 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 1044 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1045} 1046 1047void intel_psr_get_config(struct intel_encoder *encoder, 1048 struct intel_crtc_state *pipe_config) 1049{ 1050 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1051 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1052 struct intel_dp *intel_dp; 1053 u32 val; 1054 1055 if (!dig_port) 1056 return; 1057 1058 intel_dp = &dig_port->dp; 1059 if (!CAN_PSR(intel_dp)) 1060 return; 1061 1062 mutex_lock(&intel_dp->psr.lock); 1063 if (!intel_dp->psr.enabled) 1064 goto unlock; 1065 1066 /* 1067 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1068 * enabled/disabled because of frontbuffer tracking and others. 1069 */ 1070 pipe_config->has_psr = true; 1071 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; 1072 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1073 1074 if (!intel_dp->psr.psr2_enabled) 1075 goto unlock; 1076 1077 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 1078 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 1079 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1080 pipe_config->enable_psr2_sel_fetch = true; 1081 } 1082 1083 if (DISPLAY_VER(dev_priv) >= 12) { 1084 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); 1085 val &= EXITLINE_MASK; 1086 pipe_config->dc3co_exitline = val; 1087 } 1088unlock: 1089 mutex_unlock(&intel_dp->psr.lock); 1090} 1091 1092static void intel_psr_activate(struct intel_dp *intel_dp) 1093{ 1094 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1095 enum transcoder transcoder = intel_dp->psr.transcoder; 1096 1097 if (transcoder_has_psr2(dev_priv, transcoder)) 1098 drm_WARN_ON(&dev_priv->drm, 1099 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); 1100 1101 drm_WARN_ON(&dev_priv->drm, 1102 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); 1103 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); 1104 lockdep_assert_held(&intel_dp->psr.lock); 1105 1106 /* psr1 and psr2 are mutually exclusive.*/ 1107 if (intel_dp->psr.psr2_enabled) 1108 hsw_activate_psr2(intel_dp); 1109 else 1110 hsw_activate_psr1(intel_dp); 1111 1112 intel_dp->psr.active = true; 1113} 1114 1115static void intel_psr_enable_source(struct intel_dp *intel_dp) 1116{ 1117 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1118 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1119 u32 mask; 1120 1121 /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ 1122 * use hardcoded values PSR AUX transactions 1123 */ 1124 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1125 hsw_psr_setup_aux(intel_dp); 1126 1127 if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) { 1128 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); 1129 u32 chicken = intel_de_read(dev_priv, reg); 1130 1131 chicken |= PSR2_VSC_ENABLE_PROG_HEADER | 1132 PSR2_ADD_VERTICAL_LINE_COUNT; 1133 intel_de_write(dev_priv, reg, chicken); 1134 } 1135 1136 /* 1137 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 1138 * mask LPSP to avoid dependency on other drivers that might block 1139 * runtime_pm besides preventing other hw tracking issues now we 1140 * can rely on frontbuffer tracking. 1141 */ 1142 mask = EDP_PSR_DEBUG_MASK_MEMUP | 1143 EDP_PSR_DEBUG_MASK_HPD | 1144 EDP_PSR_DEBUG_MASK_LPSP | 1145 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 1146 1147 if (DISPLAY_VER(dev_priv) < 11) 1148 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 1149 1150 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), 1151 mask); 1152 1153 psr_irq_control(intel_dp); 1154 1155 if (intel_dp->psr.dc3co_exitline) { 1156 u32 val; 1157 1158 /* 1159 * TODO: if future platforms supports DC3CO in more than one 1160 * transcoder, EXITLINE will need to be unset when disabling PSR 1161 */ 1162 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 1163 val &= ~EXITLINE_MASK; 1164 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT; 1165 val |= EXITLINE_ENABLE; 1166 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 1167 } 1168 1169 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 1170 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 1171 intel_dp->psr.psr2_sel_fetch_enabled ? 1172 IGNORE_PSR2_HW_TRACKING : 0); 1173 1174 /* Wa_16011168373:adl-p */ 1175 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) && 1176 intel_dp->psr.psr2_enabled) 1177 intel_de_rmw(dev_priv, 1178 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1179 TRANS_SET_CONTEXT_LATENCY_MASK, 1180 TRANS_SET_CONTEXT_LATENCY_VALUE(1)); 1181} 1182 1183static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 1184{ 1185 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1186 u32 val; 1187 1188 /* 1189 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 1190 * will still keep the error set even after the reset done in the 1191 * irq_preinstall and irq_uninstall hooks. 1192 * And enabling in this situation cause the screen to freeze in the 1193 * first time that PSR HW tries to activate so lets keep PSR disabled 1194 * to avoid any rendering problems. 1195 */ 1196 if (DISPLAY_VER(dev_priv) >= 12) { 1197 val = intel_de_read(dev_priv, 1198 TRANS_PSR_IIR(intel_dp->psr.transcoder)); 1199 val &= EDP_PSR_ERROR(0); 1200 } else { 1201 val = intel_de_read(dev_priv, EDP_PSR_IIR); 1202 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder); 1203 } 1204 if (val) { 1205 intel_dp->psr.sink_not_reliable = true; 1206 drm_dbg_kms(&dev_priv->drm, 1207 "PSR interruption error set, not enabling PSR\n"); 1208 return false; 1209 } 1210 1211 return true; 1212} 1213 1214static void intel_psr_enable_locked(struct intel_dp *intel_dp, 1215 const struct intel_crtc_state *crtc_state, 1216 const struct drm_connector_state *conn_state) 1217{ 1218 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1219 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1220 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 1221 struct intel_encoder *encoder = &dig_port->base; 1222 u32 val; 1223 1224 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); 1225 1226 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; 1227 intel_dp->psr.busy_frontbuffer_bits = 0; 1228 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1229 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 1230 /* DC5/DC6 requires at least 6 idle frames */ 1231 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 1232 intel_dp->psr.dc3co_exit_delay = val; 1233 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 1234 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 1235 intel_dp->psr.req_psr2_sdp_prior_scanline = 1236 crtc_state->req_psr2_sdp_prior_scanline; 1237 1238 if (!psr_interrupt_error_check(intel_dp)) 1239 return; 1240 1241 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 1242 intel_dp->psr.psr2_enabled ? "2" : "1"); 1243 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 1244 &intel_dp->psr.vsc); 1245 intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc); 1246 intel_snps_phy_update_psr_power_state(dev_priv, phy, true); 1247 intel_psr_enable_sink(intel_dp); 1248 intel_psr_enable_source(intel_dp); 1249 intel_dp->psr.enabled = true; 1250 intel_dp->psr.paused = false; 1251 1252 intel_psr_activate(intel_dp); 1253} 1254 1255/** 1256 * intel_psr_enable - Enable PSR 1257 * @intel_dp: Intel DP 1258 * @crtc_state: new CRTC state 1259 * @conn_state: new CONNECTOR state 1260 * 1261 * This function can only be called after the pipe is fully trained and enabled. 1262 */ 1263void intel_psr_enable(struct intel_dp *intel_dp, 1264 const struct intel_crtc_state *crtc_state, 1265 const struct drm_connector_state *conn_state) 1266{ 1267 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1268 1269 if (!CAN_PSR(intel_dp)) 1270 return; 1271 1272 if (!crtc_state->has_psr) 1273 return; 1274 1275 drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp); 1276 1277 mutex_lock(&intel_dp->psr.lock); 1278 intel_psr_enable_locked(intel_dp, crtc_state, conn_state); 1279 mutex_unlock(&intel_dp->psr.lock); 1280} 1281 1282static void intel_psr_exit(struct intel_dp *intel_dp) 1283{ 1284 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1285 u32 val; 1286 1287 if (!intel_dp->psr.active) { 1288 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { 1289 val = intel_de_read(dev_priv, 1290 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1291 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1292 } 1293 1294 val = intel_de_read(dev_priv, 1295 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1296 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1297 1298 return; 1299 } 1300 1301 if (intel_dp->psr.psr2_enabled) { 1302 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 1303 val = intel_de_read(dev_priv, 1304 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1305 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1306 val &= ~EDP_PSR2_ENABLE; 1307 intel_de_write(dev_priv, 1308 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 1309 } else { 1310 val = intel_de_read(dev_priv, 1311 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1312 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1313 val &= ~EDP_PSR_ENABLE; 1314 intel_de_write(dev_priv, 1315 EDP_PSR_CTL(intel_dp->psr.transcoder), val); 1316 } 1317 intel_dp->psr.active = false; 1318} 1319 1320static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 1321{ 1322 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1323 i915_reg_t psr_status; 1324 u32 psr_status_mask; 1325 1326 if (intel_dp->psr.psr2_enabled) { 1327 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1328 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1329 } else { 1330 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1331 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1332 } 1333 1334 /* Wait till PSR is idle */ 1335 if (intel_de_wait_for_clear(dev_priv, psr_status, 1336 psr_status_mask, 2000)) 1337 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1338} 1339 1340static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1341{ 1342 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1343 enum phy phy = intel_port_to_phy(dev_priv, 1344 dp_to_dig_port(intel_dp)->base.port); 1345 1346 lockdep_assert_held(&intel_dp->psr.lock); 1347 1348 if (!intel_dp->psr.enabled) 1349 return; 1350 1351 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1352 intel_dp->psr.psr2_enabled ? "2" : "1"); 1353 1354 intel_psr_exit(intel_dp); 1355 intel_psr_wait_exit_locked(intel_dp); 1356 1357 /* Wa_1408330847 */ 1358 if (intel_dp->psr.psr2_sel_fetch_enabled && 1359 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1360 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1361 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1362 1363 /* Wa_16011168373:adl-p */ 1364 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) && 1365 intel_dp->psr.psr2_enabled) 1366 intel_de_rmw(dev_priv, 1367 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1368 TRANS_SET_CONTEXT_LATENCY_MASK, 0); 1369 1370 intel_snps_phy_update_psr_power_state(dev_priv, phy, false); 1371 1372 /* Disable PSR on Sink */ 1373 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1374 1375 if (intel_dp->psr.psr2_enabled) 1376 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1377 1378 intel_dp->psr.enabled = false; 1379} 1380 1381/** 1382 * intel_psr_disable - Disable PSR 1383 * @intel_dp: Intel DP 1384 * @old_crtc_state: old CRTC state 1385 * 1386 * This function needs to be called before disabling pipe. 1387 */ 1388void intel_psr_disable(struct intel_dp *intel_dp, 1389 const struct intel_crtc_state *old_crtc_state) 1390{ 1391 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1392 1393 if (!old_crtc_state->has_psr) 1394 return; 1395 1396 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) 1397 return; 1398 1399 mutex_lock(&intel_dp->psr.lock); 1400 1401 intel_psr_disable_locked(intel_dp); 1402 1403 mutex_unlock(&intel_dp->psr.lock); 1404 cancel_work_sync(&intel_dp->psr.work); 1405 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 1406} 1407 1408/** 1409 * intel_psr_pause - Pause PSR 1410 * @intel_dp: Intel DP 1411 * 1412 * This function need to be called after enabling psr. 1413 */ 1414void intel_psr_pause(struct intel_dp *intel_dp) 1415{ 1416 struct intel_psr *psr = &intel_dp->psr; 1417 1418 if (!CAN_PSR(intel_dp)) 1419 return; 1420 1421 mutex_lock(&psr->lock); 1422 1423 if (!psr->enabled) { 1424 mutex_unlock(&psr->lock); 1425 return; 1426 } 1427 1428 intel_psr_exit(intel_dp); 1429 intel_psr_wait_exit_locked(intel_dp); 1430 psr->paused = true; 1431 1432 mutex_unlock(&psr->lock); 1433 1434 cancel_work_sync(&psr->work); 1435 cancel_delayed_work_sync(&psr->dc3co_work); 1436} 1437 1438/** 1439 * intel_psr_resume - Resume PSR 1440 * @intel_dp: Intel DP 1441 * 1442 * This function need to be called after pausing psr. 1443 */ 1444void intel_psr_resume(struct intel_dp *intel_dp) 1445{ 1446 struct intel_psr *psr = &intel_dp->psr; 1447 1448 if (!CAN_PSR(intel_dp)) 1449 return; 1450 1451 mutex_lock(&psr->lock); 1452 1453 if (!psr->paused) 1454 goto unlock; 1455 1456 psr->paused = false; 1457 intel_psr_activate(intel_dp); 1458 1459unlock: 1460 mutex_unlock(&psr->lock); 1461} 1462 1463static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) 1464{ 1465 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1466 1467 if (DISPLAY_VER(dev_priv) >= 9) 1468 /* 1469 * Display WA #0884: skl+ 1470 * This documented WA for bxt can be safely applied 1471 * broadly so we can force HW tracking to exit PSR 1472 * instead of disabling and re-enabling. 1473 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1474 * but it makes more sense write to the current active 1475 * pipe. 1476 */ 1477 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 1478 else 1479 /* 1480 * A write to CURSURFLIVE do not cause HW tracking to exit PSR 1481 * on older gens so doing the manual exit instead. 1482 */ 1483 intel_psr_exit(intel_dp); 1484} 1485 1486void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1487 const struct intel_crtc_state *crtc_state, 1488 const struct intel_plane_state *plane_state, 1489 int color_plane) 1490{ 1491 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1492 enum pipe pipe = plane->pipe; 1493 const struct drm_rect *clip; 1494 u32 val, offset; 1495 int ret, x, y; 1496 1497 if (!crtc_state->enable_psr2_sel_fetch) 1498 return; 1499 1500 val = plane_state ? plane_state->ctl : 0; 1501 val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE; 1502 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val); 1503 if (!val || plane->id == PLANE_CURSOR) 1504 return; 1505 1506 clip = &plane_state->psr2_sel_fetch_area; 1507 1508 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1509 val |= plane_state->uapi.dst.x1; 1510 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1511 1512 /* TODO: consider auxiliary surfaces */ 1513 x = plane_state->uapi.src.x1 >> 16; 1514 y = (plane_state->uapi.src.y1 >> 16) + clip->y1; 1515 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); 1516 if (ret) 1517 drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n", 1518 ret); 1519 val = y << 16 | x; 1520 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1521 val); 1522 1523 /* Sizes are 0 based */ 1524 val = (drm_rect_height(clip) - 1) << 16; 1525 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1526 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1527} 1528 1529void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1530{ 1531 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1532 1533 if (!HAS_PSR2_SEL_FETCH(dev_priv) || 1534 !crtc_state->enable_psr2_sel_fetch) 1535 return; 1536 1537 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), 1538 crtc_state->psr2_man_track_ctl); 1539} 1540 1541static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1542 struct drm_rect *clip, bool full_update) 1543{ 1544 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1545 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1546 u32 val = PSR2_MAN_TRK_CTL_ENABLE; 1547 1548 if (full_update) { 1549 if (IS_ALDERLAKE_P(dev_priv)) 1550 val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1551 else 1552 val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1553 1554 goto exit; 1555 } 1556 1557 if (clip->y1 == -1) 1558 goto exit; 1559 1560 if (IS_ALDERLAKE_P(dev_priv)) { 1561 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1); 1562 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2); 1563 } else { 1564 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1565 1566 val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1567 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1568 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1569 } 1570exit: 1571 crtc_state->psr2_man_track_ctl = val; 1572} 1573 1574static void clip_area_update(struct drm_rect *overlap_damage_area, 1575 struct drm_rect *damage_area) 1576{ 1577 if (overlap_damage_area->y1 == -1) { 1578 overlap_damage_area->y1 = damage_area->y1; 1579 overlap_damage_area->y2 = damage_area->y2; 1580 return; 1581 } 1582 1583 if (damage_area->y1 < overlap_damage_area->y1) 1584 overlap_damage_area->y1 = damage_area->y1; 1585 1586 if (damage_area->y2 > overlap_damage_area->y2) 1587 overlap_damage_area->y2 = damage_area->y2; 1588} 1589 1590static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state, 1591 struct drm_rect *pipe_clip) 1592{ 1593 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1594 const u16 y_alignment = crtc_state->su_y_granularity; 1595 1596 pipe_clip->y1 -= pipe_clip->y1 % y_alignment; 1597 if (pipe_clip->y2 % y_alignment) 1598 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; 1599 1600 if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable) 1601 drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n"); 1602} 1603 1604int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1605 struct intel_crtc *crtc) 1606{ 1607 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1608 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1609 struct intel_plane_state *new_plane_state, *old_plane_state; 1610 struct intel_plane *plane; 1611 bool full_update = false; 1612 int i, ret; 1613 1614 if (!crtc_state->enable_psr2_sel_fetch) 1615 return 0; 1616 1617 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1618 if (ret) 1619 return ret; 1620 1621 /* 1622 * Calculate minimal selective fetch area of each plane and calculate 1623 * the pipe damaged area. 1624 * In the next loop the plane selective fetch area will actually be set 1625 * using whole pipe damaged area. 1626 */ 1627 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1628 new_plane_state, i) { 1629 struct drm_rect src, damaged_area = { .y1 = -1 }; 1630 struct drm_mode_rect *damaged_clips; 1631 u32 num_clips, j; 1632 1633 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1634 continue; 1635 1636 if (!new_plane_state->uapi.visible && 1637 !old_plane_state->uapi.visible) 1638 continue; 1639 1640 /* 1641 * TODO: Not clear how to handle planes with negative position, 1642 * also planes are not updated if they have a negative X 1643 * position so for now doing a full update in this cases 1644 */ 1645 if (new_plane_state->uapi.dst.y1 < 0 || 1646 new_plane_state->uapi.dst.x1 < 0) { 1647 full_update = true; 1648 break; 1649 } 1650 1651 num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi); 1652 1653 /* 1654 * If visibility or plane moved, mark the whole plane area as 1655 * damaged as it needs to be complete redraw in the new and old 1656 * position. 1657 */ 1658 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1659 !drm_rect_equals(&new_plane_state->uapi.dst, 1660 &old_plane_state->uapi.dst)) { 1661 if (old_plane_state->uapi.visible) { 1662 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1663 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1664 clip_area_update(&pipe_clip, &damaged_area); 1665 } 1666 1667 if (new_plane_state->uapi.visible) { 1668 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1669 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1670 clip_area_update(&pipe_clip, &damaged_area); 1671 } 1672 continue; 1673 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha || 1674 (!num_clips && 1675 new_plane_state->uapi.fb != old_plane_state->uapi.fb)) { 1676 /* 1677 * If the plane don't have damaged areas but the 1678 * framebuffer changed or alpha changed, mark the whole 1679 * plane area as damaged. 1680 */ 1681 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1682 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1683 clip_area_update(&pipe_clip, &damaged_area); 1684 continue; 1685 } 1686 1687 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src); 1688 damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi); 1689 1690 for (j = 0; j < num_clips; j++) { 1691 struct drm_rect clip; 1692 1693 clip.x1 = damaged_clips[j].x1; 1694 clip.y1 = damaged_clips[j].y1; 1695 clip.x2 = damaged_clips[j].x2; 1696 clip.y2 = damaged_clips[j].y2; 1697 if (drm_rect_intersect(&clip, &src)) 1698 clip_area_update(&damaged_area, &clip); 1699 } 1700 1701 if (damaged_area.y1 == -1) 1702 continue; 1703 1704 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1705 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1706 clip_area_update(&pipe_clip, &damaged_area); 1707 } 1708 1709 if (full_update) 1710 goto skip_sel_fetch_set_loop; 1711 1712 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip); 1713 1714 /* 1715 * Now that we have the pipe damaged area check if it intersect with 1716 * every plane, if it does set the plane selective fetch area. 1717 */ 1718 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1719 new_plane_state, i) { 1720 struct drm_rect *sel_fetch_area, inter; 1721 1722 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1723 !new_plane_state->uapi.visible) 1724 continue; 1725 1726 inter = pipe_clip; 1727 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1728 continue; 1729 1730 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1731 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1732 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1733 crtc_state->update_planes |= BIT(plane->id); 1734 } 1735 1736skip_sel_fetch_set_loop: 1737 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1738 return 0; 1739} 1740 1741/** 1742 * intel_psr_update - Update PSR state 1743 * @intel_dp: Intel DP 1744 * @crtc_state: new CRTC state 1745 * @conn_state: new CONNECTOR state 1746 * 1747 * This functions will update PSR states, disabling, enabling or switching PSR 1748 * version when executing fastsets. For full modeset, intel_psr_disable() and 1749 * intel_psr_enable() should be called instead. 1750 */ 1751void intel_psr_update(struct intel_dp *intel_dp, 1752 const struct intel_crtc_state *crtc_state, 1753 const struct drm_connector_state *conn_state) 1754{ 1755 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1756 struct intel_psr *psr = &intel_dp->psr; 1757 bool enable, psr2_enable; 1758 1759 if (!CAN_PSR(intel_dp)) 1760 return; 1761 1762 mutex_lock(&intel_dp->psr.lock); 1763 1764 enable = crtc_state->has_psr; 1765 psr2_enable = crtc_state->has_psr2; 1766 1767 if (enable == psr->enabled && psr2_enable == psr->psr2_enabled && 1768 crtc_state->enable_psr2_sel_fetch == psr->psr2_sel_fetch_enabled) { 1769 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1770 if (crtc_state->crc_enabled && psr->enabled) 1771 psr_force_hw_tracking_exit(intel_dp); 1772 else if (DISPLAY_VER(dev_priv) < 9 && psr->enabled) { 1773 /* 1774 * Activate PSR again after a force exit when enabling 1775 * CRC in older gens 1776 */ 1777 if (!intel_dp->psr.active && 1778 !intel_dp->psr.busy_frontbuffer_bits) 1779 schedule_work(&intel_dp->psr.work); 1780 } 1781 1782 goto unlock; 1783 } 1784 1785 if (psr->enabled) 1786 intel_psr_disable_locked(intel_dp); 1787 1788 if (enable) 1789 intel_psr_enable_locked(intel_dp, crtc_state, conn_state); 1790 1791unlock: 1792 mutex_unlock(&intel_dp->psr.lock); 1793} 1794 1795/** 1796 * psr_wait_for_idle - wait for PSR1 to idle 1797 * @intel_dp: Intel DP 1798 * @out_value: PSR status in case of failure 1799 * 1800 * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. 1801 * 1802 */ 1803static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value) 1804{ 1805 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1806 1807 /* 1808 * From bspec: Panel Self Refresh (BDW+) 1809 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 1810 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 1811 * defensive enough to cover everything. 1812 */ 1813 return __intel_wait_for_register(&dev_priv->uncore, 1814 EDP_PSR_STATUS(intel_dp->psr.transcoder), 1815 EDP_PSR_STATUS_STATE_MASK, 1816 EDP_PSR_STATUS_STATE_IDLE, 2, 50, 1817 out_value); 1818} 1819 1820/** 1821 * intel_psr_wait_for_idle - wait for PSR1 to idle 1822 * @new_crtc_state: new CRTC state 1823 * 1824 * This function is expected to be called from pipe_update_start() where it is 1825 * not expected to race with PSR enable or disable. 1826 */ 1827void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state) 1828{ 1829 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); 1830 struct intel_encoder *encoder; 1831 1832 if (!new_crtc_state->has_psr) 1833 return; 1834 1835 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 1836 new_crtc_state->uapi.encoder_mask) { 1837 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1838 u32 psr_status; 1839 1840 mutex_lock(&intel_dp->psr.lock); 1841 if (!intel_dp->psr.enabled || intel_dp->psr.psr2_enabled) { 1842 mutex_unlock(&intel_dp->psr.lock); 1843 continue; 1844 } 1845 1846 /* when the PSR1 is enabled */ 1847 if (psr_wait_for_idle(intel_dp, &psr_status)) 1848 drm_err(&dev_priv->drm, 1849 "PSR idle timed out 0x%x, atomic update may fail\n", 1850 psr_status); 1851 mutex_unlock(&intel_dp->psr.lock); 1852 } 1853} 1854 1855static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 1856{ 1857 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1858 i915_reg_t reg; 1859 u32 mask; 1860 int err; 1861 1862 if (!intel_dp->psr.enabled) 1863 return false; 1864 1865 if (intel_dp->psr.psr2_enabled) { 1866 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1867 mask = EDP_PSR2_STATUS_STATE_MASK; 1868 } else { 1869 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1870 mask = EDP_PSR_STATUS_STATE_MASK; 1871 } 1872 1873 mutex_unlock(&intel_dp->psr.lock); 1874 1875 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 1876 if (err) 1877 drm_err(&dev_priv->drm, 1878 "Timed out waiting for PSR Idle for re-enable\n"); 1879 1880 /* After the unlocked wait, verify that PSR is still wanted! */ 1881 mutex_lock(&intel_dp->psr.lock); 1882 return err == 0 && intel_dp->psr.enabled; 1883} 1884 1885static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 1886{ 1887 struct drm_connector_list_iter conn_iter; 1888 struct drm_device *dev = &dev_priv->drm; 1889 struct drm_modeset_acquire_ctx ctx; 1890 struct drm_atomic_state *state; 1891 struct drm_connector *conn; 1892 int err = 0; 1893 1894 state = drm_atomic_state_alloc(dev); 1895 if (!state) 1896 return -ENOMEM; 1897 1898 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1899 state->acquire_ctx = &ctx; 1900 1901retry: 1902 1903 drm_connector_list_iter_begin(dev, &conn_iter); 1904 drm_for_each_connector_iter(conn, &conn_iter) { 1905 struct drm_connector_state *conn_state; 1906 struct drm_crtc_state *crtc_state; 1907 1908 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 1909 continue; 1910 1911 conn_state = drm_atomic_get_connector_state(state, conn); 1912 if (IS_ERR(conn_state)) { 1913 err = PTR_ERR(conn_state); 1914 break; 1915 } 1916 1917 if (!conn_state->crtc) 1918 continue; 1919 1920 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 1921 if (IS_ERR(crtc_state)) { 1922 err = PTR_ERR(crtc_state); 1923 break; 1924 } 1925 1926 /* Mark mode as changed to trigger a pipe->update() */ 1927 crtc_state->mode_changed = true; 1928 } 1929 drm_connector_list_iter_end(&conn_iter); 1930 1931 if (err == 0) 1932 err = drm_atomic_commit(state); 1933 1934 if (err == -EDEADLK) { 1935 drm_atomic_state_clear(state); 1936 err = drm_modeset_backoff(&ctx); 1937 if (!err) 1938 goto retry; 1939 } 1940 1941 drm_modeset_drop_locks(&ctx); 1942 drm_modeset_acquire_fini(&ctx); 1943 drm_atomic_state_put(state); 1944 1945 return err; 1946} 1947 1948int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 1949{ 1950 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1951 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 1952 u32 old_mode; 1953 int ret; 1954 1955 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 1956 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 1957 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 1958 return -EINVAL; 1959 } 1960 1961 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 1962 if (ret) 1963 return ret; 1964 1965 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 1966 intel_dp->psr.debug = val; 1967 1968 /* 1969 * Do it right away if it's already enabled, otherwise it will be done 1970 * when enabling the source. 1971 */ 1972 if (intel_dp->psr.enabled) 1973 psr_irq_control(intel_dp); 1974 1975 mutex_unlock(&intel_dp->psr.lock); 1976 1977 if (old_mode != mode) 1978 ret = intel_psr_fastset_force(dev_priv); 1979 1980 return ret; 1981} 1982 1983static void intel_psr_handle_irq(struct intel_dp *intel_dp) 1984{ 1985 struct intel_psr *psr = &intel_dp->psr; 1986 1987 intel_psr_disable_locked(intel_dp); 1988 psr->sink_not_reliable = true; 1989 /* let's make sure that sink is awaken */ 1990 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 1991} 1992 1993static void intel_psr_work(struct work_struct *work) 1994{ 1995 struct intel_dp *intel_dp = 1996 container_of(work, typeof(*intel_dp), psr.work); 1997 1998 mutex_lock(&intel_dp->psr.lock); 1999 2000 if (!intel_dp->psr.enabled) 2001 goto unlock; 2002 2003 if (READ_ONCE(intel_dp->psr.irq_aux_error)) 2004 intel_psr_handle_irq(intel_dp); 2005 2006 /* 2007 * We have to make sure PSR is ready for re-enable 2008 * otherwise it keeps disabled until next full enable/disable cycle. 2009 * PSR might take some time to get fully disabled 2010 * and be ready for re-enable. 2011 */ 2012 if (!__psr_wait_for_idle_locked(intel_dp)) 2013 goto unlock; 2014 2015 /* 2016 * The delayed work can race with an invalidate hence we need to 2017 * recheck. Since psr_flush first clears this and then reschedules we 2018 * won't ever miss a flush when bailing out here. 2019 */ 2020 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 2021 goto unlock; 2022 2023 intel_psr_activate(intel_dp); 2024unlock: 2025 mutex_unlock(&intel_dp->psr.lock); 2026} 2027 2028/** 2029 * intel_psr_invalidate - Invalidade PSR 2030 * @dev_priv: i915 device 2031 * @frontbuffer_bits: frontbuffer plane tracking bits 2032 * @origin: which operation caused the invalidate 2033 * 2034 * Since the hardware frontbuffer tracking has gaps we need to integrate 2035 * with the software frontbuffer tracking. This function gets called every 2036 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 2037 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 2038 * 2039 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 2040 */ 2041void intel_psr_invalidate(struct drm_i915_private *dev_priv, 2042 unsigned frontbuffer_bits, enum fb_op_origin origin) 2043{ 2044 struct intel_encoder *encoder; 2045 2046 if (origin == ORIGIN_FLIP) 2047 return; 2048 2049 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2050 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2051 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2052 2053 mutex_lock(&intel_dp->psr.lock); 2054 if (!intel_dp->psr.enabled) { 2055 mutex_unlock(&intel_dp->psr.lock); 2056 continue; 2057 } 2058 2059 pipe_frontbuffer_bits &= 2060 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2061 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 2062 2063 if (pipe_frontbuffer_bits) 2064 intel_psr_exit(intel_dp); 2065 2066 mutex_unlock(&intel_dp->psr.lock); 2067 } 2068} 2069/* 2070 * When we will be completely rely on PSR2 S/W tracking in future, 2071 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 2072 * event also therefore tgl_dc3co_flush() require to be changed 2073 * accordingly in future. 2074 */ 2075static void 2076tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 2077 enum fb_op_origin origin) 2078{ 2079 mutex_lock(&intel_dp->psr.lock); 2080 2081 if (!intel_dp->psr.dc3co_exitline) 2082 goto unlock; 2083 2084 if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active) 2085 goto unlock; 2086 2087 /* 2088 * At every frontbuffer flush flip event modified delay of delayed work, 2089 * when delayed work schedules that means display has been idle. 2090 */ 2091 if (!(frontbuffer_bits & 2092 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 2093 goto unlock; 2094 2095 tgl_psr2_enable_dc3co(intel_dp); 2096 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work, 2097 intel_dp->psr.dc3co_exit_delay); 2098 2099unlock: 2100 mutex_unlock(&intel_dp->psr.lock); 2101} 2102 2103/** 2104 * intel_psr_flush - Flush PSR 2105 * @dev_priv: i915 device 2106 * @frontbuffer_bits: frontbuffer plane tracking bits 2107 * @origin: which operation caused the flush 2108 * 2109 * Since the hardware frontbuffer tracking has gaps we need to integrate 2110 * with the software frontbuffer tracking. This function gets called every 2111 * time frontbuffer rendering has completed and flushed out to memory. PSR 2112 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 2113 * 2114 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 2115 */ 2116void intel_psr_flush(struct drm_i915_private *dev_priv, 2117 unsigned frontbuffer_bits, enum fb_op_origin origin) 2118{ 2119 struct intel_encoder *encoder; 2120 2121 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2122 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2123 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2124 2125 if (origin == ORIGIN_FLIP) { 2126 tgl_dc3co_flush(intel_dp, frontbuffer_bits, origin); 2127 continue; 2128 } 2129 2130 mutex_lock(&intel_dp->psr.lock); 2131 if (!intel_dp->psr.enabled) { 2132 mutex_unlock(&intel_dp->psr.lock); 2133 continue; 2134 } 2135 2136 pipe_frontbuffer_bits &= 2137 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2138 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 2139 2140 /* 2141 * If the PSR is paused by an explicit intel_psr_paused() call, 2142 * we have to ensure that the PSR is not activated until 2143 * intel_psr_resume() is called. 2144 */ 2145 if (intel_dp->psr.paused) { 2146 mutex_unlock(&intel_dp->psr.lock); 2147 continue; 2148 } 2149 2150 /* By definition flush = invalidate + flush */ 2151 if (pipe_frontbuffer_bits) 2152 psr_force_hw_tracking_exit(intel_dp); 2153 2154 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 2155 schedule_work(&intel_dp->psr.work); 2156 mutex_unlock(&intel_dp->psr.lock); 2157 } 2158} 2159 2160/** 2161 * intel_psr_init - Init basic PSR work and mutex. 2162 * @intel_dp: Intel DP 2163 * 2164 * This function is called after the initializing connector. 2165 * (the initializing of connector treats the handling of connector capabilities) 2166 * And it initializes basic PSR stuff for each DP Encoder. 2167 */ 2168void intel_psr_init(struct intel_dp *intel_dp) 2169{ 2170 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2171 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2172 2173 if (!HAS_PSR(dev_priv)) 2174 return; 2175 2176 /* 2177 * HSW spec explicitly says PSR is tied to port A. 2178 * BDW+ platforms have a instance of PSR registers per transcoder but 2179 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 2180 * than eDP one. 2181 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 2182 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 2183 * But GEN12 supports a instance of PSR registers per transcoder. 2184 */ 2185 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { 2186 drm_dbg_kms(&dev_priv->drm, 2187 "PSR condition failed: Port not supported\n"); 2188 return; 2189 } 2190 2191 intel_dp->psr.source_support = true; 2192 2193 if (IS_HASWELL(dev_priv)) 2194 /* 2195 * HSW don't have PSR registers on the same space as transcoder 2196 * so set this to a value that when subtract to the register 2197 * in transcoder space results in the right offset for HSW 2198 */ 2199 dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE; 2200 2201 if (dev_priv->params.enable_psr == -1) 2202 if (DISPLAY_VER(dev_priv) < 9 || !dev_priv->vbt.psr.enable) 2203 dev_priv->params.enable_psr = 0; 2204 2205 /* Set link_standby x link_off defaults */ 2206 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 2207 /* HSW and BDW require workarounds that we don't implement. */ 2208 intel_dp->psr.link_standby = false; 2209 else if (DISPLAY_VER(dev_priv) < 12) 2210 /* For new platforms up to TGL let's respect VBT back again */ 2211 intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link; 2212 2213 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 2214 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 2215 rw_init(&intel_dp->psr.lock, "psrlk"); 2216} 2217 2218static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 2219 u8 *status, u8 *error_status) 2220{ 2221 struct drm_dp_aux *aux = &intel_dp->aux; 2222 int ret; 2223 2224 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 2225 if (ret != 1) 2226 return ret; 2227 2228 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 2229 if (ret != 1) 2230 return ret; 2231 2232 *status = *status & DP_PSR_SINK_STATE_MASK; 2233 2234 return 0; 2235} 2236 2237static void psr_alpm_check(struct intel_dp *intel_dp) 2238{ 2239 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2240 struct drm_dp_aux *aux = &intel_dp->aux; 2241 struct intel_psr *psr = &intel_dp->psr; 2242 u8 val; 2243 int r; 2244 2245 if (!psr->psr2_enabled) 2246 return; 2247 2248 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 2249 if (r != 1) { 2250 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 2251 return; 2252 } 2253 2254 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 2255 intel_psr_disable_locked(intel_dp); 2256 psr->sink_not_reliable = true; 2257 drm_dbg_kms(&dev_priv->drm, 2258 "ALPM lock timeout error, disabling PSR\n"); 2259 2260 /* Clearing error */ 2261 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 2262 } 2263} 2264 2265static void psr_capability_changed_check(struct intel_dp *intel_dp) 2266{ 2267 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2268 struct intel_psr *psr = &intel_dp->psr; 2269 u8 val; 2270 int r; 2271 2272 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 2273 if (r != 1) { 2274 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 2275 return; 2276 } 2277 2278 if (val & DP_PSR_CAPS_CHANGE) { 2279 intel_psr_disable_locked(intel_dp); 2280 psr->sink_not_reliable = true; 2281 drm_dbg_kms(&dev_priv->drm, 2282 "Sink PSR capability changed, disabling PSR\n"); 2283 2284 /* Clearing it */ 2285 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 2286 } 2287} 2288 2289void intel_psr_short_pulse(struct intel_dp *intel_dp) 2290{ 2291 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2292 struct intel_psr *psr = &intel_dp->psr; 2293 u8 status, error_status; 2294 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 2295 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 2296 DP_PSR_LINK_CRC_ERROR; 2297 2298 if (!CAN_PSR(intel_dp)) 2299 return; 2300 2301 mutex_lock(&psr->lock); 2302 2303 if (!psr->enabled) 2304 goto exit; 2305 2306 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 2307 drm_err(&dev_priv->drm, 2308 "Error reading PSR status or error status\n"); 2309 goto exit; 2310 } 2311 2312 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 2313 intel_psr_disable_locked(intel_dp); 2314 psr->sink_not_reliable = true; 2315 } 2316 2317 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 2318 drm_dbg_kms(&dev_priv->drm, 2319 "PSR sink internal error, disabling PSR\n"); 2320 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 2321 drm_dbg_kms(&dev_priv->drm, 2322 "PSR RFB storage error, disabling PSR\n"); 2323 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 2324 drm_dbg_kms(&dev_priv->drm, 2325 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 2326 if (error_status & DP_PSR_LINK_CRC_ERROR) 2327 drm_dbg_kms(&dev_priv->drm, 2328 "PSR Link CRC error, disabling PSR\n"); 2329 2330 if (error_status & ~errors) 2331 drm_err(&dev_priv->drm, 2332 "PSR_ERROR_STATUS unhandled errors %x\n", 2333 error_status & ~errors); 2334 /* clear status register */ 2335 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 2336 2337 psr_alpm_check(intel_dp); 2338 psr_capability_changed_check(intel_dp); 2339 2340exit: 2341 mutex_unlock(&psr->lock); 2342} 2343 2344bool intel_psr_enabled(struct intel_dp *intel_dp) 2345{ 2346 bool ret; 2347 2348 if (!CAN_PSR(intel_dp)) 2349 return false; 2350 2351 mutex_lock(&intel_dp->psr.lock); 2352 ret = intel_dp->psr.enabled; 2353 mutex_unlock(&intel_dp->psr.lock); 2354 2355 return ret; 2356} 2357