1// SPDX-License-Identifier: MIT 2/* 3 * Copyright �� 2022-2023 Intel Corporation 4 * 5 * High level display driver entry points. This is a layer between top level 6 * driver code and low level display functionality; no low level display code or 7 * details here. 8 */ 9 10#include <linux/vga_switcheroo.h> 11#include <acpi/video.h> 12#include <drm/display/drm_dp_mst_helper.h> 13#include <drm/drm_atomic_helper.h> 14#include <drm/drm_mode_config.h> 15#include <drm/drm_privacy_screen_consumer.h> 16#include <drm/drm_probe_helper.h> 17#include <drm/drm_vblank.h> 18 19#include "i915_drv.h" 20#include "i9xx_wm.h" 21#include "intel_acpi.h" 22#include "intel_atomic.h" 23#include "intel_audio.h" 24#include "intel_bios.h" 25#include "intel_bw.h" 26#include "intel_cdclk.h" 27#include "intel_color.h" 28#include "intel_crtc.h" 29#include "intel_display_debugfs.h" 30#include "intel_display_driver.h" 31#include "intel_display_irq.h" 32#include "intel_display_power.h" 33#include "intel_display_types.h" 34#include "intel_dkl_phy.h" 35#include "intel_dmc.h" 36#include "intel_dp.h" 37#include "intel_dpll.h" 38#include "intel_dpll_mgr.h" 39#include "intel_fb.h" 40#include "intel_fbc.h" 41#include "intel_fbdev.h" 42#include "intel_fdi.h" 43#include "intel_gmbus.h" 44#include "intel_hdcp.h" 45#include "intel_hotplug.h" 46#include "intel_hti.h" 47#include "intel_modeset_setup.h" 48#include "intel_opregion.h" 49#include "intel_overlay.h" 50#include "intel_plane_initial.h" 51#include "intel_pmdemand.h" 52#include "intel_pps.h" 53#include "intel_quirks.h" 54#include "intel_vga.h" 55#include "intel_wm.h" 56#include "skl_watermark.h" 57 58bool intel_display_driver_probe_defer(struct pci_dev *pdev) 59{ 60 struct drm_privacy_screen *privacy_screen; 61 62 /* 63 * apple-gmux is needed on dual GPU MacBook Pro 64 * to probe the panel if we're the inactive GPU. 65 */ 66 if (vga_switcheroo_client_probe_defer(pdev)) 67 return true; 68 69 /* If the LCD panel has a privacy-screen, wait for it */ 70#ifdef notyet 71 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 72 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 73 return true; 74 75 drm_privacy_screen_put(privacy_screen); 76#endif 77 78 return false; 79} 80 81void intel_display_driver_init_hw(struct drm_i915_private *i915) 82{ 83 struct intel_cdclk_state *cdclk_state; 84 85 if (!HAS_DISPLAY(i915)) 86 return; 87 88 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); 89 90 intel_update_cdclk(i915); 91 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); 92 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; 93} 94 95static const struct drm_mode_config_funcs intel_mode_funcs = { 96 .fb_create = intel_user_framebuffer_create, 97 .get_format_info = intel_fb_get_format_info, 98 .output_poll_changed = intel_fbdev_output_poll_changed, 99 .mode_valid = intel_mode_valid, 100 .atomic_check = intel_atomic_check, 101 .atomic_commit = intel_atomic_commit, 102 .atomic_state_alloc = intel_atomic_state_alloc, 103 .atomic_state_clear = intel_atomic_state_clear, 104 .atomic_state_free = intel_atomic_state_free, 105}; 106 107static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = { 108 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 109}; 110 111static void intel_mode_config_init(struct drm_i915_private *i915) 112{ 113 struct drm_mode_config *mode_config = &i915->drm.mode_config; 114 115 drm_mode_config_init(&i915->drm); 116 INIT_LIST_HEAD(&i915->display.global.obj_list); 117 118 mode_config->min_width = 0; 119 mode_config->min_height = 0; 120 121 mode_config->preferred_depth = 24; 122 mode_config->prefer_shadow = 1; 123 124 mode_config->funcs = &intel_mode_funcs; 125 mode_config->helper_private = &intel_mode_config_funcs; 126 127 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 128 129 /* 130 * Maximum framebuffer dimensions, chosen to match 131 * the maximum render engine surface size on gen4+. 132 */ 133 if (DISPLAY_VER(i915) >= 7) { 134 mode_config->max_width = 16384; 135 mode_config->max_height = 16384; 136 } else if (DISPLAY_VER(i915) >= 4) { 137 mode_config->max_width = 8192; 138 mode_config->max_height = 8192; 139 } else if (DISPLAY_VER(i915) == 3) { 140 mode_config->max_width = 4096; 141 mode_config->max_height = 4096; 142 } else { 143 mode_config->max_width = 2048; 144 mode_config->max_height = 2048; 145 } 146 147 if (IS_I845G(i915) || IS_I865G(i915)) { 148 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 149 mode_config->cursor_height = 1023; 150 } else if (IS_I830(i915) || IS_I85X(i915) || 151 IS_I915G(i915) || IS_I915GM(i915)) { 152 mode_config->cursor_width = 64; 153 mode_config->cursor_height = 64; 154 } else { 155 mode_config->cursor_width = 256; 156 mode_config->cursor_height = 256; 157 } 158} 159 160static void intel_mode_config_cleanup(struct drm_i915_private *i915) 161{ 162 intel_atomic_global_obj_cleanup(i915); 163 drm_mode_config_cleanup(&i915->drm); 164} 165 166static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 167{ 168 struct intel_plane *plane; 169 170 for_each_intel_plane(&dev_priv->drm, plane) { 171 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 172 plane->pipe); 173 174 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 175 } 176} 177 178void intel_display_driver_early_probe(struct drm_i915_private *i915) 179{ 180 if (!HAS_DISPLAY(i915)) 181 return; 182 183 intel_display_irq_init(i915); 184 intel_dkl_phy_init(i915); 185 intel_color_init_hooks(i915); 186 intel_init_cdclk_hooks(i915); 187 intel_audio_hooks_init(i915); 188 intel_dpll_init_clock_hook(i915); 189 intel_init_display_hooks(i915); 190 intel_fdi_init_hook(i915); 191} 192 193/* part #1: call before irq install */ 194int intel_display_driver_probe_noirq(struct drm_i915_private *i915) 195{ 196 int ret; 197 198 if (i915_inject_probe_failure(i915)) 199 return -ENODEV; 200 201 if (HAS_DISPLAY(i915)) { 202 ret = drm_vblank_init(&i915->drm, 203 INTEL_NUM_PIPES(i915)); 204 if (ret) 205 return ret; 206 } 207 208 intel_bios_init(i915); 209 210 ret = intel_vga_register(i915); 211 if (ret) 212 goto cleanup_bios; 213 214 /* FIXME: completely on the wrong abstraction layer */ 215 ret = intel_power_domains_init(i915); 216 if (ret < 0) 217 goto cleanup_vga; 218 219 intel_pmdemand_init_early(i915); 220 221 intel_power_domains_init_hw(i915, false); 222 223 if (!HAS_DISPLAY(i915)) 224 return 0; 225 226 intel_dmc_init(i915); 227 228 i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); 229 i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | 230 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 231 232 intel_mode_config_init(i915); 233 234 ret = intel_cdclk_init(i915); 235 if (ret) 236 goto cleanup_vga_client_pw_domain_dmc; 237 238 ret = intel_color_init(i915); 239 if (ret) 240 goto cleanup_vga_client_pw_domain_dmc; 241 242 ret = intel_dbuf_init(i915); 243 if (ret) 244 goto cleanup_vga_client_pw_domain_dmc; 245 246 ret = intel_bw_init(i915); 247 if (ret) 248 goto cleanup_vga_client_pw_domain_dmc; 249 250 ret = intel_pmdemand_init(i915); 251 if (ret) 252 goto cleanup_vga_client_pw_domain_dmc; 253 254 init_llist_head(&i915->display.atomic_helper.free_list); 255 INIT_WORK(&i915->display.atomic_helper.free_work, 256 intel_atomic_helper_free_state_worker); 257 258 intel_init_quirks(i915); 259 260 intel_fbc_init(i915); 261 262 return 0; 263 264cleanup_vga_client_pw_domain_dmc: 265 intel_dmc_fini(i915); 266 intel_power_domains_driver_remove(i915); 267cleanup_vga: 268 intel_vga_unregister(i915); 269cleanup_bios: 270 intel_bios_driver_remove(i915); 271 272 return ret; 273} 274 275/* part #2: call after irq install, but before gem init */ 276int intel_display_driver_probe_nogem(struct drm_i915_private *i915) 277{ 278 struct drm_device *dev = &i915->drm; 279 enum pipe pipe; 280 struct intel_crtc *crtc; 281 int ret; 282 283 if (!HAS_DISPLAY(i915)) 284 return 0; 285 286 intel_wm_init(i915); 287 288 intel_panel_sanitize_ssc(i915); 289 290 intel_pps_setup(i915); 291 292 intel_gmbus_setup(i915); 293 294 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 295 INTEL_NUM_PIPES(i915), 296 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 297 298 for_each_pipe(i915, pipe) { 299 ret = intel_crtc_init(i915, pipe); 300 if (ret) { 301 intel_mode_config_cleanup(i915); 302 return ret; 303 } 304 } 305 306 intel_plane_possible_crtcs_init(i915); 307 intel_shared_dpll_init(i915); 308 intel_fdi_pll_freq_update(i915); 309 310 intel_update_czclk(i915); 311 intel_display_driver_init_hw(i915); 312 intel_dpll_update_ref_clks(i915); 313 314 intel_hdcp_component_init(i915); 315 316 if (i915->display.cdclk.max_cdclk_freq == 0) 317 intel_update_max_cdclk(i915); 318 319 intel_hti_init(i915); 320 321 /* Just disable it once at startup */ 322 intel_vga_disable(i915); 323 intel_setup_outputs(i915); 324 325 drm_modeset_lock_all(dev); 326 intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx); 327 intel_acpi_assign_connector_fwnodes(i915); 328 drm_modeset_unlock_all(dev); 329 330 for_each_intel_crtc(dev, crtc) { 331 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 332 continue; 333 intel_crtc_initial_plane_config(crtc); 334 } 335 336 /* 337 * Make sure hardware watermarks really match the state we read out. 338 * Note that we need to do this after reconstructing the BIOS fb's 339 * since the watermark calculation done here will use pstate->fb. 340 */ 341 if (!HAS_GMCH(i915)) 342 ilk_wm_sanitize(i915); 343 344 return 0; 345} 346 347/* part #3: call after gem init */ 348int intel_display_driver_probe(struct drm_i915_private *i915) 349{ 350 int ret; 351 352 if (!HAS_DISPLAY(i915)) 353 return 0; 354 355 /* 356 * Force all active planes to recompute their states. So that on 357 * mode_setcrtc after probe, all the intel_plane_state variables 358 * are already calculated and there is no assert_plane warnings 359 * during bootup. 360 */ 361 ret = intel_initial_commit(&i915->drm); 362 if (ret) 363 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 364 365 intel_overlay_setup(i915); 366 367 ret = intel_fbdev_init(&i915->drm); 368 if (ret) 369 return ret; 370 371 /* Only enable hotplug handling once the fbdev is fully set up. */ 372 intel_hpd_init(i915); 373 intel_hpd_poll_disable(i915); 374 375 skl_watermark_ipc_init(i915); 376 377 return 0; 378} 379 380void intel_display_driver_register(struct drm_i915_private *i915) 381{ 382 if (!HAS_DISPLAY(i915)) 383 return; 384 385 /* Must be done after probing outputs */ 386 intel_opregion_register(i915); 387 intel_acpi_video_register(i915); 388 389 intel_audio_init(i915); 390 391 intel_audio_register(i915); 392 393 intel_display_debugfs_register(i915); 394 395 /* 396 * Some ports require correctly set-up hpd registers for 397 * detection to work properly (leading to ghost connected 398 * connector status), e.g. VGA on gm45. Hence we can only set 399 * up the initial fbdev config after hpd irqs are fully 400 * enabled. We do it last so that the async config cannot run 401 * before the connectors are registered. 402 */ 403 intel_fbdev_initial_config_async(i915); 404 405 /* 406 * We need to coordinate the hotplugs with the asynchronous 407 * fbdev configuration, for which we use the 408 * fbdev->async_cookie. 409 */ 410 drm_kms_helper_poll_init(&i915->drm); 411} 412 413/* part #1: call before irq uninstall */ 414void intel_display_driver_remove(struct drm_i915_private *i915) 415{ 416 if (!HAS_DISPLAY(i915)) 417 return; 418 419 flush_workqueue(i915->display.wq.flip); 420 flush_workqueue(i915->display.wq.modeset); 421 422 flush_work(&i915->display.atomic_helper.free_work); 423 drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list)); 424 425 /* 426 * MST topology needs to be suspended so we don't have any calls to 427 * fbdev after it's finalized. MST will be destroyed later as part of 428 * drm_mode_config_cleanup() 429 */ 430 intel_dp_mst_suspend(i915); 431} 432 433/* part #2: call after irq uninstall */ 434void intel_display_driver_remove_noirq(struct drm_i915_private *i915) 435{ 436 if (!HAS_DISPLAY(i915)) 437 return; 438 439 /* 440 * Due to the hpd irq storm handling the hotplug work can re-arm the 441 * poll handlers. Hence disable polling after hpd handling is shut down. 442 */ 443 intel_hpd_poll_fini(i915); 444 445 /* poll work can call into fbdev, hence clean that up afterwards */ 446 intel_fbdev_fini(i915); 447 448 intel_unregister_dsm_handler(); 449 450 /* flush any delayed tasks or pending work */ 451 flush_workqueue(i915->unordered_wq); 452 453 intel_hdcp_component_fini(i915); 454 455 intel_mode_config_cleanup(i915); 456 457 intel_overlay_cleanup(i915); 458 459 intel_gmbus_teardown(i915); 460 461 destroy_workqueue(i915->display.wq.flip); 462 destroy_workqueue(i915->display.wq.modeset); 463 464 intel_fbc_cleanup(i915); 465} 466 467/* part #3: call after gem init */ 468void intel_display_driver_remove_nogem(struct drm_i915_private *i915) 469{ 470 intel_dmc_fini(i915); 471 472 intel_power_domains_driver_remove(i915); 473 474 intel_vga_unregister(i915); 475 476 intel_bios_driver_remove(i915); 477} 478 479void intel_display_driver_unregister(struct drm_i915_private *i915) 480{ 481 if (!HAS_DISPLAY(i915)) 482 return; 483 484 intel_fbdev_unregister(i915); 485 intel_audio_deinit(i915); 486 487 /* 488 * After flushing the fbdev (incl. a late async config which 489 * will have delayed queuing of a hotplug event), then flush 490 * the hotplug events. 491 */ 492 drm_kms_helper_poll_fini(&i915->drm); 493 drm_atomic_helper_shutdown(&i915->drm); 494 495 acpi_video_unregister(); 496 intel_opregion_unregister(i915); 497} 498 499/* 500 * turn all crtc's off, but do not adjust state 501 * This has to be paired with a call to intel_modeset_setup_hw_state. 502 */ 503int intel_display_driver_suspend(struct drm_i915_private *i915) 504{ 505 struct drm_atomic_state *state; 506 int ret; 507 508 if (!HAS_DISPLAY(i915)) 509 return 0; 510 511 state = drm_atomic_helper_suspend(&i915->drm); 512 ret = PTR_ERR_OR_ZERO(state); 513 if (ret) 514 drm_err(&i915->drm, "Suspending crtc's failed with %i\n", 515 ret); 516 else 517 i915->display.restore.modeset_state = state; 518 return ret; 519} 520 521int 522__intel_display_driver_resume(struct drm_i915_private *i915, 523 struct drm_atomic_state *state, 524 struct drm_modeset_acquire_ctx *ctx) 525{ 526 struct drm_crtc_state *crtc_state; 527 struct drm_crtc *crtc; 528 int ret, i; 529 530 intel_modeset_setup_hw_state(i915, ctx); 531 intel_vga_redisable(i915); 532 533 if (!state) 534 return 0; 535 536 /* 537 * We've duplicated the state, pointers to the old state are invalid. 538 * 539 * Don't attempt to use the old state until we commit the duplicated state. 540 */ 541 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 542 /* 543 * Force recalculation even if we restore 544 * current state. With fast modeset this may not result 545 * in a modeset when the state is compatible. 546 */ 547 crtc_state->mode_changed = true; 548 } 549 550 /* ignore any reset values/BIOS leftovers in the WM registers */ 551 if (!HAS_GMCH(i915)) 552 to_intel_atomic_state(state)->skip_intermediate_wm = true; 553 554 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 555 556 drm_WARN_ON(&i915->drm, ret == -EDEADLK); 557 558 return ret; 559} 560 561void intel_display_driver_resume(struct drm_i915_private *i915) 562{ 563 struct drm_atomic_state *state = i915->display.restore.modeset_state; 564 struct drm_modeset_acquire_ctx ctx; 565 int ret; 566 567 if (!HAS_DISPLAY(i915)) 568 return; 569 570 i915->display.restore.modeset_state = NULL; 571 if (state) 572 state->acquire_ctx = &ctx; 573 574 drm_modeset_acquire_init(&ctx, 0); 575 576 while (1) { 577 ret = drm_modeset_lock_all_ctx(&i915->drm, &ctx); 578 if (ret != -EDEADLK) 579 break; 580 581 drm_modeset_backoff(&ctx); 582 } 583 584 if (!ret) 585 ret = __intel_display_driver_resume(i915, state, &ctx); 586 587 skl_watermark_ipc_update(i915); 588 drm_modeset_drop_locks(&ctx); 589 drm_modeset_acquire_fini(&ctx); 590 591 if (ret) 592 drm_err(&i915->drm, 593 "Restoring old state failed with %i\n", ret); 594 if (state) 595 drm_atomic_state_put(state); 596} 597