drm_edid.c revision 1.23
1/* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30#include <linux/kernel.h> 31#include <linux/slab.h> 32#include <linux/hdmi.h> 33#include <linux/i2c.h> 34#include <linux/module.h> 35#include <linux/vga_switcheroo.h> 36#include <drm/drmP.h> 37#include <drm/drm_edid.h> 38#include <drm/drm_encoder.h> 39#include <drm/drm_displayid.h> 40#include <drm/drm_scdc_helper.h> 41 42#include "drm_crtc_internal.h" 43 44#define version_greater(edid, maj, min) \ 45 (((edid)->version > (maj)) || \ 46 ((edid)->version == (maj) && (edid)->revision > (min))) 47 48#define EDID_EST_TIMINGS 16 49#define EDID_STD_TIMINGS 8 50#define EDID_DETAILED_TIMINGS 4 51 52/* 53 * EDID blocks out in the wild have a variety of bugs, try to collect 54 * them here (note that userspace may work around broken monitors first, 55 * but fixes should make their way here so that the kernel "just works" 56 * on as many displays as possible). 57 */ 58 59/* First detailed mode wrong, use largest 60Hz mode */ 60#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 61/* Reported 135MHz pixel clock is too high, needs adjustment */ 62#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 63/* Prefer the largest mode at 75 Hz */ 64#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 65/* Detail timing is in cm not mm */ 66#define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 67/* Detailed timing descriptors have bogus size values, so just take the 68 * maximum size and use that. 69 */ 70#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 71/* Monitor forgot to set the first detailed is preferred bit. */ 72#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 73/* use +hsync +vsync for detailed mode */ 74#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 75/* Force reduced-blanking timings for detailed modes */ 76#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 77/* Force 8bpc */ 78#define EDID_QUIRK_FORCE_8BPC (1 << 8) 79/* Force 12bpc */ 80#define EDID_QUIRK_FORCE_12BPC (1 << 9) 81/* Force 6bpc */ 82#define EDID_QUIRK_FORCE_6BPC (1 << 10) 83/* Force 10bpc */ 84#define EDID_QUIRK_FORCE_10BPC (1 << 11) 85/* Non desktop display (i.e. HMD) */ 86#define EDID_QUIRK_NON_DESKTOP (1 << 12) 87 88struct detailed_mode_closure { 89 struct drm_connector *connector; 90 struct edid *edid; 91 bool preferred; 92 u32 quirks; 93 int modes; 94}; 95 96#define LEVEL_DMT 0 97#define LEVEL_GTF 1 98#define LEVEL_GTF2 2 99#define LEVEL_CVT 3 100 101static const struct edid_quirk { 102 char vendor[4]; 103 int product_id; 104 u32 quirks; 105} edid_quirk_list[] = { 106 /* Acer AL1706 */ 107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 108 /* Acer F51 */ 109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 110 /* Unknown Acer */ 111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 112 113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 115 116 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 117 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 118 119 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 120 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 121 122 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 123 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 124 125 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 126 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 127 128 /* Belinea 10 15 55 */ 129 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 130 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 131 132 /* Envision Peripherals, Inc. EN-7100e */ 133 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 134 /* Envision EN2028 */ 135 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 136 137 /* Funai Electronics PM36B */ 138 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 139 EDID_QUIRK_DETAILED_IN_CM }, 140 141 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 142 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 143 144 /* LG Philips LCD LP154W01-A5 */ 145 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 147 148 /* Philips 107p5 CRT */ 149 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 150 151 /* Proview AY765C */ 152 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 153 154 /* Samsung SyncMaster 205BW. Note: irony */ 155 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 156 /* Samsung SyncMaster 22[5-6]BW */ 157 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 158 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 159 160 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 161 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 162 163 /* ViewSonic VA2026w */ 164 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 165 166 /* Medion MD 30217 PG */ 167 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 168 169 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 170 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 171 172 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 173 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 174 175 /* Valve Index Headset */ 176 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 189 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 190 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 191 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 192 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 193 194 /* HTC Vive and Vive Pro VR Headsets */ 195 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 196 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 197 198 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ 199 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 200 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 201 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 202 203 /* Windows Mixed Reality Headsets */ 204 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 205 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 206 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 207 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 208 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 209 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 210 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 211 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 212 213 /* Sony PlayStation VR Headset */ 214 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 215 216 /* Sensics VR Headsets */ 217 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 218 219 /* OSVR HDK and HDK2 VR Headsets */ 220 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 221}; 222 223/* 224 * Autogenerated from the DMT spec. 225 * This table is copied from xfree86/modes/xf86EdidModes.c. 226 */ 227static const struct drm_display_mode drm_dmt_modes[] = { 228 /* 0x01 - 640x350@85Hz */ 229 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 230 736, 832, 0, 350, 382, 385, 445, 0, 231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 232 /* 0x02 - 640x400@85Hz */ 233 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 234 736, 832, 0, 400, 401, 404, 445, 0, 235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 236 /* 0x03 - 720x400@85Hz */ 237 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 238 828, 936, 0, 400, 401, 404, 446, 0, 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 240 /* 0x04 - 640x480@60Hz */ 241 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 242 752, 800, 0, 480, 490, 492, 525, 0, 243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 244 /* 0x05 - 640x480@72Hz */ 245 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 246 704, 832, 0, 480, 489, 492, 520, 0, 247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x06 - 640x480@75Hz */ 249 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 250 720, 840, 0, 480, 481, 484, 500, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 252 /* 0x07 - 640x480@85Hz */ 253 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 254 752, 832, 0, 480, 481, 484, 509, 0, 255 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 256 /* 0x08 - 800x600@56Hz */ 257 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 258 896, 1024, 0, 600, 601, 603, 625, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 260 /* 0x09 - 800x600@60Hz */ 261 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 262 968, 1056, 0, 600, 601, 605, 628, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 264 /* 0x0a - 800x600@72Hz */ 265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 266 976, 1040, 0, 600, 637, 643, 666, 0, 267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 268 /* 0x0b - 800x600@75Hz */ 269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 270 896, 1056, 0, 600, 601, 604, 625, 0, 271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 272 /* 0x0c - 800x600@85Hz */ 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 274 896, 1048, 0, 600, 601, 604, 631, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 276 /* 0x0d - 800x600@120Hz RB */ 277 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 278 880, 960, 0, 600, 603, 607, 636, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 280 /* 0x0e - 848x480@60Hz */ 281 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 282 976, 1088, 0, 480, 486, 494, 517, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 284 /* 0x0f - 1024x768@43Hz, interlace */ 285 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 286 1208, 1264, 0, 768, 768, 776, 817, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 288 DRM_MODE_FLAG_INTERLACE) }, 289 /* 0x10 - 1024x768@60Hz */ 290 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 291 1184, 1344, 0, 768, 771, 777, 806, 0, 292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 293 /* 0x11 - 1024x768@70Hz */ 294 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 295 1184, 1328, 0, 768, 771, 777, 806, 0, 296 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 297 /* 0x12 - 1024x768@75Hz */ 298 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 299 1136, 1312, 0, 768, 769, 772, 800, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 301 /* 0x13 - 1024x768@85Hz */ 302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 303 1168, 1376, 0, 768, 769, 772, 808, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 305 /* 0x14 - 1024x768@120Hz RB */ 306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 307 1104, 1184, 0, 768, 771, 775, 813, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 309 /* 0x15 - 1152x864@75Hz */ 310 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 311 1344, 1600, 0, 864, 865, 868, 900, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 313 /* 0x55 - 1280x720@60Hz */ 314 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 315 1430, 1650, 0, 720, 725, 730, 750, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 317 /* 0x16 - 1280x768@60Hz RB */ 318 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 319 1360, 1440, 0, 768, 771, 778, 790, 0, 320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 321 /* 0x17 - 1280x768@60Hz */ 322 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 323 1472, 1664, 0, 768, 771, 778, 798, 0, 324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 0x18 - 1280x768@75Hz */ 326 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 327 1488, 1696, 0, 768, 771, 778, 805, 0, 328 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x19 - 1280x768@85Hz */ 330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 331 1496, 1712, 0, 768, 771, 778, 809, 0, 332 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 333 /* 0x1a - 1280x768@120Hz RB */ 334 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 335 1360, 1440, 0, 768, 771, 778, 813, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 337 /* 0x1b - 1280x800@60Hz RB */ 338 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 339 1360, 1440, 0, 800, 803, 809, 823, 0, 340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 341 /* 0x1c - 1280x800@60Hz */ 342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 343 1480, 1680, 0, 800, 803, 809, 831, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 0x1d - 1280x800@75Hz */ 346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 347 1488, 1696, 0, 800, 803, 809, 838, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 349 /* 0x1e - 1280x800@85Hz */ 350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 351 1496, 1712, 0, 800, 803, 809, 843, 0, 352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 353 /* 0x1f - 1280x800@120Hz RB */ 354 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 355 1360, 1440, 0, 800, 803, 809, 847, 0, 356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 357 /* 0x20 - 1280x960@60Hz */ 358 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 359 1488, 1800, 0, 960, 961, 964, 1000, 0, 360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x21 - 1280x960@85Hz */ 362 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 363 1504, 1728, 0, 960, 961, 964, 1011, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 365 /* 0x22 - 1280x960@120Hz RB */ 366 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 367 1360, 1440, 0, 960, 963, 967, 1017, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 369 /* 0x23 - 1280x1024@60Hz */ 370 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 371 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 373 /* 0x24 - 1280x1024@75Hz */ 374 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 375 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x25 - 1280x1024@85Hz */ 378 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 379 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 381 /* 0x26 - 1280x1024@120Hz RB */ 382 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 383 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 385 /* 0x27 - 1360x768@60Hz */ 386 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 387 1536, 1792, 0, 768, 771, 777, 795, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 0x28 - 1360x768@120Hz RB */ 390 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 391 1440, 1520, 0, 768, 771, 776, 813, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 393 /* 0x51 - 1366x768@60Hz */ 394 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 395 1579, 1792, 0, 768, 771, 774, 798, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 397 /* 0x56 - 1366x768@60Hz */ 398 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 399 1436, 1500, 0, 768, 769, 772, 800, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 401 /* 0x29 - 1400x1050@60Hz RB */ 402 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 403 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 405 /* 0x2a - 1400x1050@60Hz */ 406 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 407 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 0x2b - 1400x1050@75Hz */ 410 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 411 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 0x2c - 1400x1050@85Hz */ 414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 415 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 417 /* 0x2d - 1400x1050@120Hz RB */ 418 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 419 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 421 /* 0x2e - 1440x900@60Hz RB */ 422 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 423 1520, 1600, 0, 900, 903, 909, 926, 0, 424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 425 /* 0x2f - 1440x900@60Hz */ 426 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 427 1672, 1904, 0, 900, 903, 909, 934, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x30 - 1440x900@75Hz */ 430 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 431 1688, 1936, 0, 900, 903, 909, 942, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 0x31 - 1440x900@85Hz */ 434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 435 1696, 1952, 0, 900, 903, 909, 948, 0, 436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 437 /* 0x32 - 1440x900@120Hz RB */ 438 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 439 1520, 1600, 0, 900, 903, 909, 953, 0, 440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 441 /* 0x53 - 1600x900@60Hz */ 442 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 443 1704, 1800, 0, 900, 901, 904, 1000, 0, 444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 445 /* 0x33 - 1600x1200@60Hz */ 446 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 447 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x34 - 1600x1200@65Hz */ 450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x35 - 1600x1200@70Hz */ 454 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 455 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 0x36 - 1600x1200@75Hz */ 458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 0x37 - 1600x1200@85Hz */ 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 463 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 0x38 - 1600x1200@120Hz RB */ 466 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 467 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 469 /* 0x39 - 1680x1050@60Hz RB */ 470 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 471 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 473 /* 0x3a - 1680x1050@60Hz */ 474 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 475 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x3b - 1680x1050@75Hz */ 478 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 479 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 481 /* 0x3c - 1680x1050@85Hz */ 482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 483 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 485 /* 0x3d - 1680x1050@120Hz RB */ 486 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 487 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 489 /* 0x3e - 1792x1344@60Hz */ 490 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 491 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x3f - 1792x1344@75Hz */ 494 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 495 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 497 /* 0x40 - 1792x1344@120Hz RB */ 498 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 499 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 501 /* 0x41 - 1856x1392@60Hz */ 502 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 503 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 505 /* 0x42 - 1856x1392@75Hz */ 506 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 507 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 509 /* 0x43 - 1856x1392@120Hz RB */ 510 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 511 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 513 /* 0x52 - 1920x1080@60Hz */ 514 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 515 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 516 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 517 /* 0x44 - 1920x1200@60Hz RB */ 518 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 519 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 521 /* 0x45 - 1920x1200@60Hz */ 522 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 523 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 525 /* 0x46 - 1920x1200@75Hz */ 526 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 527 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 529 /* 0x47 - 1920x1200@85Hz */ 530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 531 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 533 /* 0x48 - 1920x1200@120Hz RB */ 534 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 535 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 537 /* 0x49 - 1920x1440@60Hz */ 538 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 539 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 541 /* 0x4a - 1920x1440@75Hz */ 542 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 543 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 545 /* 0x4b - 1920x1440@120Hz RB */ 546 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 547 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 549 /* 0x54 - 2048x1152@60Hz */ 550 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 551 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 553 /* 0x4c - 2560x1600@60Hz RB */ 554 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 555 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 557 /* 0x4d - 2560x1600@60Hz */ 558 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 559 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 561 /* 0x4e - 2560x1600@75Hz */ 562 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 563 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 565 /* 0x4f - 2560x1600@85Hz */ 566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 567 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 568 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 569 /* 0x50 - 2560x1600@120Hz RB */ 570 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 571 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 573 /* 0x57 - 4096x2160@60Hz RB */ 574 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 575 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 577 /* 0x58 - 4096x2160@59.94Hz RB */ 578 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 579 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 581}; 582 583/* 584 * These more or less come from the DMT spec. The 720x400 modes are 585 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 586 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 587 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 588 * mode. 589 * 590 * The DMT modes have been fact-checked; the rest are mild guesses. 591 */ 592static const struct drm_display_mode edid_est_modes[] = { 593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 594 968, 1056, 0, 600, 601, 605, 628, 0, 595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 596 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 597 896, 1024, 0, 600, 601, 603, 625, 0, 598 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 600 720, 840, 0, 480, 481, 484, 500, 0, 601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 603 704, 832, 0, 480, 489, 492, 520, 0, 604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 606 768, 864, 0, 480, 483, 486, 525, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 608 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 609 752, 800, 0, 480, 490, 492, 525, 0, 610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 612 846, 900, 0, 400, 421, 423, 449, 0, 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 614 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 615 846, 900, 0, 400, 412, 414, 449, 0, 616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 617 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 618 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 621 1136, 1312, 0, 768, 769, 772, 800, 0, 622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 624 1184, 1328, 0, 768, 771, 777, 806, 0, 625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 626 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 627 1184, 1344, 0, 768, 771, 777, 806, 0, 628 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 629 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 630 1208, 1264, 0, 768, 768, 776, 817, 0, 631 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 632 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 633 928, 1152, 0, 624, 625, 628, 667, 0, 634 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 636 896, 1056, 0, 600, 601, 604, 625, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 638 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 639 976, 1040, 0, 600, 637, 643, 666, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 641 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 642 1344, 1600, 0, 864, 865, 868, 900, 0, 643 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 644}; 645 646struct minimode { 647 short w; 648 short h; 649 short r; 650 short rb; 651}; 652 653static const struct minimode est3_modes[] = { 654 /* byte 6 */ 655 { 640, 350, 85, 0 }, 656 { 640, 400, 85, 0 }, 657 { 720, 400, 85, 0 }, 658 { 640, 480, 85, 0 }, 659 { 848, 480, 60, 0 }, 660 { 800, 600, 85, 0 }, 661 { 1024, 768, 85, 0 }, 662 { 1152, 864, 75, 0 }, 663 /* byte 7 */ 664 { 1280, 768, 60, 1 }, 665 { 1280, 768, 60, 0 }, 666 { 1280, 768, 75, 0 }, 667 { 1280, 768, 85, 0 }, 668 { 1280, 960, 60, 0 }, 669 { 1280, 960, 85, 0 }, 670 { 1280, 1024, 60, 0 }, 671 { 1280, 1024, 85, 0 }, 672 /* byte 8 */ 673 { 1360, 768, 60, 0 }, 674 { 1440, 900, 60, 1 }, 675 { 1440, 900, 60, 0 }, 676 { 1440, 900, 75, 0 }, 677 { 1440, 900, 85, 0 }, 678 { 1400, 1050, 60, 1 }, 679 { 1400, 1050, 60, 0 }, 680 { 1400, 1050, 75, 0 }, 681 /* byte 9 */ 682 { 1400, 1050, 85, 0 }, 683 { 1680, 1050, 60, 1 }, 684 { 1680, 1050, 60, 0 }, 685 { 1680, 1050, 75, 0 }, 686 { 1680, 1050, 85, 0 }, 687 { 1600, 1200, 60, 0 }, 688 { 1600, 1200, 65, 0 }, 689 { 1600, 1200, 70, 0 }, 690 /* byte 10 */ 691 { 1600, 1200, 75, 0 }, 692 { 1600, 1200, 85, 0 }, 693 { 1792, 1344, 60, 0 }, 694 { 1792, 1344, 75, 0 }, 695 { 1856, 1392, 60, 0 }, 696 { 1856, 1392, 75, 0 }, 697 { 1920, 1200, 60, 1 }, 698 { 1920, 1200, 60, 0 }, 699 /* byte 11 */ 700 { 1920, 1200, 75, 0 }, 701 { 1920, 1200, 85, 0 }, 702 { 1920, 1440, 60, 0 }, 703 { 1920, 1440, 75, 0 }, 704}; 705 706static const struct minimode extra_modes[] = { 707 { 1024, 576, 60, 0 }, 708 { 1366, 768, 60, 0 }, 709 { 1600, 900, 60, 0 }, 710 { 1680, 945, 60, 0 }, 711 { 1920, 1080, 60, 0 }, 712 { 2048, 1152, 60, 0 }, 713 { 2048, 1536, 60, 0 }, 714}; 715 716/* 717 * Probably taken from CEA-861 spec. 718 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 719 * 720 * Index using the VIC. 721 */ 722static const struct drm_display_mode edid_cea_modes[] = { 723 /* 0 - dummy, VICs start at 1 */ 724 { }, 725 /* 1 - 640x480@60Hz 4:3 */ 726 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 727 752, 800, 0, 480, 490, 492, 525, 0, 728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 729 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 730 /* 2 - 720x480@60Hz 4:3 */ 731 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 732 798, 858, 0, 480, 489, 495, 525, 0, 733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 734 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 735 /* 3 - 720x480@60Hz 16:9 */ 736 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 737 798, 858, 0, 480, 489, 495, 525, 0, 738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 739 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 740 /* 4 - 1280x720@60Hz 16:9 */ 741 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 742 1430, 1650, 0, 720, 725, 730, 750, 0, 743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 744 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 745 /* 5 - 1920x1080i@60Hz 16:9 */ 746 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 747 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 748 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 749 DRM_MODE_FLAG_INTERLACE), 750 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 751 /* 6 - 720(1440)x480i@60Hz 4:3 */ 752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 753 801, 858, 0, 480, 488, 494, 525, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 756 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 757 /* 7 - 720(1440)x480i@60Hz 16:9 */ 758 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 759 801, 858, 0, 480, 488, 494, 525, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 761 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 762 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 763 /* 8 - 720(1440)x240@60Hz 4:3 */ 764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 765 801, 858, 0, 240, 244, 247, 262, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 767 DRM_MODE_FLAG_DBLCLK), 768 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 769 /* 9 - 720(1440)x240@60Hz 16:9 */ 770 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 771 801, 858, 0, 240, 244, 247, 262, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 773 DRM_MODE_FLAG_DBLCLK), 774 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 775 /* 10 - 2880x480i@60Hz 4:3 */ 776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 777 3204, 3432, 0, 480, 488, 494, 525, 0, 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 779 DRM_MODE_FLAG_INTERLACE), 780 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 781 /* 11 - 2880x480i@60Hz 16:9 */ 782 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 783 3204, 3432, 0, 480, 488, 494, 525, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 785 DRM_MODE_FLAG_INTERLACE), 786 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 787 /* 12 - 2880x240@60Hz 4:3 */ 788 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 789 3204, 3432, 0, 240, 244, 247, 262, 0, 790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 791 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 792 /* 13 - 2880x240@60Hz 16:9 */ 793 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 794 3204, 3432, 0, 240, 244, 247, 262, 0, 795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 796 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 797 /* 14 - 1440x480@60Hz 4:3 */ 798 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 799 1596, 1716, 0, 480, 489, 495, 525, 0, 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 801 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 802 /* 15 - 1440x480@60Hz 16:9 */ 803 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 804 1596, 1716, 0, 480, 489, 495, 525, 0, 805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 806 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 807 /* 16 - 1920x1080@60Hz 16:9 */ 808 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 809 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 810 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 811 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 812 /* 17 - 720x576@50Hz 4:3 */ 813 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 814 796, 864, 0, 576, 581, 586, 625, 0, 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 816 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 817 /* 18 - 720x576@50Hz 16:9 */ 818 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 819 796, 864, 0, 576, 581, 586, 625, 0, 820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 821 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 822 /* 19 - 1280x720@50Hz 16:9 */ 823 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 824 1760, 1980, 0, 720, 725, 730, 750, 0, 825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 826 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 827 /* 20 - 1920x1080i@50Hz 16:9 */ 828 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 829 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 831 DRM_MODE_FLAG_INTERLACE), 832 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 833 /* 21 - 720(1440)x576i@50Hz 4:3 */ 834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 835 795, 864, 0, 576, 580, 586, 625, 0, 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 838 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 839 /* 22 - 720(1440)x576i@50Hz 16:9 */ 840 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 841 795, 864, 0, 576, 580, 586, 625, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 843 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 844 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 845 /* 23 - 720(1440)x288@50Hz 4:3 */ 846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 847 795, 864, 0, 288, 290, 293, 312, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 849 DRM_MODE_FLAG_DBLCLK), 850 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 851 /* 24 - 720(1440)x288@50Hz 16:9 */ 852 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 853 795, 864, 0, 288, 290, 293, 312, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 855 DRM_MODE_FLAG_DBLCLK), 856 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 857 /* 25 - 2880x576i@50Hz 4:3 */ 858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 859 3180, 3456, 0, 576, 580, 586, 625, 0, 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 861 DRM_MODE_FLAG_INTERLACE), 862 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 863 /* 26 - 2880x576i@50Hz 16:9 */ 864 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 865 3180, 3456, 0, 576, 580, 586, 625, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 867 DRM_MODE_FLAG_INTERLACE), 868 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 869 /* 27 - 2880x288@50Hz 4:3 */ 870 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 871 3180, 3456, 0, 288, 290, 293, 312, 0, 872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 873 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 874 /* 28 - 2880x288@50Hz 16:9 */ 875 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 876 3180, 3456, 0, 288, 290, 293, 312, 0, 877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 878 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 879 /* 29 - 1440x576@50Hz 4:3 */ 880 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 881 1592, 1728, 0, 576, 581, 586, 625, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 883 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 884 /* 30 - 1440x576@50Hz 16:9 */ 885 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 886 1592, 1728, 0, 576, 581, 586, 625, 0, 887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 888 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 889 /* 31 - 1920x1080@50Hz 16:9 */ 890 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 891 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 893 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 894 /* 32 - 1920x1080@24Hz 16:9 */ 895 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 896 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 898 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 899 /* 33 - 1920x1080@25Hz 16:9 */ 900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 901 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 903 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 904 /* 34 - 1920x1080@30Hz 16:9 */ 905 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 906 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 908 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 909 /* 35 - 2880x480@60Hz 4:3 */ 910 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 911 3192, 3432, 0, 480, 489, 495, 525, 0, 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 913 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 914 /* 36 - 2880x480@60Hz 16:9 */ 915 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 916 3192, 3432, 0, 480, 489, 495, 525, 0, 917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 918 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 919 /* 37 - 2880x576@50Hz 4:3 */ 920 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 921 3184, 3456, 0, 576, 581, 586, 625, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 923 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 924 /* 38 - 2880x576@50Hz 16:9 */ 925 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 926 3184, 3456, 0, 576, 581, 586, 625, 0, 927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 928 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 39 - 1920x1080i@50Hz 16:9 */ 930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 931 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 933 DRM_MODE_FLAG_INTERLACE), 934 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 40 - 1920x1080i@100Hz 16:9 */ 936 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 937 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 939 DRM_MODE_FLAG_INTERLACE), 940 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 941 /* 41 - 1280x720@100Hz 16:9 */ 942 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 943 1760, 1980, 0, 720, 725, 730, 750, 0, 944 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 945 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 946 /* 42 - 720x576@100Hz 4:3 */ 947 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 948 796, 864, 0, 576, 581, 586, 625, 0, 949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 950 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 951 /* 43 - 720x576@100Hz 16:9 */ 952 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 953 796, 864, 0, 576, 581, 586, 625, 0, 954 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 955 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 956 /* 44 - 720(1440)x576i@100Hz 4:3 */ 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 958 795, 864, 0, 576, 580, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 961 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 962 /* 45 - 720(1440)x576i@100Hz 16:9 */ 963 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 964 795, 864, 0, 576, 580, 586, 625, 0, 965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 966 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 967 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 968 /* 46 - 1920x1080i@120Hz 16:9 */ 969 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 970 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 972 DRM_MODE_FLAG_INTERLACE), 973 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 974 /* 47 - 1280x720@120Hz 16:9 */ 975 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 976 1430, 1650, 0, 720, 725, 730, 750, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 978 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 979 /* 48 - 720x480@120Hz 4:3 */ 980 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 981 798, 858, 0, 480, 489, 495, 525, 0, 982 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 983 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 984 /* 49 - 720x480@120Hz 16:9 */ 985 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 986 798, 858, 0, 480, 489, 495, 525, 0, 987 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 988 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 989 /* 50 - 720(1440)x480i@120Hz 4:3 */ 990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 991 801, 858, 0, 480, 488, 494, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 994 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 995 /* 51 - 720(1440)x480i@120Hz 16:9 */ 996 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 997 801, 858, 0, 480, 488, 494, 525, 0, 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 999 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1000 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1001 /* 52 - 720x576@200Hz 4:3 */ 1002 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1003 796, 864, 0, 576, 581, 586, 625, 0, 1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1005 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1006 /* 53 - 720x576@200Hz 16:9 */ 1007 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1008 796, 864, 0, 576, 581, 586, 625, 0, 1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1010 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1011 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1013 795, 864, 0, 576, 580, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1016 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1017 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1018 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1019 795, 864, 0, 576, 580, 586, 625, 0, 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1021 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1022 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1023 /* 56 - 720x480@240Hz 4:3 */ 1024 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1025 798, 858, 0, 480, 489, 495, 525, 0, 1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1027 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1028 /* 57 - 720x480@240Hz 16:9 */ 1029 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1030 798, 858, 0, 480, 489, 495, 525, 0, 1031 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1032 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1033 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1035 801, 858, 0, 480, 488, 494, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1038 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1039 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1040 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1041 801, 858, 0, 480, 488, 494, 525, 0, 1042 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1043 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1044 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1045 /* 60 - 1280x720@24Hz 16:9 */ 1046 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1047 3080, 3300, 0, 720, 725, 730, 750, 0, 1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1049 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1050 /* 61 - 1280x720@25Hz 16:9 */ 1051 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1052 3740, 3960, 0, 720, 725, 730, 750, 0, 1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1054 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1055 /* 62 - 1280x720@30Hz 16:9 */ 1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1057 3080, 3300, 0, 720, 725, 730, 750, 0, 1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1059 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1060 /* 63 - 1920x1080@120Hz 16:9 */ 1061 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1062 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1064 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1065 /* 64 - 1920x1080@100Hz 16:9 */ 1066 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1067 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1069 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1070 /* 65 - 1280x720@24Hz 64:27 */ 1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1072 3080, 3300, 0, 720, 725, 730, 750, 0, 1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1074 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1075 /* 66 - 1280x720@25Hz 64:27 */ 1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1077 3740, 3960, 0, 720, 725, 730, 750, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1079 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1080 /* 67 - 1280x720@30Hz 64:27 */ 1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1082 3080, 3300, 0, 720, 725, 730, 750, 0, 1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1084 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1085 /* 68 - 1280x720@50Hz 64:27 */ 1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1087 1760, 1980, 0, 720, 725, 730, 750, 0, 1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1089 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1090 /* 69 - 1280x720@60Hz 64:27 */ 1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1092 1430, 1650, 0, 720, 725, 730, 750, 0, 1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1094 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1095 /* 70 - 1280x720@100Hz 64:27 */ 1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1097 1760, 1980, 0, 720, 725, 730, 750, 0, 1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1099 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1100 /* 71 - 1280x720@120Hz 64:27 */ 1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1102 1430, 1650, 0, 720, 725, 730, 750, 0, 1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1104 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1105 /* 72 - 1920x1080@24Hz 64:27 */ 1106 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1107 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1109 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1110 /* 73 - 1920x1080@25Hz 64:27 */ 1111 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1112 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1114 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1115 /* 74 - 1920x1080@30Hz 64:27 */ 1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1117 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1119 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1120 /* 75 - 1920x1080@50Hz 64:27 */ 1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1122 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1124 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1125 /* 76 - 1920x1080@60Hz 64:27 */ 1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1127 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1129 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1130 /* 77 - 1920x1080@100Hz 64:27 */ 1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1132 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1134 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1135 /* 78 - 1920x1080@120Hz 64:27 */ 1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1137 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1139 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1140 /* 79 - 1680x720@24Hz 64:27 */ 1141 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1142 3080, 3300, 0, 720, 725, 730, 750, 0, 1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1144 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1145 /* 80 - 1680x720@25Hz 64:27 */ 1146 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1147 2948, 3168, 0, 720, 725, 730, 750, 0, 1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1149 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1150 /* 81 - 1680x720@30Hz 64:27 */ 1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1152 2420, 2640, 0, 720, 725, 730, 750, 0, 1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1154 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1155 /* 82 - 1680x720@50Hz 64:27 */ 1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1157 1980, 2200, 0, 720, 725, 730, 750, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1159 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1160 /* 83 - 1680x720@60Hz 64:27 */ 1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1162 1980, 2200, 0, 720, 725, 730, 750, 0, 1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1164 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1165 /* 84 - 1680x720@100Hz 64:27 */ 1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1167 1780, 2000, 0, 720, 725, 730, 825, 0, 1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1169 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1170 /* 85 - 1680x720@120Hz 64:27 */ 1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1172 1780, 2000, 0, 720, 725, 730, 825, 0, 1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1174 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1175 /* 86 - 2560x1080@24Hz 64:27 */ 1176 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1177 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1179 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1180 /* 87 - 2560x1080@25Hz 64:27 */ 1181 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1182 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1184 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1185 /* 88 - 2560x1080@30Hz 64:27 */ 1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1187 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1189 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1190 /* 89 - 2560x1080@50Hz 64:27 */ 1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1192 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1194 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1195 /* 90 - 2560x1080@60Hz 64:27 */ 1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1197 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1199 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1200 /* 91 - 2560x1080@100Hz 64:27 */ 1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1202 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1204 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1205 /* 92 - 2560x1080@120Hz 64:27 */ 1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1207 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1209 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1210 /* 93 - 3840x2160@24Hz 16:9 */ 1211 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1212 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1214 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1215 /* 94 - 3840x2160@25Hz 16:9 */ 1216 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1217 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1219 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1220 /* 95 - 3840x2160@30Hz 16:9 */ 1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1222 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1224 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1225 /* 96 - 3840x2160@50Hz 16:9 */ 1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1227 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1229 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1230 /* 97 - 3840x2160@60Hz 16:9 */ 1231 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1232 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1234 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1235 /* 98 - 4096x2160@24Hz 256:135 */ 1236 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1237 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1239 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1240 /* 99 - 4096x2160@25Hz 256:135 */ 1241 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1242 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1244 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1245 /* 100 - 4096x2160@30Hz 256:135 */ 1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1247 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1249 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1250 /* 101 - 4096x2160@50Hz 256:135 */ 1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1252 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1254 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1255 /* 102 - 4096x2160@60Hz 256:135 */ 1256 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1257 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1259 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1260 /* 103 - 3840x2160@24Hz 64:27 */ 1261 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1262 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1264 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1265 /* 104 - 3840x2160@25Hz 64:27 */ 1266 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1267 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1269 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1270 /* 105 - 3840x2160@30Hz 64:27 */ 1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1272 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1274 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1275 /* 106 - 3840x2160@50Hz 64:27 */ 1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1277 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1279 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1280 /* 107 - 3840x2160@60Hz 64:27 */ 1281 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1282 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1284 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1285}; 1286 1287/* 1288 * HDMI 1.4 4k modes. Index using the VIC. 1289 */ 1290static const struct drm_display_mode edid_4k_modes[] = { 1291 /* 0 - dummy, VICs start at 1 */ 1292 { }, 1293 /* 1 - 3840x2160@30Hz */ 1294 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1295 3840, 4016, 4104, 4400, 0, 1296 2160, 2168, 2178, 2250, 0, 1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1298 .vrefresh = 30, }, 1299 /* 2 - 3840x2160@25Hz */ 1300 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1301 3840, 4896, 4984, 5280, 0, 1302 2160, 2168, 2178, 2250, 0, 1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1304 .vrefresh = 25, }, 1305 /* 3 - 3840x2160@24Hz */ 1306 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1307 3840, 5116, 5204, 5500, 0, 1308 2160, 2168, 2178, 2250, 0, 1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1310 .vrefresh = 24, }, 1311 /* 4 - 4096x2160@24Hz (SMPTE) */ 1312 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1313 4096, 5116, 5204, 5500, 0, 1314 2160, 2168, 2178, 2250, 0, 1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1316 .vrefresh = 24, }, 1317}; 1318 1319/*** DDC fetch and block validation ***/ 1320 1321static const u8 edid_header[] = { 1322 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1323}; 1324 1325/** 1326 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1327 * @raw_edid: pointer to raw base EDID block 1328 * 1329 * Sanity check the header of the base EDID block. 1330 * 1331 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1332 */ 1333int drm_edid_header_is_valid(const u8 *raw_edid) 1334{ 1335 int i, score = 0; 1336 1337 for (i = 0; i < sizeof(edid_header); i++) 1338 if (raw_edid[i] == edid_header[i]) 1339 score++; 1340 1341 return score; 1342} 1343EXPORT_SYMBOL(drm_edid_header_is_valid); 1344 1345static int edid_fixup __read_mostly = 6; 1346module_param_named(edid_fixup, edid_fixup, int, 0400); 1347MODULE_PARM_DESC(edid_fixup, 1348 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1349 1350static void drm_get_displayid(struct drm_connector *connector, 1351 struct edid *edid); 1352 1353static int drm_edid_block_checksum(const u8 *raw_edid) 1354{ 1355 int i; 1356 u8 csum = 0; 1357 for (i = 0; i < EDID_LENGTH; i++) 1358 csum += raw_edid[i]; 1359 1360 return csum; 1361} 1362 1363static bool drm_edid_is_zero(const u8 *in_edid, int length) 1364{ 1365 if (memchr_inv(in_edid, 0, length)) 1366 return false; 1367 1368 return true; 1369} 1370 1371/** 1372 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1373 * @raw_edid: pointer to raw EDID block 1374 * @block: type of block to validate (0 for base, extension otherwise) 1375 * @print_bad_edid: if true, dump bad EDID blocks to the console 1376 * @edid_corrupt: if true, the header or checksum is invalid 1377 * 1378 * Validate a base or extension EDID block and optionally dump bad blocks to 1379 * the console. 1380 * 1381 * Return: True if the block is valid, false otherwise. 1382 */ 1383bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1384 bool *edid_corrupt) 1385{ 1386 u8 csum; 1387 struct edid *edid = (struct edid *)raw_edid; 1388 1389 if (WARN_ON(!raw_edid)) 1390 return false; 1391 1392 if (edid_fixup > 8 || edid_fixup < 0) 1393 edid_fixup = 6; 1394 1395 if (block == 0) { 1396 int score = drm_edid_header_is_valid(raw_edid); 1397 if (score == 8) { 1398 if (edid_corrupt) 1399 *edid_corrupt = false; 1400 } else if (score >= edid_fixup) { 1401 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1402 * The corrupt flag needs to be set here otherwise, the 1403 * fix-up code here will correct the problem, the 1404 * checksum is correct and the test fails 1405 */ 1406 if (edid_corrupt) 1407 *edid_corrupt = true; 1408 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1409 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1410 } else { 1411 if (edid_corrupt) 1412 *edid_corrupt = true; 1413 goto bad; 1414 } 1415 } 1416 1417 csum = drm_edid_block_checksum(raw_edid); 1418 if (csum) { 1419 if (edid_corrupt) 1420 *edid_corrupt = true; 1421 1422 /* allow CEA to slide through, switches mangle this */ 1423 if (raw_edid[0] == CEA_EXT) { 1424 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1425 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1426 } else { 1427 if (print_bad_edid) 1428 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1429 1430 goto bad; 1431 } 1432 } 1433 1434 /* per-block-type checks */ 1435 switch (raw_edid[0]) { 1436 case 0: /* base */ 1437 if (edid->version != 1) { 1438 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1439 goto bad; 1440 } 1441 1442 if (edid->revision > 4) 1443 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1444 break; 1445 1446 default: 1447 break; 1448 } 1449 1450 return true; 1451 1452bad: 1453 if (print_bad_edid) { 1454 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1455 pr_notice("EDID block is all zeroes\n"); 1456 } else { 1457 pr_notice("Raw EDID:\n"); 1458 print_hex_dump(KERN_NOTICE, 1459 " \t", DUMP_PREFIX_NONE, 16, 1, 1460 raw_edid, EDID_LENGTH, false); 1461 } 1462 } 1463 return false; 1464} 1465EXPORT_SYMBOL(drm_edid_block_valid); 1466 1467/** 1468 * drm_edid_is_valid - sanity check EDID data 1469 * @edid: EDID data 1470 * 1471 * Sanity-check an entire EDID record (including extensions) 1472 * 1473 * Return: True if the EDID data is valid, false otherwise. 1474 */ 1475bool drm_edid_is_valid(struct edid *edid) 1476{ 1477 int i; 1478 u8 *raw = (u8 *)edid; 1479 1480 if (!edid) 1481 return false; 1482 1483 for (i = 0; i <= edid->extensions; i++) 1484 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1485 return false; 1486 1487 return true; 1488} 1489EXPORT_SYMBOL(drm_edid_is_valid); 1490 1491#define DDC_SEGMENT_ADDR 0x30 1492/** 1493 * drm_do_probe_ddc_edid() - get EDID information via I2C 1494 * @data: I2C device adapter 1495 * @buf: EDID data buffer to be filled 1496 * @block: 128 byte EDID block to start fetching from 1497 * @len: EDID data buffer length to fetch 1498 * 1499 * Try to fetch EDID information by calling I2C driver functions. 1500 * 1501 * Return: 0 on success or -1 on failure. 1502 */ 1503static int 1504drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1505{ 1506 struct i2c_adapter *adapter = data; 1507 unsigned char start = block * EDID_LENGTH; 1508 unsigned char segment = block >> 1; 1509 unsigned char xfers = segment ? 3 : 2; 1510 int ret, retries = 5; 1511 1512 /* 1513 * The core I2C driver will automatically retry the transfer if the 1514 * adapter reports EAGAIN. However, we find that bit-banging transfers 1515 * are susceptible to errors under a heavily loaded machine and 1516 * generate spurious NAKs and timeouts. Retrying the transfer 1517 * of the individual block a few times seems to overcome this. 1518 */ 1519 do { 1520 struct i2c_msg msgs[] = { 1521 { 1522 .addr = DDC_SEGMENT_ADDR, 1523 .flags = 0, 1524 .len = 1, 1525 .buf = &segment, 1526 }, { 1527 .addr = DDC_ADDR, 1528 .flags = 0, 1529 .len = 1, 1530 .buf = &start, 1531 }, { 1532 .addr = DDC_ADDR, 1533 .flags = I2C_M_RD, 1534 .len = len, 1535 .buf = buf, 1536 } 1537 }; 1538 1539 /* 1540 * Avoid sending the segment addr to not upset non-compliant 1541 * DDC monitors. 1542 */ 1543 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1544 1545 if (ret == -ENXIO) { 1546 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1547 adapter->name); 1548 break; 1549 } 1550 } while (ret != xfers && --retries); 1551 1552 return ret == xfers ? 0 : -1; 1553} 1554 1555static void connector_bad_edid(struct drm_connector *connector, 1556 u8 *edid, int num_blocks) 1557{ 1558 int i; 1559 1560 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS)) 1561 return; 1562 1563 dev_warn(connector->dev->dev, 1564 "%s: EDID is invalid:\n", 1565 connector->name); 1566 for (i = 0; i < num_blocks; i++) { 1567 u8 *block = edid + i * EDID_LENGTH; 1568 char prefix[20]; 1569 1570 if (drm_edid_is_zero(block, EDID_LENGTH)) 1571 snprintf(prefix, sizeof(prefix), "\t[%02x] ZERO ", i); 1572 else if (!drm_edid_block_valid(block, i, false, NULL)) 1573 snprintf(prefix, sizeof(prefix), "\t[%02x] BAD ", i); 1574 else 1575 snprintf(prefix, sizeof(prefix), "\t[%02x] GOOD ", i); 1576 1577 print_hex_dump(KERN_WARNING, 1578 prefix, DUMP_PREFIX_NONE, 16, 1, 1579 block, EDID_LENGTH, false); 1580 } 1581} 1582 1583/* Get override or firmware EDID */ 1584static struct edid *drm_get_override_edid(struct drm_connector *connector) 1585{ 1586 struct edid *override = NULL; 1587 1588 if (connector->override_edid) 1589 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1590 1591 if (!override) 1592 override = drm_load_edid_firmware(connector); 1593 1594 return IS_ERR(override) ? NULL : override; 1595} 1596 1597/** 1598 * drm_add_override_edid_modes - add modes from override/firmware EDID 1599 * @connector: connector we're probing 1600 * 1601 * Add modes from the override/firmware EDID, if available. Only to be used from 1602 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1603 * failed during drm_get_edid() and caused the override/firmware EDID to be 1604 * skipped. 1605 * 1606 * Return: The number of modes added or 0 if we couldn't find any. 1607 */ 1608int drm_add_override_edid_modes(struct drm_connector *connector) 1609{ 1610 struct edid *override; 1611 int num_modes = 0; 1612 1613 override = drm_get_override_edid(connector); 1614 if (override) { 1615 drm_connector_update_edid_property(connector, override); 1616 num_modes = drm_add_edid_modes(connector, override); 1617 kfree(override); 1618 1619 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1620 connector->base.id, connector->name, num_modes); 1621 } 1622 1623 return num_modes; 1624} 1625EXPORT_SYMBOL(drm_add_override_edid_modes); 1626 1627/** 1628 * drm_do_get_edid - get EDID data using a custom EDID block read function 1629 * @connector: connector we're probing 1630 * @get_edid_block: EDID block read function 1631 * @data: private data passed to the block read function 1632 * 1633 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1634 * exposes a different interface to read EDID blocks this function can be used 1635 * to get EDID data using a custom block read function. 1636 * 1637 * As in the general case the DDC bus is accessible by the kernel at the I2C 1638 * level, drivers must make all reasonable efforts to expose it as an I2C 1639 * adapter and use drm_get_edid() instead of abusing this function. 1640 * 1641 * The EDID may be overridden using debugfs override_edid or firmare EDID 1642 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1643 * order. Having either of them bypasses actual EDID reads. 1644 * 1645 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1646 */ 1647struct edid *drm_do_get_edid(struct drm_connector *connector, 1648 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1649 size_t len), 1650 void *data) 1651{ 1652 int i, j = 0, valid_extensions = 0; 1653 u8 *edid, *new; 1654 struct edid *override; 1655 1656 override = drm_get_override_edid(connector); 1657 if (override) 1658 return override; 1659 1660 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1661 return NULL; 1662 1663 /* base block fetch */ 1664 for (i = 0; i < 4; i++) { 1665 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1666 goto out; 1667 if (drm_edid_block_valid(edid, 0, false, 1668 &connector->edid_corrupt)) 1669 break; 1670 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1671 connector->null_edid_counter++; 1672 goto carp; 1673 } 1674 } 1675 if (i == 4) 1676 goto carp; 1677 1678 /* if there's no extensions, we're done */ 1679 valid_extensions = edid[0x7e]; 1680 if (valid_extensions == 0) 1681 return (struct edid *)edid; 1682 1683 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1684 if (!new) 1685 goto out; 1686 memcpy(new, edid, EDID_LENGTH); 1687 kfree(edid); 1688 edid = new; 1689 1690 for (j = 1; j <= edid[0x7e]; j++) { 1691 u8 *block = edid + j * EDID_LENGTH; 1692 1693 for (i = 0; i < 4; i++) { 1694 if (get_edid_block(data, block, j, EDID_LENGTH)) 1695 goto out; 1696 if (drm_edid_block_valid(block, j, false, NULL)) 1697 break; 1698 } 1699 1700 if (i == 4) 1701 valid_extensions--; 1702 } 1703 1704 if (valid_extensions != edid[0x7e]) { 1705 u8 *base; 1706 1707 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1708 1709 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1710 edid[0x7e] = valid_extensions; 1711 1712 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1713 GFP_KERNEL); 1714 if (!new) 1715 goto out; 1716 1717 base = new; 1718 for (i = 0; i <= edid[0x7e]; i++) { 1719 u8 *block = edid + i * EDID_LENGTH; 1720 1721 if (!drm_edid_block_valid(block, i, false, NULL)) 1722 continue; 1723 1724 memcpy(base, block, EDID_LENGTH); 1725 base += EDID_LENGTH; 1726 } 1727 1728 kfree(edid); 1729 edid = new; 1730 } 1731 1732 return (struct edid *)edid; 1733 1734carp: 1735 connector_bad_edid(connector, edid, 1); 1736out: 1737 kfree(edid); 1738 return NULL; 1739} 1740EXPORT_SYMBOL_GPL(drm_do_get_edid); 1741 1742/** 1743 * drm_probe_ddc() - probe DDC presence 1744 * @adapter: I2C adapter to probe 1745 * 1746 * Return: True on success, false on failure. 1747 */ 1748bool 1749drm_probe_ddc(struct i2c_adapter *adapter) 1750{ 1751 unsigned char out; 1752 1753 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1754} 1755EXPORT_SYMBOL(drm_probe_ddc); 1756 1757/** 1758 * drm_get_edid - get EDID data, if available 1759 * @connector: connector we're probing 1760 * @adapter: I2C adapter to use for DDC 1761 * 1762 * Poke the given I2C channel to grab EDID data if possible. If found, 1763 * attach it to the connector. 1764 * 1765 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1766 */ 1767struct edid *drm_get_edid(struct drm_connector *connector, 1768 struct i2c_adapter *adapter) 1769{ 1770 struct edid *edid; 1771 1772 if (connector->force == DRM_FORCE_OFF) 1773 return NULL; 1774 1775 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 1776 return NULL; 1777 1778 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1779 if (edid) 1780 drm_get_displayid(connector, edid); 1781 return edid; 1782} 1783EXPORT_SYMBOL(drm_get_edid); 1784 1785/** 1786 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1787 * @connector: connector we're probing 1788 * @adapter: I2C adapter to use for DDC 1789 * 1790 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1791 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1792 * switch DDC to the GPU which is retrieving EDID. 1793 * 1794 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1795 */ 1796struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1797 struct i2c_adapter *adapter) 1798{ 1799#ifdef __linux__ 1800 struct pci_dev *pdev = connector->dev->pdev; 1801#endif 1802 struct edid *edid; 1803 1804 vga_switcheroo_lock_ddc(pdev); 1805 edid = drm_get_edid(connector, adapter); 1806 vga_switcheroo_unlock_ddc(pdev); 1807 1808 return edid; 1809} 1810EXPORT_SYMBOL(drm_get_edid_switcheroo); 1811 1812/** 1813 * drm_edid_duplicate - duplicate an EDID and the extensions 1814 * @edid: EDID to duplicate 1815 * 1816 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1817 */ 1818struct edid *drm_edid_duplicate(const struct edid *edid) 1819{ 1820 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1821} 1822EXPORT_SYMBOL(drm_edid_duplicate); 1823 1824/*** EDID parsing ***/ 1825 1826/** 1827 * edid_vendor - match a string against EDID's obfuscated vendor field 1828 * @edid: EDID to match 1829 * @vendor: vendor string 1830 * 1831 * Returns true if @vendor is in @edid, false otherwise 1832 */ 1833static bool edid_vendor(const struct edid *edid, const char *vendor) 1834{ 1835 char edid_vendor[3]; 1836 1837 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1838 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1839 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1840 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1841 1842 return !strncmp(edid_vendor, vendor, 3); 1843} 1844 1845/** 1846 * edid_get_quirks - return quirk flags for a given EDID 1847 * @edid: EDID to process 1848 * 1849 * This tells subsequent routines what fixes they need to apply. 1850 */ 1851static u32 edid_get_quirks(const struct edid *edid) 1852{ 1853 const struct edid_quirk *quirk; 1854 int i; 1855 1856 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1857 quirk = &edid_quirk_list[i]; 1858 1859 if (edid_vendor(edid, quirk->vendor) && 1860 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1861 return quirk->quirks; 1862 } 1863 1864 return 0; 1865} 1866 1867#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1868#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1869 1870/** 1871 * edid_fixup_preferred - set preferred modes based on quirk list 1872 * @connector: has mode list to fix up 1873 * @quirks: quirks list 1874 * 1875 * Walk the mode list for @connector, clearing the preferred status 1876 * on existing modes and setting it anew for the right mode ala @quirks. 1877 */ 1878static void edid_fixup_preferred(struct drm_connector *connector, 1879 u32 quirks) 1880{ 1881 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1882 int target_refresh = 0; 1883 int cur_vrefresh, preferred_vrefresh; 1884 1885 if (list_empty(&connector->probed_modes)) 1886 return; 1887 1888 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1889 target_refresh = 60; 1890 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1891 target_refresh = 75; 1892 1893 preferred_mode = list_first_entry(&connector->probed_modes, 1894 struct drm_display_mode, head); 1895 1896 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1897 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1898 1899 if (cur_mode == preferred_mode) 1900 continue; 1901 1902 /* Largest mode is preferred */ 1903 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1904 preferred_mode = cur_mode; 1905 1906 cur_vrefresh = cur_mode->vrefresh ? 1907 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1908 preferred_vrefresh = preferred_mode->vrefresh ? 1909 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1910 /* At a given size, try to get closest to target refresh */ 1911 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1912 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1913 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1914 preferred_mode = cur_mode; 1915 } 1916 } 1917 1918 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1919} 1920 1921static bool 1922mode_is_rb(const struct drm_display_mode *mode) 1923{ 1924 return (mode->htotal - mode->hdisplay == 160) && 1925 (mode->hsync_end - mode->hdisplay == 80) && 1926 (mode->hsync_end - mode->hsync_start == 32) && 1927 (mode->vsync_start - mode->vdisplay == 3); 1928} 1929 1930/* 1931 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1932 * @dev: Device to duplicate against 1933 * @hsize: Mode width 1934 * @vsize: Mode height 1935 * @fresh: Mode refresh rate 1936 * @rb: Mode reduced-blanking-ness 1937 * 1938 * Walk the DMT mode list looking for a match for the given parameters. 1939 * 1940 * Return: A newly allocated copy of the mode, or NULL if not found. 1941 */ 1942struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1943 int hsize, int vsize, int fresh, 1944 bool rb) 1945{ 1946 int i; 1947 1948 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1949 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1950 if (hsize != ptr->hdisplay) 1951 continue; 1952 if (vsize != ptr->vdisplay) 1953 continue; 1954 if (fresh != drm_mode_vrefresh(ptr)) 1955 continue; 1956 if (rb != mode_is_rb(ptr)) 1957 continue; 1958 1959 return drm_mode_duplicate(dev, ptr); 1960 } 1961 1962 return NULL; 1963} 1964EXPORT_SYMBOL(drm_mode_find_dmt); 1965 1966typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1967 1968static void 1969cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1970{ 1971 int i, n = 0; 1972 u8 d = ext[0x02]; 1973 u8 *det_base = ext + d; 1974 1975 n = (127 - d) / 18; 1976 for (i = 0; i < n; i++) 1977 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1978} 1979 1980static void 1981vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1982{ 1983 unsigned int i, n = min((int)ext[0x02], 6); 1984 u8 *det_base = ext + 5; 1985 1986 if (ext[0x01] != 1) 1987 return; /* unknown version */ 1988 1989 for (i = 0; i < n; i++) 1990 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1991} 1992 1993static void 1994drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1995{ 1996 int i; 1997 struct edid *edid = (struct edid *)raw_edid; 1998 1999 if (edid == NULL) 2000 return; 2001 2002 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2003 cb(&(edid->detailed_timings[i]), closure); 2004 2005 for (i = 1; i <= raw_edid[0x7e]; i++) { 2006 u8 *ext = raw_edid + (i * EDID_LENGTH); 2007 switch (*ext) { 2008 case CEA_EXT: 2009 cea_for_each_detailed_block(ext, cb, closure); 2010 break; 2011 case VTB_EXT: 2012 vtb_for_each_detailed_block(ext, cb, closure); 2013 break; 2014 default: 2015 break; 2016 } 2017 } 2018} 2019 2020static void 2021is_rb(struct detailed_timing *t, void *data) 2022{ 2023 u8 *r = (u8 *)t; 2024 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 2025 if (r[15] & 0x10) 2026 *(bool *)data = true; 2027} 2028 2029/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2030static bool 2031drm_monitor_supports_rb(struct edid *edid) 2032{ 2033 if (edid->revision >= 4) { 2034 bool ret = false; 2035 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2036 return ret; 2037 } 2038 2039 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2040} 2041 2042static void 2043find_gtf2(struct detailed_timing *t, void *data) 2044{ 2045 u8 *r = (u8 *)t; 2046 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 2047 *(u8 **)data = r; 2048} 2049 2050/* Secondary GTF curve kicks in above some break frequency */ 2051static int 2052drm_gtf2_hbreak(struct edid *edid) 2053{ 2054 u8 *r = NULL; 2055 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2056 return r ? (r[12] * 2) : 0; 2057} 2058 2059static int 2060drm_gtf2_2c(struct edid *edid) 2061{ 2062 u8 *r = NULL; 2063 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2064 return r ? r[13] : 0; 2065} 2066 2067static int 2068drm_gtf2_m(struct edid *edid) 2069{ 2070 u8 *r = NULL; 2071 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2072 return r ? (r[15] << 8) + r[14] : 0; 2073} 2074 2075static int 2076drm_gtf2_k(struct edid *edid) 2077{ 2078 u8 *r = NULL; 2079 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2080 return r ? r[16] : 0; 2081} 2082 2083static int 2084drm_gtf2_2j(struct edid *edid) 2085{ 2086 u8 *r = NULL; 2087 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2088 return r ? r[17] : 0; 2089} 2090 2091/** 2092 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2093 * @edid: EDID block to scan 2094 */ 2095static int standard_timing_level(struct edid *edid) 2096{ 2097 if (edid->revision >= 2) { 2098 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2099 return LEVEL_CVT; 2100 if (drm_gtf2_hbreak(edid)) 2101 return LEVEL_GTF2; 2102 return LEVEL_GTF; 2103 } 2104 return LEVEL_DMT; 2105} 2106 2107/* 2108 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2109 * monitors fill with ascii space (0x20) instead. 2110 */ 2111static int 2112bad_std_timing(u8 a, u8 b) 2113{ 2114 return (a == 0x00 && b == 0x00) || 2115 (a == 0x01 && b == 0x01) || 2116 (a == 0x20 && b == 0x20); 2117} 2118 2119/** 2120 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2121 * @connector: connector of for the EDID block 2122 * @edid: EDID block to scan 2123 * @t: standard timing params 2124 * 2125 * Take the standard timing params (in this case width, aspect, and refresh) 2126 * and convert them into a real mode using CVT/GTF/DMT. 2127 */ 2128static struct drm_display_mode * 2129drm_mode_std(struct drm_connector *connector, struct edid *edid, 2130 struct std_timing *t) 2131{ 2132 struct drm_device *dev = connector->dev; 2133 struct drm_display_mode *m, *mode = NULL; 2134 int hsize, vsize; 2135 int vrefresh_rate; 2136 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2137 >> EDID_TIMING_ASPECT_SHIFT; 2138 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2139 >> EDID_TIMING_VFREQ_SHIFT; 2140 int timing_level = standard_timing_level(edid); 2141 2142 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2143 return NULL; 2144 2145 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2146 hsize = t->hsize * 8 + 248; 2147 /* vrefresh_rate = vfreq + 60 */ 2148 vrefresh_rate = vfreq + 60; 2149 /* the vdisplay is calculated based on the aspect ratio */ 2150 if (aspect_ratio == 0) { 2151 if (edid->revision < 3) 2152 vsize = hsize; 2153 else 2154 vsize = (hsize * 10) / 16; 2155 } else if (aspect_ratio == 1) 2156 vsize = (hsize * 3) / 4; 2157 else if (aspect_ratio == 2) 2158 vsize = (hsize * 4) / 5; 2159 else 2160 vsize = (hsize * 9) / 16; 2161 2162 /* HDTV hack, part 1 */ 2163 if (vrefresh_rate == 60 && 2164 ((hsize == 1360 && vsize == 765) || 2165 (hsize == 1368 && vsize == 769))) { 2166 hsize = 1366; 2167 vsize = 768; 2168 } 2169 2170 /* 2171 * If this connector already has a mode for this size and refresh 2172 * rate (because it came from detailed or CVT info), use that 2173 * instead. This way we don't have to guess at interlace or 2174 * reduced blanking. 2175 */ 2176 list_for_each_entry(m, &connector->probed_modes, head) 2177 if (m->hdisplay == hsize && m->vdisplay == vsize && 2178 drm_mode_vrefresh(m) == vrefresh_rate) 2179 return NULL; 2180 2181 /* HDTV hack, part 2 */ 2182 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2183 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2184 false); 2185 if (!mode) 2186 return NULL; 2187 mode->hdisplay = 1366; 2188 mode->hsync_start = mode->hsync_start - 1; 2189 mode->hsync_end = mode->hsync_end - 1; 2190 return mode; 2191 } 2192 2193 /* check whether it can be found in default mode table */ 2194 if (drm_monitor_supports_rb(edid)) { 2195 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2196 true); 2197 if (mode) 2198 return mode; 2199 } 2200 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2201 if (mode) 2202 return mode; 2203 2204 /* okay, generate it */ 2205 switch (timing_level) { 2206 case LEVEL_DMT: 2207 break; 2208 case LEVEL_GTF: 2209 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2210 break; 2211 case LEVEL_GTF2: 2212 /* 2213 * This is potentially wrong if there's ever a monitor with 2214 * more than one ranges section, each claiming a different 2215 * secondary GTF curve. Please don't do that. 2216 */ 2217 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2218 if (!mode) 2219 return NULL; 2220 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2221 drm_mode_destroy(dev, mode); 2222 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2223 vrefresh_rate, 0, 0, 2224 drm_gtf2_m(edid), 2225 drm_gtf2_2c(edid), 2226 drm_gtf2_k(edid), 2227 drm_gtf2_2j(edid)); 2228 } 2229 break; 2230 case LEVEL_CVT: 2231 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2232 false); 2233 break; 2234 } 2235 return mode; 2236} 2237 2238/* 2239 * EDID is delightfully ambiguous about how interlaced modes are to be 2240 * encoded. Our internal representation is of frame height, but some 2241 * HDTV detailed timings are encoded as field height. 2242 * 2243 * The format list here is from CEA, in frame size. Technically we 2244 * should be checking refresh rate too. Whatever. 2245 */ 2246static void 2247drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2248 struct detailed_pixel_timing *pt) 2249{ 2250 int i; 2251 static const struct { 2252 int w, h; 2253 } cea_interlaced[] = { 2254 { 1920, 1080 }, 2255 { 720, 480 }, 2256 { 1440, 480 }, 2257 { 2880, 480 }, 2258 { 720, 576 }, 2259 { 1440, 576 }, 2260 { 2880, 576 }, 2261 }; 2262 2263 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2264 return; 2265 2266 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2267 if ((mode->hdisplay == cea_interlaced[i].w) && 2268 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2269 mode->vdisplay *= 2; 2270 mode->vsync_start *= 2; 2271 mode->vsync_end *= 2; 2272 mode->vtotal *= 2; 2273 mode->vtotal |= 1; 2274 } 2275 } 2276 2277 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2278} 2279 2280/** 2281 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2282 * @dev: DRM device (needed to create new mode) 2283 * @edid: EDID block 2284 * @timing: EDID detailed timing info 2285 * @quirks: quirks to apply 2286 * 2287 * An EDID detailed timing block contains enough info for us to create and 2288 * return a new struct drm_display_mode. 2289 */ 2290static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2291 struct edid *edid, 2292 struct detailed_timing *timing, 2293 u32 quirks) 2294{ 2295 struct drm_display_mode *mode; 2296 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2297 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2298 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2299 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2300 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2301 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2302 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2303 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2304 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2305 2306 /* ignore tiny modes */ 2307 if (hactive < 64 || vactive < 64) 2308 return NULL; 2309 2310 if (pt->misc & DRM_EDID_PT_STEREO) { 2311 DRM_DEBUG_KMS("stereo mode not supported\n"); 2312 return NULL; 2313 } 2314 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2315 DRM_DEBUG_KMS("composite sync not supported\n"); 2316 } 2317 2318 /* it is incorrect if hsync/vsync width is zero */ 2319 if (!hsync_pulse_width || !vsync_pulse_width) { 2320 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2321 "Wrong Hsync/Vsync pulse width\n"); 2322 return NULL; 2323 } 2324 2325 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2326 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2327 if (!mode) 2328 return NULL; 2329 2330 goto set_size; 2331 } 2332 2333 mode = drm_mode_create(dev); 2334 if (!mode) 2335 return NULL; 2336 2337 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2338 timing->pixel_clock = cpu_to_le16(1088); 2339 2340 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2341 2342 mode->hdisplay = hactive; 2343 mode->hsync_start = mode->hdisplay + hsync_offset; 2344 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2345 mode->htotal = mode->hdisplay + hblank; 2346 2347 mode->vdisplay = vactive; 2348 mode->vsync_start = mode->vdisplay + vsync_offset; 2349 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2350 mode->vtotal = mode->vdisplay + vblank; 2351 2352 /* Some EDIDs have bogus h/vtotal values */ 2353 if (mode->hsync_end > mode->htotal) 2354 mode->htotal = mode->hsync_end + 1; 2355 if (mode->vsync_end > mode->vtotal) 2356 mode->vtotal = mode->vsync_end + 1; 2357 2358 drm_mode_do_interlace_quirk(mode, pt); 2359 2360 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2361 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2362 } 2363 2364 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2365 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2366 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2367 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2368 2369set_size: 2370 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2371 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2372 2373 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2374 mode->width_mm *= 10; 2375 mode->height_mm *= 10; 2376 } 2377 2378 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2379 mode->width_mm = edid->width_cm * 10; 2380 mode->height_mm = edid->height_cm * 10; 2381 } 2382 2383 mode->type = DRM_MODE_TYPE_DRIVER; 2384 mode->vrefresh = drm_mode_vrefresh(mode); 2385 drm_mode_set_name(mode); 2386 2387 return mode; 2388} 2389 2390static bool 2391mode_in_hsync_range(const struct drm_display_mode *mode, 2392 struct edid *edid, u8 *t) 2393{ 2394 int hsync, hmin, hmax; 2395 2396 hmin = t[7]; 2397 if (edid->revision >= 4) 2398 hmin += ((t[4] & 0x04) ? 255 : 0); 2399 hmax = t[8]; 2400 if (edid->revision >= 4) 2401 hmax += ((t[4] & 0x08) ? 255 : 0); 2402 hsync = drm_mode_hsync(mode); 2403 2404 return (hsync <= hmax && hsync >= hmin); 2405} 2406 2407static bool 2408mode_in_vsync_range(const struct drm_display_mode *mode, 2409 struct edid *edid, u8 *t) 2410{ 2411 int vsync, vmin, vmax; 2412 2413 vmin = t[5]; 2414 if (edid->revision >= 4) 2415 vmin += ((t[4] & 0x01) ? 255 : 0); 2416 vmax = t[6]; 2417 if (edid->revision >= 4) 2418 vmax += ((t[4] & 0x02) ? 255 : 0); 2419 vsync = drm_mode_vrefresh(mode); 2420 2421 return (vsync <= vmax && vsync >= vmin); 2422} 2423 2424static u32 2425range_pixel_clock(struct edid *edid, u8 *t) 2426{ 2427 /* unspecified */ 2428 if (t[9] == 0 || t[9] == 255) 2429 return 0; 2430 2431 /* 1.4 with CVT support gives us real precision, yay */ 2432 if (edid->revision >= 4 && t[10] == 0x04) 2433 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2434 2435 /* 1.3 is pathetic, so fuzz up a bit */ 2436 return t[9] * 10000 + 5001; 2437} 2438 2439static bool 2440mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2441 struct detailed_timing *timing) 2442{ 2443 u32 max_clock; 2444 u8 *t = (u8 *)timing; 2445 2446 if (!mode_in_hsync_range(mode, edid, t)) 2447 return false; 2448 2449 if (!mode_in_vsync_range(mode, edid, t)) 2450 return false; 2451 2452 if ((max_clock = range_pixel_clock(edid, t))) 2453 if (mode->clock > max_clock) 2454 return false; 2455 2456 /* 1.4 max horizontal check */ 2457 if (edid->revision >= 4 && t[10] == 0x04) 2458 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2459 return false; 2460 2461 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2462 return false; 2463 2464 return true; 2465} 2466 2467static bool valid_inferred_mode(const struct drm_connector *connector, 2468 const struct drm_display_mode *mode) 2469{ 2470 const struct drm_display_mode *m; 2471 bool ok = false; 2472 2473 list_for_each_entry(m, &connector->probed_modes, head) { 2474 if (mode->hdisplay == m->hdisplay && 2475 mode->vdisplay == m->vdisplay && 2476 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2477 return false; /* duplicated */ 2478 if (mode->hdisplay <= m->hdisplay && 2479 mode->vdisplay <= m->vdisplay) 2480 ok = true; 2481 } 2482 return ok; 2483} 2484 2485static int 2486drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2487 struct detailed_timing *timing) 2488{ 2489 int i, modes = 0; 2490 struct drm_display_mode *newmode; 2491 struct drm_device *dev = connector->dev; 2492 2493 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2494 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2495 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2496 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2497 if (newmode) { 2498 drm_mode_probed_add(connector, newmode); 2499 modes++; 2500 } 2501 } 2502 } 2503 2504 return modes; 2505} 2506 2507/* fix up 1366x768 mode from 1368x768; 2508 * GFT/CVT can't express 1366 width which isn't dividable by 8 2509 */ 2510void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2511{ 2512 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2513 mode->hdisplay = 1366; 2514 mode->hsync_start--; 2515 mode->hsync_end--; 2516 drm_mode_set_name(mode); 2517 } 2518} 2519 2520static int 2521drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2522 struct detailed_timing *timing) 2523{ 2524 int i, modes = 0; 2525 struct drm_display_mode *newmode; 2526 struct drm_device *dev = connector->dev; 2527 2528 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2529 const struct minimode *m = &extra_modes[i]; 2530 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2531 if (!newmode) 2532 return modes; 2533 2534 drm_mode_fixup_1366x768(newmode); 2535 if (!mode_in_range(newmode, edid, timing) || 2536 !valid_inferred_mode(connector, newmode)) { 2537 drm_mode_destroy(dev, newmode); 2538 continue; 2539 } 2540 2541 drm_mode_probed_add(connector, newmode); 2542 modes++; 2543 } 2544 2545 return modes; 2546} 2547 2548static int 2549drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2550 struct detailed_timing *timing) 2551{ 2552 int i, modes = 0; 2553 struct drm_display_mode *newmode; 2554 struct drm_device *dev = connector->dev; 2555 bool rb = drm_monitor_supports_rb(edid); 2556 2557 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2558 const struct minimode *m = &extra_modes[i]; 2559 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2560 if (!newmode) 2561 return modes; 2562 2563 drm_mode_fixup_1366x768(newmode); 2564 if (!mode_in_range(newmode, edid, timing) || 2565 !valid_inferred_mode(connector, newmode)) { 2566 drm_mode_destroy(dev, newmode); 2567 continue; 2568 } 2569 2570 drm_mode_probed_add(connector, newmode); 2571 modes++; 2572 } 2573 2574 return modes; 2575} 2576 2577static void 2578do_inferred_modes(struct detailed_timing *timing, void *c) 2579{ 2580 struct detailed_mode_closure *closure = c; 2581 struct detailed_non_pixel *data = &timing->data.other_data; 2582 struct detailed_data_monitor_range *range = &data->data.range; 2583 2584 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2585 return; 2586 2587 closure->modes += drm_dmt_modes_for_range(closure->connector, 2588 closure->edid, 2589 timing); 2590 2591 if (!version_greater(closure->edid, 1, 1)) 2592 return; /* GTF not defined yet */ 2593 2594 switch (range->flags) { 2595 case 0x02: /* secondary gtf, XXX could do more */ 2596 case 0x00: /* default gtf */ 2597 closure->modes += drm_gtf_modes_for_range(closure->connector, 2598 closure->edid, 2599 timing); 2600 break; 2601 case 0x04: /* cvt, only in 1.4+ */ 2602 if (!version_greater(closure->edid, 1, 3)) 2603 break; 2604 2605 closure->modes += drm_cvt_modes_for_range(closure->connector, 2606 closure->edid, 2607 timing); 2608 break; 2609 case 0x01: /* just the ranges, no formula */ 2610 default: 2611 break; 2612 } 2613} 2614 2615static int 2616add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2617{ 2618 struct detailed_mode_closure closure = { 2619 .connector = connector, 2620 .edid = edid, 2621 }; 2622 2623 if (version_greater(edid, 1, 0)) 2624 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2625 &closure); 2626 2627 return closure.modes; 2628} 2629 2630static int 2631drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2632{ 2633 int i, j, m, modes = 0; 2634 struct drm_display_mode *mode; 2635 u8 *est = ((u8 *)timing) + 6; 2636 2637 for (i = 0; i < 6; i++) { 2638 for (j = 7; j >= 0; j--) { 2639 m = (i * 8) + (7 - j); 2640 if (m >= ARRAY_SIZE(est3_modes)) 2641 break; 2642 if (est[i] & (1 << j)) { 2643 mode = drm_mode_find_dmt(connector->dev, 2644 est3_modes[m].w, 2645 est3_modes[m].h, 2646 est3_modes[m].r, 2647 est3_modes[m].rb); 2648 if (mode) { 2649 drm_mode_probed_add(connector, mode); 2650 modes++; 2651 } 2652 } 2653 } 2654 } 2655 2656 return modes; 2657} 2658 2659static void 2660do_established_modes(struct detailed_timing *timing, void *c) 2661{ 2662 struct detailed_mode_closure *closure = c; 2663 struct detailed_non_pixel *data = &timing->data.other_data; 2664 2665 if (data->type == EDID_DETAIL_EST_TIMINGS) 2666 closure->modes += drm_est3_modes(closure->connector, timing); 2667} 2668 2669/** 2670 * add_established_modes - get est. modes from EDID and add them 2671 * @connector: connector to add mode(s) to 2672 * @edid: EDID block to scan 2673 * 2674 * Each EDID block contains a bitmap of the supported "established modes" list 2675 * (defined above). Tease them out and add them to the global modes list. 2676 */ 2677static int 2678add_established_modes(struct drm_connector *connector, struct edid *edid) 2679{ 2680 struct drm_device *dev = connector->dev; 2681 unsigned long est_bits = edid->established_timings.t1 | 2682 (edid->established_timings.t2 << 8) | 2683 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2684 int i, modes = 0; 2685 struct detailed_mode_closure closure = { 2686 .connector = connector, 2687 .edid = edid, 2688 }; 2689 2690 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2691 if (est_bits & (1<<i)) { 2692 struct drm_display_mode *newmode; 2693 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2694 if (newmode) { 2695 drm_mode_probed_add(connector, newmode); 2696 modes++; 2697 } 2698 } 2699 } 2700 2701 if (version_greater(edid, 1, 0)) 2702 drm_for_each_detailed_block((u8 *)edid, 2703 do_established_modes, &closure); 2704 2705 return modes + closure.modes; 2706} 2707 2708static void 2709do_standard_modes(struct detailed_timing *timing, void *c) 2710{ 2711 struct detailed_mode_closure *closure = c; 2712 struct detailed_non_pixel *data = &timing->data.other_data; 2713 struct drm_connector *connector = closure->connector; 2714 struct edid *edid = closure->edid; 2715 2716 if (data->type == EDID_DETAIL_STD_MODES) { 2717 int i; 2718 for (i = 0; i < 6; i++) { 2719 struct std_timing *std; 2720 struct drm_display_mode *newmode; 2721 2722 std = &data->data.timings[i]; 2723 newmode = drm_mode_std(connector, edid, std); 2724 if (newmode) { 2725 drm_mode_probed_add(connector, newmode); 2726 closure->modes++; 2727 } 2728 } 2729 } 2730} 2731 2732/** 2733 * add_standard_modes - get std. modes from EDID and add them 2734 * @connector: connector to add mode(s) to 2735 * @edid: EDID block to scan 2736 * 2737 * Standard modes can be calculated using the appropriate standard (DMT, 2738 * GTF or CVT. Grab them from @edid and add them to the list. 2739 */ 2740static int 2741add_standard_modes(struct drm_connector *connector, struct edid *edid) 2742{ 2743 int i, modes = 0; 2744 struct detailed_mode_closure closure = { 2745 .connector = connector, 2746 .edid = edid, 2747 }; 2748 2749 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2750 struct drm_display_mode *newmode; 2751 2752 newmode = drm_mode_std(connector, edid, 2753 &edid->standard_timings[i]); 2754 if (newmode) { 2755 drm_mode_probed_add(connector, newmode); 2756 modes++; 2757 } 2758 } 2759 2760 if (version_greater(edid, 1, 0)) 2761 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2762 &closure); 2763 2764 /* XXX should also look for standard codes in VTB blocks */ 2765 2766 return modes + closure.modes; 2767} 2768 2769static int drm_cvt_modes(struct drm_connector *connector, 2770 struct detailed_timing *timing) 2771{ 2772 int i, j, modes = 0; 2773 struct drm_display_mode *newmode; 2774 struct drm_device *dev = connector->dev; 2775 struct cvt_timing *cvt; 2776 const int rates[] = { 60, 85, 75, 60, 50 }; 2777 const u8 empty[3] = { 0, 0, 0 }; 2778 2779 for (i = 0; i < 4; i++) { 2780 int uninitialized_var(width), height; 2781 cvt = &(timing->data.other_data.data.cvt[i]); 2782 2783 if (!memcmp(cvt->code, empty, 3)) 2784 continue; 2785 2786 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2787 switch (cvt->code[1] & 0x0c) { 2788 case 0x00: 2789 width = height * 4 / 3; 2790 break; 2791 case 0x04: 2792 width = height * 16 / 9; 2793 break; 2794 case 0x08: 2795 width = height * 16 / 10; 2796 break; 2797 case 0x0c: 2798 width = height * 15 / 9; 2799 break; 2800 } 2801 2802 for (j = 1; j < 5; j++) { 2803 if (cvt->code[2] & (1 << j)) { 2804 newmode = drm_cvt_mode(dev, width, height, 2805 rates[j], j == 0, 2806 false, false); 2807 if (newmode) { 2808 drm_mode_probed_add(connector, newmode); 2809 modes++; 2810 } 2811 } 2812 } 2813 } 2814 2815 return modes; 2816} 2817 2818static void 2819do_cvt_mode(struct detailed_timing *timing, void *c) 2820{ 2821 struct detailed_mode_closure *closure = c; 2822 struct detailed_non_pixel *data = &timing->data.other_data; 2823 2824 if (data->type == EDID_DETAIL_CVT_3BYTE) 2825 closure->modes += drm_cvt_modes(closure->connector, timing); 2826} 2827 2828static int 2829add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2830{ 2831 struct detailed_mode_closure closure = { 2832 .connector = connector, 2833 .edid = edid, 2834 }; 2835 2836 if (version_greater(edid, 1, 2)) 2837 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2838 2839 /* XXX should also look for CVT codes in VTB blocks */ 2840 2841 return closure.modes; 2842} 2843 2844static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2845 2846static void 2847do_detailed_mode(struct detailed_timing *timing, void *c) 2848{ 2849 struct detailed_mode_closure *closure = c; 2850 struct drm_display_mode *newmode; 2851 2852 if (timing->pixel_clock) { 2853 newmode = drm_mode_detailed(closure->connector->dev, 2854 closure->edid, timing, 2855 closure->quirks); 2856 if (!newmode) 2857 return; 2858 2859 if (closure->preferred) 2860 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2861 2862 /* 2863 * Detailed modes are limited to 10kHz pixel clock resolution, 2864 * so fix up anything that looks like CEA/HDMI mode, but the clock 2865 * is just slightly off. 2866 */ 2867 fixup_detailed_cea_mode_clock(newmode); 2868 2869 drm_mode_probed_add(closure->connector, newmode); 2870 closure->modes++; 2871 closure->preferred = false; 2872 } 2873} 2874 2875/* 2876 * add_detailed_modes - Add modes from detailed timings 2877 * @connector: attached connector 2878 * @edid: EDID block to scan 2879 * @quirks: quirks to apply 2880 */ 2881static int 2882add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2883 u32 quirks) 2884{ 2885 struct detailed_mode_closure closure = { 2886 .connector = connector, 2887 .edid = edid, 2888 .preferred = true, 2889 .quirks = quirks, 2890 }; 2891 2892 if (closure.preferred && !version_greater(edid, 1, 3)) 2893 closure.preferred = 2894 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2895 2896 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2897 2898 return closure.modes; 2899} 2900 2901#define AUDIO_BLOCK 0x01 2902#define VIDEO_BLOCK 0x02 2903#define VENDOR_BLOCK 0x03 2904#define SPEAKER_BLOCK 0x04 2905#define USE_EXTENDED_TAG 0x07 2906#define EXT_VIDEO_CAPABILITY_BLOCK 0x00 2907#define EXT_VIDEO_DATA_BLOCK_420 0x0E 2908#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 2909#define EDID_BASIC_AUDIO (1 << 6) 2910#define EDID_CEA_YCRCB444 (1 << 5) 2911#define EDID_CEA_YCRCB422 (1 << 4) 2912#define EDID_CEA_VCDB_QS (1 << 6) 2913 2914/* 2915 * Search EDID for CEA extension block. 2916 */ 2917static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 2918{ 2919 u8 *edid_ext = NULL; 2920 int i; 2921 2922 /* No EDID or EDID extensions */ 2923 if (edid == NULL || edid->extensions == 0) 2924 return NULL; 2925 2926 /* Find CEA extension */ 2927 for (i = 0; i < edid->extensions; i++) { 2928 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2929 if (edid_ext[0] == ext_id) 2930 break; 2931 } 2932 2933 if (i == edid->extensions) 2934 return NULL; 2935 2936 return edid_ext; 2937} 2938 2939static u8 *drm_find_cea_extension(const struct edid *edid) 2940{ 2941 return drm_find_edid_extension(edid, CEA_EXT); 2942} 2943 2944static u8 *drm_find_displayid_extension(const struct edid *edid) 2945{ 2946 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2947} 2948 2949/* 2950 * Calculate the alternate clock for the CEA mode 2951 * (60Hz vs. 59.94Hz etc.) 2952 */ 2953static unsigned int 2954cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2955{ 2956 unsigned int clock = cea_mode->clock; 2957 2958 if (cea_mode->vrefresh % 6 != 0) 2959 return clock; 2960 2961 /* 2962 * edid_cea_modes contains the 59.94Hz 2963 * variant for 240 and 480 line modes, 2964 * and the 60Hz variant otherwise. 2965 */ 2966 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2967 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2968 else 2969 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2970 2971 return clock; 2972} 2973 2974static bool 2975cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 2976{ 2977 /* 2978 * For certain VICs the spec allows the vertical 2979 * front porch to vary by one or two lines. 2980 * 2981 * cea_modes[] stores the variant with the shortest 2982 * vertical front porch. We can adjust the mode to 2983 * get the other variants by simply increasing the 2984 * vertical front porch length. 2985 */ 2986#ifdef notyet 2987 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || 2988 edid_cea_modes[9].vtotal != 262 || 2989 edid_cea_modes[12].vtotal != 262 || 2990 edid_cea_modes[13].vtotal != 262 || 2991 edid_cea_modes[23].vtotal != 312 || 2992 edid_cea_modes[24].vtotal != 312 || 2993 edid_cea_modes[27].vtotal != 312 || 2994 edid_cea_modes[28].vtotal != 312); 2995#endif 2996 2997 if (((vic == 8 || vic == 9 || 2998 vic == 12 || vic == 13) && mode->vtotal < 263) || 2999 ((vic == 23 || vic == 24 || 3000 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3001 mode->vsync_start++; 3002 mode->vsync_end++; 3003 mode->vtotal++; 3004 3005 return true; 3006 } 3007 3008 return false; 3009} 3010 3011static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3012 unsigned int clock_tolerance) 3013{ 3014 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3015 u8 vic; 3016 3017 if (!to_match->clock) 3018 return 0; 3019 3020 if (to_match->picture_aspect_ratio) 3021 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3022 3023 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3024 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 3025 unsigned int clock1, clock2; 3026 3027 /* Check both 60Hz and 59.94Hz */ 3028 clock1 = cea_mode.clock; 3029 clock2 = cea_mode_alternate_clock(&cea_mode); 3030 3031 if (abs(to_match->clock - clock1) > clock_tolerance && 3032 abs(to_match->clock - clock2) > clock_tolerance) 3033 continue; 3034 3035 do { 3036 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3037 return vic; 3038 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3039 } 3040 3041 return 0; 3042} 3043 3044/** 3045 * drm_match_cea_mode - look for a CEA mode matching given mode 3046 * @to_match: display mode 3047 * 3048 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3049 * mode. 3050 */ 3051u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3052{ 3053 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3054 u8 vic; 3055 3056 if (!to_match->clock) 3057 return 0; 3058 3059 if (to_match->picture_aspect_ratio) 3060 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3061 3062 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3063 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 3064 unsigned int clock1, clock2; 3065 3066 /* Check both 60Hz and 59.94Hz */ 3067 clock1 = cea_mode.clock; 3068 clock2 = cea_mode_alternate_clock(&cea_mode); 3069 3070 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3071 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3072 continue; 3073 3074 do { 3075 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3076 return vic; 3077 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3078 } 3079 3080 return 0; 3081} 3082EXPORT_SYMBOL(drm_match_cea_mode); 3083 3084static bool drm_valid_cea_vic(u8 vic) 3085{ 3086 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 3087} 3088 3089/** 3090 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 3091 * the input VIC from the CEA mode list 3092 * @video_code: ID given to each of the CEA modes 3093 * 3094 * Returns picture aspect ratio 3095 */ 3096enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3097{ 3098 return edid_cea_modes[video_code].picture_aspect_ratio; 3099} 3100EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 3101 3102/* 3103 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3104 * specific block). 3105 * 3106 * It's almost like cea_mode_alternate_clock(), we just need to add an 3107 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 3108 * one. 3109 */ 3110static unsigned int 3111hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3112{ 3113 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3114 return hdmi_mode->clock; 3115 3116 return cea_mode_alternate_clock(hdmi_mode); 3117} 3118 3119static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3120 unsigned int clock_tolerance) 3121{ 3122 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3123 u8 vic; 3124 3125 if (!to_match->clock) 3126 return 0; 3127 3128 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3129 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3130 unsigned int clock1, clock2; 3131 3132 /* Make sure to also match alternate clocks */ 3133 clock1 = hdmi_mode->clock; 3134 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3135 3136 if (abs(to_match->clock - clock1) > clock_tolerance && 3137 abs(to_match->clock - clock2) > clock_tolerance) 3138 continue; 3139 3140 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3141 return vic; 3142 } 3143 3144 return 0; 3145} 3146 3147/* 3148 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3149 * @to_match: display mode 3150 * 3151 * An HDMI mode is one defined in the HDMI vendor specific block. 3152 * 3153 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3154 */ 3155static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3156{ 3157 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3158 u8 vic; 3159 3160 if (!to_match->clock) 3161 return 0; 3162 3163 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3164 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3165 unsigned int clock1, clock2; 3166 3167 /* Make sure to also match alternate clocks */ 3168 clock1 = hdmi_mode->clock; 3169 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3170 3171 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3172 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3173 drm_mode_match(to_match, hdmi_mode, match_flags)) 3174 return vic; 3175 } 3176 return 0; 3177} 3178 3179static bool drm_valid_hdmi_vic(u8 vic) 3180{ 3181 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3182} 3183 3184static int 3185add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3186{ 3187 struct drm_device *dev = connector->dev; 3188 struct drm_display_mode *mode, *tmp; 3189 DRM_LIST_HEAD(list); 3190 int modes = 0; 3191 3192 /* Don't add CEA modes if the CEA extension block is missing */ 3193 if (!drm_find_cea_extension(edid)) 3194 return 0; 3195 3196 /* 3197 * Go through all probed modes and create a new mode 3198 * with the alternate clock for certain CEA modes. 3199 */ 3200 list_for_each_entry(mode, &connector->probed_modes, head) { 3201 const struct drm_display_mode *cea_mode = NULL; 3202 struct drm_display_mode *newmode; 3203 u8 vic = drm_match_cea_mode(mode); 3204 unsigned int clock1, clock2; 3205 3206 if (drm_valid_cea_vic(vic)) { 3207 cea_mode = &edid_cea_modes[vic]; 3208 clock2 = cea_mode_alternate_clock(cea_mode); 3209 } else { 3210 vic = drm_match_hdmi_mode(mode); 3211 if (drm_valid_hdmi_vic(vic)) { 3212 cea_mode = &edid_4k_modes[vic]; 3213 clock2 = hdmi_mode_alternate_clock(cea_mode); 3214 } 3215 } 3216 3217 if (!cea_mode) 3218 continue; 3219 3220 clock1 = cea_mode->clock; 3221 3222 if (clock1 == clock2) 3223 continue; 3224 3225 if (mode->clock != clock1 && mode->clock != clock2) 3226 continue; 3227 3228 newmode = drm_mode_duplicate(dev, cea_mode); 3229 if (!newmode) 3230 continue; 3231 3232 /* Carry over the stereo flags */ 3233 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3234 3235 /* 3236 * The current mode could be either variant. Make 3237 * sure to pick the "other" clock for the new mode. 3238 */ 3239 if (mode->clock != clock1) 3240 newmode->clock = clock1; 3241 else 3242 newmode->clock = clock2; 3243 3244 list_add_tail(&newmode->head, &list); 3245 } 3246 3247 list_for_each_entry_safe(mode, tmp, &list, head) { 3248 list_del(&mode->head); 3249 drm_mode_probed_add(connector, mode); 3250 modes++; 3251 } 3252 3253 return modes; 3254} 3255 3256static u8 svd_to_vic(u8 svd) 3257{ 3258 /* 0-6 bit vic, 7th bit native mode indicator */ 3259 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3260 return svd & 127; 3261 3262 return svd; 3263} 3264 3265static struct drm_display_mode * 3266drm_display_mode_from_vic_index(struct drm_connector *connector, 3267 const u8 *video_db, u8 video_len, 3268 u8 video_index) 3269{ 3270 struct drm_device *dev = connector->dev; 3271 struct drm_display_mode *newmode; 3272 u8 vic; 3273 3274 if (video_db == NULL || video_index >= video_len) 3275 return NULL; 3276 3277 /* CEA modes are numbered 1..127 */ 3278 vic = svd_to_vic(video_db[video_index]); 3279 if (!drm_valid_cea_vic(vic)) 3280 return NULL; 3281 3282 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3283 if (!newmode) 3284 return NULL; 3285 3286 newmode->vrefresh = 0; 3287 3288 return newmode; 3289} 3290 3291/* 3292 * do_y420vdb_modes - Parse YCBCR 420 only modes 3293 * @connector: connector corresponding to the HDMI sink 3294 * @svds: start of the data block of CEA YCBCR 420 VDB 3295 * @len: length of the CEA YCBCR 420 VDB 3296 * 3297 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3298 * which contains modes which can be supported in YCBCR 420 3299 * output format only. 3300 */ 3301static int do_y420vdb_modes(struct drm_connector *connector, 3302 const u8 *svds, u8 svds_len) 3303{ 3304 int modes = 0, i; 3305 struct drm_device *dev = connector->dev; 3306 struct drm_display_info *info = &connector->display_info; 3307 struct drm_hdmi_info *hdmi = &info->hdmi; 3308 3309 for (i = 0; i < svds_len; i++) { 3310 u8 vic = svd_to_vic(svds[i]); 3311 struct drm_display_mode *newmode; 3312 3313 if (!drm_valid_cea_vic(vic)) 3314 continue; 3315 3316 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3317 if (!newmode) 3318 break; 3319 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3320 drm_mode_probed_add(connector, newmode); 3321 modes++; 3322 } 3323 3324 if (modes > 0) 3325 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3326 return modes; 3327} 3328 3329/* 3330 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3331 * @connector: connector corresponding to the HDMI sink 3332 * @vic: CEA vic for the video mode to be added in the map 3333 * 3334 * Makes an entry for a videomode in the YCBCR 420 bitmap 3335 */ 3336static void 3337drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3338{ 3339 u8 vic = svd_to_vic(svd); 3340 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3341 3342 if (!drm_valid_cea_vic(vic)) 3343 return; 3344 3345 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3346} 3347 3348static int 3349do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3350{ 3351 int i, modes = 0; 3352 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3353 3354 for (i = 0; i < len; i++) { 3355 struct drm_display_mode *mode; 3356 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3357 if (mode) { 3358 /* 3359 * YCBCR420 capability block contains a bitmap which 3360 * gives the index of CEA modes from CEA VDB, which 3361 * can support YCBCR 420 sampling output also (apart 3362 * from RGB/YCBCR444 etc). 3363 * For example, if the bit 0 in bitmap is set, 3364 * first mode in VDB can support YCBCR420 output too. 3365 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3366 */ 3367 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3368 drm_add_cmdb_modes(connector, db[i]); 3369 3370 drm_mode_probed_add(connector, mode); 3371 modes++; 3372 } 3373 } 3374 3375 return modes; 3376} 3377 3378struct stereo_mandatory_mode { 3379 int width, height, vrefresh; 3380 unsigned int flags; 3381}; 3382 3383static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3384 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3385 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3386 { 1920, 1080, 50, 3387 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3388 { 1920, 1080, 60, 3389 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3390 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3391 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3392 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3393 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3394}; 3395 3396static bool 3397stereo_match_mandatory(const struct drm_display_mode *mode, 3398 const struct stereo_mandatory_mode *stereo_mode) 3399{ 3400 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3401 3402 return mode->hdisplay == stereo_mode->width && 3403 mode->vdisplay == stereo_mode->height && 3404 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3405 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3406} 3407 3408static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3409{ 3410 struct drm_device *dev = connector->dev; 3411 const struct drm_display_mode *mode; 3412 struct list_head stereo_modes; 3413 int modes = 0, i; 3414 3415 INIT_LIST_HEAD(&stereo_modes); 3416 3417 list_for_each_entry(mode, &connector->probed_modes, head) { 3418 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3419 const struct stereo_mandatory_mode *mandatory; 3420 struct drm_display_mode *new_mode; 3421 3422 if (!stereo_match_mandatory(mode, 3423 &stereo_mandatory_modes[i])) 3424 continue; 3425 3426 mandatory = &stereo_mandatory_modes[i]; 3427 new_mode = drm_mode_duplicate(dev, mode); 3428 if (!new_mode) 3429 continue; 3430 3431 new_mode->flags |= mandatory->flags; 3432 list_add_tail(&new_mode->head, &stereo_modes); 3433 modes++; 3434 } 3435 } 3436 3437 list_splice_tail(&stereo_modes, &connector->probed_modes); 3438 3439 return modes; 3440} 3441 3442static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3443{ 3444 struct drm_device *dev = connector->dev; 3445 struct drm_display_mode *newmode; 3446 3447 if (!drm_valid_hdmi_vic(vic)) { 3448 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3449 return 0; 3450 } 3451 3452 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3453 if (!newmode) 3454 return 0; 3455 3456 drm_mode_probed_add(connector, newmode); 3457 3458 return 1; 3459} 3460 3461static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3462 const u8 *video_db, u8 video_len, u8 video_index) 3463{ 3464 struct drm_display_mode *newmode; 3465 int modes = 0; 3466 3467 if (structure & (1 << 0)) { 3468 newmode = drm_display_mode_from_vic_index(connector, video_db, 3469 video_len, 3470 video_index); 3471 if (newmode) { 3472 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3473 drm_mode_probed_add(connector, newmode); 3474 modes++; 3475 } 3476 } 3477 if (structure & (1 << 6)) { 3478 newmode = drm_display_mode_from_vic_index(connector, video_db, 3479 video_len, 3480 video_index); 3481 if (newmode) { 3482 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3483 drm_mode_probed_add(connector, newmode); 3484 modes++; 3485 } 3486 } 3487 if (structure & (1 << 8)) { 3488 newmode = drm_display_mode_from_vic_index(connector, video_db, 3489 video_len, 3490 video_index); 3491 if (newmode) { 3492 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3493 drm_mode_probed_add(connector, newmode); 3494 modes++; 3495 } 3496 } 3497 3498 return modes; 3499} 3500 3501/* 3502 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3503 * @connector: connector corresponding to the HDMI sink 3504 * @db: start of the CEA vendor specific block 3505 * @len: length of the CEA block payload, ie. one can access up to db[len] 3506 * 3507 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3508 * also adds the stereo 3d modes when applicable. 3509 */ 3510static int 3511do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3512 const u8 *video_db, u8 video_len) 3513{ 3514 struct drm_display_info *info = &connector->display_info; 3515 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3516 u8 vic_len, hdmi_3d_len = 0; 3517 u16 mask; 3518 u16 structure_all; 3519 3520 if (len < 8) 3521 goto out; 3522 3523 /* no HDMI_Video_Present */ 3524 if (!(db[8] & (1 << 5))) 3525 goto out; 3526 3527 /* Latency_Fields_Present */ 3528 if (db[8] & (1 << 7)) 3529 offset += 2; 3530 3531 /* I_Latency_Fields_Present */ 3532 if (db[8] & (1 << 6)) 3533 offset += 2; 3534 3535 /* the declared length is not long enough for the 2 first bytes 3536 * of additional video format capabilities */ 3537 if (len < (8 + offset + 2)) 3538 goto out; 3539 3540 /* 3D_Present */ 3541 offset++; 3542 if (db[8 + offset] & (1 << 7)) { 3543 modes += add_hdmi_mandatory_stereo_modes(connector); 3544 3545 /* 3D_Multi_present */ 3546 multi_present = (db[8 + offset] & 0x60) >> 5; 3547 } 3548 3549 offset++; 3550 vic_len = db[8 + offset] >> 5; 3551 hdmi_3d_len = db[8 + offset] & 0x1f; 3552 3553 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3554 u8 vic; 3555 3556 vic = db[9 + offset + i]; 3557 modes += add_hdmi_mode(connector, vic); 3558 } 3559 offset += 1 + vic_len; 3560 3561 if (multi_present == 1) 3562 multi_len = 2; 3563 else if (multi_present == 2) 3564 multi_len = 4; 3565 else 3566 multi_len = 0; 3567 3568 if (len < (8 + offset + hdmi_3d_len - 1)) 3569 goto out; 3570 3571 if (hdmi_3d_len < multi_len) 3572 goto out; 3573 3574 if (multi_present == 1 || multi_present == 2) { 3575 /* 3D_Structure_ALL */ 3576 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3577 3578 /* check if 3D_MASK is present */ 3579 if (multi_present == 2) 3580 mask = (db[10 + offset] << 8) | db[11 + offset]; 3581 else 3582 mask = 0xffff; 3583 3584 for (i = 0; i < 16; i++) { 3585 if (mask & (1 << i)) 3586 modes += add_3d_struct_modes(connector, 3587 structure_all, 3588 video_db, 3589 video_len, i); 3590 } 3591 } 3592 3593 offset += multi_len; 3594 3595 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3596 int vic_index; 3597 struct drm_display_mode *newmode = NULL; 3598 unsigned int newflag = 0; 3599 bool detail_present; 3600 3601 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3602 3603 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3604 break; 3605 3606 /* 2D_VIC_order_X */ 3607 vic_index = db[8 + offset + i] >> 4; 3608 3609 /* 3D_Structure_X */ 3610 switch (db[8 + offset + i] & 0x0f) { 3611 case 0: 3612 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3613 break; 3614 case 6: 3615 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3616 break; 3617 case 8: 3618 /* 3D_Detail_X */ 3619 if ((db[9 + offset + i] >> 4) == 1) 3620 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3621 break; 3622 } 3623 3624 if (newflag != 0) { 3625 newmode = drm_display_mode_from_vic_index(connector, 3626 video_db, 3627 video_len, 3628 vic_index); 3629 3630 if (newmode) { 3631 newmode->flags |= newflag; 3632 drm_mode_probed_add(connector, newmode); 3633 modes++; 3634 } 3635 } 3636 3637 if (detail_present) 3638 i++; 3639 } 3640 3641out: 3642 if (modes > 0) 3643 info->has_hdmi_infoframe = true; 3644 return modes; 3645} 3646 3647static int 3648cea_db_payload_len(const u8 *db) 3649{ 3650 return db[0] & 0x1f; 3651} 3652 3653static int 3654cea_db_extended_tag(const u8 *db) 3655{ 3656 return db[1]; 3657} 3658 3659static int 3660cea_db_tag(const u8 *db) 3661{ 3662 return db[0] >> 5; 3663} 3664 3665static int 3666cea_revision(const u8 *cea) 3667{ 3668 return cea[1]; 3669} 3670 3671static int 3672cea_db_offsets(const u8 *cea, int *start, int *end) 3673{ 3674 /* Data block offset in CEA extension block */ 3675 *start = 4; 3676 *end = cea[2]; 3677 if (*end == 0) 3678 *end = 127; 3679 if (*end < 4 || *end > 127) 3680 return -ERANGE; 3681 return 0; 3682} 3683 3684static bool cea_db_is_hdmi_vsdb(const u8 *db) 3685{ 3686 int hdmi_id; 3687 3688 if (cea_db_tag(db) != VENDOR_BLOCK) 3689 return false; 3690 3691 if (cea_db_payload_len(db) < 5) 3692 return false; 3693 3694 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3695 3696 return hdmi_id == HDMI_IEEE_OUI; 3697} 3698 3699static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 3700{ 3701 unsigned int oui; 3702 3703 if (cea_db_tag(db) != VENDOR_BLOCK) 3704 return false; 3705 3706 if (cea_db_payload_len(db) < 7) 3707 return false; 3708 3709 oui = db[3] << 16 | db[2] << 8 | db[1]; 3710 3711 return oui == HDMI_FORUM_IEEE_OUI; 3712} 3713 3714static bool cea_db_is_y420cmdb(const u8 *db) 3715{ 3716 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3717 return false; 3718 3719 if (!cea_db_payload_len(db)) 3720 return false; 3721 3722 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 3723 return false; 3724 3725 return true; 3726} 3727 3728static bool cea_db_is_y420vdb(const u8 *db) 3729{ 3730 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3731 return false; 3732 3733 if (!cea_db_payload_len(db)) 3734 return false; 3735 3736 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 3737 return false; 3738 3739 return true; 3740} 3741 3742#define for_each_cea_db(cea, i, start, end) \ 3743 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3744 3745static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 3746 const u8 *db) 3747{ 3748 struct drm_display_info *info = &connector->display_info; 3749 struct drm_hdmi_info *hdmi = &info->hdmi; 3750 u8 map_len = cea_db_payload_len(db) - 1; 3751 u8 count; 3752 u64 map = 0; 3753 3754 if (map_len == 0) { 3755 /* All CEA modes support ycbcr420 sampling also.*/ 3756 hdmi->y420_cmdb_map = U64_MAX; 3757 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3758 return; 3759 } 3760 3761 /* 3762 * This map indicates which of the existing CEA block modes 3763 * from VDB can support YCBCR420 output too. So if bit=0 is 3764 * set, first mode from VDB can support YCBCR420 output too. 3765 * We will parse and keep this map, before parsing VDB itself 3766 * to avoid going through the same block again and again. 3767 * 3768 * Spec is not clear about max possible size of this block. 3769 * Clamping max bitmap block size at 8 bytes. Every byte can 3770 * address 8 CEA modes, in this way this map can address 3771 * 8*8 = first 64 SVDs. 3772 */ 3773 if (WARN_ON_ONCE(map_len > 8)) 3774 map_len = 8; 3775 3776 for (count = 0; count < map_len; count++) 3777 map |= (u64)db[2 + count] << (8 * count); 3778 3779 if (map) 3780 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3781 3782 hdmi->y420_cmdb_map = map; 3783} 3784 3785static int 3786add_cea_modes(struct drm_connector *connector, struct edid *edid) 3787{ 3788 const u8 *cea = drm_find_cea_extension(edid); 3789 const u8 *db, *hdmi = NULL, *video = NULL; 3790 u8 dbl, hdmi_len, video_len = 0; 3791 int modes = 0; 3792 3793 if (cea && cea_revision(cea) >= 3) { 3794 int i, start, end; 3795 3796 if (cea_db_offsets(cea, &start, &end)) 3797 return 0; 3798 3799 for_each_cea_db(cea, i, start, end) { 3800 db = &cea[i]; 3801 dbl = cea_db_payload_len(db); 3802 3803 if (cea_db_tag(db) == VIDEO_BLOCK) { 3804 video = db + 1; 3805 video_len = dbl; 3806 modes += do_cea_modes(connector, video, dbl); 3807 } else if (cea_db_is_hdmi_vsdb(db)) { 3808 hdmi = db; 3809 hdmi_len = dbl; 3810 } else if (cea_db_is_y420vdb(db)) { 3811 const u8 *vdb420 = &db[2]; 3812 3813 /* Add 4:2:0(only) modes present in EDID */ 3814 modes += do_y420vdb_modes(connector, 3815 vdb420, 3816 dbl - 1); 3817 } 3818 } 3819 } 3820 3821 /* 3822 * We parse the HDMI VSDB after having added the cea modes as we will 3823 * be patching their flags when the sink supports stereo 3D. 3824 */ 3825 if (hdmi) 3826 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3827 video_len); 3828 3829 return modes; 3830} 3831 3832static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3833{ 3834 const struct drm_display_mode *cea_mode; 3835 int clock1, clock2, clock; 3836 u8 vic; 3837 const char *type; 3838 3839 /* 3840 * allow 5kHz clock difference either way to account for 3841 * the 10kHz clock resolution limit of detailed timings. 3842 */ 3843 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3844 if (drm_valid_cea_vic(vic)) { 3845 type = "CEA"; 3846 cea_mode = &edid_cea_modes[vic]; 3847 clock1 = cea_mode->clock; 3848 clock2 = cea_mode_alternate_clock(cea_mode); 3849 } else { 3850 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3851 if (drm_valid_hdmi_vic(vic)) { 3852 type = "HDMI"; 3853 cea_mode = &edid_4k_modes[vic]; 3854 clock1 = cea_mode->clock; 3855 clock2 = hdmi_mode_alternate_clock(cea_mode); 3856 } else { 3857 return; 3858 } 3859 } 3860 3861 /* pick whichever is closest */ 3862 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3863 clock = clock1; 3864 else 3865 clock = clock2; 3866 3867 if (mode->clock == clock) 3868 return; 3869 3870 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3871 type, vic, mode->clock, clock); 3872 mode->clock = clock; 3873} 3874 3875static void 3876drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 3877{ 3878 u8 len = cea_db_payload_len(db); 3879 3880 if (len >= 6 && (db[6] & (1 << 7))) 3881 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 3882 if (len >= 8) { 3883 connector->latency_present[0] = db[8] >> 7; 3884 connector->latency_present[1] = (db[8] >> 6) & 1; 3885 } 3886 if (len >= 9) 3887 connector->video_latency[0] = db[9]; 3888 if (len >= 10) 3889 connector->audio_latency[0] = db[10]; 3890 if (len >= 11) 3891 connector->video_latency[1] = db[11]; 3892 if (len >= 12) 3893 connector->audio_latency[1] = db[12]; 3894 3895 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 3896 "video latency %d %d, " 3897 "audio latency %d %d\n", 3898 connector->latency_present[0], 3899 connector->latency_present[1], 3900 connector->video_latency[0], 3901 connector->video_latency[1], 3902 connector->audio_latency[0], 3903 connector->audio_latency[1]); 3904} 3905 3906static void 3907monitor_name(struct detailed_timing *t, void *data) 3908{ 3909 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3910 *(u8 **)data = t->data.other_data.data.str.str; 3911} 3912 3913static int get_monitor_name(struct edid *edid, char name[13]) 3914{ 3915 char *edid_name = NULL; 3916 int mnl; 3917 3918 if (!edid || !name) 3919 return 0; 3920 3921 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3922 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3923 if (edid_name[mnl] == 0x0a) 3924 break; 3925 3926 name[mnl] = edid_name[mnl]; 3927 } 3928 3929 return mnl; 3930} 3931 3932/** 3933 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3934 * @edid: monitor EDID information 3935 * @name: pointer to a character array to hold the name of the monitor 3936 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3937 * 3938 */ 3939void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3940{ 3941 int name_length; 3942 char buf[13]; 3943 3944 if (bufsize <= 0) 3945 return; 3946 3947 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3948 memcpy(name, buf, name_length); 3949 name[name_length] = '\0'; 3950} 3951EXPORT_SYMBOL(drm_edid_get_monitor_name); 3952 3953static void clear_eld(struct drm_connector *connector) 3954{ 3955 memset(connector->eld, 0, sizeof(connector->eld)); 3956 3957 connector->latency_present[0] = false; 3958 connector->latency_present[1] = false; 3959 connector->video_latency[0] = 0; 3960 connector->audio_latency[0] = 0; 3961 connector->video_latency[1] = 0; 3962 connector->audio_latency[1] = 0; 3963} 3964 3965/* 3966 * drm_edid_to_eld - build ELD from EDID 3967 * @connector: connector corresponding to the HDMI/DP sink 3968 * @edid: EDID to parse 3969 * 3970 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3971 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 3972 */ 3973static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3974{ 3975 uint8_t *eld = connector->eld; 3976 u8 *cea; 3977 u8 *db; 3978 int total_sad_count = 0; 3979 int mnl; 3980 int dbl; 3981 3982 clear_eld(connector); 3983 3984 if (!edid) 3985 return; 3986 3987 cea = drm_find_cea_extension(edid); 3988 if (!cea) { 3989 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3990 return; 3991 } 3992 3993 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 3994 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 3995 3996 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 3997 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 3998 3999 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4000 4001 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4002 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4003 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4004 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4005 4006 if (cea_revision(cea) >= 3) { 4007 int i, start, end; 4008 4009 if (cea_db_offsets(cea, &start, &end)) { 4010 start = 0; 4011 end = 0; 4012 } 4013 4014 for_each_cea_db(cea, i, start, end) { 4015 db = &cea[i]; 4016 dbl = cea_db_payload_len(db); 4017 4018 switch (cea_db_tag(db)) { 4019 int sad_count; 4020 4021 case AUDIO_BLOCK: 4022 /* Audio Data Block, contains SADs */ 4023 sad_count = min(dbl / 3, 15 - total_sad_count); 4024 if (sad_count >= 1) 4025 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4026 &db[1], sad_count * 3); 4027 total_sad_count += sad_count; 4028 break; 4029 case SPEAKER_BLOCK: 4030 /* Speaker Allocation Data Block */ 4031 if (dbl >= 1) 4032 eld[DRM_ELD_SPEAKER] = db[1]; 4033 break; 4034 case VENDOR_BLOCK: 4035 /* HDMI Vendor-Specific Data Block */ 4036 if (cea_db_is_hdmi_vsdb(db)) 4037 drm_parse_hdmi_vsdb_audio(connector, db); 4038 break; 4039 default: 4040 break; 4041 } 4042 } 4043 } 4044 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4045 4046 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4047 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4048 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4049 else 4050 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4051 4052 eld[DRM_ELD_BASELINE_ELD_LEN] = 4053 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4054 4055 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4056 drm_eld_size(eld), total_sad_count); 4057} 4058 4059/** 4060 * drm_edid_to_sad - extracts SADs from EDID 4061 * @edid: EDID to parse 4062 * @sads: pointer that will be set to the extracted SADs 4063 * 4064 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4065 * 4066 * Note: The returned pointer needs to be freed using kfree(). 4067 * 4068 * Return: The number of found SADs or negative number on error. 4069 */ 4070int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4071{ 4072 int count = 0; 4073 int i, start, end, dbl; 4074 u8 *cea; 4075 4076 cea = drm_find_cea_extension(edid); 4077 if (!cea) { 4078 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4079 return -ENOENT; 4080 } 4081 4082 if (cea_revision(cea) < 3) { 4083 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4084 return -ENOTSUPP; 4085 } 4086 4087 if (cea_db_offsets(cea, &start, &end)) { 4088 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4089 return -EPROTO; 4090 } 4091 4092 for_each_cea_db(cea, i, start, end) { 4093 u8 *db = &cea[i]; 4094 4095 if (cea_db_tag(db) == AUDIO_BLOCK) { 4096 int j; 4097 dbl = cea_db_payload_len(db); 4098 4099 count = dbl / 3; /* SAD is 3B */ 4100 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4101 if (!*sads) 4102 return -ENOMEM; 4103 for (j = 0; j < count; j++) { 4104 u8 *sad = &db[1 + j * 3]; 4105 4106 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4107 (*sads)[j].channels = sad[0] & 0x7; 4108 (*sads)[j].freq = sad[1] & 0x7F; 4109 (*sads)[j].byte2 = sad[2]; 4110 } 4111 break; 4112 } 4113 } 4114 4115 return count; 4116} 4117EXPORT_SYMBOL(drm_edid_to_sad); 4118 4119/** 4120 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4121 * @edid: EDID to parse 4122 * @sadb: pointer to the speaker block 4123 * 4124 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4125 * 4126 * Note: The returned pointer needs to be freed using kfree(). 4127 * 4128 * Return: The number of found Speaker Allocation Blocks or negative number on 4129 * error. 4130 */ 4131int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4132{ 4133 int count = 0; 4134 int i, start, end, dbl; 4135 const u8 *cea; 4136 4137 cea = drm_find_cea_extension(edid); 4138 if (!cea) { 4139 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4140 return -ENOENT; 4141 } 4142 4143 if (cea_revision(cea) < 3) { 4144 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4145 return -ENOTSUPP; 4146 } 4147 4148 if (cea_db_offsets(cea, &start, &end)) { 4149 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4150 return -EPROTO; 4151 } 4152 4153 for_each_cea_db(cea, i, start, end) { 4154 const u8 *db = &cea[i]; 4155 4156 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4157 dbl = cea_db_payload_len(db); 4158 4159 /* Speaker Allocation Data Block */ 4160 if (dbl == 3) { 4161 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4162 if (!*sadb) 4163 return -ENOMEM; 4164 count = dbl; 4165 break; 4166 } 4167 } 4168 } 4169 4170 return count; 4171} 4172EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4173 4174/** 4175 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4176 * @connector: connector associated with the HDMI/DP sink 4177 * @mode: the display mode 4178 * 4179 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4180 * the sink doesn't support audio or video. 4181 */ 4182int drm_av_sync_delay(struct drm_connector *connector, 4183 const struct drm_display_mode *mode) 4184{ 4185 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4186 int a, v; 4187 4188 if (!connector->latency_present[0]) 4189 return 0; 4190 if (!connector->latency_present[1]) 4191 i = 0; 4192 4193 a = connector->audio_latency[i]; 4194 v = connector->video_latency[i]; 4195 4196 /* 4197 * HDMI/DP sink doesn't support audio or video? 4198 */ 4199 if (a == 255 || v == 255) 4200 return 0; 4201 4202 /* 4203 * Convert raw EDID values to millisecond. 4204 * Treat unknown latency as 0ms. 4205 */ 4206 if (a) 4207 a = min(2 * (a - 1), 500); 4208 if (v) 4209 v = min(2 * (v - 1), 500); 4210 4211 return max(v - a, 0); 4212} 4213EXPORT_SYMBOL(drm_av_sync_delay); 4214 4215/** 4216 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4217 * @edid: monitor EDID information 4218 * 4219 * Parse the CEA extension according to CEA-861-B. 4220 * 4221 * Return: True if the monitor is HDMI, false if not or unknown. 4222 */ 4223bool drm_detect_hdmi_monitor(struct edid *edid) 4224{ 4225 u8 *edid_ext; 4226 int i; 4227 int start_offset, end_offset; 4228 4229 edid_ext = drm_find_cea_extension(edid); 4230 if (!edid_ext) 4231 return false; 4232 4233 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4234 return false; 4235 4236 /* 4237 * Because HDMI identifier is in Vendor Specific Block, 4238 * search it from all data blocks of CEA extension. 4239 */ 4240 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4241 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4242 return true; 4243 } 4244 4245 return false; 4246} 4247EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4248 4249/** 4250 * drm_detect_monitor_audio - check monitor audio capability 4251 * @edid: EDID block to scan 4252 * 4253 * Monitor should have CEA extension block. 4254 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4255 * audio' only. If there is any audio extension block and supported 4256 * audio format, assume at least 'basic audio' support, even if 'basic 4257 * audio' is not defined in EDID. 4258 * 4259 * Return: True if the monitor supports audio, false otherwise. 4260 */ 4261bool drm_detect_monitor_audio(struct edid *edid) 4262{ 4263 u8 *edid_ext; 4264 int i, j; 4265 bool has_audio = false; 4266 int start_offset, end_offset; 4267 4268 edid_ext = drm_find_cea_extension(edid); 4269 if (!edid_ext) 4270 goto end; 4271 4272 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4273 4274 if (has_audio) { 4275 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4276 goto end; 4277 } 4278 4279 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4280 goto end; 4281 4282 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4283 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4284 has_audio = true; 4285 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4286 DRM_DEBUG_KMS("CEA audio format %d\n", 4287 (edid_ext[i + j] >> 3) & 0xf); 4288 goto end; 4289 } 4290 } 4291end: 4292 return has_audio; 4293} 4294EXPORT_SYMBOL(drm_detect_monitor_audio); 4295 4296/** 4297 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 4298 * @edid: EDID block to scan 4299 * 4300 * Check whether the monitor reports the RGB quantization range selection 4301 * as supported. The AVI infoframe can then be used to inform the monitor 4302 * which quantization range (full or limited) is used. 4303 * 4304 * Return: True if the RGB quantization range is selectable, false otherwise. 4305 */ 4306bool drm_rgb_quant_range_selectable(struct edid *edid) 4307{ 4308 u8 *edid_ext; 4309 int i, start, end; 4310 4311 edid_ext = drm_find_cea_extension(edid); 4312 if (!edid_ext) 4313 return false; 4314 4315 if (cea_db_offsets(edid_ext, &start, &end)) 4316 return false; 4317 4318 for_each_cea_db(edid_ext, i, start, end) { 4319 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG && 4320 cea_db_payload_len(&edid_ext[i]) == 2 && 4321 cea_db_extended_tag(&edid_ext[i]) == 4322 EXT_VIDEO_CAPABILITY_BLOCK) { 4323 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 4324 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 4325 } 4326 } 4327 4328 return false; 4329} 4330EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 4331 4332/** 4333 * drm_default_rgb_quant_range - default RGB quantization range 4334 * @mode: display mode 4335 * 4336 * Determine the default RGB quantization range for the mode, 4337 * as specified in CEA-861. 4338 * 4339 * Return: The default RGB quantization range for the mode 4340 */ 4341enum hdmi_quantization_range 4342drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4343{ 4344 /* All CEA modes other than VIC 1 use limited quantization range. */ 4345 return drm_match_cea_mode(mode) > 1 ? 4346 HDMI_QUANTIZATION_RANGE_LIMITED : 4347 HDMI_QUANTIZATION_RANGE_FULL; 4348} 4349EXPORT_SYMBOL(drm_default_rgb_quant_range); 4350 4351static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4352 const u8 *db) 4353{ 4354 u8 dc_mask; 4355 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4356 4357 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4358 hdmi->y420_dc_modes = dc_mask; 4359} 4360 4361static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4362 const u8 *hf_vsdb) 4363{ 4364 struct drm_display_info *display = &connector->display_info; 4365 struct drm_hdmi_info *hdmi = &display->hdmi; 4366 4367 display->has_hdmi_infoframe = true; 4368 4369 if (hf_vsdb[6] & 0x80) { 4370 hdmi->scdc.supported = true; 4371 if (hf_vsdb[6] & 0x40) 4372 hdmi->scdc.read_request = true; 4373 } 4374 4375 /* 4376 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4377 * And as per the spec, three factors confirm this: 4378 * * Availability of a HF-VSDB block in EDID (check) 4379 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4380 * * SCDC support available (let's check) 4381 * Lets check it out. 4382 */ 4383 4384 if (hf_vsdb[5]) { 4385 /* max clock is 5000 KHz times block value */ 4386 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4387 struct drm_scdc *scdc = &hdmi->scdc; 4388 4389 if (max_tmds_clock > 340000) { 4390 display->max_tmds_clock = max_tmds_clock; 4391 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4392 display->max_tmds_clock); 4393 } 4394 4395 if (scdc->supported) { 4396 scdc->scrambling.supported = true; 4397 4398 /* Few sinks support scrambling for cloks < 340M */ 4399 if ((hf_vsdb[6] & 0x8)) 4400 scdc->scrambling.low_rates = true; 4401 } 4402 } 4403 4404 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4405} 4406 4407static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4408 const u8 *hdmi) 4409{ 4410 struct drm_display_info *info = &connector->display_info; 4411 unsigned int dc_bpc = 0; 4412 4413 /* HDMI supports at least 8 bpc */ 4414 info->bpc = 8; 4415 4416 if (cea_db_payload_len(hdmi) < 6) 4417 return; 4418 4419 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4420 dc_bpc = 10; 4421 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4422 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4423 connector->name); 4424 } 4425 4426 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4427 dc_bpc = 12; 4428 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4429 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4430 connector->name); 4431 } 4432 4433 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4434 dc_bpc = 16; 4435 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4436 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4437 connector->name); 4438 } 4439 4440 if (dc_bpc == 0) { 4441 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4442 connector->name); 4443 return; 4444 } 4445 4446 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4447 connector->name, dc_bpc); 4448 info->bpc = dc_bpc; 4449 4450 /* 4451 * Deep color support mandates RGB444 support for all video 4452 * modes and forbids YCRCB422 support for all video modes per 4453 * HDMI 1.3 spec. 4454 */ 4455 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4456 4457 /* YCRCB444 is optional according to spec. */ 4458 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4459 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4460 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4461 connector->name); 4462 } 4463 4464 /* 4465 * Spec says that if any deep color mode is supported at all, 4466 * then deep color 36 bit must be supported. 4467 */ 4468 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4469 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4470 connector->name); 4471 } 4472} 4473 4474static void 4475drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4476{ 4477 struct drm_display_info *info = &connector->display_info; 4478 u8 len = cea_db_payload_len(db); 4479 4480 if (len >= 6) 4481 info->dvi_dual = db[6] & 1; 4482 if (len >= 7) 4483 info->max_tmds_clock = db[7] * 5000; 4484 4485 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4486 "max TMDS clock %d kHz\n", 4487 info->dvi_dual, 4488 info->max_tmds_clock); 4489 4490 drm_parse_hdmi_deep_color_info(connector, db); 4491} 4492 4493static void drm_parse_cea_ext(struct drm_connector *connector, 4494 const struct edid *edid) 4495{ 4496 struct drm_display_info *info = &connector->display_info; 4497 const u8 *edid_ext; 4498 int i, start, end; 4499 4500 edid_ext = drm_find_cea_extension(edid); 4501 if (!edid_ext) 4502 return; 4503 4504 info->cea_rev = edid_ext[1]; 4505 4506 /* The existence of a CEA block should imply RGB support */ 4507 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4508 if (edid_ext[3] & EDID_CEA_YCRCB444) 4509 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4510 if (edid_ext[3] & EDID_CEA_YCRCB422) 4511 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4512 4513 if (cea_db_offsets(edid_ext, &start, &end)) 4514 return; 4515 4516 for_each_cea_db(edid_ext, i, start, end) { 4517 const u8 *db = &edid_ext[i]; 4518 4519 if (cea_db_is_hdmi_vsdb(db)) 4520 drm_parse_hdmi_vsdb_video(connector, db); 4521 if (cea_db_is_hdmi_forum_vsdb(db)) 4522 drm_parse_hdmi_forum_vsdb(connector, db); 4523 if (cea_db_is_y420cmdb(db)) 4524 drm_parse_y420cmdb_bitmap(connector, db); 4525 } 4526} 4527 4528/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4529 * all of the values which would have been set from EDID 4530 */ 4531void 4532drm_reset_display_info(struct drm_connector *connector) 4533{ 4534 struct drm_display_info *info = &connector->display_info; 4535 4536 info->width_mm = 0; 4537 info->height_mm = 0; 4538 4539 info->bpc = 0; 4540 info->color_formats = 0; 4541 info->cea_rev = 0; 4542 info->max_tmds_clock = 0; 4543 info->dvi_dual = false; 4544 info->has_hdmi_infoframe = false; 4545 memset(&info->hdmi, 0, sizeof(info->hdmi)); 4546 4547 info->non_desktop = 0; 4548} 4549 4550u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 4551{ 4552 struct drm_display_info *info = &connector->display_info; 4553 4554 u32 quirks = edid_get_quirks(edid); 4555 4556 drm_reset_display_info(connector); 4557 4558 info->width_mm = edid->width_cm * 10; 4559 info->height_mm = edid->height_cm * 10; 4560 4561 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 4562 4563 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 4564 4565 if (edid->revision < 3) 4566 return quirks; 4567 4568 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4569 return quirks; 4570 4571 drm_parse_cea_ext(connector, edid); 4572 4573 /* 4574 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4575 * 4576 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4577 * tells us to assume 8 bpc color depth if the EDID doesn't have 4578 * extensions which tell otherwise. 4579 */ 4580 if ((info->bpc == 0) && (edid->revision < 4) && 4581 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 4582 info->bpc = 8; 4583 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4584 connector->name, info->bpc); 4585 } 4586 4587 /* Only defined for 1.4 with digital displays */ 4588 if (edid->revision < 4) 4589 return quirks; 4590 4591 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4592 case DRM_EDID_DIGITAL_DEPTH_6: 4593 info->bpc = 6; 4594 break; 4595 case DRM_EDID_DIGITAL_DEPTH_8: 4596 info->bpc = 8; 4597 break; 4598 case DRM_EDID_DIGITAL_DEPTH_10: 4599 info->bpc = 10; 4600 break; 4601 case DRM_EDID_DIGITAL_DEPTH_12: 4602 info->bpc = 12; 4603 break; 4604 case DRM_EDID_DIGITAL_DEPTH_14: 4605 info->bpc = 14; 4606 break; 4607 case DRM_EDID_DIGITAL_DEPTH_16: 4608 info->bpc = 16; 4609 break; 4610 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4611 default: 4612 info->bpc = 0; 4613 break; 4614 } 4615 4616 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4617 connector->name, info->bpc); 4618 4619 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4620 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4621 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4622 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4623 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4624 return quirks; 4625} 4626 4627static int validate_displayid(u8 *displayid, int length, int idx) 4628{ 4629 int i; 4630 u8 csum = 0; 4631 struct displayid_hdr *base; 4632 4633 base = (struct displayid_hdr *)&displayid[idx]; 4634 4635 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4636 base->rev, base->bytes, base->prod_id, base->ext_count); 4637 4638 if (base->bytes + 5 > length - idx) 4639 return -EINVAL; 4640 for (i = idx; i <= base->bytes + 5; i++) { 4641 csum += displayid[i]; 4642 } 4643 if (csum) { 4644 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 4645 return -EINVAL; 4646 } 4647 return 0; 4648} 4649 4650static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4651 struct displayid_detailed_timings_1 *timings) 4652{ 4653 struct drm_display_mode *mode; 4654 unsigned pixel_clock = (timings->pixel_clock[0] | 4655 (timings->pixel_clock[1] << 8) | 4656 (timings->pixel_clock[2] << 16)); 4657 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4658 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4659 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4660 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4661 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4662 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4663 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4664 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4665 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4666 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4667 mode = drm_mode_create(dev); 4668 if (!mode) 4669 return NULL; 4670 4671 mode->clock = pixel_clock * 10; 4672 mode->hdisplay = hactive; 4673 mode->hsync_start = mode->hdisplay + hsync; 4674 mode->hsync_end = mode->hsync_start + hsync_width; 4675 mode->htotal = mode->hdisplay + hblank; 4676 4677 mode->vdisplay = vactive; 4678 mode->vsync_start = mode->vdisplay + vsync; 4679 mode->vsync_end = mode->vsync_start + vsync_width; 4680 mode->vtotal = mode->vdisplay + vblank; 4681 4682 mode->flags = 0; 4683 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4684 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4685 mode->type = DRM_MODE_TYPE_DRIVER; 4686 4687 if (timings->flags & 0x80) 4688 mode->type |= DRM_MODE_TYPE_PREFERRED; 4689 mode->vrefresh = drm_mode_vrefresh(mode); 4690 drm_mode_set_name(mode); 4691 4692 return mode; 4693} 4694 4695static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4696 struct displayid_block *block) 4697{ 4698 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4699 int i; 4700 int num_timings; 4701 struct drm_display_mode *newmode; 4702 int num_modes = 0; 4703 /* blocks must be multiple of 20 bytes length */ 4704 if (block->num_bytes % 20) 4705 return 0; 4706 4707 num_timings = block->num_bytes / 20; 4708 for (i = 0; i < num_timings; i++) { 4709 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4710 4711 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4712 if (!newmode) 4713 continue; 4714 4715 drm_mode_probed_add(connector, newmode); 4716 num_modes++; 4717 } 4718 return num_modes; 4719} 4720 4721static int add_displayid_detailed_modes(struct drm_connector *connector, 4722 struct edid *edid) 4723{ 4724 u8 *displayid; 4725 int ret; 4726 int idx = 1; 4727 int length = EDID_LENGTH; 4728 struct displayid_block *block; 4729 int num_modes = 0; 4730 4731 displayid = drm_find_displayid_extension(edid); 4732 if (!displayid) 4733 return 0; 4734 4735 ret = validate_displayid(displayid, length, idx); 4736 if (ret) 4737 return 0; 4738 4739 idx += sizeof(struct displayid_hdr); 4740 while (block = (struct displayid_block *)&displayid[idx], 4741 idx + sizeof(struct displayid_block) <= length && 4742 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4743 block->num_bytes > 0) { 4744 idx += block->num_bytes + sizeof(struct displayid_block); 4745 switch (block->tag) { 4746 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4747 num_modes += add_displayid_detailed_1_modes(connector, block); 4748 break; 4749 } 4750 } 4751 return num_modes; 4752} 4753 4754/** 4755 * drm_add_edid_modes - add modes from EDID data, if available 4756 * @connector: connector we're probing 4757 * @edid: EDID data 4758 * 4759 * Add the specified modes to the connector's mode list. Also fills out the 4760 * &drm_display_info structure and ELD in @connector with any information which 4761 * can be derived from the edid. 4762 * 4763 * Return: The number of modes added or 0 if we couldn't find any. 4764 */ 4765int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4766{ 4767 int num_modes = 0; 4768 u32 quirks; 4769 4770 if (edid == NULL) { 4771 clear_eld(connector); 4772 return 0; 4773 } 4774 if (!drm_edid_is_valid(edid)) { 4775 clear_eld(connector); 4776 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4777 connector->name); 4778 return 0; 4779 } 4780 4781 drm_edid_to_eld(connector, edid); 4782 4783 /* 4784 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4785 * To avoid multiple parsing of same block, lets parse that map 4786 * from sink info, before parsing CEA modes. 4787 */ 4788 quirks = drm_add_display_info(connector, edid); 4789 4790 /* 4791 * EDID spec says modes should be preferred in this order: 4792 * - preferred detailed mode 4793 * - other detailed modes from base block 4794 * - detailed modes from extension blocks 4795 * - CVT 3-byte code modes 4796 * - standard timing codes 4797 * - established timing codes 4798 * - modes inferred from GTF or CVT range information 4799 * 4800 * We get this pretty much right. 4801 * 4802 * XXX order for additional mode types in extension blocks? 4803 */ 4804 num_modes += add_detailed_modes(connector, edid, quirks); 4805 num_modes += add_cvt_modes(connector, edid); 4806 num_modes += add_standard_modes(connector, edid); 4807 num_modes += add_established_modes(connector, edid); 4808 num_modes += add_cea_modes(connector, edid); 4809 num_modes += add_alternate_cea_modes(connector, edid); 4810 num_modes += add_displayid_detailed_modes(connector, edid); 4811 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4812 num_modes += add_inferred_modes(connector, edid); 4813 4814 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4815 edid_fixup_preferred(connector, quirks); 4816 4817 if (quirks & EDID_QUIRK_FORCE_6BPC) 4818 connector->display_info.bpc = 6; 4819 4820 if (quirks & EDID_QUIRK_FORCE_8BPC) 4821 connector->display_info.bpc = 8; 4822 4823 if (quirks & EDID_QUIRK_FORCE_10BPC) 4824 connector->display_info.bpc = 10; 4825 4826 if (quirks & EDID_QUIRK_FORCE_12BPC) 4827 connector->display_info.bpc = 12; 4828 4829 return num_modes; 4830} 4831EXPORT_SYMBOL(drm_add_edid_modes); 4832 4833/** 4834 * drm_add_modes_noedid - add modes for the connectors without EDID 4835 * @connector: connector we're probing 4836 * @hdisplay: the horizontal display limit 4837 * @vdisplay: the vertical display limit 4838 * 4839 * Add the specified modes to the connector's mode list. Only when the 4840 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4841 * 4842 * Return: The number of modes added or 0 if we couldn't find any. 4843 */ 4844int drm_add_modes_noedid(struct drm_connector *connector, 4845 int hdisplay, int vdisplay) 4846{ 4847 int i, count, num_modes = 0; 4848 struct drm_display_mode *mode; 4849 struct drm_device *dev = connector->dev; 4850 4851 count = ARRAY_SIZE(drm_dmt_modes); 4852 if (hdisplay < 0) 4853 hdisplay = 0; 4854 if (vdisplay < 0) 4855 vdisplay = 0; 4856 4857 for (i = 0; i < count; i++) { 4858 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4859 if (hdisplay && vdisplay) { 4860 /* 4861 * Only when two are valid, they will be used to check 4862 * whether the mode should be added to the mode list of 4863 * the connector. 4864 */ 4865 if (ptr->hdisplay > hdisplay || 4866 ptr->vdisplay > vdisplay) 4867 continue; 4868 } 4869 if (drm_mode_vrefresh(ptr) > 61) 4870 continue; 4871 mode = drm_mode_duplicate(dev, ptr); 4872 if (mode) { 4873 drm_mode_probed_add(connector, mode); 4874 num_modes++; 4875 } 4876 } 4877 return num_modes; 4878} 4879EXPORT_SYMBOL(drm_add_modes_noedid); 4880 4881/** 4882 * drm_set_preferred_mode - Sets the preferred mode of a connector 4883 * @connector: connector whose mode list should be processed 4884 * @hpref: horizontal resolution of preferred mode 4885 * @vpref: vertical resolution of preferred mode 4886 * 4887 * Marks a mode as preferred if it matches the resolution specified by @hpref 4888 * and @vpref. 4889 */ 4890void drm_set_preferred_mode(struct drm_connector *connector, 4891 int hpref, int vpref) 4892{ 4893 struct drm_display_mode *mode; 4894 4895 list_for_each_entry(mode, &connector->probed_modes, head) { 4896 if (mode->hdisplay == hpref && 4897 mode->vdisplay == vpref) 4898 mode->type |= DRM_MODE_TYPE_PREFERRED; 4899 } 4900} 4901EXPORT_SYMBOL(drm_set_preferred_mode); 4902 4903/** 4904 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4905 * data from a DRM display mode 4906 * @frame: HDMI AVI infoframe 4907 * @mode: DRM display mode 4908 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant 4909 * 4910 * Return: 0 on success or a negative error code on failure. 4911 */ 4912int 4913drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4914 const struct drm_display_mode *mode, 4915 bool is_hdmi2_sink) 4916{ 4917 enum hdmi_picture_aspect picture_aspect; 4918 int err; 4919 4920 if (!frame || !mode) 4921 return -EINVAL; 4922 4923 err = hdmi_avi_infoframe_init(frame); 4924 if (err < 0) 4925 return err; 4926 4927 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4928 frame->pixel_repeat = 1; 4929 4930 frame->video_code = drm_match_cea_mode(mode); 4931 4932 /* 4933 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 4934 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 4935 * have to make sure we dont break HDMI 1.4 sinks. 4936 */ 4937 if (!is_hdmi2_sink && frame->video_code > 64) 4938 frame->video_code = 0; 4939 4940 /* 4941 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 4942 * we should send its VIC in vendor infoframes, else send the 4943 * VIC in AVI infoframes. Lets check if this mode is present in 4944 * HDMI 1.4b 4K modes 4945 */ 4946 if (frame->video_code) { 4947 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 4948 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 4949 4950 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 4951 frame->video_code = 0; 4952 } 4953 4954 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4955 4956 /* 4957 * As some drivers don't support atomic, we can't use connector state. 4958 * So just initialize the frame with default values, just the same way 4959 * as it's done with other properties here. 4960 */ 4961 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 4962 frame->itc = 0; 4963 4964 /* 4965 * Populate picture aspect ratio from either 4966 * user input (if specified) or from the CEA mode list. 4967 */ 4968 picture_aspect = mode->picture_aspect_ratio; 4969 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) 4970 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code); 4971 4972 /* 4973 * The infoframe can't convey anything but none, 4:3 4974 * and 16:9, so if the user has asked for anything else 4975 * we can only satisfy it by specifying the right VIC. 4976 */ 4977 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 4978 if (picture_aspect != 4979 drm_get_cea_aspect_ratio(frame->video_code)) 4980 return -EINVAL; 4981 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4982 } 4983 4984 frame->picture_aspect = picture_aspect; 4985 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4986 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4987 4988 return 0; 4989} 4990EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4991 4992/** 4993 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 4994 * quantization range information 4995 * @frame: HDMI AVI infoframe 4996 * @mode: DRM display mode 4997 * @rgb_quant_range: RGB quantization range (Q) 4998 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 4999 * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations 5000 * 5001 * Note that @is_hdmi2_sink can be derived by looking at the 5002 * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc, 5003 * &drm_display_info.hdmi, which can be found in &drm_connector.display_info. 5004 */ 5005void 5006drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5007 const struct drm_display_mode *mode, 5008 enum hdmi_quantization_range rgb_quant_range, 5009 bool rgb_quant_range_selectable, 5010 bool is_hdmi2_sink) 5011{ 5012 /* 5013 * CEA-861: 5014 * "A Source shall not send a non-zero Q value that does not correspond 5015 * to the default RGB Quantization Range for the transmitted Picture 5016 * unless the Sink indicates support for the Q bit in a Video 5017 * Capabilities Data Block." 5018 * 5019 * HDMI 2.0 recommends sending non-zero Q when it does match the 5020 * default RGB quantization range for the mode, even when QS=0. 5021 */ 5022 if (rgb_quant_range_selectable || 5023 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5024 frame->quantization_range = rgb_quant_range; 5025 else 5026 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5027 5028 /* 5029 * CEA-861-F: 5030 * "When transmitting any RGB colorimetry, the Source should set the 5031 * YQ-field to match the RGB Quantization Range being transmitted 5032 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5033 * set YQ=1) and the Sink shall ignore the YQ-field." 5034 * 5035 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5036 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5037 * good way to tell which version of CEA-861 the sink supports, so 5038 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5039 * on on CEA-861-F. 5040 */ 5041 if (!is_hdmi2_sink || 5042 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5043 frame->ycc_quantization_range = 5044 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5045 else 5046 frame->ycc_quantization_range = 5047 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5048} 5049EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5050 5051static enum hdmi_3d_structure 5052s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5053{ 5054 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5055 5056 switch (layout) { 5057 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5058 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5059 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5060 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5061 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5062 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5063 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5064 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5065 case DRM_MODE_FLAG_3D_L_DEPTH: 5066 return HDMI_3D_STRUCTURE_L_DEPTH; 5067 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5068 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5069 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5070 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5071 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5072 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5073 default: 5074 return HDMI_3D_STRUCTURE_INVALID; 5075 } 5076} 5077 5078/** 5079 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5080 * data from a DRM display mode 5081 * @frame: HDMI vendor infoframe 5082 * @connector: the connector 5083 * @mode: DRM display mode 5084 * 5085 * Note that there's is a need to send HDMI vendor infoframes only when using a 5086 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5087 * function will return -EINVAL, error that can be safely ignored. 5088 * 5089 * Return: 0 on success or a negative error code on failure. 5090 */ 5091int 5092drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5093 struct drm_connector *connector, 5094 const struct drm_display_mode *mode) 5095{ 5096 /* 5097 * FIXME: sil-sii8620 doesn't have a connector around when 5098 * we need one, so we have to be prepared for a NULL connector. 5099 */ 5100 bool has_hdmi_infoframe = connector ? 5101 connector->display_info.has_hdmi_infoframe : false; 5102 int err; 5103 u32 s3d_flags; 5104 u8 vic; 5105 5106 if (!frame || !mode) 5107 return -EINVAL; 5108 5109 if (!has_hdmi_infoframe) 5110 return -EINVAL; 5111 5112 vic = drm_match_hdmi_mode(mode); 5113 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5114 5115 /* 5116 * Even if it's not absolutely necessary to send the infoframe 5117 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5118 * know that the sink can handle it. This is based on a 5119 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5120 * have trouble realizing that they shuld switch from 3D to 2D 5121 * mode if the source simply stops sending the infoframe when 5122 * it wants to switch from 3D to 2D. 5123 */ 5124 5125 if (vic && s3d_flags) 5126 return -EINVAL; 5127 5128 err = hdmi_vendor_infoframe_init(frame); 5129 if (err < 0) 5130 return err; 5131 5132 frame->vic = vic; 5133 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5134 5135 return 0; 5136} 5137EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5138 5139static int drm_parse_tiled_block(struct drm_connector *connector, 5140 struct displayid_block *block) 5141{ 5142 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5143 u16 w, h; 5144 u8 tile_v_loc, tile_h_loc; 5145 u8 num_v_tile, num_h_tile; 5146 struct drm_tile_group *tg; 5147 5148 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5149 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5150 5151 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5152 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5153 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5154 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5155 5156 connector->has_tile = true; 5157 if (tile->tile_cap & 0x80) 5158 connector->tile_is_single_monitor = true; 5159 5160 connector->num_h_tile = num_h_tile + 1; 5161 connector->num_v_tile = num_v_tile + 1; 5162 connector->tile_h_loc = tile_h_loc; 5163 connector->tile_v_loc = tile_v_loc; 5164 connector->tile_h_size = w + 1; 5165 connector->tile_v_size = h + 1; 5166 5167 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5168 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5169 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5170 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5171 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5172 5173 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5174 if (!tg) { 5175 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5176 } 5177 if (!tg) 5178 return -ENOMEM; 5179 5180 if (connector->tile_group != tg) { 5181 /* if we haven't got a pointer, 5182 take the reference, drop ref to old tile group */ 5183 if (connector->tile_group) { 5184 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5185 } 5186 connector->tile_group = tg; 5187 } else 5188 /* if same tile group, then release the ref we just took. */ 5189 drm_mode_put_tile_group(connector->dev, tg); 5190 return 0; 5191} 5192 5193static int drm_parse_display_id(struct drm_connector *connector, 5194 u8 *displayid, int length, 5195 bool is_edid_extension) 5196{ 5197 /* if this is an EDID extension the first byte will be 0x70 */ 5198 int idx = 0; 5199 struct displayid_block *block; 5200 int ret; 5201 5202 if (is_edid_extension) 5203 idx = 1; 5204 5205 ret = validate_displayid(displayid, length, idx); 5206 if (ret) 5207 return ret; 5208 5209 idx += sizeof(struct displayid_hdr); 5210 while (block = (struct displayid_block *)&displayid[idx], 5211 idx + sizeof(struct displayid_block) <= length && 5212 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 5213 block->num_bytes > 0) { 5214 idx += block->num_bytes + sizeof(struct displayid_block); 5215 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5216 block->tag, block->rev, block->num_bytes); 5217 5218 switch (block->tag) { 5219 case DATA_BLOCK_TILED_DISPLAY: 5220 ret = drm_parse_tiled_block(connector, block); 5221 if (ret) 5222 return ret; 5223 break; 5224 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5225 /* handled in mode gathering code. */ 5226 break; 5227 default: 5228 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5229 break; 5230 } 5231 } 5232 return 0; 5233} 5234 5235static void drm_get_displayid(struct drm_connector *connector, 5236 struct edid *edid) 5237{ 5238 void *displayid = NULL; 5239 int ret; 5240 connector->has_tile = false; 5241 displayid = drm_find_displayid_extension(edid); 5242 if (!displayid) { 5243 /* drop reference to any tile group we had */ 5244 goto out_drop_ref; 5245 } 5246 5247 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5248 if (ret < 0) 5249 goto out_drop_ref; 5250 if (!connector->has_tile) 5251 goto out_drop_ref; 5252 return; 5253out_drop_ref: 5254 if (connector->tile_group) { 5255 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5256 connector->tile_group = NULL; 5257 } 5258 return; 5259} 5260