drm_edid.c revision 1.19
1/* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30#include <linux/kernel.h> 31#include <linux/slab.h> 32#include <linux/hdmi.h> 33#include <linux/i2c.h> 34#include <linux/module.h> 35#include <linux/vga_switcheroo.h> 36#include <drm/drmP.h> 37#include <drm/drm_edid.h> 38#include <drm/drm_encoder.h> 39#include <drm/drm_displayid.h> 40#include <drm/drm_scdc_helper.h> 41 42#include "drm_crtc_internal.h" 43 44#define version_greater(edid, maj, min) \ 45 (((edid)->version > (maj)) || \ 46 ((edid)->version == (maj) && (edid)->revision > (min))) 47 48#define EDID_EST_TIMINGS 16 49#define EDID_STD_TIMINGS 8 50#define EDID_DETAILED_TIMINGS 4 51 52/* 53 * EDID blocks out in the wild have a variety of bugs, try to collect 54 * them here (note that userspace may work around broken monitors first, 55 * but fixes should make their way here so that the kernel "just works" 56 * on as many displays as possible). 57 */ 58 59/* First detailed mode wrong, use largest 60Hz mode */ 60#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 61/* Reported 135MHz pixel clock is too high, needs adjustment */ 62#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 63/* Prefer the largest mode at 75 Hz */ 64#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 65/* Detail timing is in cm not mm */ 66#define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 67/* Detailed timing descriptors have bogus size values, so just take the 68 * maximum size and use that. 69 */ 70#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 71/* Monitor forgot to set the first detailed is preferred bit. */ 72#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 73/* use +hsync +vsync for detailed mode */ 74#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 75/* Force reduced-blanking timings for detailed modes */ 76#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 77/* Force 8bpc */ 78#define EDID_QUIRK_FORCE_8BPC (1 << 8) 79/* Force 12bpc */ 80#define EDID_QUIRK_FORCE_12BPC (1 << 9) 81/* Force 6bpc */ 82#define EDID_QUIRK_FORCE_6BPC (1 << 10) 83/* Force 10bpc */ 84#define EDID_QUIRK_FORCE_10BPC (1 << 11) 85/* Non desktop display (i.e. HMD) */ 86#define EDID_QUIRK_NON_DESKTOP (1 << 12) 87 88struct detailed_mode_closure { 89 struct drm_connector *connector; 90 struct edid *edid; 91 bool preferred; 92 u32 quirks; 93 int modes; 94}; 95 96#define LEVEL_DMT 0 97#define LEVEL_GTF 1 98#define LEVEL_GTF2 2 99#define LEVEL_CVT 3 100 101static const struct edid_quirk { 102 char vendor[4]; 103 int product_id; 104 u32 quirks; 105} edid_quirk_list[] = { 106 /* Acer AL1706 */ 107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 108 /* Acer F51 */ 109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 110 /* Unknown Acer */ 111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 112 113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 115 116 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 117 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 118 119 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 120 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 121 122 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 123 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 124 125 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 126 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 127 128 /* Belinea 10 15 55 */ 129 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 130 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 131 132 /* Envision Peripherals, Inc. EN-7100e */ 133 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 134 /* Envision EN2028 */ 135 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 136 137 /* Funai Electronics PM36B */ 138 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 139 EDID_QUIRK_DETAILED_IN_CM }, 140 141 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 142 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 143 144 /* LG Philips LCD LP154W01-A5 */ 145 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 147 148 /* Philips 107p5 CRT */ 149 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 150 151 /* Proview AY765C */ 152 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 153 154 /* Samsung SyncMaster 205BW. Note: irony */ 155 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 156 /* Samsung SyncMaster 22[5-6]BW */ 157 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 158 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 159 160 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 161 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 162 163 /* ViewSonic VA2026w */ 164 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 165 166 /* Medion MD 30217 PG */ 167 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 168 169 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 170 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 171 172 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 173 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 174 175 /* HTC Vive and Vive Pro VR Headsets */ 176 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 177 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 178 179 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ 180 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 181 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 182 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 183 184 /* Windows Mixed Reality Headsets */ 185 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 186 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 187 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 188 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 189 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 190 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 191 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 192 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 193 194 /* Sony PlayStation VR Headset */ 195 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 196}; 197 198/* 199 * Autogenerated from the DMT spec. 200 * This table is copied from xfree86/modes/xf86EdidModes.c. 201 */ 202static const struct drm_display_mode drm_dmt_modes[] = { 203 /* 0x01 - 640x350@85Hz */ 204 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 205 736, 832, 0, 350, 382, 385, 445, 0, 206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 207 /* 0x02 - 640x400@85Hz */ 208 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 209 736, 832, 0, 400, 401, 404, 445, 0, 210 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 211 /* 0x03 - 720x400@85Hz */ 212 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 213 828, 936, 0, 400, 401, 404, 446, 0, 214 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 215 /* 0x04 - 640x480@60Hz */ 216 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 217 752, 800, 0, 480, 490, 492, 525, 0, 218 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 219 /* 0x05 - 640x480@72Hz */ 220 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 221 704, 832, 0, 480, 489, 492, 520, 0, 222 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 223 /* 0x06 - 640x480@75Hz */ 224 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 225 720, 840, 0, 480, 481, 484, 500, 0, 226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 227 /* 0x07 - 640x480@85Hz */ 228 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 229 752, 832, 0, 480, 481, 484, 509, 0, 230 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 231 /* 0x08 - 800x600@56Hz */ 232 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 233 896, 1024, 0, 600, 601, 603, 625, 0, 234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 235 /* 0x09 - 800x600@60Hz */ 236 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 237 968, 1056, 0, 600, 601, 605, 628, 0, 238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 239 /* 0x0a - 800x600@72Hz */ 240 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 241 976, 1040, 0, 600, 637, 643, 666, 0, 242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 243 /* 0x0b - 800x600@75Hz */ 244 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 245 896, 1056, 0, 600, 601, 604, 625, 0, 246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 247 /* 0x0c - 800x600@85Hz */ 248 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 249 896, 1048, 0, 600, 601, 604, 631, 0, 250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 251 /* 0x0d - 800x600@120Hz RB */ 252 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 253 880, 960, 0, 600, 603, 607, 636, 0, 254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 255 /* 0x0e - 848x480@60Hz */ 256 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 257 976, 1088, 0, 480, 486, 494, 517, 0, 258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 259 /* 0x0f - 1024x768@43Hz, interlace */ 260 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 261 1208, 1264, 0, 768, 768, 776, 817, 0, 262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 263 DRM_MODE_FLAG_INTERLACE) }, 264 /* 0x10 - 1024x768@60Hz */ 265 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 266 1184, 1344, 0, 768, 771, 777, 806, 0, 267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 268 /* 0x11 - 1024x768@70Hz */ 269 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 270 1184, 1328, 0, 768, 771, 777, 806, 0, 271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 272 /* 0x12 - 1024x768@75Hz */ 273 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 274 1136, 1312, 0, 768, 769, 772, 800, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 276 /* 0x13 - 1024x768@85Hz */ 277 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 278 1168, 1376, 0, 768, 769, 772, 808, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x14 - 1024x768@120Hz RB */ 281 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 282 1104, 1184, 0, 768, 771, 775, 813, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 284 /* 0x15 - 1152x864@75Hz */ 285 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 286 1344, 1600, 0, 864, 865, 868, 900, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 288 /* 0x55 - 1280x720@60Hz */ 289 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 290 1430, 1650, 0, 720, 725, 730, 750, 0, 291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 292 /* 0x16 - 1280x768@60Hz RB */ 293 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 294 1360, 1440, 0, 768, 771, 778, 790, 0, 295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 296 /* 0x17 - 1280x768@60Hz */ 297 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 298 1472, 1664, 0, 768, 771, 778, 798, 0, 299 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 300 /* 0x18 - 1280x768@75Hz */ 301 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 302 1488, 1696, 0, 768, 771, 778, 805, 0, 303 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 304 /* 0x19 - 1280x768@85Hz */ 305 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 306 1496, 1712, 0, 768, 771, 778, 809, 0, 307 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 308 /* 0x1a - 1280x768@120Hz RB */ 309 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 310 1360, 1440, 0, 768, 771, 778, 813, 0, 311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 312 /* 0x1b - 1280x800@60Hz RB */ 313 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 314 1360, 1440, 0, 800, 803, 809, 823, 0, 315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 316 /* 0x1c - 1280x800@60Hz */ 317 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 318 1480, 1680, 0, 800, 803, 809, 831, 0, 319 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 320 /* 0x1d - 1280x800@75Hz */ 321 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 322 1488, 1696, 0, 800, 803, 809, 838, 0, 323 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 324 /* 0x1e - 1280x800@85Hz */ 325 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 326 1496, 1712, 0, 800, 803, 809, 843, 0, 327 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 328 /* 0x1f - 1280x800@120Hz RB */ 329 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 330 1360, 1440, 0, 800, 803, 809, 847, 0, 331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 332 /* 0x20 - 1280x960@60Hz */ 333 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 334 1488, 1800, 0, 960, 961, 964, 1000, 0, 335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 336 /* 0x21 - 1280x960@85Hz */ 337 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 338 1504, 1728, 0, 960, 961, 964, 1011, 0, 339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 340 /* 0x22 - 1280x960@120Hz RB */ 341 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 342 1360, 1440, 0, 960, 963, 967, 1017, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 344 /* 0x23 - 1280x1024@60Hz */ 345 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 346 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 348 /* 0x24 - 1280x1024@75Hz */ 349 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 350 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 352 /* 0x25 - 1280x1024@85Hz */ 353 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 354 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 356 /* 0x26 - 1280x1024@120Hz RB */ 357 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 358 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 360 /* 0x27 - 1360x768@60Hz */ 361 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 362 1536, 1792, 0, 768, 771, 777, 795, 0, 363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 364 /* 0x28 - 1360x768@120Hz RB */ 365 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 366 1440, 1520, 0, 768, 771, 776, 813, 0, 367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 368 /* 0x51 - 1366x768@60Hz */ 369 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 370 1579, 1792, 0, 768, 771, 774, 798, 0, 371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 372 /* 0x56 - 1366x768@60Hz */ 373 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 374 1436, 1500, 0, 768, 769, 772, 800, 0, 375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 376 /* 0x29 - 1400x1050@60Hz RB */ 377 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 378 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 380 /* 0x2a - 1400x1050@60Hz */ 381 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 382 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 384 /* 0x2b - 1400x1050@75Hz */ 385 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 386 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 387 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 388 /* 0x2c - 1400x1050@85Hz */ 389 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 390 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 391 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 392 /* 0x2d - 1400x1050@120Hz RB */ 393 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 394 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 396 /* 0x2e - 1440x900@60Hz RB */ 397 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 398 1520, 1600, 0, 900, 903, 909, 926, 0, 399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 400 /* 0x2f - 1440x900@60Hz */ 401 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 402 1672, 1904, 0, 900, 903, 909, 934, 0, 403 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 404 /* 0x30 - 1440x900@75Hz */ 405 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 406 1688, 1936, 0, 900, 903, 909, 942, 0, 407 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 408 /* 0x31 - 1440x900@85Hz */ 409 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 410 1696, 1952, 0, 900, 903, 909, 948, 0, 411 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 412 /* 0x32 - 1440x900@120Hz RB */ 413 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 414 1520, 1600, 0, 900, 903, 909, 953, 0, 415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 416 /* 0x53 - 1600x900@60Hz */ 417 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 418 1704, 1800, 0, 900, 901, 904, 1000, 0, 419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 420 /* 0x33 - 1600x1200@60Hz */ 421 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 422 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 424 /* 0x34 - 1600x1200@65Hz */ 425 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 426 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 428 /* 0x35 - 1600x1200@70Hz */ 429 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 430 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 432 /* 0x36 - 1600x1200@75Hz */ 433 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 434 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 436 /* 0x37 - 1600x1200@85Hz */ 437 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 438 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 440 /* 0x38 - 1600x1200@120Hz RB */ 441 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 442 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 444 /* 0x39 - 1680x1050@60Hz RB */ 445 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 446 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 448 /* 0x3a - 1680x1050@60Hz */ 449 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 450 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 452 /* 0x3b - 1680x1050@75Hz */ 453 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 454 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 456 /* 0x3c - 1680x1050@85Hz */ 457 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 458 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 459 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 460 /* 0x3d - 1680x1050@120Hz RB */ 461 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 462 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 464 /* 0x3e - 1792x1344@60Hz */ 465 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 466 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 468 /* 0x3f - 1792x1344@75Hz */ 469 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 470 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 471 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 472 /* 0x40 - 1792x1344@120Hz RB */ 473 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 474 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 476 /* 0x41 - 1856x1392@60Hz */ 477 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 478 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 480 /* 0x42 - 1856x1392@75Hz */ 481 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 482 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 483 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 484 /* 0x43 - 1856x1392@120Hz RB */ 485 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 486 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 488 /* 0x52 - 1920x1080@60Hz */ 489 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 490 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 492 /* 0x44 - 1920x1200@60Hz RB */ 493 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 494 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 496 /* 0x45 - 1920x1200@60Hz */ 497 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 498 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 500 /* 0x46 - 1920x1200@75Hz */ 501 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 502 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 504 /* 0x47 - 1920x1200@85Hz */ 505 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 506 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 507 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 508 /* 0x48 - 1920x1200@120Hz RB */ 509 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 510 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 512 /* 0x49 - 1920x1440@60Hz */ 513 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 514 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 516 /* 0x4a - 1920x1440@75Hz */ 517 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 518 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 519 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 520 /* 0x4b - 1920x1440@120Hz RB */ 521 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 522 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 524 /* 0x54 - 2048x1152@60Hz */ 525 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 526 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 528 /* 0x4c - 2560x1600@60Hz RB */ 529 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 530 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 532 /* 0x4d - 2560x1600@60Hz */ 533 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 534 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 536 /* 0x4e - 2560x1600@75Hz */ 537 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 538 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 539 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 540 /* 0x4f - 2560x1600@85Hz */ 541 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 542 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 544 /* 0x50 - 2560x1600@120Hz RB */ 545 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 546 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 548 /* 0x57 - 4096x2160@60Hz RB */ 549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 550 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 552 /* 0x58 - 4096x2160@59.94Hz RB */ 553 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 554 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 556}; 557 558/* 559 * These more or less come from the DMT spec. The 720x400 modes are 560 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 561 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 562 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 563 * mode. 564 * 565 * The DMT modes have been fact-checked; the rest are mild guesses. 566 */ 567static const struct drm_display_mode edid_est_modes[] = { 568 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 569 968, 1056, 0, 600, 601, 605, 628, 0, 570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 571 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 572 896, 1024, 0, 600, 601, 603, 625, 0, 573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 574 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 575 720, 840, 0, 480, 481, 484, 500, 0, 576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 577 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 578 704, 832, 0, 480, 489, 492, 520, 0, 579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 580 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 581 768, 864, 0, 480, 483, 486, 525, 0, 582 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 583 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 584 752, 800, 0, 480, 490, 492, 525, 0, 585 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 586 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 587 846, 900, 0, 400, 421, 423, 449, 0, 588 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 589 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 590 846, 900, 0, 400, 412, 414, 449, 0, 591 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 592 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 593 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 595 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 596 1136, 1312, 0, 768, 769, 772, 800, 0, 597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 598 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 599 1184, 1328, 0, 768, 771, 777, 806, 0, 600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 601 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 602 1184, 1344, 0, 768, 771, 777, 806, 0, 603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 604 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 605 1208, 1264, 0, 768, 768, 776, 817, 0, 606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 607 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 608 928, 1152, 0, 624, 625, 628, 667, 0, 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 610 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 611 896, 1056, 0, 600, 601, 604, 625, 0, 612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 613 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 614 976, 1040, 0, 600, 637, 643, 666, 0, 615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 616 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 617 1344, 1600, 0, 864, 865, 868, 900, 0, 618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 619}; 620 621struct minimode { 622 short w; 623 short h; 624 short r; 625 short rb; 626}; 627 628static const struct minimode est3_modes[] = { 629 /* byte 6 */ 630 { 640, 350, 85, 0 }, 631 { 640, 400, 85, 0 }, 632 { 720, 400, 85, 0 }, 633 { 640, 480, 85, 0 }, 634 { 848, 480, 60, 0 }, 635 { 800, 600, 85, 0 }, 636 { 1024, 768, 85, 0 }, 637 { 1152, 864, 75, 0 }, 638 /* byte 7 */ 639 { 1280, 768, 60, 1 }, 640 { 1280, 768, 60, 0 }, 641 { 1280, 768, 75, 0 }, 642 { 1280, 768, 85, 0 }, 643 { 1280, 960, 60, 0 }, 644 { 1280, 960, 85, 0 }, 645 { 1280, 1024, 60, 0 }, 646 { 1280, 1024, 85, 0 }, 647 /* byte 8 */ 648 { 1360, 768, 60, 0 }, 649 { 1440, 900, 60, 1 }, 650 { 1440, 900, 60, 0 }, 651 { 1440, 900, 75, 0 }, 652 { 1440, 900, 85, 0 }, 653 { 1400, 1050, 60, 1 }, 654 { 1400, 1050, 60, 0 }, 655 { 1400, 1050, 75, 0 }, 656 /* byte 9 */ 657 { 1400, 1050, 85, 0 }, 658 { 1680, 1050, 60, 1 }, 659 { 1680, 1050, 60, 0 }, 660 { 1680, 1050, 75, 0 }, 661 { 1680, 1050, 85, 0 }, 662 { 1600, 1200, 60, 0 }, 663 { 1600, 1200, 65, 0 }, 664 { 1600, 1200, 70, 0 }, 665 /* byte 10 */ 666 { 1600, 1200, 75, 0 }, 667 { 1600, 1200, 85, 0 }, 668 { 1792, 1344, 60, 0 }, 669 { 1792, 1344, 75, 0 }, 670 { 1856, 1392, 60, 0 }, 671 { 1856, 1392, 75, 0 }, 672 { 1920, 1200, 60, 1 }, 673 { 1920, 1200, 60, 0 }, 674 /* byte 11 */ 675 { 1920, 1200, 75, 0 }, 676 { 1920, 1200, 85, 0 }, 677 { 1920, 1440, 60, 0 }, 678 { 1920, 1440, 75, 0 }, 679}; 680 681static const struct minimode extra_modes[] = { 682 { 1024, 576, 60, 0 }, 683 { 1366, 768, 60, 0 }, 684 { 1600, 900, 60, 0 }, 685 { 1680, 945, 60, 0 }, 686 { 1920, 1080, 60, 0 }, 687 { 2048, 1152, 60, 0 }, 688 { 2048, 1536, 60, 0 }, 689}; 690 691/* 692 * Probably taken from CEA-861 spec. 693 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 694 * 695 * Index using the VIC. 696 */ 697static const struct drm_display_mode edid_cea_modes[] = { 698 /* 0 - dummy, VICs start at 1 */ 699 { }, 700 /* 1 - 640x480@60Hz 4:3 */ 701 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 702 752, 800, 0, 480, 490, 492, 525, 0, 703 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 704 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 705 /* 2 - 720x480@60Hz 4:3 */ 706 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 707 798, 858, 0, 480, 489, 495, 525, 0, 708 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 710 /* 3 - 720x480@60Hz 16:9 */ 711 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 712 798, 858, 0, 480, 489, 495, 525, 0, 713 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 714 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 715 /* 4 - 1280x720@60Hz 16:9 */ 716 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 717 1430, 1650, 0, 720, 725, 730, 750, 0, 718 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 719 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 720 /* 5 - 1920x1080i@60Hz 16:9 */ 721 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 722 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 723 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 724 DRM_MODE_FLAG_INTERLACE), 725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 726 /* 6 - 720(1440)x480i@60Hz 4:3 */ 727 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 728 801, 858, 0, 480, 488, 494, 525, 0, 729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 730 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 731 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 732 /* 7 - 720(1440)x480i@60Hz 16:9 */ 733 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 734 801, 858, 0, 480, 488, 494, 525, 0, 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 736 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 738 /* 8 - 720(1440)x240@60Hz 4:3 */ 739 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 740 801, 858, 0, 240, 244, 247, 262, 0, 741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 742 DRM_MODE_FLAG_DBLCLK), 743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 744 /* 9 - 720(1440)x240@60Hz 16:9 */ 745 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 746 801, 858, 0, 240, 244, 247, 262, 0, 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 748 DRM_MODE_FLAG_DBLCLK), 749 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 750 /* 10 - 2880x480i@60Hz 4:3 */ 751 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 752 3204, 3432, 0, 480, 488, 494, 525, 0, 753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 754 DRM_MODE_FLAG_INTERLACE), 755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 756 /* 11 - 2880x480i@60Hz 16:9 */ 757 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 758 3204, 3432, 0, 480, 488, 494, 525, 0, 759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 760 DRM_MODE_FLAG_INTERLACE), 761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 762 /* 12 - 2880x240@60Hz 4:3 */ 763 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 764 3204, 3432, 0, 240, 244, 247, 262, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 766 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 767 /* 13 - 2880x240@60Hz 16:9 */ 768 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 769 3204, 3432, 0, 240, 244, 247, 262, 0, 770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 771 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 772 /* 14 - 1440x480@60Hz 4:3 */ 773 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 774 1596, 1716, 0, 480, 489, 495, 525, 0, 775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 776 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 777 /* 15 - 1440x480@60Hz 16:9 */ 778 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 779 1596, 1716, 0, 480, 489, 495, 525, 0, 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 781 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 782 /* 16 - 1920x1080@60Hz 16:9 */ 783 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 784 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 785 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 786 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 787 /* 17 - 720x576@50Hz 4:3 */ 788 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 789 796, 864, 0, 576, 581, 586, 625, 0, 790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 792 /* 18 - 720x576@50Hz 16:9 */ 793 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 794 796, 864, 0, 576, 581, 586, 625, 0, 795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 796 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 797 /* 19 - 1280x720@50Hz 16:9 */ 798 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 799 1760, 1980, 0, 720, 725, 730, 750, 0, 800 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 801 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 802 /* 20 - 1920x1080i@50Hz 16:9 */ 803 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 804 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 806 DRM_MODE_FLAG_INTERLACE), 807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 808 /* 21 - 720(1440)x576i@50Hz 4:3 */ 809 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 810 795, 864, 0, 576, 580, 586, 625, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 812 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 814 /* 22 - 720(1440)x576i@50Hz 16:9 */ 815 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 816 795, 864, 0, 576, 580, 586, 625, 0, 817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 818 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 820 /* 23 - 720(1440)x288@50Hz 4:3 */ 821 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 822 795, 864, 0, 288, 290, 293, 312, 0, 823 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 824 DRM_MODE_FLAG_DBLCLK), 825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 826 /* 24 - 720(1440)x288@50Hz 16:9 */ 827 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 828 795, 864, 0, 288, 290, 293, 312, 0, 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 830 DRM_MODE_FLAG_DBLCLK), 831 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 832 /* 25 - 2880x576i@50Hz 4:3 */ 833 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 834 3180, 3456, 0, 576, 580, 586, 625, 0, 835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 836 DRM_MODE_FLAG_INTERLACE), 837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 838 /* 26 - 2880x576i@50Hz 16:9 */ 839 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 840 3180, 3456, 0, 576, 580, 586, 625, 0, 841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 842 DRM_MODE_FLAG_INTERLACE), 843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 844 /* 27 - 2880x288@50Hz 4:3 */ 845 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 846 3180, 3456, 0, 288, 290, 293, 312, 0, 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 848 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 849 /* 28 - 2880x288@50Hz 16:9 */ 850 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 851 3180, 3456, 0, 288, 290, 293, 312, 0, 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 853 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 854 /* 29 - 1440x576@50Hz 4:3 */ 855 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 856 1592, 1728, 0, 576, 581, 586, 625, 0, 857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 859 /* 30 - 1440x576@50Hz 16:9 */ 860 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 861 1592, 1728, 0, 576, 581, 586, 625, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 863 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 864 /* 31 - 1920x1080@50Hz 16:9 */ 865 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 866 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 868 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 869 /* 32 - 1920x1080@24Hz 16:9 */ 870 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 871 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 873 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 874 /* 33 - 1920x1080@25Hz 16:9 */ 875 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 876 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 878 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 879 /* 34 - 1920x1080@30Hz 16:9 */ 880 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 881 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 883 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 884 /* 35 - 2880x480@60Hz 4:3 */ 885 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 886 3192, 3432, 0, 480, 489, 495, 525, 0, 887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 888 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 889 /* 36 - 2880x480@60Hz 16:9 */ 890 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 891 3192, 3432, 0, 480, 489, 495, 525, 0, 892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 893 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 894 /* 37 - 2880x576@50Hz 4:3 */ 895 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 896 3184, 3456, 0, 576, 581, 586, 625, 0, 897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 898 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 899 /* 38 - 2880x576@50Hz 16:9 */ 900 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 901 3184, 3456, 0, 576, 581, 586, 625, 0, 902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 903 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 904 /* 39 - 1920x1080i@50Hz 16:9 */ 905 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 906 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 908 DRM_MODE_FLAG_INTERLACE), 909 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 910 /* 40 - 1920x1080i@100Hz 16:9 */ 911 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 912 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 914 DRM_MODE_FLAG_INTERLACE), 915 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 916 /* 41 - 1280x720@100Hz 16:9 */ 917 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 918 1760, 1980, 0, 720, 725, 730, 750, 0, 919 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 920 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 921 /* 42 - 720x576@100Hz 4:3 */ 922 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 923 796, 864, 0, 576, 581, 586, 625, 0, 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 925 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 926 /* 43 - 720x576@100Hz 16:9 */ 927 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 928 796, 864, 0, 576, 581, 586, 625, 0, 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 930 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 931 /* 44 - 720(1440)x576i@100Hz 4:3 */ 932 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 933 795, 864, 0, 576, 580, 586, 625, 0, 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 935 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 936 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 937 /* 45 - 720(1440)x576i@100Hz 16:9 */ 938 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 939 795, 864, 0, 576, 580, 586, 625, 0, 940 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 941 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 942 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 943 /* 46 - 1920x1080i@120Hz 16:9 */ 944 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 945 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 947 DRM_MODE_FLAG_INTERLACE), 948 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 949 /* 47 - 1280x720@120Hz 16:9 */ 950 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 951 1430, 1650, 0, 720, 725, 730, 750, 0, 952 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 953 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 954 /* 48 - 720x480@120Hz 4:3 */ 955 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 956 798, 858, 0, 480, 489, 495, 525, 0, 957 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 958 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 959 /* 49 - 720x480@120Hz 16:9 */ 960 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 961 798, 858, 0, 480, 489, 495, 525, 0, 962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 963 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 964 /* 50 - 720(1440)x480i@120Hz 4:3 */ 965 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 966 801, 858, 0, 480, 488, 494, 525, 0, 967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 969 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 970 /* 51 - 720(1440)x480i@120Hz 16:9 */ 971 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 972 801, 858, 0, 480, 488, 494, 525, 0, 973 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 974 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 975 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 976 /* 52 - 720x576@200Hz 4:3 */ 977 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 978 796, 864, 0, 576, 581, 586, 625, 0, 979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 980 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 981 /* 53 - 720x576@200Hz 16:9 */ 982 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 983 796, 864, 0, 576, 581, 586, 625, 0, 984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 985 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 986 /* 54 - 720(1440)x576i@200Hz 4:3 */ 987 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 988 795, 864, 0, 576, 580, 586, 625, 0, 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 990 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 991 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 992 /* 55 - 720(1440)x576i@200Hz 16:9 */ 993 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 994 795, 864, 0, 576, 580, 586, 625, 0, 995 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 996 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 997 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 998 /* 56 - 720x480@240Hz 4:3 */ 999 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1000 798, 858, 0, 480, 489, 495, 525, 0, 1001 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1002 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1003 /* 57 - 720x480@240Hz 16:9 */ 1004 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1005 798, 858, 0, 480, 489, 495, 525, 0, 1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1007 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1008 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1009 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1010 801, 858, 0, 480, 488, 494, 525, 0, 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1012 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1013 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1014 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1015 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1016 801, 858, 0, 480, 488, 494, 525, 0, 1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1018 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1019 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1020 /* 60 - 1280x720@24Hz 16:9 */ 1021 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1022 3080, 3300, 0, 720, 725, 730, 750, 0, 1023 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1024 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1025 /* 61 - 1280x720@25Hz 16:9 */ 1026 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1027 3740, 3960, 0, 720, 725, 730, 750, 0, 1028 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1029 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1030 /* 62 - 1280x720@30Hz 16:9 */ 1031 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1032 3080, 3300, 0, 720, 725, 730, 750, 0, 1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1034 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1035 /* 63 - 1920x1080@120Hz 16:9 */ 1036 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1037 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1038 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1039 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1040 /* 64 - 1920x1080@100Hz 16:9 */ 1041 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1042 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1044 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1045 /* 65 - 1280x720@24Hz 64:27 */ 1046 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1047 3080, 3300, 0, 720, 725, 730, 750, 0, 1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1049 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1050 /* 66 - 1280x720@25Hz 64:27 */ 1051 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1052 3740, 3960, 0, 720, 725, 730, 750, 0, 1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1054 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1055 /* 67 - 1280x720@30Hz 64:27 */ 1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1057 3080, 3300, 0, 720, 725, 730, 750, 0, 1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1059 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1060 /* 68 - 1280x720@50Hz 64:27 */ 1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1062 1760, 1980, 0, 720, 725, 730, 750, 0, 1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1064 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1065 /* 69 - 1280x720@60Hz 64:27 */ 1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1067 1430, 1650, 0, 720, 725, 730, 750, 0, 1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1069 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1070 /* 70 - 1280x720@100Hz 64:27 */ 1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1072 1760, 1980, 0, 720, 725, 730, 750, 0, 1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1074 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1075 /* 71 - 1280x720@120Hz 64:27 */ 1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1077 1430, 1650, 0, 720, 725, 730, 750, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1079 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1080 /* 72 - 1920x1080@24Hz 64:27 */ 1081 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1082 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1084 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1085 /* 73 - 1920x1080@25Hz 64:27 */ 1086 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1087 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1089 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1090 /* 74 - 1920x1080@30Hz 64:27 */ 1091 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1092 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1094 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1095 /* 75 - 1920x1080@50Hz 64:27 */ 1096 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1097 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1099 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1100 /* 76 - 1920x1080@60Hz 64:27 */ 1101 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1102 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1104 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1105 /* 77 - 1920x1080@100Hz 64:27 */ 1106 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1107 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1109 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1110 /* 78 - 1920x1080@120Hz 64:27 */ 1111 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1112 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1114 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1115 /* 79 - 1680x720@24Hz 64:27 */ 1116 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1117 3080, 3300, 0, 720, 725, 730, 750, 0, 1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1119 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1120 /* 80 - 1680x720@25Hz 64:27 */ 1121 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1122 2948, 3168, 0, 720, 725, 730, 750, 0, 1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1124 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1125 /* 81 - 1680x720@30Hz 64:27 */ 1126 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1127 2420, 2640, 0, 720, 725, 730, 750, 0, 1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1129 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1130 /* 82 - 1680x720@50Hz 64:27 */ 1131 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1132 1980, 2200, 0, 720, 725, 730, 750, 0, 1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1134 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1135 /* 83 - 1680x720@60Hz 64:27 */ 1136 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1137 1980, 2200, 0, 720, 725, 730, 750, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1139 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1140 /* 84 - 1680x720@100Hz 64:27 */ 1141 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1142 1780, 2000, 0, 720, 725, 730, 825, 0, 1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1144 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1145 /* 85 - 1680x720@120Hz 64:27 */ 1146 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1147 1780, 2000, 0, 720, 725, 730, 825, 0, 1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1149 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1150 /* 86 - 2560x1080@24Hz 64:27 */ 1151 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1152 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1154 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1155 /* 87 - 2560x1080@25Hz 64:27 */ 1156 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1157 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1159 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1160 /* 88 - 2560x1080@30Hz 64:27 */ 1161 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1162 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1164 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1165 /* 89 - 2560x1080@50Hz 64:27 */ 1166 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1167 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1169 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1170 /* 90 - 2560x1080@60Hz 64:27 */ 1171 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1172 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1174 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1175 /* 91 - 2560x1080@100Hz 64:27 */ 1176 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1177 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1179 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1180 /* 92 - 2560x1080@120Hz 64:27 */ 1181 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1182 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1184 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1185 /* 93 - 3840x2160@24Hz 16:9 */ 1186 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1187 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1189 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1190 /* 94 - 3840x2160@25Hz 16:9 */ 1191 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1192 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1194 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1195 /* 95 - 3840x2160@30Hz 16:9 */ 1196 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1197 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1199 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1200 /* 96 - 3840x2160@50Hz 16:9 */ 1201 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1202 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1204 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1205 /* 97 - 3840x2160@60Hz 16:9 */ 1206 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1207 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1209 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1210 /* 98 - 4096x2160@24Hz 256:135 */ 1211 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1212 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1214 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1215 /* 99 - 4096x2160@25Hz 256:135 */ 1216 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1217 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1219 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1220 /* 100 - 4096x2160@30Hz 256:135 */ 1221 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1222 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1224 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1225 /* 101 - 4096x2160@50Hz 256:135 */ 1226 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1227 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1229 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1230 /* 102 - 4096x2160@60Hz 256:135 */ 1231 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1232 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1234 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1235 /* 103 - 3840x2160@24Hz 64:27 */ 1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1237 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1239 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1240 /* 104 - 3840x2160@25Hz 64:27 */ 1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1242 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1244 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1245 /* 105 - 3840x2160@30Hz 64:27 */ 1246 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1247 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1249 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1250 /* 106 - 3840x2160@50Hz 64:27 */ 1251 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1252 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1254 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1255 /* 107 - 3840x2160@60Hz 64:27 */ 1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1257 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1259 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1260}; 1261 1262/* 1263 * HDMI 1.4 4k modes. Index using the VIC. 1264 */ 1265static const struct drm_display_mode edid_4k_modes[] = { 1266 /* 0 - dummy, VICs start at 1 */ 1267 { }, 1268 /* 1 - 3840x2160@30Hz */ 1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1270 3840, 4016, 4104, 4400, 0, 1271 2160, 2168, 2178, 2250, 0, 1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1273 .vrefresh = 30, }, 1274 /* 2 - 3840x2160@25Hz */ 1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1276 3840, 4896, 4984, 5280, 0, 1277 2160, 2168, 2178, 2250, 0, 1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1279 .vrefresh = 25, }, 1280 /* 3 - 3840x2160@24Hz */ 1281 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1282 3840, 5116, 5204, 5500, 0, 1283 2160, 2168, 2178, 2250, 0, 1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1285 .vrefresh = 24, }, 1286 /* 4 - 4096x2160@24Hz (SMPTE) */ 1287 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1288 4096, 5116, 5204, 5500, 0, 1289 2160, 2168, 2178, 2250, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1291 .vrefresh = 24, }, 1292}; 1293 1294/*** DDC fetch and block validation ***/ 1295 1296static const u8 edid_header[] = { 1297 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1298}; 1299 1300/** 1301 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1302 * @raw_edid: pointer to raw base EDID block 1303 * 1304 * Sanity check the header of the base EDID block. 1305 * 1306 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1307 */ 1308int drm_edid_header_is_valid(const u8 *raw_edid) 1309{ 1310 int i, score = 0; 1311 1312 for (i = 0; i < sizeof(edid_header); i++) 1313 if (raw_edid[i] == edid_header[i]) 1314 score++; 1315 1316 return score; 1317} 1318EXPORT_SYMBOL(drm_edid_header_is_valid); 1319 1320static int edid_fixup __read_mostly = 6; 1321module_param_named(edid_fixup, edid_fixup, int, 0400); 1322MODULE_PARM_DESC(edid_fixup, 1323 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1324 1325static void drm_get_displayid(struct drm_connector *connector, 1326 struct edid *edid); 1327 1328static int drm_edid_block_checksum(const u8 *raw_edid) 1329{ 1330 int i; 1331 u8 csum = 0; 1332 for (i = 0; i < EDID_LENGTH; i++) 1333 csum += raw_edid[i]; 1334 1335 return csum; 1336} 1337 1338static bool drm_edid_is_zero(const u8 *in_edid, int length) 1339{ 1340 if (memchr_inv(in_edid, 0, length)) 1341 return false; 1342 1343 return true; 1344} 1345 1346/** 1347 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1348 * @raw_edid: pointer to raw EDID block 1349 * @block: type of block to validate (0 for base, extension otherwise) 1350 * @print_bad_edid: if true, dump bad EDID blocks to the console 1351 * @edid_corrupt: if true, the header or checksum is invalid 1352 * 1353 * Validate a base or extension EDID block and optionally dump bad blocks to 1354 * the console. 1355 * 1356 * Return: True if the block is valid, false otherwise. 1357 */ 1358bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1359 bool *edid_corrupt) 1360{ 1361 u8 csum; 1362 struct edid *edid = (struct edid *)raw_edid; 1363 1364 if (WARN_ON(!raw_edid)) 1365 return false; 1366 1367 if (edid_fixup > 8 || edid_fixup < 0) 1368 edid_fixup = 6; 1369 1370 if (block == 0) { 1371 int score = drm_edid_header_is_valid(raw_edid); 1372 if (score == 8) { 1373 if (edid_corrupt) 1374 *edid_corrupt = false; 1375 } else if (score >= edid_fixup) { 1376 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1377 * The corrupt flag needs to be set here otherwise, the 1378 * fix-up code here will correct the problem, the 1379 * checksum is correct and the test fails 1380 */ 1381 if (edid_corrupt) 1382 *edid_corrupt = true; 1383 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1384 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1385 } else { 1386 if (edid_corrupt) 1387 *edid_corrupt = true; 1388 goto bad; 1389 } 1390 } 1391 1392 csum = drm_edid_block_checksum(raw_edid); 1393 if (csum) { 1394 if (edid_corrupt) 1395 *edid_corrupt = true; 1396 1397 /* allow CEA to slide through, switches mangle this */ 1398 if (raw_edid[0] == CEA_EXT) { 1399 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1400 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1401 } else { 1402 if (print_bad_edid) 1403 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1404 1405 goto bad; 1406 } 1407 } 1408 1409 /* per-block-type checks */ 1410 switch (raw_edid[0]) { 1411 case 0: /* base */ 1412 if (edid->version != 1) { 1413 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1414 goto bad; 1415 } 1416 1417 if (edid->revision > 4) 1418 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1419 break; 1420 1421 default: 1422 break; 1423 } 1424 1425 return true; 1426 1427bad: 1428 if (print_bad_edid) { 1429 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1430 pr_notice("EDID block is all zeroes\n"); 1431 } else { 1432 pr_notice("Raw EDID:\n"); 1433 print_hex_dump(KERN_NOTICE, 1434 " \t", DUMP_PREFIX_NONE, 16, 1, 1435 raw_edid, EDID_LENGTH, false); 1436 } 1437 } 1438 return false; 1439} 1440EXPORT_SYMBOL(drm_edid_block_valid); 1441 1442/** 1443 * drm_edid_is_valid - sanity check EDID data 1444 * @edid: EDID data 1445 * 1446 * Sanity-check an entire EDID record (including extensions) 1447 * 1448 * Return: True if the EDID data is valid, false otherwise. 1449 */ 1450bool drm_edid_is_valid(struct edid *edid) 1451{ 1452 int i; 1453 u8 *raw = (u8 *)edid; 1454 1455 if (!edid) 1456 return false; 1457 1458 for (i = 0; i <= edid->extensions; i++) 1459 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1460 return false; 1461 1462 return true; 1463} 1464EXPORT_SYMBOL(drm_edid_is_valid); 1465 1466#define DDC_SEGMENT_ADDR 0x30 1467/** 1468 * drm_do_probe_ddc_edid() - get EDID information via I2C 1469 * @data: I2C device adapter 1470 * @buf: EDID data buffer to be filled 1471 * @block: 128 byte EDID block to start fetching from 1472 * @len: EDID data buffer length to fetch 1473 * 1474 * Try to fetch EDID information by calling I2C driver functions. 1475 * 1476 * Return: 0 on success or -1 on failure. 1477 */ 1478static int 1479drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1480{ 1481 struct i2c_adapter *adapter = data; 1482 unsigned char start = block * EDID_LENGTH; 1483 unsigned char segment = block >> 1; 1484 unsigned char xfers = segment ? 3 : 2; 1485 int ret, retries = 5; 1486 1487 /* 1488 * The core I2C driver will automatically retry the transfer if the 1489 * adapter reports EAGAIN. However, we find that bit-banging transfers 1490 * are susceptible to errors under a heavily loaded machine and 1491 * generate spurious NAKs and timeouts. Retrying the transfer 1492 * of the individual block a few times seems to overcome this. 1493 */ 1494 do { 1495 struct i2c_msg msgs[] = { 1496 { 1497 .addr = DDC_SEGMENT_ADDR, 1498 .flags = 0, 1499 .len = 1, 1500 .buf = &segment, 1501 }, { 1502 .addr = DDC_ADDR, 1503 .flags = 0, 1504 .len = 1, 1505 .buf = &start, 1506 }, { 1507 .addr = DDC_ADDR, 1508 .flags = I2C_M_RD, 1509 .len = len, 1510 .buf = buf, 1511 } 1512 }; 1513 1514 /* 1515 * Avoid sending the segment addr to not upset non-compliant 1516 * DDC monitors. 1517 */ 1518 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1519 1520 if (ret == -ENXIO) { 1521 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1522 adapter->name); 1523 break; 1524 } 1525 } while (ret != xfers && --retries); 1526 1527 return ret == xfers ? 0 : -1; 1528} 1529 1530static void connector_bad_edid(struct drm_connector *connector, 1531 u8 *edid, int num_blocks) 1532{ 1533 int i; 1534 1535 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS)) 1536 return; 1537 1538 dev_warn(connector->dev->dev, 1539 "%s: EDID is invalid:\n", 1540 connector->name); 1541 for (i = 0; i < num_blocks; i++) { 1542 u8 *block = edid + i * EDID_LENGTH; 1543 char prefix[20]; 1544 1545 if (drm_edid_is_zero(block, EDID_LENGTH)) 1546 snprintf(prefix, sizeof(prefix), "\t[%02x] ZERO ", i); 1547 else if (!drm_edid_block_valid(block, i, false, NULL)) 1548 snprintf(prefix, sizeof(prefix), "\t[%02x] BAD ", i); 1549 else 1550 snprintf(prefix, sizeof(prefix), "\t[%02x] GOOD ", i); 1551 1552 print_hex_dump(KERN_WARNING, 1553 prefix, DUMP_PREFIX_NONE, 16, 1, 1554 block, EDID_LENGTH, false); 1555 } 1556} 1557 1558/** 1559 * drm_do_get_edid - get EDID data using a custom EDID block read function 1560 * @connector: connector we're probing 1561 * @get_edid_block: EDID block read function 1562 * @data: private data passed to the block read function 1563 * 1564 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1565 * exposes a different interface to read EDID blocks this function can be used 1566 * to get EDID data using a custom block read function. 1567 * 1568 * As in the general case the DDC bus is accessible by the kernel at the I2C 1569 * level, drivers must make all reasonable efforts to expose it as an I2C 1570 * adapter and use drm_get_edid() instead of abusing this function. 1571 * 1572 * The EDID may be overridden using debugfs override_edid or firmare EDID 1573 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1574 * order. Having either of them bypasses actual EDID reads. 1575 * 1576 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1577 */ 1578struct edid *drm_do_get_edid(struct drm_connector *connector, 1579 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1580 size_t len), 1581 void *data) 1582{ 1583 int i, j = 0, valid_extensions = 0; 1584 u8 *edid, *new; 1585 struct edid *override = NULL; 1586 1587 if (connector->override_edid) 1588 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1589 1590 if (!override) 1591 override = drm_load_edid_firmware(connector); 1592 1593 if (!IS_ERR_OR_NULL(override)) 1594 return override; 1595 1596 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1597 return NULL; 1598 1599 /* base block fetch */ 1600 for (i = 0; i < 4; i++) { 1601 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1602 goto out; 1603 if (drm_edid_block_valid(edid, 0, false, 1604 &connector->edid_corrupt)) 1605 break; 1606 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1607 connector->null_edid_counter++; 1608 goto carp; 1609 } 1610 } 1611 if (i == 4) 1612 goto carp; 1613 1614 /* if there's no extensions, we're done */ 1615 valid_extensions = edid[0x7e]; 1616 if (valid_extensions == 0) 1617 return (struct edid *)edid; 1618 1619 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1620 if (!new) 1621 goto out; 1622 memcpy(new, edid, EDID_LENGTH); 1623 kfree(edid); 1624 edid = new; 1625 1626 for (j = 1; j <= edid[0x7e]; j++) { 1627 u8 *block = edid + j * EDID_LENGTH; 1628 1629 for (i = 0; i < 4; i++) { 1630 if (get_edid_block(data, block, j, EDID_LENGTH)) 1631 goto out; 1632 if (drm_edid_block_valid(block, j, false, NULL)) 1633 break; 1634 } 1635 1636 if (i == 4) 1637 valid_extensions--; 1638 } 1639 1640 if (valid_extensions != edid[0x7e]) { 1641 u8 *base; 1642 1643 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1644 1645 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1646 edid[0x7e] = valid_extensions; 1647 1648 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1649 GFP_KERNEL); 1650 if (!new) 1651 goto out; 1652 1653 base = new; 1654 for (i = 0; i <= edid[0x7e]; i++) { 1655 u8 *block = edid + i * EDID_LENGTH; 1656 1657 if (!drm_edid_block_valid(block, i, false, NULL)) 1658 continue; 1659 1660 memcpy(base, block, EDID_LENGTH); 1661 base += EDID_LENGTH; 1662 } 1663 1664 kfree(edid); 1665 edid = new; 1666 } 1667 1668 return (struct edid *)edid; 1669 1670carp: 1671 connector_bad_edid(connector, edid, 1); 1672out: 1673 kfree(edid); 1674 return NULL; 1675} 1676EXPORT_SYMBOL_GPL(drm_do_get_edid); 1677 1678/** 1679 * drm_probe_ddc() - probe DDC presence 1680 * @adapter: I2C adapter to probe 1681 * 1682 * Return: True on success, false on failure. 1683 */ 1684bool 1685drm_probe_ddc(struct i2c_adapter *adapter) 1686{ 1687 unsigned char out; 1688 1689 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1690} 1691EXPORT_SYMBOL(drm_probe_ddc); 1692 1693/** 1694 * drm_get_edid - get EDID data, if available 1695 * @connector: connector we're probing 1696 * @adapter: I2C adapter to use for DDC 1697 * 1698 * Poke the given I2C channel to grab EDID data if possible. If found, 1699 * attach it to the connector. 1700 * 1701 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1702 */ 1703struct edid *drm_get_edid(struct drm_connector *connector, 1704 struct i2c_adapter *adapter) 1705{ 1706 struct edid *edid; 1707 1708 if (connector->force == DRM_FORCE_OFF) 1709 return NULL; 1710 1711 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 1712 return NULL; 1713 1714 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1715 if (edid) 1716 drm_get_displayid(connector, edid); 1717 return edid; 1718} 1719EXPORT_SYMBOL(drm_get_edid); 1720 1721/** 1722 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1723 * @connector: connector we're probing 1724 * @adapter: I2C adapter to use for DDC 1725 * 1726 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1727 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1728 * switch DDC to the GPU which is retrieving EDID. 1729 * 1730 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1731 */ 1732struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1733 struct i2c_adapter *adapter) 1734{ 1735#ifdef __linux__ 1736 struct pci_dev *pdev = connector->dev->pdev; 1737#endif 1738 struct edid *edid; 1739 1740 vga_switcheroo_lock_ddc(pdev); 1741 edid = drm_get_edid(connector, adapter); 1742 vga_switcheroo_unlock_ddc(pdev); 1743 1744 return edid; 1745} 1746EXPORT_SYMBOL(drm_get_edid_switcheroo); 1747 1748/** 1749 * drm_edid_duplicate - duplicate an EDID and the extensions 1750 * @edid: EDID to duplicate 1751 * 1752 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1753 */ 1754struct edid *drm_edid_duplicate(const struct edid *edid) 1755{ 1756 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1757} 1758EXPORT_SYMBOL(drm_edid_duplicate); 1759 1760/*** EDID parsing ***/ 1761 1762/** 1763 * edid_vendor - match a string against EDID's obfuscated vendor field 1764 * @edid: EDID to match 1765 * @vendor: vendor string 1766 * 1767 * Returns true if @vendor is in @edid, false otherwise 1768 */ 1769static bool edid_vendor(const struct edid *edid, const char *vendor) 1770{ 1771 char edid_vendor[3]; 1772 1773 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1774 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1775 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1776 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1777 1778 return !strncmp(edid_vendor, vendor, 3); 1779} 1780 1781/** 1782 * edid_get_quirks - return quirk flags for a given EDID 1783 * @edid: EDID to process 1784 * 1785 * This tells subsequent routines what fixes they need to apply. 1786 */ 1787static u32 edid_get_quirks(const struct edid *edid) 1788{ 1789 const struct edid_quirk *quirk; 1790 int i; 1791 1792 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1793 quirk = &edid_quirk_list[i]; 1794 1795 if (edid_vendor(edid, quirk->vendor) && 1796 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1797 return quirk->quirks; 1798 } 1799 1800 return 0; 1801} 1802 1803#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1804#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1805 1806/** 1807 * edid_fixup_preferred - set preferred modes based on quirk list 1808 * @connector: has mode list to fix up 1809 * @quirks: quirks list 1810 * 1811 * Walk the mode list for @connector, clearing the preferred status 1812 * on existing modes and setting it anew for the right mode ala @quirks. 1813 */ 1814static void edid_fixup_preferred(struct drm_connector *connector, 1815 u32 quirks) 1816{ 1817 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1818 int target_refresh = 0; 1819 int cur_vrefresh, preferred_vrefresh; 1820 1821 if (list_empty(&connector->probed_modes)) 1822 return; 1823 1824 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1825 target_refresh = 60; 1826 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1827 target_refresh = 75; 1828 1829 preferred_mode = list_first_entry(&connector->probed_modes, 1830 struct drm_display_mode, head); 1831 1832 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1833 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1834 1835 if (cur_mode == preferred_mode) 1836 continue; 1837 1838 /* Largest mode is preferred */ 1839 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1840 preferred_mode = cur_mode; 1841 1842 cur_vrefresh = cur_mode->vrefresh ? 1843 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1844 preferred_vrefresh = preferred_mode->vrefresh ? 1845 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1846 /* At a given size, try to get closest to target refresh */ 1847 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1848 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1849 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1850 preferred_mode = cur_mode; 1851 } 1852 } 1853 1854 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1855} 1856 1857static bool 1858mode_is_rb(const struct drm_display_mode *mode) 1859{ 1860 return (mode->htotal - mode->hdisplay == 160) && 1861 (mode->hsync_end - mode->hdisplay == 80) && 1862 (mode->hsync_end - mode->hsync_start == 32) && 1863 (mode->vsync_start - mode->vdisplay == 3); 1864} 1865 1866/* 1867 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1868 * @dev: Device to duplicate against 1869 * @hsize: Mode width 1870 * @vsize: Mode height 1871 * @fresh: Mode refresh rate 1872 * @rb: Mode reduced-blanking-ness 1873 * 1874 * Walk the DMT mode list looking for a match for the given parameters. 1875 * 1876 * Return: A newly allocated copy of the mode, or NULL if not found. 1877 */ 1878struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1879 int hsize, int vsize, int fresh, 1880 bool rb) 1881{ 1882 int i; 1883 1884 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1885 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1886 if (hsize != ptr->hdisplay) 1887 continue; 1888 if (vsize != ptr->vdisplay) 1889 continue; 1890 if (fresh != drm_mode_vrefresh(ptr)) 1891 continue; 1892 if (rb != mode_is_rb(ptr)) 1893 continue; 1894 1895 return drm_mode_duplicate(dev, ptr); 1896 } 1897 1898 return NULL; 1899} 1900EXPORT_SYMBOL(drm_mode_find_dmt); 1901 1902typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1903 1904static void 1905cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1906{ 1907 int i, n = 0; 1908 u8 d = ext[0x02]; 1909 u8 *det_base = ext + d; 1910 1911 n = (127 - d) / 18; 1912 for (i = 0; i < n; i++) 1913 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1914} 1915 1916static void 1917vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1918{ 1919 unsigned int i, n = min((int)ext[0x02], 6); 1920 u8 *det_base = ext + 5; 1921 1922 if (ext[0x01] != 1) 1923 return; /* unknown version */ 1924 1925 for (i = 0; i < n; i++) 1926 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1927} 1928 1929static void 1930drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1931{ 1932 int i; 1933 struct edid *edid = (struct edid *)raw_edid; 1934 1935 if (edid == NULL) 1936 return; 1937 1938 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1939 cb(&(edid->detailed_timings[i]), closure); 1940 1941 for (i = 1; i <= raw_edid[0x7e]; i++) { 1942 u8 *ext = raw_edid + (i * EDID_LENGTH); 1943 switch (*ext) { 1944 case CEA_EXT: 1945 cea_for_each_detailed_block(ext, cb, closure); 1946 break; 1947 case VTB_EXT: 1948 vtb_for_each_detailed_block(ext, cb, closure); 1949 break; 1950 default: 1951 break; 1952 } 1953 } 1954} 1955 1956static void 1957is_rb(struct detailed_timing *t, void *data) 1958{ 1959 u8 *r = (u8 *)t; 1960 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1961 if (r[15] & 0x10) 1962 *(bool *)data = true; 1963} 1964 1965/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1966static bool 1967drm_monitor_supports_rb(struct edid *edid) 1968{ 1969 if (edid->revision >= 4) { 1970 bool ret = false; 1971 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1972 return ret; 1973 } 1974 1975 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1976} 1977 1978static void 1979find_gtf2(struct detailed_timing *t, void *data) 1980{ 1981 u8 *r = (u8 *)t; 1982 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1983 *(u8 **)data = r; 1984} 1985 1986/* Secondary GTF curve kicks in above some break frequency */ 1987static int 1988drm_gtf2_hbreak(struct edid *edid) 1989{ 1990 u8 *r = NULL; 1991 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1992 return r ? (r[12] * 2) : 0; 1993} 1994 1995static int 1996drm_gtf2_2c(struct edid *edid) 1997{ 1998 u8 *r = NULL; 1999 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2000 return r ? r[13] : 0; 2001} 2002 2003static int 2004drm_gtf2_m(struct edid *edid) 2005{ 2006 u8 *r = NULL; 2007 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2008 return r ? (r[15] << 8) + r[14] : 0; 2009} 2010 2011static int 2012drm_gtf2_k(struct edid *edid) 2013{ 2014 u8 *r = NULL; 2015 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2016 return r ? r[16] : 0; 2017} 2018 2019static int 2020drm_gtf2_2j(struct edid *edid) 2021{ 2022 u8 *r = NULL; 2023 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2024 return r ? r[17] : 0; 2025} 2026 2027/** 2028 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2029 * @edid: EDID block to scan 2030 */ 2031static int standard_timing_level(struct edid *edid) 2032{ 2033 if (edid->revision >= 2) { 2034 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2035 return LEVEL_CVT; 2036 if (drm_gtf2_hbreak(edid)) 2037 return LEVEL_GTF2; 2038 return LEVEL_GTF; 2039 } 2040 return LEVEL_DMT; 2041} 2042 2043/* 2044 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2045 * monitors fill with ascii space (0x20) instead. 2046 */ 2047static int 2048bad_std_timing(u8 a, u8 b) 2049{ 2050 return (a == 0x00 && b == 0x00) || 2051 (a == 0x01 && b == 0x01) || 2052 (a == 0x20 && b == 0x20); 2053} 2054 2055/** 2056 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2057 * @connector: connector of for the EDID block 2058 * @edid: EDID block to scan 2059 * @t: standard timing params 2060 * 2061 * Take the standard timing params (in this case width, aspect, and refresh) 2062 * and convert them into a real mode using CVT/GTF/DMT. 2063 */ 2064static struct drm_display_mode * 2065drm_mode_std(struct drm_connector *connector, struct edid *edid, 2066 struct std_timing *t) 2067{ 2068 struct drm_device *dev = connector->dev; 2069 struct drm_display_mode *m, *mode = NULL; 2070 int hsize, vsize; 2071 int vrefresh_rate; 2072 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2073 >> EDID_TIMING_ASPECT_SHIFT; 2074 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2075 >> EDID_TIMING_VFREQ_SHIFT; 2076 int timing_level = standard_timing_level(edid); 2077 2078 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2079 return NULL; 2080 2081 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2082 hsize = t->hsize * 8 + 248; 2083 /* vrefresh_rate = vfreq + 60 */ 2084 vrefresh_rate = vfreq + 60; 2085 /* the vdisplay is calculated based on the aspect ratio */ 2086 if (aspect_ratio == 0) { 2087 if (edid->revision < 3) 2088 vsize = hsize; 2089 else 2090 vsize = (hsize * 10) / 16; 2091 } else if (aspect_ratio == 1) 2092 vsize = (hsize * 3) / 4; 2093 else if (aspect_ratio == 2) 2094 vsize = (hsize * 4) / 5; 2095 else 2096 vsize = (hsize * 9) / 16; 2097 2098 /* HDTV hack, part 1 */ 2099 if (vrefresh_rate == 60 && 2100 ((hsize == 1360 && vsize == 765) || 2101 (hsize == 1368 && vsize == 769))) { 2102 hsize = 1366; 2103 vsize = 768; 2104 } 2105 2106 /* 2107 * If this connector already has a mode for this size and refresh 2108 * rate (because it came from detailed or CVT info), use that 2109 * instead. This way we don't have to guess at interlace or 2110 * reduced blanking. 2111 */ 2112 list_for_each_entry(m, &connector->probed_modes, head) 2113 if (m->hdisplay == hsize && m->vdisplay == vsize && 2114 drm_mode_vrefresh(m) == vrefresh_rate) 2115 return NULL; 2116 2117 /* HDTV hack, part 2 */ 2118 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2119 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2120 false); 2121 if (!mode) 2122 return NULL; 2123 mode->hdisplay = 1366; 2124 mode->hsync_start = mode->hsync_start - 1; 2125 mode->hsync_end = mode->hsync_end - 1; 2126 return mode; 2127 } 2128 2129 /* check whether it can be found in default mode table */ 2130 if (drm_monitor_supports_rb(edid)) { 2131 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2132 true); 2133 if (mode) 2134 return mode; 2135 } 2136 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2137 if (mode) 2138 return mode; 2139 2140 /* okay, generate it */ 2141 switch (timing_level) { 2142 case LEVEL_DMT: 2143 break; 2144 case LEVEL_GTF: 2145 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2146 break; 2147 case LEVEL_GTF2: 2148 /* 2149 * This is potentially wrong if there's ever a monitor with 2150 * more than one ranges section, each claiming a different 2151 * secondary GTF curve. Please don't do that. 2152 */ 2153 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2154 if (!mode) 2155 return NULL; 2156 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2157 drm_mode_destroy(dev, mode); 2158 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2159 vrefresh_rate, 0, 0, 2160 drm_gtf2_m(edid), 2161 drm_gtf2_2c(edid), 2162 drm_gtf2_k(edid), 2163 drm_gtf2_2j(edid)); 2164 } 2165 break; 2166 case LEVEL_CVT: 2167 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2168 false); 2169 break; 2170 } 2171 return mode; 2172} 2173 2174/* 2175 * EDID is delightfully ambiguous about how interlaced modes are to be 2176 * encoded. Our internal representation is of frame height, but some 2177 * HDTV detailed timings are encoded as field height. 2178 * 2179 * The format list here is from CEA, in frame size. Technically we 2180 * should be checking refresh rate too. Whatever. 2181 */ 2182static void 2183drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2184 struct detailed_pixel_timing *pt) 2185{ 2186 int i; 2187 static const struct { 2188 int w, h; 2189 } cea_interlaced[] = { 2190 { 1920, 1080 }, 2191 { 720, 480 }, 2192 { 1440, 480 }, 2193 { 2880, 480 }, 2194 { 720, 576 }, 2195 { 1440, 576 }, 2196 { 2880, 576 }, 2197 }; 2198 2199 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2200 return; 2201 2202 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2203 if ((mode->hdisplay == cea_interlaced[i].w) && 2204 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2205 mode->vdisplay *= 2; 2206 mode->vsync_start *= 2; 2207 mode->vsync_end *= 2; 2208 mode->vtotal *= 2; 2209 mode->vtotal |= 1; 2210 } 2211 } 2212 2213 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2214} 2215 2216/** 2217 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2218 * @dev: DRM device (needed to create new mode) 2219 * @edid: EDID block 2220 * @timing: EDID detailed timing info 2221 * @quirks: quirks to apply 2222 * 2223 * An EDID detailed timing block contains enough info for us to create and 2224 * return a new struct drm_display_mode. 2225 */ 2226static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2227 struct edid *edid, 2228 struct detailed_timing *timing, 2229 u32 quirks) 2230{ 2231 struct drm_display_mode *mode; 2232 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2233 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2234 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2235 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2236 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2237 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2238 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2239 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2240 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2241 2242 /* ignore tiny modes */ 2243 if (hactive < 64 || vactive < 64) 2244 return NULL; 2245 2246 if (pt->misc & DRM_EDID_PT_STEREO) { 2247 DRM_DEBUG_KMS("stereo mode not supported\n"); 2248 return NULL; 2249 } 2250 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2251 DRM_DEBUG_KMS("composite sync not supported\n"); 2252 } 2253 2254 /* it is incorrect if hsync/vsync width is zero */ 2255 if (!hsync_pulse_width || !vsync_pulse_width) { 2256 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2257 "Wrong Hsync/Vsync pulse width\n"); 2258 return NULL; 2259 } 2260 2261 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2262 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2263 if (!mode) 2264 return NULL; 2265 2266 goto set_size; 2267 } 2268 2269 mode = drm_mode_create(dev); 2270 if (!mode) 2271 return NULL; 2272 2273 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2274 timing->pixel_clock = cpu_to_le16(1088); 2275 2276 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2277 2278 mode->hdisplay = hactive; 2279 mode->hsync_start = mode->hdisplay + hsync_offset; 2280 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2281 mode->htotal = mode->hdisplay + hblank; 2282 2283 mode->vdisplay = vactive; 2284 mode->vsync_start = mode->vdisplay + vsync_offset; 2285 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2286 mode->vtotal = mode->vdisplay + vblank; 2287 2288 /* Some EDIDs have bogus h/vtotal values */ 2289 if (mode->hsync_end > mode->htotal) 2290 mode->htotal = mode->hsync_end + 1; 2291 if (mode->vsync_end > mode->vtotal) 2292 mode->vtotal = mode->vsync_end + 1; 2293 2294 drm_mode_do_interlace_quirk(mode, pt); 2295 2296 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2297 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2298 } 2299 2300 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2301 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2302 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2303 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2304 2305set_size: 2306 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2307 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2308 2309 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2310 mode->width_mm *= 10; 2311 mode->height_mm *= 10; 2312 } 2313 2314 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2315 mode->width_mm = edid->width_cm * 10; 2316 mode->height_mm = edid->height_cm * 10; 2317 } 2318 2319 mode->type = DRM_MODE_TYPE_DRIVER; 2320 mode->vrefresh = drm_mode_vrefresh(mode); 2321 drm_mode_set_name(mode); 2322 2323 return mode; 2324} 2325 2326static bool 2327mode_in_hsync_range(const struct drm_display_mode *mode, 2328 struct edid *edid, u8 *t) 2329{ 2330 int hsync, hmin, hmax; 2331 2332 hmin = t[7]; 2333 if (edid->revision >= 4) 2334 hmin += ((t[4] & 0x04) ? 255 : 0); 2335 hmax = t[8]; 2336 if (edid->revision >= 4) 2337 hmax += ((t[4] & 0x08) ? 255 : 0); 2338 hsync = drm_mode_hsync(mode); 2339 2340 return (hsync <= hmax && hsync >= hmin); 2341} 2342 2343static bool 2344mode_in_vsync_range(const struct drm_display_mode *mode, 2345 struct edid *edid, u8 *t) 2346{ 2347 int vsync, vmin, vmax; 2348 2349 vmin = t[5]; 2350 if (edid->revision >= 4) 2351 vmin += ((t[4] & 0x01) ? 255 : 0); 2352 vmax = t[6]; 2353 if (edid->revision >= 4) 2354 vmax += ((t[4] & 0x02) ? 255 : 0); 2355 vsync = drm_mode_vrefresh(mode); 2356 2357 return (vsync <= vmax && vsync >= vmin); 2358} 2359 2360static u32 2361range_pixel_clock(struct edid *edid, u8 *t) 2362{ 2363 /* unspecified */ 2364 if (t[9] == 0 || t[9] == 255) 2365 return 0; 2366 2367 /* 1.4 with CVT support gives us real precision, yay */ 2368 if (edid->revision >= 4 && t[10] == 0x04) 2369 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2370 2371 /* 1.3 is pathetic, so fuzz up a bit */ 2372 return t[9] * 10000 + 5001; 2373} 2374 2375static bool 2376mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2377 struct detailed_timing *timing) 2378{ 2379 u32 max_clock; 2380 u8 *t = (u8 *)timing; 2381 2382 if (!mode_in_hsync_range(mode, edid, t)) 2383 return false; 2384 2385 if (!mode_in_vsync_range(mode, edid, t)) 2386 return false; 2387 2388 if ((max_clock = range_pixel_clock(edid, t))) 2389 if (mode->clock > max_clock) 2390 return false; 2391 2392 /* 1.4 max horizontal check */ 2393 if (edid->revision >= 4 && t[10] == 0x04) 2394 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2395 return false; 2396 2397 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2398 return false; 2399 2400 return true; 2401} 2402 2403static bool valid_inferred_mode(const struct drm_connector *connector, 2404 const struct drm_display_mode *mode) 2405{ 2406 const struct drm_display_mode *m; 2407 bool ok = false; 2408 2409 list_for_each_entry(m, &connector->probed_modes, head) { 2410 if (mode->hdisplay == m->hdisplay && 2411 mode->vdisplay == m->vdisplay && 2412 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2413 return false; /* duplicated */ 2414 if (mode->hdisplay <= m->hdisplay && 2415 mode->vdisplay <= m->vdisplay) 2416 ok = true; 2417 } 2418 return ok; 2419} 2420 2421static int 2422drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2423 struct detailed_timing *timing) 2424{ 2425 int i, modes = 0; 2426 struct drm_display_mode *newmode; 2427 struct drm_device *dev = connector->dev; 2428 2429 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2430 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2431 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2432 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2433 if (newmode) { 2434 drm_mode_probed_add(connector, newmode); 2435 modes++; 2436 } 2437 } 2438 } 2439 2440 return modes; 2441} 2442 2443/* fix up 1366x768 mode from 1368x768; 2444 * GFT/CVT can't express 1366 width which isn't dividable by 8 2445 */ 2446void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2447{ 2448 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2449 mode->hdisplay = 1366; 2450 mode->hsync_start--; 2451 mode->hsync_end--; 2452 drm_mode_set_name(mode); 2453 } 2454} 2455 2456static int 2457drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2458 struct detailed_timing *timing) 2459{ 2460 int i, modes = 0; 2461 struct drm_display_mode *newmode; 2462 struct drm_device *dev = connector->dev; 2463 2464 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2465 const struct minimode *m = &extra_modes[i]; 2466 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2467 if (!newmode) 2468 return modes; 2469 2470 drm_mode_fixup_1366x768(newmode); 2471 if (!mode_in_range(newmode, edid, timing) || 2472 !valid_inferred_mode(connector, newmode)) { 2473 drm_mode_destroy(dev, newmode); 2474 continue; 2475 } 2476 2477 drm_mode_probed_add(connector, newmode); 2478 modes++; 2479 } 2480 2481 return modes; 2482} 2483 2484static int 2485drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2486 struct detailed_timing *timing) 2487{ 2488 int i, modes = 0; 2489 struct drm_display_mode *newmode; 2490 struct drm_device *dev = connector->dev; 2491 bool rb = drm_monitor_supports_rb(edid); 2492 2493 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2494 const struct minimode *m = &extra_modes[i]; 2495 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2496 if (!newmode) 2497 return modes; 2498 2499 drm_mode_fixup_1366x768(newmode); 2500 if (!mode_in_range(newmode, edid, timing) || 2501 !valid_inferred_mode(connector, newmode)) { 2502 drm_mode_destroy(dev, newmode); 2503 continue; 2504 } 2505 2506 drm_mode_probed_add(connector, newmode); 2507 modes++; 2508 } 2509 2510 return modes; 2511} 2512 2513static void 2514do_inferred_modes(struct detailed_timing *timing, void *c) 2515{ 2516 struct detailed_mode_closure *closure = c; 2517 struct detailed_non_pixel *data = &timing->data.other_data; 2518 struct detailed_data_monitor_range *range = &data->data.range; 2519 2520 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2521 return; 2522 2523 closure->modes += drm_dmt_modes_for_range(closure->connector, 2524 closure->edid, 2525 timing); 2526 2527 if (!version_greater(closure->edid, 1, 1)) 2528 return; /* GTF not defined yet */ 2529 2530 switch (range->flags) { 2531 case 0x02: /* secondary gtf, XXX could do more */ 2532 case 0x00: /* default gtf */ 2533 closure->modes += drm_gtf_modes_for_range(closure->connector, 2534 closure->edid, 2535 timing); 2536 break; 2537 case 0x04: /* cvt, only in 1.4+ */ 2538 if (!version_greater(closure->edid, 1, 3)) 2539 break; 2540 2541 closure->modes += drm_cvt_modes_for_range(closure->connector, 2542 closure->edid, 2543 timing); 2544 break; 2545 case 0x01: /* just the ranges, no formula */ 2546 default: 2547 break; 2548 } 2549} 2550 2551static int 2552add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2553{ 2554 struct detailed_mode_closure closure = { 2555 .connector = connector, 2556 .edid = edid, 2557 }; 2558 2559 if (version_greater(edid, 1, 0)) 2560 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2561 &closure); 2562 2563 return closure.modes; 2564} 2565 2566static int 2567drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2568{ 2569 int i, j, m, modes = 0; 2570 struct drm_display_mode *mode; 2571 u8 *est = ((u8 *)timing) + 6; 2572 2573 for (i = 0; i < 6; i++) { 2574 for (j = 7; j >= 0; j--) { 2575 m = (i * 8) + (7 - j); 2576 if (m >= ARRAY_SIZE(est3_modes)) 2577 break; 2578 if (est[i] & (1 << j)) { 2579 mode = drm_mode_find_dmt(connector->dev, 2580 est3_modes[m].w, 2581 est3_modes[m].h, 2582 est3_modes[m].r, 2583 est3_modes[m].rb); 2584 if (mode) { 2585 drm_mode_probed_add(connector, mode); 2586 modes++; 2587 } 2588 } 2589 } 2590 } 2591 2592 return modes; 2593} 2594 2595static void 2596do_established_modes(struct detailed_timing *timing, void *c) 2597{ 2598 struct detailed_mode_closure *closure = c; 2599 struct detailed_non_pixel *data = &timing->data.other_data; 2600 2601 if (data->type == EDID_DETAIL_EST_TIMINGS) 2602 closure->modes += drm_est3_modes(closure->connector, timing); 2603} 2604 2605/** 2606 * add_established_modes - get est. modes from EDID and add them 2607 * @connector: connector to add mode(s) to 2608 * @edid: EDID block to scan 2609 * 2610 * Each EDID block contains a bitmap of the supported "established modes" list 2611 * (defined above). Tease them out and add them to the global modes list. 2612 */ 2613static int 2614add_established_modes(struct drm_connector *connector, struct edid *edid) 2615{ 2616 struct drm_device *dev = connector->dev; 2617 unsigned long est_bits = edid->established_timings.t1 | 2618 (edid->established_timings.t2 << 8) | 2619 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2620 int i, modes = 0; 2621 struct detailed_mode_closure closure = { 2622 .connector = connector, 2623 .edid = edid, 2624 }; 2625 2626 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2627 if (est_bits & (1<<i)) { 2628 struct drm_display_mode *newmode; 2629 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2630 if (newmode) { 2631 drm_mode_probed_add(connector, newmode); 2632 modes++; 2633 } 2634 } 2635 } 2636 2637 if (version_greater(edid, 1, 0)) 2638 drm_for_each_detailed_block((u8 *)edid, 2639 do_established_modes, &closure); 2640 2641 return modes + closure.modes; 2642} 2643 2644static void 2645do_standard_modes(struct detailed_timing *timing, void *c) 2646{ 2647 struct detailed_mode_closure *closure = c; 2648 struct detailed_non_pixel *data = &timing->data.other_data; 2649 struct drm_connector *connector = closure->connector; 2650 struct edid *edid = closure->edid; 2651 2652 if (data->type == EDID_DETAIL_STD_MODES) { 2653 int i; 2654 for (i = 0; i < 6; i++) { 2655 struct std_timing *std; 2656 struct drm_display_mode *newmode; 2657 2658 std = &data->data.timings[i]; 2659 newmode = drm_mode_std(connector, edid, std); 2660 if (newmode) { 2661 drm_mode_probed_add(connector, newmode); 2662 closure->modes++; 2663 } 2664 } 2665 } 2666} 2667 2668/** 2669 * add_standard_modes - get std. modes from EDID and add them 2670 * @connector: connector to add mode(s) to 2671 * @edid: EDID block to scan 2672 * 2673 * Standard modes can be calculated using the appropriate standard (DMT, 2674 * GTF or CVT. Grab them from @edid and add them to the list. 2675 */ 2676static int 2677add_standard_modes(struct drm_connector *connector, struct edid *edid) 2678{ 2679 int i, modes = 0; 2680 struct detailed_mode_closure closure = { 2681 .connector = connector, 2682 .edid = edid, 2683 }; 2684 2685 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2686 struct drm_display_mode *newmode; 2687 2688 newmode = drm_mode_std(connector, edid, 2689 &edid->standard_timings[i]); 2690 if (newmode) { 2691 drm_mode_probed_add(connector, newmode); 2692 modes++; 2693 } 2694 } 2695 2696 if (version_greater(edid, 1, 0)) 2697 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2698 &closure); 2699 2700 /* XXX should also look for standard codes in VTB blocks */ 2701 2702 return modes + closure.modes; 2703} 2704 2705static int drm_cvt_modes(struct drm_connector *connector, 2706 struct detailed_timing *timing) 2707{ 2708 int i, j, modes = 0; 2709 struct drm_display_mode *newmode; 2710 struct drm_device *dev = connector->dev; 2711 struct cvt_timing *cvt; 2712 const int rates[] = { 60, 85, 75, 60, 50 }; 2713 const u8 empty[3] = { 0, 0, 0 }; 2714 2715 for (i = 0; i < 4; i++) { 2716 int uninitialized_var(width), height; 2717 cvt = &(timing->data.other_data.data.cvt[i]); 2718 2719 if (!memcmp(cvt->code, empty, 3)) 2720 continue; 2721 2722 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2723 switch (cvt->code[1] & 0x0c) { 2724 case 0x00: 2725 width = height * 4 / 3; 2726 break; 2727 case 0x04: 2728 width = height * 16 / 9; 2729 break; 2730 case 0x08: 2731 width = height * 16 / 10; 2732 break; 2733 case 0x0c: 2734 width = height * 15 / 9; 2735 break; 2736 } 2737 2738 for (j = 1; j < 5; j++) { 2739 if (cvt->code[2] & (1 << j)) { 2740 newmode = drm_cvt_mode(dev, width, height, 2741 rates[j], j == 0, 2742 false, false); 2743 if (newmode) { 2744 drm_mode_probed_add(connector, newmode); 2745 modes++; 2746 } 2747 } 2748 } 2749 } 2750 2751 return modes; 2752} 2753 2754static void 2755do_cvt_mode(struct detailed_timing *timing, void *c) 2756{ 2757 struct detailed_mode_closure *closure = c; 2758 struct detailed_non_pixel *data = &timing->data.other_data; 2759 2760 if (data->type == EDID_DETAIL_CVT_3BYTE) 2761 closure->modes += drm_cvt_modes(closure->connector, timing); 2762} 2763 2764static int 2765add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2766{ 2767 struct detailed_mode_closure closure = { 2768 .connector = connector, 2769 .edid = edid, 2770 }; 2771 2772 if (version_greater(edid, 1, 2)) 2773 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2774 2775 /* XXX should also look for CVT codes in VTB blocks */ 2776 2777 return closure.modes; 2778} 2779 2780static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2781 2782static void 2783do_detailed_mode(struct detailed_timing *timing, void *c) 2784{ 2785 struct detailed_mode_closure *closure = c; 2786 struct drm_display_mode *newmode; 2787 2788 if (timing->pixel_clock) { 2789 newmode = drm_mode_detailed(closure->connector->dev, 2790 closure->edid, timing, 2791 closure->quirks); 2792 if (!newmode) 2793 return; 2794 2795 if (closure->preferred) 2796 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2797 2798 /* 2799 * Detailed modes are limited to 10kHz pixel clock resolution, 2800 * so fix up anything that looks like CEA/HDMI mode, but the clock 2801 * is just slightly off. 2802 */ 2803 fixup_detailed_cea_mode_clock(newmode); 2804 2805 drm_mode_probed_add(closure->connector, newmode); 2806 closure->modes++; 2807 closure->preferred = false; 2808 } 2809} 2810 2811/* 2812 * add_detailed_modes - Add modes from detailed timings 2813 * @connector: attached connector 2814 * @edid: EDID block to scan 2815 * @quirks: quirks to apply 2816 */ 2817static int 2818add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2819 u32 quirks) 2820{ 2821 struct detailed_mode_closure closure = { 2822 .connector = connector, 2823 .edid = edid, 2824 .preferred = true, 2825 .quirks = quirks, 2826 }; 2827 2828 if (closure.preferred && !version_greater(edid, 1, 3)) 2829 closure.preferred = 2830 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2831 2832 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2833 2834 return closure.modes; 2835} 2836 2837#define AUDIO_BLOCK 0x01 2838#define VIDEO_BLOCK 0x02 2839#define VENDOR_BLOCK 0x03 2840#define SPEAKER_BLOCK 0x04 2841#define USE_EXTENDED_TAG 0x07 2842#define EXT_VIDEO_CAPABILITY_BLOCK 0x00 2843#define EXT_VIDEO_DATA_BLOCK_420 0x0E 2844#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 2845#define EDID_BASIC_AUDIO (1 << 6) 2846#define EDID_CEA_YCRCB444 (1 << 5) 2847#define EDID_CEA_YCRCB422 (1 << 4) 2848#define EDID_CEA_VCDB_QS (1 << 6) 2849 2850/* 2851 * Search EDID for CEA extension block. 2852 */ 2853static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 2854{ 2855 u8 *edid_ext = NULL; 2856 int i; 2857 2858 /* No EDID or EDID extensions */ 2859 if (edid == NULL || edid->extensions == 0) 2860 return NULL; 2861 2862 /* Find CEA extension */ 2863 for (i = 0; i < edid->extensions; i++) { 2864 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2865 if (edid_ext[0] == ext_id) 2866 break; 2867 } 2868 2869 if (i == edid->extensions) 2870 return NULL; 2871 2872 return edid_ext; 2873} 2874 2875static u8 *drm_find_cea_extension(const struct edid *edid) 2876{ 2877 return drm_find_edid_extension(edid, CEA_EXT); 2878} 2879 2880static u8 *drm_find_displayid_extension(const struct edid *edid) 2881{ 2882 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2883} 2884 2885/* 2886 * Calculate the alternate clock for the CEA mode 2887 * (60Hz vs. 59.94Hz etc.) 2888 */ 2889static unsigned int 2890cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2891{ 2892 unsigned int clock = cea_mode->clock; 2893 2894 if (cea_mode->vrefresh % 6 != 0) 2895 return clock; 2896 2897 /* 2898 * edid_cea_modes contains the 59.94Hz 2899 * variant for 240 and 480 line modes, 2900 * and the 60Hz variant otherwise. 2901 */ 2902 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2903 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2904 else 2905 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2906 2907 return clock; 2908} 2909 2910static bool 2911cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 2912{ 2913 /* 2914 * For certain VICs the spec allows the vertical 2915 * front porch to vary by one or two lines. 2916 * 2917 * cea_modes[] stores the variant with the shortest 2918 * vertical front porch. We can adjust the mode to 2919 * get the other variants by simply increasing the 2920 * vertical front porch length. 2921 */ 2922#ifdef notyet 2923 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || 2924 edid_cea_modes[9].vtotal != 262 || 2925 edid_cea_modes[12].vtotal != 262 || 2926 edid_cea_modes[13].vtotal != 262 || 2927 edid_cea_modes[23].vtotal != 312 || 2928 edid_cea_modes[24].vtotal != 312 || 2929 edid_cea_modes[27].vtotal != 312 || 2930 edid_cea_modes[28].vtotal != 312); 2931#endif 2932 2933 if (((vic == 8 || vic == 9 || 2934 vic == 12 || vic == 13) && mode->vtotal < 263) || 2935 ((vic == 23 || vic == 24 || 2936 vic == 27 || vic == 28) && mode->vtotal < 314)) { 2937 mode->vsync_start++; 2938 mode->vsync_end++; 2939 mode->vtotal++; 2940 2941 return true; 2942 } 2943 2944 return false; 2945} 2946 2947static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2948 unsigned int clock_tolerance) 2949{ 2950 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 2951 u8 vic; 2952 2953 if (!to_match->clock) 2954 return 0; 2955 2956 if (to_match->picture_aspect_ratio) 2957 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 2958 2959 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2960 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 2961 unsigned int clock1, clock2; 2962 2963 /* Check both 60Hz and 59.94Hz */ 2964 clock1 = cea_mode.clock; 2965 clock2 = cea_mode_alternate_clock(&cea_mode); 2966 2967 if (abs(to_match->clock - clock1) > clock_tolerance && 2968 abs(to_match->clock - clock2) > clock_tolerance) 2969 continue; 2970 2971 do { 2972 if (drm_mode_match(to_match, &cea_mode, match_flags)) 2973 return vic; 2974 } while (cea_mode_alternate_timings(vic, &cea_mode)); 2975 } 2976 2977 return 0; 2978} 2979 2980/** 2981 * drm_match_cea_mode - look for a CEA mode matching given mode 2982 * @to_match: display mode 2983 * 2984 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2985 * mode. 2986 */ 2987u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2988{ 2989 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 2990 u8 vic; 2991 2992 if (!to_match->clock) 2993 return 0; 2994 2995 if (to_match->picture_aspect_ratio) 2996 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 2997 2998 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2999 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 3000 unsigned int clock1, clock2; 3001 3002 /* Check both 60Hz and 59.94Hz */ 3003 clock1 = cea_mode.clock; 3004 clock2 = cea_mode_alternate_clock(&cea_mode); 3005 3006 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3007 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3008 continue; 3009 3010 do { 3011 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3012 return vic; 3013 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3014 } 3015 3016 return 0; 3017} 3018EXPORT_SYMBOL(drm_match_cea_mode); 3019 3020static bool drm_valid_cea_vic(u8 vic) 3021{ 3022 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 3023} 3024 3025/** 3026 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 3027 * the input VIC from the CEA mode list 3028 * @video_code: ID given to each of the CEA modes 3029 * 3030 * Returns picture aspect ratio 3031 */ 3032enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3033{ 3034 return edid_cea_modes[video_code].picture_aspect_ratio; 3035} 3036EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 3037 3038/* 3039 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3040 * specific block). 3041 * 3042 * It's almost like cea_mode_alternate_clock(), we just need to add an 3043 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 3044 * one. 3045 */ 3046static unsigned int 3047hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3048{ 3049 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3050 return hdmi_mode->clock; 3051 3052 return cea_mode_alternate_clock(hdmi_mode); 3053} 3054 3055static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3056 unsigned int clock_tolerance) 3057{ 3058 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3059 u8 vic; 3060 3061 if (!to_match->clock) 3062 return 0; 3063 3064 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3065 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3066 unsigned int clock1, clock2; 3067 3068 /* Make sure to also match alternate clocks */ 3069 clock1 = hdmi_mode->clock; 3070 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3071 3072 if (abs(to_match->clock - clock1) > clock_tolerance && 3073 abs(to_match->clock - clock2) > clock_tolerance) 3074 continue; 3075 3076 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3077 return vic; 3078 } 3079 3080 return 0; 3081} 3082 3083/* 3084 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3085 * @to_match: display mode 3086 * 3087 * An HDMI mode is one defined in the HDMI vendor specific block. 3088 * 3089 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3090 */ 3091static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3092{ 3093 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3094 u8 vic; 3095 3096 if (!to_match->clock) 3097 return 0; 3098 3099 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3100 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3101 unsigned int clock1, clock2; 3102 3103 /* Make sure to also match alternate clocks */ 3104 clock1 = hdmi_mode->clock; 3105 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3106 3107 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3108 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3109 drm_mode_match(to_match, hdmi_mode, match_flags)) 3110 return vic; 3111 } 3112 return 0; 3113} 3114 3115static bool drm_valid_hdmi_vic(u8 vic) 3116{ 3117 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3118} 3119 3120static int 3121add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3122{ 3123 struct drm_device *dev = connector->dev; 3124 struct drm_display_mode *mode, *tmp; 3125 DRM_LIST_HEAD(list); 3126 int modes = 0; 3127 3128 /* Don't add CEA modes if the CEA extension block is missing */ 3129 if (!drm_find_cea_extension(edid)) 3130 return 0; 3131 3132 /* 3133 * Go through all probed modes and create a new mode 3134 * with the alternate clock for certain CEA modes. 3135 */ 3136 list_for_each_entry(mode, &connector->probed_modes, head) { 3137 const struct drm_display_mode *cea_mode = NULL; 3138 struct drm_display_mode *newmode; 3139 u8 vic = drm_match_cea_mode(mode); 3140 unsigned int clock1, clock2; 3141 3142 if (drm_valid_cea_vic(vic)) { 3143 cea_mode = &edid_cea_modes[vic]; 3144 clock2 = cea_mode_alternate_clock(cea_mode); 3145 } else { 3146 vic = drm_match_hdmi_mode(mode); 3147 if (drm_valid_hdmi_vic(vic)) { 3148 cea_mode = &edid_4k_modes[vic]; 3149 clock2 = hdmi_mode_alternate_clock(cea_mode); 3150 } 3151 } 3152 3153 if (!cea_mode) 3154 continue; 3155 3156 clock1 = cea_mode->clock; 3157 3158 if (clock1 == clock2) 3159 continue; 3160 3161 if (mode->clock != clock1 && mode->clock != clock2) 3162 continue; 3163 3164 newmode = drm_mode_duplicate(dev, cea_mode); 3165 if (!newmode) 3166 continue; 3167 3168 /* Carry over the stereo flags */ 3169 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3170 3171 /* 3172 * The current mode could be either variant. Make 3173 * sure to pick the "other" clock for the new mode. 3174 */ 3175 if (mode->clock != clock1) 3176 newmode->clock = clock1; 3177 else 3178 newmode->clock = clock2; 3179 3180 list_add_tail(&newmode->head, &list); 3181 } 3182 3183 list_for_each_entry_safe(mode, tmp, &list, head) { 3184 list_del(&mode->head); 3185 drm_mode_probed_add(connector, mode); 3186 modes++; 3187 } 3188 3189 return modes; 3190} 3191 3192static u8 svd_to_vic(u8 svd) 3193{ 3194 /* 0-6 bit vic, 7th bit native mode indicator */ 3195 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3196 return svd & 127; 3197 3198 return svd; 3199} 3200 3201static struct drm_display_mode * 3202drm_display_mode_from_vic_index(struct drm_connector *connector, 3203 const u8 *video_db, u8 video_len, 3204 u8 video_index) 3205{ 3206 struct drm_device *dev = connector->dev; 3207 struct drm_display_mode *newmode; 3208 u8 vic; 3209 3210 if (video_db == NULL || video_index >= video_len) 3211 return NULL; 3212 3213 /* CEA modes are numbered 1..127 */ 3214 vic = svd_to_vic(video_db[video_index]); 3215 if (!drm_valid_cea_vic(vic)) 3216 return NULL; 3217 3218 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3219 if (!newmode) 3220 return NULL; 3221 3222 newmode->vrefresh = 0; 3223 3224 return newmode; 3225} 3226 3227/* 3228 * do_y420vdb_modes - Parse YCBCR 420 only modes 3229 * @connector: connector corresponding to the HDMI sink 3230 * @svds: start of the data block of CEA YCBCR 420 VDB 3231 * @len: length of the CEA YCBCR 420 VDB 3232 * 3233 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3234 * which contains modes which can be supported in YCBCR 420 3235 * output format only. 3236 */ 3237static int do_y420vdb_modes(struct drm_connector *connector, 3238 const u8 *svds, u8 svds_len) 3239{ 3240 int modes = 0, i; 3241 struct drm_device *dev = connector->dev; 3242 struct drm_display_info *info = &connector->display_info; 3243 struct drm_hdmi_info *hdmi = &info->hdmi; 3244 3245 for (i = 0; i < svds_len; i++) { 3246 u8 vic = svd_to_vic(svds[i]); 3247 struct drm_display_mode *newmode; 3248 3249 if (!drm_valid_cea_vic(vic)) 3250 continue; 3251 3252 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3253 if (!newmode) 3254 break; 3255 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3256 drm_mode_probed_add(connector, newmode); 3257 modes++; 3258 } 3259 3260 if (modes > 0) 3261 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3262 return modes; 3263} 3264 3265/* 3266 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3267 * @connector: connector corresponding to the HDMI sink 3268 * @vic: CEA vic for the video mode to be added in the map 3269 * 3270 * Makes an entry for a videomode in the YCBCR 420 bitmap 3271 */ 3272static void 3273drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3274{ 3275 u8 vic = svd_to_vic(svd); 3276 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3277 3278 if (!drm_valid_cea_vic(vic)) 3279 return; 3280 3281 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3282} 3283 3284static int 3285do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3286{ 3287 int i, modes = 0; 3288 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3289 3290 for (i = 0; i < len; i++) { 3291 struct drm_display_mode *mode; 3292 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3293 if (mode) { 3294 /* 3295 * YCBCR420 capability block contains a bitmap which 3296 * gives the index of CEA modes from CEA VDB, which 3297 * can support YCBCR 420 sampling output also (apart 3298 * from RGB/YCBCR444 etc). 3299 * For example, if the bit 0 in bitmap is set, 3300 * first mode in VDB can support YCBCR420 output too. 3301 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3302 */ 3303 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3304 drm_add_cmdb_modes(connector, db[i]); 3305 3306 drm_mode_probed_add(connector, mode); 3307 modes++; 3308 } 3309 } 3310 3311 return modes; 3312} 3313 3314struct stereo_mandatory_mode { 3315 int width, height, vrefresh; 3316 unsigned int flags; 3317}; 3318 3319static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3320 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3321 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3322 { 1920, 1080, 50, 3323 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3324 { 1920, 1080, 60, 3325 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3326 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3327 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3328 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3329 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3330}; 3331 3332static bool 3333stereo_match_mandatory(const struct drm_display_mode *mode, 3334 const struct stereo_mandatory_mode *stereo_mode) 3335{ 3336 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3337 3338 return mode->hdisplay == stereo_mode->width && 3339 mode->vdisplay == stereo_mode->height && 3340 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3341 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3342} 3343 3344static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3345{ 3346 struct drm_device *dev = connector->dev; 3347 const struct drm_display_mode *mode; 3348 struct list_head stereo_modes; 3349 int modes = 0, i; 3350 3351 INIT_LIST_HEAD(&stereo_modes); 3352 3353 list_for_each_entry(mode, &connector->probed_modes, head) { 3354 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3355 const struct stereo_mandatory_mode *mandatory; 3356 struct drm_display_mode *new_mode; 3357 3358 if (!stereo_match_mandatory(mode, 3359 &stereo_mandatory_modes[i])) 3360 continue; 3361 3362 mandatory = &stereo_mandatory_modes[i]; 3363 new_mode = drm_mode_duplicate(dev, mode); 3364 if (!new_mode) 3365 continue; 3366 3367 new_mode->flags |= mandatory->flags; 3368 list_add_tail(&new_mode->head, &stereo_modes); 3369 modes++; 3370 } 3371 } 3372 3373 list_splice_tail(&stereo_modes, &connector->probed_modes); 3374 3375 return modes; 3376} 3377 3378static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3379{ 3380 struct drm_device *dev = connector->dev; 3381 struct drm_display_mode *newmode; 3382 3383 if (!drm_valid_hdmi_vic(vic)) { 3384 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3385 return 0; 3386 } 3387 3388 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3389 if (!newmode) 3390 return 0; 3391 3392 drm_mode_probed_add(connector, newmode); 3393 3394 return 1; 3395} 3396 3397static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3398 const u8 *video_db, u8 video_len, u8 video_index) 3399{ 3400 struct drm_display_mode *newmode; 3401 int modes = 0; 3402 3403 if (structure & (1 << 0)) { 3404 newmode = drm_display_mode_from_vic_index(connector, video_db, 3405 video_len, 3406 video_index); 3407 if (newmode) { 3408 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3409 drm_mode_probed_add(connector, newmode); 3410 modes++; 3411 } 3412 } 3413 if (structure & (1 << 6)) { 3414 newmode = drm_display_mode_from_vic_index(connector, video_db, 3415 video_len, 3416 video_index); 3417 if (newmode) { 3418 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3419 drm_mode_probed_add(connector, newmode); 3420 modes++; 3421 } 3422 } 3423 if (structure & (1 << 8)) { 3424 newmode = drm_display_mode_from_vic_index(connector, video_db, 3425 video_len, 3426 video_index); 3427 if (newmode) { 3428 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3429 drm_mode_probed_add(connector, newmode); 3430 modes++; 3431 } 3432 } 3433 3434 return modes; 3435} 3436 3437/* 3438 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3439 * @connector: connector corresponding to the HDMI sink 3440 * @db: start of the CEA vendor specific block 3441 * @len: length of the CEA block payload, ie. one can access up to db[len] 3442 * 3443 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3444 * also adds the stereo 3d modes when applicable. 3445 */ 3446static int 3447do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3448 const u8 *video_db, u8 video_len) 3449{ 3450 struct drm_display_info *info = &connector->display_info; 3451 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3452 u8 vic_len, hdmi_3d_len = 0; 3453 u16 mask; 3454 u16 structure_all; 3455 3456 if (len < 8) 3457 goto out; 3458 3459 /* no HDMI_Video_Present */ 3460 if (!(db[8] & (1 << 5))) 3461 goto out; 3462 3463 /* Latency_Fields_Present */ 3464 if (db[8] & (1 << 7)) 3465 offset += 2; 3466 3467 /* I_Latency_Fields_Present */ 3468 if (db[8] & (1 << 6)) 3469 offset += 2; 3470 3471 /* the declared length is not long enough for the 2 first bytes 3472 * of additional video format capabilities */ 3473 if (len < (8 + offset + 2)) 3474 goto out; 3475 3476 /* 3D_Present */ 3477 offset++; 3478 if (db[8 + offset] & (1 << 7)) { 3479 modes += add_hdmi_mandatory_stereo_modes(connector); 3480 3481 /* 3D_Multi_present */ 3482 multi_present = (db[8 + offset] & 0x60) >> 5; 3483 } 3484 3485 offset++; 3486 vic_len = db[8 + offset] >> 5; 3487 hdmi_3d_len = db[8 + offset] & 0x1f; 3488 3489 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3490 u8 vic; 3491 3492 vic = db[9 + offset + i]; 3493 modes += add_hdmi_mode(connector, vic); 3494 } 3495 offset += 1 + vic_len; 3496 3497 if (multi_present == 1) 3498 multi_len = 2; 3499 else if (multi_present == 2) 3500 multi_len = 4; 3501 else 3502 multi_len = 0; 3503 3504 if (len < (8 + offset + hdmi_3d_len - 1)) 3505 goto out; 3506 3507 if (hdmi_3d_len < multi_len) 3508 goto out; 3509 3510 if (multi_present == 1 || multi_present == 2) { 3511 /* 3D_Structure_ALL */ 3512 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3513 3514 /* check if 3D_MASK is present */ 3515 if (multi_present == 2) 3516 mask = (db[10 + offset] << 8) | db[11 + offset]; 3517 else 3518 mask = 0xffff; 3519 3520 for (i = 0; i < 16; i++) { 3521 if (mask & (1 << i)) 3522 modes += add_3d_struct_modes(connector, 3523 structure_all, 3524 video_db, 3525 video_len, i); 3526 } 3527 } 3528 3529 offset += multi_len; 3530 3531 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3532 int vic_index; 3533 struct drm_display_mode *newmode = NULL; 3534 unsigned int newflag = 0; 3535 bool detail_present; 3536 3537 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3538 3539 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3540 break; 3541 3542 /* 2D_VIC_order_X */ 3543 vic_index = db[8 + offset + i] >> 4; 3544 3545 /* 3D_Structure_X */ 3546 switch (db[8 + offset + i] & 0x0f) { 3547 case 0: 3548 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3549 break; 3550 case 6: 3551 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3552 break; 3553 case 8: 3554 /* 3D_Detail_X */ 3555 if ((db[9 + offset + i] >> 4) == 1) 3556 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3557 break; 3558 } 3559 3560 if (newflag != 0) { 3561 newmode = drm_display_mode_from_vic_index(connector, 3562 video_db, 3563 video_len, 3564 vic_index); 3565 3566 if (newmode) { 3567 newmode->flags |= newflag; 3568 drm_mode_probed_add(connector, newmode); 3569 modes++; 3570 } 3571 } 3572 3573 if (detail_present) 3574 i++; 3575 } 3576 3577out: 3578 if (modes > 0) 3579 info->has_hdmi_infoframe = true; 3580 return modes; 3581} 3582 3583static int 3584cea_db_payload_len(const u8 *db) 3585{ 3586 return db[0] & 0x1f; 3587} 3588 3589static int 3590cea_db_extended_tag(const u8 *db) 3591{ 3592 return db[1]; 3593} 3594 3595static int 3596cea_db_tag(const u8 *db) 3597{ 3598 return db[0] >> 5; 3599} 3600 3601static int 3602cea_revision(const u8 *cea) 3603{ 3604 return cea[1]; 3605} 3606 3607static int 3608cea_db_offsets(const u8 *cea, int *start, int *end) 3609{ 3610 /* Data block offset in CEA extension block */ 3611 *start = 4; 3612 *end = cea[2]; 3613 if (*end == 0) 3614 *end = 127; 3615 if (*end < 4 || *end > 127) 3616 return -ERANGE; 3617 return 0; 3618} 3619 3620static bool cea_db_is_hdmi_vsdb(const u8 *db) 3621{ 3622 int hdmi_id; 3623 3624 if (cea_db_tag(db) != VENDOR_BLOCK) 3625 return false; 3626 3627 if (cea_db_payload_len(db) < 5) 3628 return false; 3629 3630 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3631 3632 return hdmi_id == HDMI_IEEE_OUI; 3633} 3634 3635static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 3636{ 3637 unsigned int oui; 3638 3639 if (cea_db_tag(db) != VENDOR_BLOCK) 3640 return false; 3641 3642 if (cea_db_payload_len(db) < 7) 3643 return false; 3644 3645 oui = db[3] << 16 | db[2] << 8 | db[1]; 3646 3647 return oui == HDMI_FORUM_IEEE_OUI; 3648} 3649 3650static bool cea_db_is_y420cmdb(const u8 *db) 3651{ 3652 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3653 return false; 3654 3655 if (!cea_db_payload_len(db)) 3656 return false; 3657 3658 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 3659 return false; 3660 3661 return true; 3662} 3663 3664static bool cea_db_is_y420vdb(const u8 *db) 3665{ 3666 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3667 return false; 3668 3669 if (!cea_db_payload_len(db)) 3670 return false; 3671 3672 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 3673 return false; 3674 3675 return true; 3676} 3677 3678#define for_each_cea_db(cea, i, start, end) \ 3679 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3680 3681static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 3682 const u8 *db) 3683{ 3684 struct drm_display_info *info = &connector->display_info; 3685 struct drm_hdmi_info *hdmi = &info->hdmi; 3686 u8 map_len = cea_db_payload_len(db) - 1; 3687 u8 count; 3688 u64 map = 0; 3689 3690 if (map_len == 0) { 3691 /* All CEA modes support ycbcr420 sampling also.*/ 3692 hdmi->y420_cmdb_map = U64_MAX; 3693 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3694 return; 3695 } 3696 3697 /* 3698 * This map indicates which of the existing CEA block modes 3699 * from VDB can support YCBCR420 output too. So if bit=0 is 3700 * set, first mode from VDB can support YCBCR420 output too. 3701 * We will parse and keep this map, before parsing VDB itself 3702 * to avoid going through the same block again and again. 3703 * 3704 * Spec is not clear about max possible size of this block. 3705 * Clamping max bitmap block size at 8 bytes. Every byte can 3706 * address 8 CEA modes, in this way this map can address 3707 * 8*8 = first 64 SVDs. 3708 */ 3709 if (WARN_ON_ONCE(map_len > 8)) 3710 map_len = 8; 3711 3712 for (count = 0; count < map_len; count++) 3713 map |= (u64)db[2 + count] << (8 * count); 3714 3715 if (map) 3716 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3717 3718 hdmi->y420_cmdb_map = map; 3719} 3720 3721static int 3722add_cea_modes(struct drm_connector *connector, struct edid *edid) 3723{ 3724 const u8 *cea = drm_find_cea_extension(edid); 3725 const u8 *db, *hdmi = NULL, *video = NULL; 3726 u8 dbl, hdmi_len, video_len = 0; 3727 int modes = 0; 3728 3729 if (cea && cea_revision(cea) >= 3) { 3730 int i, start, end; 3731 3732 if (cea_db_offsets(cea, &start, &end)) 3733 return 0; 3734 3735 for_each_cea_db(cea, i, start, end) { 3736 db = &cea[i]; 3737 dbl = cea_db_payload_len(db); 3738 3739 if (cea_db_tag(db) == VIDEO_BLOCK) { 3740 video = db + 1; 3741 video_len = dbl; 3742 modes += do_cea_modes(connector, video, dbl); 3743 } else if (cea_db_is_hdmi_vsdb(db)) { 3744 hdmi = db; 3745 hdmi_len = dbl; 3746 } else if (cea_db_is_y420vdb(db)) { 3747 const u8 *vdb420 = &db[2]; 3748 3749 /* Add 4:2:0(only) modes present in EDID */ 3750 modes += do_y420vdb_modes(connector, 3751 vdb420, 3752 dbl - 1); 3753 } 3754 } 3755 } 3756 3757 /* 3758 * We parse the HDMI VSDB after having added the cea modes as we will 3759 * be patching their flags when the sink supports stereo 3D. 3760 */ 3761 if (hdmi) 3762 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3763 video_len); 3764 3765 return modes; 3766} 3767 3768static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3769{ 3770 const struct drm_display_mode *cea_mode; 3771 int clock1, clock2, clock; 3772 u8 vic; 3773 const char *type; 3774 3775 /* 3776 * allow 5kHz clock difference either way to account for 3777 * the 10kHz clock resolution limit of detailed timings. 3778 */ 3779 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3780 if (drm_valid_cea_vic(vic)) { 3781 type = "CEA"; 3782 cea_mode = &edid_cea_modes[vic]; 3783 clock1 = cea_mode->clock; 3784 clock2 = cea_mode_alternate_clock(cea_mode); 3785 } else { 3786 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3787 if (drm_valid_hdmi_vic(vic)) { 3788 type = "HDMI"; 3789 cea_mode = &edid_4k_modes[vic]; 3790 clock1 = cea_mode->clock; 3791 clock2 = hdmi_mode_alternate_clock(cea_mode); 3792 } else { 3793 return; 3794 } 3795 } 3796 3797 /* pick whichever is closest */ 3798 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3799 clock = clock1; 3800 else 3801 clock = clock2; 3802 3803 if (mode->clock == clock) 3804 return; 3805 3806 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3807 type, vic, mode->clock, clock); 3808 mode->clock = clock; 3809} 3810 3811static void 3812drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 3813{ 3814 u8 len = cea_db_payload_len(db); 3815 3816 if (len >= 6 && (db[6] & (1 << 7))) 3817 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 3818 if (len >= 8) { 3819 connector->latency_present[0] = db[8] >> 7; 3820 connector->latency_present[1] = (db[8] >> 6) & 1; 3821 } 3822 if (len >= 9) 3823 connector->video_latency[0] = db[9]; 3824 if (len >= 10) 3825 connector->audio_latency[0] = db[10]; 3826 if (len >= 11) 3827 connector->video_latency[1] = db[11]; 3828 if (len >= 12) 3829 connector->audio_latency[1] = db[12]; 3830 3831 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 3832 "video latency %d %d, " 3833 "audio latency %d %d\n", 3834 connector->latency_present[0], 3835 connector->latency_present[1], 3836 connector->video_latency[0], 3837 connector->video_latency[1], 3838 connector->audio_latency[0], 3839 connector->audio_latency[1]); 3840} 3841 3842static void 3843monitor_name(struct detailed_timing *t, void *data) 3844{ 3845 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3846 *(u8 **)data = t->data.other_data.data.str.str; 3847} 3848 3849static int get_monitor_name(struct edid *edid, char name[13]) 3850{ 3851 char *edid_name = NULL; 3852 int mnl; 3853 3854 if (!edid || !name) 3855 return 0; 3856 3857 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3858 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3859 if (edid_name[mnl] == 0x0a) 3860 break; 3861 3862 name[mnl] = edid_name[mnl]; 3863 } 3864 3865 return mnl; 3866} 3867 3868/** 3869 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3870 * @edid: monitor EDID information 3871 * @name: pointer to a character array to hold the name of the monitor 3872 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3873 * 3874 */ 3875void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3876{ 3877 int name_length; 3878 char buf[13]; 3879 3880 if (bufsize <= 0) 3881 return; 3882 3883 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3884 memcpy(name, buf, name_length); 3885 name[name_length] = '\0'; 3886} 3887EXPORT_SYMBOL(drm_edid_get_monitor_name); 3888 3889static void clear_eld(struct drm_connector *connector) 3890{ 3891 memset(connector->eld, 0, sizeof(connector->eld)); 3892 3893 connector->latency_present[0] = false; 3894 connector->latency_present[1] = false; 3895 connector->video_latency[0] = 0; 3896 connector->audio_latency[0] = 0; 3897 connector->video_latency[1] = 0; 3898 connector->audio_latency[1] = 0; 3899} 3900 3901/* 3902 * drm_edid_to_eld - build ELD from EDID 3903 * @connector: connector corresponding to the HDMI/DP sink 3904 * @edid: EDID to parse 3905 * 3906 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3907 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 3908 */ 3909static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3910{ 3911 uint8_t *eld = connector->eld; 3912 u8 *cea; 3913 u8 *db; 3914 int total_sad_count = 0; 3915 int mnl; 3916 int dbl; 3917 3918 clear_eld(connector); 3919 3920 if (!edid) 3921 return; 3922 3923 cea = drm_find_cea_extension(edid); 3924 if (!cea) { 3925 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3926 return; 3927 } 3928 3929 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 3930 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 3931 3932 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 3933 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 3934 3935 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 3936 3937 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 3938 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 3939 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 3940 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 3941 3942 if (cea_revision(cea) >= 3) { 3943 int i, start, end; 3944 3945 if (cea_db_offsets(cea, &start, &end)) { 3946 start = 0; 3947 end = 0; 3948 } 3949 3950 for_each_cea_db(cea, i, start, end) { 3951 db = &cea[i]; 3952 dbl = cea_db_payload_len(db); 3953 3954 switch (cea_db_tag(db)) { 3955 int sad_count; 3956 3957 case AUDIO_BLOCK: 3958 /* Audio Data Block, contains SADs */ 3959 sad_count = min(dbl / 3, 15 - total_sad_count); 3960 if (sad_count >= 1) 3961 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 3962 &db[1], sad_count * 3); 3963 total_sad_count += sad_count; 3964 break; 3965 case SPEAKER_BLOCK: 3966 /* Speaker Allocation Data Block */ 3967 if (dbl >= 1) 3968 eld[DRM_ELD_SPEAKER] = db[1]; 3969 break; 3970 case VENDOR_BLOCK: 3971 /* HDMI Vendor-Specific Data Block */ 3972 if (cea_db_is_hdmi_vsdb(db)) 3973 drm_parse_hdmi_vsdb_audio(connector, db); 3974 break; 3975 default: 3976 break; 3977 } 3978 } 3979 } 3980 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 3981 3982 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3983 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3984 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 3985 else 3986 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 3987 3988 eld[DRM_ELD_BASELINE_ELD_LEN] = 3989 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3990 3991 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3992 drm_eld_size(eld), total_sad_count); 3993} 3994 3995/** 3996 * drm_edid_to_sad - extracts SADs from EDID 3997 * @edid: EDID to parse 3998 * @sads: pointer that will be set to the extracted SADs 3999 * 4000 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4001 * 4002 * Note: The returned pointer needs to be freed using kfree(). 4003 * 4004 * Return: The number of found SADs or negative number on error. 4005 */ 4006int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4007{ 4008 int count = 0; 4009 int i, start, end, dbl; 4010 u8 *cea; 4011 4012 cea = drm_find_cea_extension(edid); 4013 if (!cea) { 4014 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4015 return -ENOENT; 4016 } 4017 4018 if (cea_revision(cea) < 3) { 4019 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4020 return -ENOTSUPP; 4021 } 4022 4023 if (cea_db_offsets(cea, &start, &end)) { 4024 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4025 return -EPROTO; 4026 } 4027 4028 for_each_cea_db(cea, i, start, end) { 4029 u8 *db = &cea[i]; 4030 4031 if (cea_db_tag(db) == AUDIO_BLOCK) { 4032 int j; 4033 dbl = cea_db_payload_len(db); 4034 4035 count = dbl / 3; /* SAD is 3B */ 4036 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4037 if (!*sads) 4038 return -ENOMEM; 4039 for (j = 0; j < count; j++) { 4040 u8 *sad = &db[1 + j * 3]; 4041 4042 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4043 (*sads)[j].channels = sad[0] & 0x7; 4044 (*sads)[j].freq = sad[1] & 0x7F; 4045 (*sads)[j].byte2 = sad[2]; 4046 } 4047 break; 4048 } 4049 } 4050 4051 return count; 4052} 4053EXPORT_SYMBOL(drm_edid_to_sad); 4054 4055/** 4056 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4057 * @edid: EDID to parse 4058 * @sadb: pointer to the speaker block 4059 * 4060 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4061 * 4062 * Note: The returned pointer needs to be freed using kfree(). 4063 * 4064 * Return: The number of found Speaker Allocation Blocks or negative number on 4065 * error. 4066 */ 4067int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4068{ 4069 int count = 0; 4070 int i, start, end, dbl; 4071 const u8 *cea; 4072 4073 cea = drm_find_cea_extension(edid); 4074 if (!cea) { 4075 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4076 return -ENOENT; 4077 } 4078 4079 if (cea_revision(cea) < 3) { 4080 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4081 return -ENOTSUPP; 4082 } 4083 4084 if (cea_db_offsets(cea, &start, &end)) { 4085 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4086 return -EPROTO; 4087 } 4088 4089 for_each_cea_db(cea, i, start, end) { 4090 const u8 *db = &cea[i]; 4091 4092 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4093 dbl = cea_db_payload_len(db); 4094 4095 /* Speaker Allocation Data Block */ 4096 if (dbl == 3) { 4097 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4098 if (!*sadb) 4099 return -ENOMEM; 4100 count = dbl; 4101 break; 4102 } 4103 } 4104 } 4105 4106 return count; 4107} 4108EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4109 4110/** 4111 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4112 * @connector: connector associated with the HDMI/DP sink 4113 * @mode: the display mode 4114 * 4115 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4116 * the sink doesn't support audio or video. 4117 */ 4118int drm_av_sync_delay(struct drm_connector *connector, 4119 const struct drm_display_mode *mode) 4120{ 4121 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4122 int a, v; 4123 4124 if (!connector->latency_present[0]) 4125 return 0; 4126 if (!connector->latency_present[1]) 4127 i = 0; 4128 4129 a = connector->audio_latency[i]; 4130 v = connector->video_latency[i]; 4131 4132 /* 4133 * HDMI/DP sink doesn't support audio or video? 4134 */ 4135 if (a == 255 || v == 255) 4136 return 0; 4137 4138 /* 4139 * Convert raw EDID values to millisecond. 4140 * Treat unknown latency as 0ms. 4141 */ 4142 if (a) 4143 a = min(2 * (a - 1), 500); 4144 if (v) 4145 v = min(2 * (v - 1), 500); 4146 4147 return max(v - a, 0); 4148} 4149EXPORT_SYMBOL(drm_av_sync_delay); 4150 4151/** 4152 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4153 * @edid: monitor EDID information 4154 * 4155 * Parse the CEA extension according to CEA-861-B. 4156 * 4157 * Return: True if the monitor is HDMI, false if not or unknown. 4158 */ 4159bool drm_detect_hdmi_monitor(struct edid *edid) 4160{ 4161 u8 *edid_ext; 4162 int i; 4163 int start_offset, end_offset; 4164 4165 edid_ext = drm_find_cea_extension(edid); 4166 if (!edid_ext) 4167 return false; 4168 4169 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4170 return false; 4171 4172 /* 4173 * Because HDMI identifier is in Vendor Specific Block, 4174 * search it from all data blocks of CEA extension. 4175 */ 4176 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4177 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4178 return true; 4179 } 4180 4181 return false; 4182} 4183EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4184 4185/** 4186 * drm_detect_monitor_audio - check monitor audio capability 4187 * @edid: EDID block to scan 4188 * 4189 * Monitor should have CEA extension block. 4190 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4191 * audio' only. If there is any audio extension block and supported 4192 * audio format, assume at least 'basic audio' support, even if 'basic 4193 * audio' is not defined in EDID. 4194 * 4195 * Return: True if the monitor supports audio, false otherwise. 4196 */ 4197bool drm_detect_monitor_audio(struct edid *edid) 4198{ 4199 u8 *edid_ext; 4200 int i, j; 4201 bool has_audio = false; 4202 int start_offset, end_offset; 4203 4204 edid_ext = drm_find_cea_extension(edid); 4205 if (!edid_ext) 4206 goto end; 4207 4208 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4209 4210 if (has_audio) { 4211 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4212 goto end; 4213 } 4214 4215 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4216 goto end; 4217 4218 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4219 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4220 has_audio = true; 4221 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4222 DRM_DEBUG_KMS("CEA audio format %d\n", 4223 (edid_ext[i + j] >> 3) & 0xf); 4224 goto end; 4225 } 4226 } 4227end: 4228 return has_audio; 4229} 4230EXPORT_SYMBOL(drm_detect_monitor_audio); 4231 4232/** 4233 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 4234 * @edid: EDID block to scan 4235 * 4236 * Check whether the monitor reports the RGB quantization range selection 4237 * as supported. The AVI infoframe can then be used to inform the monitor 4238 * which quantization range (full or limited) is used. 4239 * 4240 * Return: True if the RGB quantization range is selectable, false otherwise. 4241 */ 4242bool drm_rgb_quant_range_selectable(struct edid *edid) 4243{ 4244 u8 *edid_ext; 4245 int i, start, end; 4246 4247 edid_ext = drm_find_cea_extension(edid); 4248 if (!edid_ext) 4249 return false; 4250 4251 if (cea_db_offsets(edid_ext, &start, &end)) 4252 return false; 4253 4254 for_each_cea_db(edid_ext, i, start, end) { 4255 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG && 4256 cea_db_payload_len(&edid_ext[i]) == 2 && 4257 cea_db_extended_tag(&edid_ext[i]) == 4258 EXT_VIDEO_CAPABILITY_BLOCK) { 4259 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 4260 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 4261 } 4262 } 4263 4264 return false; 4265} 4266EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 4267 4268/** 4269 * drm_default_rgb_quant_range - default RGB quantization range 4270 * @mode: display mode 4271 * 4272 * Determine the default RGB quantization range for the mode, 4273 * as specified in CEA-861. 4274 * 4275 * Return: The default RGB quantization range for the mode 4276 */ 4277enum hdmi_quantization_range 4278drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4279{ 4280 /* All CEA modes other than VIC 1 use limited quantization range. */ 4281 return drm_match_cea_mode(mode) > 1 ? 4282 HDMI_QUANTIZATION_RANGE_LIMITED : 4283 HDMI_QUANTIZATION_RANGE_FULL; 4284} 4285EXPORT_SYMBOL(drm_default_rgb_quant_range); 4286 4287static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4288 const u8 *db) 4289{ 4290 u8 dc_mask; 4291 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4292 4293 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4294 hdmi->y420_dc_modes = dc_mask; 4295} 4296 4297static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4298 const u8 *hf_vsdb) 4299{ 4300 struct drm_display_info *display = &connector->display_info; 4301 struct drm_hdmi_info *hdmi = &display->hdmi; 4302 4303 display->has_hdmi_infoframe = true; 4304 4305 if (hf_vsdb[6] & 0x80) { 4306 hdmi->scdc.supported = true; 4307 if (hf_vsdb[6] & 0x40) 4308 hdmi->scdc.read_request = true; 4309 } 4310 4311 /* 4312 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4313 * And as per the spec, three factors confirm this: 4314 * * Availability of a HF-VSDB block in EDID (check) 4315 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4316 * * SCDC support available (let's check) 4317 * Lets check it out. 4318 */ 4319 4320 if (hf_vsdb[5]) { 4321 /* max clock is 5000 KHz times block value */ 4322 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4323 struct drm_scdc *scdc = &hdmi->scdc; 4324 4325 if (max_tmds_clock > 340000) { 4326 display->max_tmds_clock = max_tmds_clock; 4327 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4328 display->max_tmds_clock); 4329 } 4330 4331 if (scdc->supported) { 4332 scdc->scrambling.supported = true; 4333 4334 /* Few sinks support scrambling for cloks < 340M */ 4335 if ((hf_vsdb[6] & 0x8)) 4336 scdc->scrambling.low_rates = true; 4337 } 4338 } 4339 4340 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4341} 4342 4343static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4344 const u8 *hdmi) 4345{ 4346 struct drm_display_info *info = &connector->display_info; 4347 unsigned int dc_bpc = 0; 4348 4349 /* HDMI supports at least 8 bpc */ 4350 info->bpc = 8; 4351 4352 if (cea_db_payload_len(hdmi) < 6) 4353 return; 4354 4355 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4356 dc_bpc = 10; 4357 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4358 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4359 connector->name); 4360 } 4361 4362 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4363 dc_bpc = 12; 4364 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4365 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4366 connector->name); 4367 } 4368 4369 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4370 dc_bpc = 16; 4371 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4372 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4373 connector->name); 4374 } 4375 4376 if (dc_bpc == 0) { 4377 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4378 connector->name); 4379 return; 4380 } 4381 4382 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4383 connector->name, dc_bpc); 4384 info->bpc = dc_bpc; 4385 4386 /* 4387 * Deep color support mandates RGB444 support for all video 4388 * modes and forbids YCRCB422 support for all video modes per 4389 * HDMI 1.3 spec. 4390 */ 4391 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4392 4393 /* YCRCB444 is optional according to spec. */ 4394 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4395 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4396 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4397 connector->name); 4398 } 4399 4400 /* 4401 * Spec says that if any deep color mode is supported at all, 4402 * then deep color 36 bit must be supported. 4403 */ 4404 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4405 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4406 connector->name); 4407 } 4408} 4409 4410static void 4411drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4412{ 4413 struct drm_display_info *info = &connector->display_info; 4414 u8 len = cea_db_payload_len(db); 4415 4416 if (len >= 6) 4417 info->dvi_dual = db[6] & 1; 4418 if (len >= 7) 4419 info->max_tmds_clock = db[7] * 5000; 4420 4421 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4422 "max TMDS clock %d kHz\n", 4423 info->dvi_dual, 4424 info->max_tmds_clock); 4425 4426 drm_parse_hdmi_deep_color_info(connector, db); 4427} 4428 4429static void drm_parse_cea_ext(struct drm_connector *connector, 4430 const struct edid *edid) 4431{ 4432 struct drm_display_info *info = &connector->display_info; 4433 const u8 *edid_ext; 4434 int i, start, end; 4435 4436 edid_ext = drm_find_cea_extension(edid); 4437 if (!edid_ext) 4438 return; 4439 4440 info->cea_rev = edid_ext[1]; 4441 4442 /* The existence of a CEA block should imply RGB support */ 4443 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4444 if (edid_ext[3] & EDID_CEA_YCRCB444) 4445 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4446 if (edid_ext[3] & EDID_CEA_YCRCB422) 4447 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4448 4449 if (cea_db_offsets(edid_ext, &start, &end)) 4450 return; 4451 4452 for_each_cea_db(edid_ext, i, start, end) { 4453 const u8 *db = &edid_ext[i]; 4454 4455 if (cea_db_is_hdmi_vsdb(db)) 4456 drm_parse_hdmi_vsdb_video(connector, db); 4457 if (cea_db_is_hdmi_forum_vsdb(db)) 4458 drm_parse_hdmi_forum_vsdb(connector, db); 4459 if (cea_db_is_y420cmdb(db)) 4460 drm_parse_y420cmdb_bitmap(connector, db); 4461 } 4462} 4463 4464/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4465 * all of the values which would have been set from EDID 4466 */ 4467void 4468drm_reset_display_info(struct drm_connector *connector) 4469{ 4470 struct drm_display_info *info = &connector->display_info; 4471 4472 info->width_mm = 0; 4473 info->height_mm = 0; 4474 4475 info->bpc = 0; 4476 info->color_formats = 0; 4477 info->cea_rev = 0; 4478 info->max_tmds_clock = 0; 4479 info->dvi_dual = false; 4480 info->has_hdmi_infoframe = false; 4481 memset(&info->hdmi, 0, sizeof(info->hdmi)); 4482 4483 info->non_desktop = 0; 4484} 4485 4486u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 4487{ 4488 struct drm_display_info *info = &connector->display_info; 4489 4490 u32 quirks = edid_get_quirks(edid); 4491 4492 drm_reset_display_info(connector); 4493 4494 info->width_mm = edid->width_cm * 10; 4495 info->height_mm = edid->height_cm * 10; 4496 4497 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 4498 4499 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 4500 4501 if (edid->revision < 3) 4502 return quirks; 4503 4504 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4505 return quirks; 4506 4507 drm_parse_cea_ext(connector, edid); 4508 4509 /* 4510 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4511 * 4512 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4513 * tells us to assume 8 bpc color depth if the EDID doesn't have 4514 * extensions which tell otherwise. 4515 */ 4516 if ((info->bpc == 0) && (edid->revision < 4) && 4517 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 4518 info->bpc = 8; 4519 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4520 connector->name, info->bpc); 4521 } 4522 4523 /* Only defined for 1.4 with digital displays */ 4524 if (edid->revision < 4) 4525 return quirks; 4526 4527 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4528 case DRM_EDID_DIGITAL_DEPTH_6: 4529 info->bpc = 6; 4530 break; 4531 case DRM_EDID_DIGITAL_DEPTH_8: 4532 info->bpc = 8; 4533 break; 4534 case DRM_EDID_DIGITAL_DEPTH_10: 4535 info->bpc = 10; 4536 break; 4537 case DRM_EDID_DIGITAL_DEPTH_12: 4538 info->bpc = 12; 4539 break; 4540 case DRM_EDID_DIGITAL_DEPTH_14: 4541 info->bpc = 14; 4542 break; 4543 case DRM_EDID_DIGITAL_DEPTH_16: 4544 info->bpc = 16; 4545 break; 4546 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4547 default: 4548 info->bpc = 0; 4549 break; 4550 } 4551 4552 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4553 connector->name, info->bpc); 4554 4555 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4556 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4557 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4558 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4559 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4560 return quirks; 4561} 4562 4563static int validate_displayid(u8 *displayid, int length, int idx) 4564{ 4565 int i; 4566 u8 csum = 0; 4567 struct displayid_hdr *base; 4568 4569 base = (struct displayid_hdr *)&displayid[idx]; 4570 4571 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4572 base->rev, base->bytes, base->prod_id, base->ext_count); 4573 4574 if (base->bytes + 5 > length - idx) 4575 return -EINVAL; 4576 for (i = idx; i <= base->bytes + 5; i++) { 4577 csum += displayid[i]; 4578 } 4579 if (csum) { 4580 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 4581 return -EINVAL; 4582 } 4583 return 0; 4584} 4585 4586static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4587 struct displayid_detailed_timings_1 *timings) 4588{ 4589 struct drm_display_mode *mode; 4590 unsigned pixel_clock = (timings->pixel_clock[0] | 4591 (timings->pixel_clock[1] << 8) | 4592 (timings->pixel_clock[2] << 16)); 4593 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4594 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4595 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4596 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4597 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4598 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4599 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4600 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4601 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4602 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4603 mode = drm_mode_create(dev); 4604 if (!mode) 4605 return NULL; 4606 4607 mode->clock = pixel_clock * 10; 4608 mode->hdisplay = hactive; 4609 mode->hsync_start = mode->hdisplay + hsync; 4610 mode->hsync_end = mode->hsync_start + hsync_width; 4611 mode->htotal = mode->hdisplay + hblank; 4612 4613 mode->vdisplay = vactive; 4614 mode->vsync_start = mode->vdisplay + vsync; 4615 mode->vsync_end = mode->vsync_start + vsync_width; 4616 mode->vtotal = mode->vdisplay + vblank; 4617 4618 mode->flags = 0; 4619 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4620 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4621 mode->type = DRM_MODE_TYPE_DRIVER; 4622 4623 if (timings->flags & 0x80) 4624 mode->type |= DRM_MODE_TYPE_PREFERRED; 4625 mode->vrefresh = drm_mode_vrefresh(mode); 4626 drm_mode_set_name(mode); 4627 4628 return mode; 4629} 4630 4631static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4632 struct displayid_block *block) 4633{ 4634 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4635 int i; 4636 int num_timings; 4637 struct drm_display_mode *newmode; 4638 int num_modes = 0; 4639 /* blocks must be multiple of 20 bytes length */ 4640 if (block->num_bytes % 20) 4641 return 0; 4642 4643 num_timings = block->num_bytes / 20; 4644 for (i = 0; i < num_timings; i++) { 4645 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4646 4647 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4648 if (!newmode) 4649 continue; 4650 4651 drm_mode_probed_add(connector, newmode); 4652 num_modes++; 4653 } 4654 return num_modes; 4655} 4656 4657static int add_displayid_detailed_modes(struct drm_connector *connector, 4658 struct edid *edid) 4659{ 4660 u8 *displayid; 4661 int ret; 4662 int idx = 1; 4663 int length = EDID_LENGTH; 4664 struct displayid_block *block; 4665 int num_modes = 0; 4666 4667 displayid = drm_find_displayid_extension(edid); 4668 if (!displayid) 4669 return 0; 4670 4671 ret = validate_displayid(displayid, length, idx); 4672 if (ret) 4673 return 0; 4674 4675 idx += sizeof(struct displayid_hdr); 4676 while (block = (struct displayid_block *)&displayid[idx], 4677 idx + sizeof(struct displayid_block) <= length && 4678 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4679 block->num_bytes > 0) { 4680 idx += block->num_bytes + sizeof(struct displayid_block); 4681 switch (block->tag) { 4682 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4683 num_modes += add_displayid_detailed_1_modes(connector, block); 4684 break; 4685 } 4686 } 4687 return num_modes; 4688} 4689 4690/** 4691 * drm_add_edid_modes - add modes from EDID data, if available 4692 * @connector: connector we're probing 4693 * @edid: EDID data 4694 * 4695 * Add the specified modes to the connector's mode list. Also fills out the 4696 * &drm_display_info structure and ELD in @connector with any information which 4697 * can be derived from the edid. 4698 * 4699 * Return: The number of modes added or 0 if we couldn't find any. 4700 */ 4701int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4702{ 4703 int num_modes = 0; 4704 u32 quirks; 4705 4706 if (edid == NULL) { 4707 clear_eld(connector); 4708 return 0; 4709 } 4710 if (!drm_edid_is_valid(edid)) { 4711 clear_eld(connector); 4712 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4713 connector->name); 4714 return 0; 4715 } 4716 4717 drm_edid_to_eld(connector, edid); 4718 4719 /* 4720 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4721 * To avoid multiple parsing of same block, lets parse that map 4722 * from sink info, before parsing CEA modes. 4723 */ 4724 quirks = drm_add_display_info(connector, edid); 4725 4726 /* 4727 * EDID spec says modes should be preferred in this order: 4728 * - preferred detailed mode 4729 * - other detailed modes from base block 4730 * - detailed modes from extension blocks 4731 * - CVT 3-byte code modes 4732 * - standard timing codes 4733 * - established timing codes 4734 * - modes inferred from GTF or CVT range information 4735 * 4736 * We get this pretty much right. 4737 * 4738 * XXX order for additional mode types in extension blocks? 4739 */ 4740 num_modes += add_detailed_modes(connector, edid, quirks); 4741 num_modes += add_cvt_modes(connector, edid); 4742 num_modes += add_standard_modes(connector, edid); 4743 num_modes += add_established_modes(connector, edid); 4744 num_modes += add_cea_modes(connector, edid); 4745 num_modes += add_alternate_cea_modes(connector, edid); 4746 num_modes += add_displayid_detailed_modes(connector, edid); 4747 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4748 num_modes += add_inferred_modes(connector, edid); 4749 4750 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4751 edid_fixup_preferred(connector, quirks); 4752 4753 if (quirks & EDID_QUIRK_FORCE_6BPC) 4754 connector->display_info.bpc = 6; 4755 4756 if (quirks & EDID_QUIRK_FORCE_8BPC) 4757 connector->display_info.bpc = 8; 4758 4759 if (quirks & EDID_QUIRK_FORCE_10BPC) 4760 connector->display_info.bpc = 10; 4761 4762 if (quirks & EDID_QUIRK_FORCE_12BPC) 4763 connector->display_info.bpc = 12; 4764 4765 return num_modes; 4766} 4767EXPORT_SYMBOL(drm_add_edid_modes); 4768 4769/** 4770 * drm_add_modes_noedid - add modes for the connectors without EDID 4771 * @connector: connector we're probing 4772 * @hdisplay: the horizontal display limit 4773 * @vdisplay: the vertical display limit 4774 * 4775 * Add the specified modes to the connector's mode list. Only when the 4776 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4777 * 4778 * Return: The number of modes added or 0 if we couldn't find any. 4779 */ 4780int drm_add_modes_noedid(struct drm_connector *connector, 4781 int hdisplay, int vdisplay) 4782{ 4783 int i, count, num_modes = 0; 4784 struct drm_display_mode *mode; 4785 struct drm_device *dev = connector->dev; 4786 4787 count = ARRAY_SIZE(drm_dmt_modes); 4788 if (hdisplay < 0) 4789 hdisplay = 0; 4790 if (vdisplay < 0) 4791 vdisplay = 0; 4792 4793 for (i = 0; i < count; i++) { 4794 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4795 if (hdisplay && vdisplay) { 4796 /* 4797 * Only when two are valid, they will be used to check 4798 * whether the mode should be added to the mode list of 4799 * the connector. 4800 */ 4801 if (ptr->hdisplay > hdisplay || 4802 ptr->vdisplay > vdisplay) 4803 continue; 4804 } 4805 if (drm_mode_vrefresh(ptr) > 61) 4806 continue; 4807 mode = drm_mode_duplicate(dev, ptr); 4808 if (mode) { 4809 drm_mode_probed_add(connector, mode); 4810 num_modes++; 4811 } 4812 } 4813 return num_modes; 4814} 4815EXPORT_SYMBOL(drm_add_modes_noedid); 4816 4817/** 4818 * drm_set_preferred_mode - Sets the preferred mode of a connector 4819 * @connector: connector whose mode list should be processed 4820 * @hpref: horizontal resolution of preferred mode 4821 * @vpref: vertical resolution of preferred mode 4822 * 4823 * Marks a mode as preferred if it matches the resolution specified by @hpref 4824 * and @vpref. 4825 */ 4826void drm_set_preferred_mode(struct drm_connector *connector, 4827 int hpref, int vpref) 4828{ 4829 struct drm_display_mode *mode; 4830 4831 list_for_each_entry(mode, &connector->probed_modes, head) { 4832 if (mode->hdisplay == hpref && 4833 mode->vdisplay == vpref) 4834 mode->type |= DRM_MODE_TYPE_PREFERRED; 4835 } 4836} 4837EXPORT_SYMBOL(drm_set_preferred_mode); 4838 4839/** 4840 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4841 * data from a DRM display mode 4842 * @frame: HDMI AVI infoframe 4843 * @mode: DRM display mode 4844 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant 4845 * 4846 * Return: 0 on success or a negative error code on failure. 4847 */ 4848int 4849drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4850 const struct drm_display_mode *mode, 4851 bool is_hdmi2_sink) 4852{ 4853 enum hdmi_picture_aspect picture_aspect; 4854 int err; 4855 4856 if (!frame || !mode) 4857 return -EINVAL; 4858 4859 err = hdmi_avi_infoframe_init(frame); 4860 if (err < 0) 4861 return err; 4862 4863 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4864 frame->pixel_repeat = 1; 4865 4866 frame->video_code = drm_match_cea_mode(mode); 4867 4868 /* 4869 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 4870 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 4871 * have to make sure we dont break HDMI 1.4 sinks. 4872 */ 4873 if (!is_hdmi2_sink && frame->video_code > 64) 4874 frame->video_code = 0; 4875 4876 /* 4877 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 4878 * we should send its VIC in vendor infoframes, else send the 4879 * VIC in AVI infoframes. Lets check if this mode is present in 4880 * HDMI 1.4b 4K modes 4881 */ 4882 if (frame->video_code) { 4883 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 4884 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 4885 4886 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 4887 frame->video_code = 0; 4888 } 4889 4890 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4891 4892 /* 4893 * As some drivers don't support atomic, we can't use connector state. 4894 * So just initialize the frame with default values, just the same way 4895 * as it's done with other properties here. 4896 */ 4897 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 4898 frame->itc = 0; 4899 4900 /* 4901 * Populate picture aspect ratio from either 4902 * user input (if specified) or from the CEA mode list. 4903 */ 4904 picture_aspect = mode->picture_aspect_ratio; 4905 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) 4906 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code); 4907 4908 /* 4909 * The infoframe can't convey anything but none, 4:3 4910 * and 16:9, so if the user has asked for anything else 4911 * we can only satisfy it by specifying the right VIC. 4912 */ 4913 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 4914 if (picture_aspect != 4915 drm_get_cea_aspect_ratio(frame->video_code)) 4916 return -EINVAL; 4917 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4918 } 4919 4920 frame->picture_aspect = picture_aspect; 4921 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4922 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4923 4924 return 0; 4925} 4926EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4927 4928/** 4929 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 4930 * quantization range information 4931 * @frame: HDMI AVI infoframe 4932 * @mode: DRM display mode 4933 * @rgb_quant_range: RGB quantization range (Q) 4934 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 4935 * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations 4936 * 4937 * Note that @is_hdmi2_sink can be derived by looking at the 4938 * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc, 4939 * &drm_display_info.hdmi, which can be found in &drm_connector.display_info. 4940 */ 4941void 4942drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 4943 const struct drm_display_mode *mode, 4944 enum hdmi_quantization_range rgb_quant_range, 4945 bool rgb_quant_range_selectable, 4946 bool is_hdmi2_sink) 4947{ 4948 /* 4949 * CEA-861: 4950 * "A Source shall not send a non-zero Q value that does not correspond 4951 * to the default RGB Quantization Range for the transmitted Picture 4952 * unless the Sink indicates support for the Q bit in a Video 4953 * Capabilities Data Block." 4954 * 4955 * HDMI 2.0 recommends sending non-zero Q when it does match the 4956 * default RGB quantization range for the mode, even when QS=0. 4957 */ 4958 if (rgb_quant_range_selectable || 4959 rgb_quant_range == drm_default_rgb_quant_range(mode)) 4960 frame->quantization_range = rgb_quant_range; 4961 else 4962 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 4963 4964 /* 4965 * CEA-861-F: 4966 * "When transmitting any RGB colorimetry, the Source should set the 4967 * YQ-field to match the RGB Quantization Range being transmitted 4968 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 4969 * set YQ=1) and the Sink shall ignore the YQ-field." 4970 * 4971 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 4972 * by non-zero YQ when receiving RGB. There doesn't seem to be any 4973 * good way to tell which version of CEA-861 the sink supports, so 4974 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 4975 * on on CEA-861-F. 4976 */ 4977 if (!is_hdmi2_sink || 4978 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 4979 frame->ycc_quantization_range = 4980 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 4981 else 4982 frame->ycc_quantization_range = 4983 HDMI_YCC_QUANTIZATION_RANGE_FULL; 4984} 4985EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 4986 4987static enum hdmi_3d_structure 4988s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4989{ 4990 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4991 4992 switch (layout) { 4993 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4994 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4995 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4996 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4997 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4998 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4999 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5000 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5001 case DRM_MODE_FLAG_3D_L_DEPTH: 5002 return HDMI_3D_STRUCTURE_L_DEPTH; 5003 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5004 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5005 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5006 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5007 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5008 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5009 default: 5010 return HDMI_3D_STRUCTURE_INVALID; 5011 } 5012} 5013 5014/** 5015 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5016 * data from a DRM display mode 5017 * @frame: HDMI vendor infoframe 5018 * @connector: the connector 5019 * @mode: DRM display mode 5020 * 5021 * Note that there's is a need to send HDMI vendor infoframes only when using a 5022 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5023 * function will return -EINVAL, error that can be safely ignored. 5024 * 5025 * Return: 0 on success or a negative error code on failure. 5026 */ 5027int 5028drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5029 struct drm_connector *connector, 5030 const struct drm_display_mode *mode) 5031{ 5032 /* 5033 * FIXME: sil-sii8620 doesn't have a connector around when 5034 * we need one, so we have to be prepared for a NULL connector. 5035 */ 5036 bool has_hdmi_infoframe = connector ? 5037 connector->display_info.has_hdmi_infoframe : false; 5038 int err; 5039 u32 s3d_flags; 5040 u8 vic; 5041 5042 if (!frame || !mode) 5043 return -EINVAL; 5044 5045 if (!has_hdmi_infoframe) 5046 return -EINVAL; 5047 5048 vic = drm_match_hdmi_mode(mode); 5049 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5050 5051 /* 5052 * Even if it's not absolutely necessary to send the infoframe 5053 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5054 * know that the sink can handle it. This is based on a 5055 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5056 * have trouble realizing that they shuld switch from 3D to 2D 5057 * mode if the source simply stops sending the infoframe when 5058 * it wants to switch from 3D to 2D. 5059 */ 5060 5061 if (vic && s3d_flags) 5062 return -EINVAL; 5063 5064 err = hdmi_vendor_infoframe_init(frame); 5065 if (err < 0) 5066 return err; 5067 5068 frame->vic = vic; 5069 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5070 5071 return 0; 5072} 5073EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5074 5075static int drm_parse_tiled_block(struct drm_connector *connector, 5076 struct displayid_block *block) 5077{ 5078 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5079 u16 w, h; 5080 u8 tile_v_loc, tile_h_loc; 5081 u8 num_v_tile, num_h_tile; 5082 struct drm_tile_group *tg; 5083 5084 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5085 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5086 5087 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5088 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5089 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5090 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5091 5092 connector->has_tile = true; 5093 if (tile->tile_cap & 0x80) 5094 connector->tile_is_single_monitor = true; 5095 5096 connector->num_h_tile = num_h_tile + 1; 5097 connector->num_v_tile = num_v_tile + 1; 5098 connector->tile_h_loc = tile_h_loc; 5099 connector->tile_v_loc = tile_v_loc; 5100 connector->tile_h_size = w + 1; 5101 connector->tile_v_size = h + 1; 5102 5103 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5104 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5105 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5106 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5107 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5108 5109 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5110 if (!tg) { 5111 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5112 } 5113 if (!tg) 5114 return -ENOMEM; 5115 5116 if (connector->tile_group != tg) { 5117 /* if we haven't got a pointer, 5118 take the reference, drop ref to old tile group */ 5119 if (connector->tile_group) { 5120 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5121 } 5122 connector->tile_group = tg; 5123 } else 5124 /* if same tile group, then release the ref we just took. */ 5125 drm_mode_put_tile_group(connector->dev, tg); 5126 return 0; 5127} 5128 5129static int drm_parse_display_id(struct drm_connector *connector, 5130 u8 *displayid, int length, 5131 bool is_edid_extension) 5132{ 5133 /* if this is an EDID extension the first byte will be 0x70 */ 5134 int idx = 0; 5135 struct displayid_block *block; 5136 int ret; 5137 5138 if (is_edid_extension) 5139 idx = 1; 5140 5141 ret = validate_displayid(displayid, length, idx); 5142 if (ret) 5143 return ret; 5144 5145 idx += sizeof(struct displayid_hdr); 5146 while (block = (struct displayid_block *)&displayid[idx], 5147 idx + sizeof(struct displayid_block) <= length && 5148 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 5149 block->num_bytes > 0) { 5150 idx += block->num_bytes + sizeof(struct displayid_block); 5151 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5152 block->tag, block->rev, block->num_bytes); 5153 5154 switch (block->tag) { 5155 case DATA_BLOCK_TILED_DISPLAY: 5156 ret = drm_parse_tiled_block(connector, block); 5157 if (ret) 5158 return ret; 5159 break; 5160 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5161 /* handled in mode gathering code. */ 5162 break; 5163 default: 5164 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5165 break; 5166 } 5167 } 5168 return 0; 5169} 5170 5171static void drm_get_displayid(struct drm_connector *connector, 5172 struct edid *edid) 5173{ 5174 void *displayid = NULL; 5175 int ret; 5176 connector->has_tile = false; 5177 displayid = drm_find_displayid_extension(edid); 5178 if (!displayid) { 5179 /* drop reference to any tile group we had */ 5180 goto out_drop_ref; 5181 } 5182 5183 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5184 if (ret < 0) 5185 goto out_drop_ref; 5186 if (!connector->has_tile) 5187 goto out_drop_ref; 5188 return; 5189out_drop_ref: 5190 if (connector->tile_group) { 5191 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5192 connector->tile_group = NULL; 5193 } 5194 return; 5195} 5196