smu_v13_0.c revision 1.4
1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#include <linux/firmware.h> 24#include <linux/module.h> 25#include <linux/pci.h> 26#include <linux/reboot.h> 27 28#define SMU_13_0_PARTIAL_PPTABLE 29#define SWSMU_CODE_LAYER_L3 30 31#include "amdgpu.h" 32#include "amdgpu_smu.h" 33#include "atomfirmware.h" 34#include "amdgpu_atomfirmware.h" 35#include "amdgpu_atombios.h" 36#include "smu_v13_0.h" 37#include "soc15_common.h" 38#include "atom.h" 39#include "amdgpu_ras.h" 40#include "smu_cmn.h" 41 42#include "asic_reg/thm/thm_13_0_2_offset.h" 43#include "asic_reg/thm/thm_13_0_2_sh_mask.h" 44#include "asic_reg/mp/mp_13_0_2_offset.h" 45#include "asic_reg/mp/mp_13_0_2_sh_mask.h" 46#include "asic_reg/smuio/smuio_13_0_2_offset.h" 47#include "asic_reg/smuio/smuio_13_0_2_sh_mask.h" 48 49/* 50 * DO NOT use these for err/warn/info/debug messages. 51 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 52 * They are more MGPU friendly. 53 */ 54#undef pr_err 55#undef pr_warn 56#undef pr_info 57#undef pr_debug 58 59MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin"); 60MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin"); 61MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin"); 62MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin"); 63 64#define mmMP1_SMN_C2PMSG_66 0x0282 65#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 66 67#define mmMP1_SMN_C2PMSG_82 0x0292 68#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 69 70#define mmMP1_SMN_C2PMSG_90 0x029a 71#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 72 73#define SMU13_VOLTAGE_SCALE 4 74 75#define LINK_WIDTH_MAX 6 76#define LINK_SPEED_MAX 3 77 78#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 79#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L 80#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 81#define smnPCIE_LC_SPEED_CNTL 0x11140290 82#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000 83#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE 84 85static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 86static const int link_speed[] = {25, 50, 80, 160}; 87 88int smu_v13_0_init_microcode(struct smu_context *smu) 89{ 90 struct amdgpu_device *adev = smu->adev; 91 const char *chip_name; 92 char fw_name[30]; 93 char ucode_prefix[30]; 94 int err = 0; 95 const struct smc_firmware_header_v1_0 *hdr; 96 const struct common_firmware_header *header; 97 struct amdgpu_firmware_info *ucode = NULL; 98 99 /* doesn't need to load smu firmware in IOV mode */ 100 if (amdgpu_sriov_vf(adev)) 101 return 0; 102 103 switch (adev->ip_versions[MP1_HWIP][0]) { 104 case IP_VERSION(13, 0, 2): 105 chip_name = "aldebaran_smc"; 106 break; 107 default: 108 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); 109 chip_name = ucode_prefix; 110 } 111 112 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); 113 114 err = request_firmware(&adev->pm.fw, fw_name, adev->dev); 115 if (err) 116 goto out; 117 err = amdgpu_ucode_validate(adev->pm.fw); 118 if (err) 119 goto out; 120 121 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 122 amdgpu_ucode_print_smc_hdr(&hdr->header); 123 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 124 125 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 126 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 127 ucode->ucode_id = AMDGPU_UCODE_ID_SMC; 128 ucode->fw = adev->pm.fw; 129 header = (const struct common_firmware_header *)ucode->fw->data; 130 adev->firmware.fw_size += 131 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 132 } 133 134out: 135 if (err) { 136 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n", 137 fw_name); 138 release_firmware(adev->pm.fw); 139 adev->pm.fw = NULL; 140 } 141 return err; 142} 143 144void smu_v13_0_fini_microcode(struct smu_context *smu) 145{ 146 struct amdgpu_device *adev = smu->adev; 147 148 release_firmware(adev->pm.fw); 149 adev->pm.fw = NULL; 150 adev->pm.fw_version = 0; 151} 152 153int smu_v13_0_load_microcode(struct smu_context *smu) 154{ 155#if 0 156 struct amdgpu_device *adev = smu->adev; 157 const uint32_t *src; 158 const struct smc_firmware_header_v1_0 *hdr; 159 uint32_t addr_start = MP1_SRAM; 160 uint32_t i; 161 uint32_t smc_fw_size; 162 uint32_t mp1_fw_flags; 163 164 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 165 src = (const uint32_t *)(adev->pm.fw->data + 166 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 167 smc_fw_size = hdr->header.ucode_size_bytes; 168 169 for (i = 1; i < smc_fw_size/4 - 1; i++) { 170 WREG32_PCIE(addr_start, src[i]); 171 addr_start += 4; 172 } 173 174 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 175 1 & MP1_SMN_PUB_CTRL__RESET_MASK); 176 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 177 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK); 178 179 for (i = 0; i < adev->usec_timeout; i++) { 180 mp1_fw_flags = RREG32_PCIE(MP1_Public | 181 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 182 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 183 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 184 break; 185 udelay(1); 186 } 187 188 if (i == adev->usec_timeout) 189 return -ETIME; 190#endif 191 192 return 0; 193} 194 195int smu_v13_0_init_pptable_microcode(struct smu_context *smu) 196{ 197 struct amdgpu_device *adev = smu->adev; 198 struct amdgpu_firmware_info *ucode = NULL; 199 uint32_t size = 0, pptable_id = 0; 200 int ret = 0; 201 void *table; 202 203 /* doesn't need to load smu firmware in IOV mode */ 204 if (amdgpu_sriov_vf(adev)) 205 return 0; 206 207 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 208 return 0; 209 210 if (!adev->scpm_enabled) 211 return 0; 212 213 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7)) || 214 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) || 215 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10))) 216 return 0; 217 218 /* override pptable_id from driver parameter */ 219 if (amdgpu_smu_pptable_id >= 0) { 220 pptable_id = amdgpu_smu_pptable_id; 221 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 222 } else { 223 pptable_id = smu->smu_table.boot_values.pp_table_id; 224 } 225 226 /* "pptable_id == 0" means vbios carries the pptable. */ 227 if (!pptable_id) 228 return 0; 229 230 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 231 if (ret) 232 return ret; 233 234 smu->pptable_firmware.data = table; 235 smu->pptable_firmware.size = size; 236 237 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE]; 238 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE; 239 ucode->fw = &smu->pptable_firmware; 240 adev->firmware.fw_size += 241 roundup2(smu->pptable_firmware.size, PAGE_SIZE); 242 243 return 0; 244} 245 246int smu_v13_0_check_fw_status(struct smu_context *smu) 247{ 248 struct amdgpu_device *adev = smu->adev; 249 uint32_t mp1_fw_flags; 250 251 switch (adev->ip_versions[MP1_HWIP][0]) { 252 case IP_VERSION(13, 0, 4): 253 mp1_fw_flags = RREG32_PCIE(MP1_Public | 254 (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff)); 255 break; 256 default: 257 mp1_fw_flags = RREG32_PCIE(MP1_Public | 258 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 259 break; 260 } 261 262 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 263 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 264 return 0; 265 266 return -EIO; 267} 268 269int smu_v13_0_check_fw_version(struct smu_context *smu) 270{ 271 struct amdgpu_device *adev = smu->adev; 272 uint32_t if_version = 0xff, smu_version = 0xff; 273 uint8_t smu_program, smu_major, smu_minor, smu_debug; 274 int ret = 0; 275 276 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 277 if (ret) 278 return ret; 279 280 smu_program = (smu_version >> 24) & 0xff; 281 smu_major = (smu_version >> 16) & 0xff; 282 smu_minor = (smu_version >> 8) & 0xff; 283 smu_debug = (smu_version >> 0) & 0xff; 284 if (smu->is_apu) 285 adev->pm.fw_version = smu_version; 286 287 switch (adev->ip_versions[MP1_HWIP][0]) { 288 case IP_VERSION(13, 0, 2): 289 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE; 290 break; 291 case IP_VERSION(13, 0, 0): 292 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0; 293 break; 294 case IP_VERSION(13, 0, 10): 295 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10; 296 break; 297 case IP_VERSION(13, 0, 7): 298 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7; 299 break; 300 case IP_VERSION(13, 0, 1): 301 case IP_VERSION(13, 0, 3): 302 case IP_VERSION(13, 0, 8): 303 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP; 304 break; 305 case IP_VERSION(13, 0, 4): 306 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4; 307 break; 308 case IP_VERSION(13, 0, 5): 309 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5; 310 break; 311 default: 312 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n", 313 adev->ip_versions[MP1_HWIP][0]); 314 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV; 315 break; 316 } 317 318 /* only for dGPU w/ SMU13*/ 319 if (adev->pm.fw) 320 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n", 321 smu_program, smu_version, smu_major, smu_minor, smu_debug); 322 323 /* 324 * 1. if_version mismatch is not critical as our fw is designed 325 * to be backward compatible. 326 * 2. New fw usually brings some optimizations. But that's visible 327 * only on the paired driver. 328 * Considering above, we just leave user a warning message instead 329 * of halt driver loading. 330 */ 331 if (if_version != smu->smc_driver_if_version) { 332 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " 333 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", 334 smu->smc_driver_if_version, if_version, 335 smu_program, smu_version, smu_major, smu_minor, smu_debug); 336 dev_warn(adev->dev, "SMU driver if version not matched\n"); 337 } 338 339 return ret; 340} 341 342static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) 343{ 344 struct amdgpu_device *adev = smu->adev; 345 uint32_t ppt_offset_bytes; 346 const struct smc_firmware_header_v2_0 *v2; 347 348 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; 349 350 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); 351 *size = le32_to_cpu(v2->ppt_size_bytes); 352 *table = (uint8_t *)v2 + ppt_offset_bytes; 353 354 return 0; 355} 356 357static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table, 358 uint32_t *size, uint32_t pptable_id) 359{ 360 struct amdgpu_device *adev = smu->adev; 361 const struct smc_firmware_header_v2_1 *v2_1; 362 struct smc_soft_pptable_entry *entries; 363 uint32_t pptable_count = 0; 364 int i = 0; 365 366 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; 367 entries = (struct smc_soft_pptable_entry *) 368 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); 369 pptable_count = le32_to_cpu(v2_1->pptable_count); 370 for (i = 0; i < pptable_count; i++) { 371 if (le32_to_cpu(entries[i].id) == pptable_id) { 372 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); 373 *size = le32_to_cpu(entries[i].ppt_size_bytes); 374 break; 375 } 376 } 377 378 if (i == pptable_count) 379 return -EINVAL; 380 381 return 0; 382} 383 384static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size) 385{ 386 struct amdgpu_device *adev = smu->adev; 387 uint16_t atom_table_size; 388 uint8_t frev, crev; 389 int ret, index; 390 391 dev_info(adev->dev, "use vbios provided pptable\n"); 392 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 393 powerplayinfo); 394 395 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, 396 (uint8_t **)table); 397 if (ret) 398 return ret; 399 400 if (size) 401 *size = atom_table_size; 402 403 return 0; 404} 405 406int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, 407 void **table, 408 uint32_t *size, 409 uint32_t pptable_id) 410{ 411 const struct smc_firmware_header_v1_0 *hdr; 412 struct amdgpu_device *adev = smu->adev; 413 uint16_t version_major, version_minor; 414 int ret; 415 416 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 417 if (!hdr) 418 return -EINVAL; 419 420 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id); 421 422 version_major = le16_to_cpu(hdr->header.header_version_major); 423 version_minor = le16_to_cpu(hdr->header.header_version_minor); 424 if (version_major != 2) { 425 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n", 426 version_major, version_minor); 427 return -EINVAL; 428 } 429 430 switch (version_minor) { 431 case 0: 432 ret = smu_v13_0_set_pptable_v2_0(smu, table, size); 433 break; 434 case 1: 435 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id); 436 break; 437 default: 438 ret = -EINVAL; 439 break; 440 } 441 442 return ret; 443} 444 445int smu_v13_0_setup_pptable(struct smu_context *smu) 446{ 447 struct amdgpu_device *adev = smu->adev; 448 uint32_t size = 0, pptable_id = 0; 449 void *table; 450 int ret = 0; 451 452 /* override pptable_id from driver parameter */ 453 if (amdgpu_smu_pptable_id >= 0) { 454 pptable_id = amdgpu_smu_pptable_id; 455 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 456 } else { 457 pptable_id = smu->smu_table.boot_values.pp_table_id; 458 } 459 460 /* force using vbios pptable in sriov mode */ 461 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1)) 462 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size); 463 else 464 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 465 466 if (ret) 467 return ret; 468 469 if (!smu->smu_table.power_play_table) 470 smu->smu_table.power_play_table = table; 471 if (!smu->smu_table.power_play_table_size) 472 smu->smu_table.power_play_table_size = size; 473 474 return 0; 475} 476 477int smu_v13_0_init_smc_tables(struct smu_context *smu) 478{ 479 struct smu_table_context *smu_table = &smu->smu_table; 480 struct smu_table *tables = smu_table->tables; 481 int ret = 0; 482 483 smu_table->driver_pptable = 484 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); 485 if (!smu_table->driver_pptable) { 486 ret = -ENOMEM; 487 goto err0_out; 488 } 489 490 smu_table->max_sustainable_clocks = 491 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL); 492 if (!smu_table->max_sustainable_clocks) { 493 ret = -ENOMEM; 494 goto err1_out; 495 } 496 497 /* Aldebaran does not support OVERDRIVE */ 498 if (tables[SMU_TABLE_OVERDRIVE].size) { 499 smu_table->overdrive_table = 500 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 501 if (!smu_table->overdrive_table) { 502 ret = -ENOMEM; 503 goto err2_out; 504 } 505 506 smu_table->boot_overdrive_table = 507 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 508 if (!smu_table->boot_overdrive_table) { 509 ret = -ENOMEM; 510 goto err3_out; 511 } 512 } 513 514 smu_table->combo_pptable = 515 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL); 516 if (!smu_table->combo_pptable) { 517 ret = -ENOMEM; 518 goto err4_out; 519 } 520 521 return 0; 522 523err4_out: 524 kfree(smu_table->boot_overdrive_table); 525err3_out: 526 kfree(smu_table->overdrive_table); 527err2_out: 528 kfree(smu_table->max_sustainable_clocks); 529err1_out: 530 kfree(smu_table->driver_pptable); 531err0_out: 532 return ret; 533} 534 535int smu_v13_0_fini_smc_tables(struct smu_context *smu) 536{ 537 struct smu_table_context *smu_table = &smu->smu_table; 538 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 539 540 kfree(smu_table->gpu_metrics_table); 541 kfree(smu_table->combo_pptable); 542 kfree(smu_table->boot_overdrive_table); 543 kfree(smu_table->overdrive_table); 544 kfree(smu_table->max_sustainable_clocks); 545 kfree(smu_table->driver_pptable); 546 smu_table->gpu_metrics_table = NULL; 547 smu_table->combo_pptable = NULL; 548 smu_table->boot_overdrive_table = NULL; 549 smu_table->overdrive_table = NULL; 550 smu_table->max_sustainable_clocks = NULL; 551 smu_table->driver_pptable = NULL; 552 kfree(smu_table->hardcode_pptable); 553 smu_table->hardcode_pptable = NULL; 554 555 kfree(smu_table->ecc_table); 556 kfree(smu_table->metrics_table); 557 kfree(smu_table->watermarks_table); 558 smu_table->ecc_table = NULL; 559 smu_table->metrics_table = NULL; 560 smu_table->watermarks_table = NULL; 561 smu_table->metrics_time = 0; 562 563 kfree(smu_dpm->dpm_context); 564 kfree(smu_dpm->golden_dpm_context); 565 kfree(smu_dpm->dpm_current_power_state); 566 kfree(smu_dpm->dpm_request_power_state); 567 smu_dpm->dpm_context = NULL; 568 smu_dpm->golden_dpm_context = NULL; 569 smu_dpm->dpm_context_size = 0; 570 smu_dpm->dpm_current_power_state = NULL; 571 smu_dpm->dpm_request_power_state = NULL; 572 573 return 0; 574} 575 576int smu_v13_0_init_power(struct smu_context *smu) 577{ 578 struct smu_power_context *smu_power = &smu->smu_power; 579 580 if (smu_power->power_context || smu_power->power_context_size != 0) 581 return -EINVAL; 582 583 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 584 GFP_KERNEL); 585 if (!smu_power->power_context) 586 return -ENOMEM; 587 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context); 588 589 return 0; 590} 591 592int smu_v13_0_fini_power(struct smu_context *smu) 593{ 594 struct smu_power_context *smu_power = &smu->smu_power; 595 596 if (!smu_power->power_context || smu_power->power_context_size == 0) 597 return -EINVAL; 598 599 kfree(smu_power->power_context); 600 smu_power->power_context = NULL; 601 smu_power->power_context_size = 0; 602 603 return 0; 604} 605 606int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu) 607{ 608 int ret, index; 609 uint16_t size; 610 uint8_t frev, crev; 611 struct atom_common_table_header *header; 612 struct atom_firmware_info_v3_4 *v_3_4; 613 struct atom_firmware_info_v3_3 *v_3_3; 614 struct atom_firmware_info_v3_1 *v_3_1; 615 struct atom_smu_info_v3_6 *smu_info_v3_6; 616 struct atom_smu_info_v4_0 *smu_info_v4_0; 617 618 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 619 firmwareinfo); 620 621 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 622 (uint8_t **)&header); 623 if (ret) 624 return ret; 625 626 if (header->format_revision != 3) { 627 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n"); 628 return -EINVAL; 629 } 630 631 switch (header->content_revision) { 632 case 0: 633 case 1: 634 case 2: 635 v_3_1 = (struct atom_firmware_info_v3_1 *)header; 636 smu->smu_table.boot_values.revision = v_3_1->firmware_revision; 637 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; 638 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; 639 smu->smu_table.boot_values.socclk = 0; 640 smu->smu_table.boot_values.dcefclk = 0; 641 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; 642 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; 643 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; 644 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; 645 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; 646 smu->smu_table.boot_values.pp_table_id = 0; 647 break; 648 case 3: 649 v_3_3 = (struct atom_firmware_info_v3_3 *)header; 650 smu->smu_table.boot_values.revision = v_3_3->firmware_revision; 651 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; 652 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; 653 smu->smu_table.boot_values.socclk = 0; 654 smu->smu_table.boot_values.dcefclk = 0; 655 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; 656 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; 657 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; 658 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; 659 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; 660 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; 661 break; 662 case 4: 663 default: 664 v_3_4 = (struct atom_firmware_info_v3_4 *)header; 665 smu->smu_table.boot_values.revision = v_3_4->firmware_revision; 666 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz; 667 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; 668 smu->smu_table.boot_values.socclk = 0; 669 smu->smu_table.boot_values.dcefclk = 0; 670 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv; 671 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv; 672 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv; 673 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv; 674 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id; 675 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id; 676 break; 677 } 678 679 smu->smu_table.boot_values.format_revision = header->format_revision; 680 smu->smu_table.boot_values.content_revision = header->content_revision; 681 682 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 683 smu_info); 684 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 685 (uint8_t **)&header)) { 686 687 if ((frev == 3) && (crev == 6)) { 688 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header; 689 690 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz; 691 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz; 692 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz; 693 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz; 694 } else if ((frev == 3) && (crev == 1)) { 695 return 0; 696 } else if ((frev == 4) && (crev == 0)) { 697 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header; 698 699 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz; 700 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz; 701 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz; 702 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz; 703 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz; 704 } else { 705 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n", 706 (uint32_t)frev, (uint32_t)crev); 707 } 708 } 709 710 return 0; 711} 712 713 714int smu_v13_0_notify_memory_pool_location(struct smu_context *smu) 715{ 716 struct smu_table_context *smu_table = &smu->smu_table; 717 struct smu_table *memory_pool = &smu_table->memory_pool; 718 int ret = 0; 719 uint64_t address; 720 uint32_t address_low, address_high; 721 722 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) 723 return ret; 724 725 address = memory_pool->mc_address; 726 address_high = (uint32_t)upper_32_bits(address); 727 address_low = (uint32_t)lower_32_bits(address); 728 729 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, 730 address_high, NULL); 731 if (ret) 732 return ret; 733 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, 734 address_low, NULL); 735 if (ret) 736 return ret; 737 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, 738 (uint32_t)memory_pool->size, NULL); 739 if (ret) 740 return ret; 741 742 return ret; 743} 744 745int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) 746{ 747 int ret; 748 749 ret = smu_cmn_send_smc_msg_with_param(smu, 750 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL); 751 if (ret) 752 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!"); 753 754 return ret; 755} 756 757int smu_v13_0_set_driver_table_location(struct smu_context *smu) 758{ 759 struct smu_table *driver_table = &smu->smu_table.driver_table; 760 int ret = 0; 761 762 if (driver_table->mc_address) { 763 ret = smu_cmn_send_smc_msg_with_param(smu, 764 SMU_MSG_SetDriverDramAddrHigh, 765 upper_32_bits(driver_table->mc_address), 766 NULL); 767 if (!ret) 768 ret = smu_cmn_send_smc_msg_with_param(smu, 769 SMU_MSG_SetDriverDramAddrLow, 770 lower_32_bits(driver_table->mc_address), 771 NULL); 772 } 773 774 return ret; 775} 776 777int smu_v13_0_set_tool_table_location(struct smu_context *smu) 778{ 779 int ret = 0; 780 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; 781 782 if (tool_table->mc_address) { 783 ret = smu_cmn_send_smc_msg_with_param(smu, 784 SMU_MSG_SetToolsDramAddrHigh, 785 upper_32_bits(tool_table->mc_address), 786 NULL); 787 if (!ret) 788 ret = smu_cmn_send_smc_msg_with_param(smu, 789 SMU_MSG_SetToolsDramAddrLow, 790 lower_32_bits(tool_table->mc_address), 791 NULL); 792 } 793 794 return ret; 795} 796 797int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count) 798{ 799 int ret = 0; 800 801 if (!smu->pm_enabled) 802 return ret; 803 804 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL); 805 806 return ret; 807} 808 809int smu_v13_0_set_allowed_mask(struct smu_context *smu) 810{ 811 struct smu_feature *feature = &smu->smu_feature; 812 int ret = 0; 813 uint32_t feature_mask[2]; 814 815 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || 816 feature->feature_num < 64) 817 return -EINVAL; 818 819 bitmap_to_arr32(feature_mask, feature->allowed, 64); 820 821 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 822 feature_mask[1], NULL); 823 if (ret) 824 return ret; 825 826 return smu_cmn_send_smc_msg_with_param(smu, 827 SMU_MSG_SetAllowedFeaturesMaskLow, 828 feature_mask[0], 829 NULL); 830} 831 832int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable) 833{ 834 int ret = 0; 835 struct amdgpu_device *adev = smu->adev; 836 837 switch (adev->ip_versions[MP1_HWIP][0]) { 838 case IP_VERSION(13, 0, 0): 839 case IP_VERSION(13, 0, 1): 840 case IP_VERSION(13, 0, 3): 841 case IP_VERSION(13, 0, 4): 842 case IP_VERSION(13, 0, 5): 843 case IP_VERSION(13, 0, 7): 844 case IP_VERSION(13, 0, 8): 845 case IP_VERSION(13, 0, 10): 846 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 847 return 0; 848 if (enable) 849 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); 850 else 851 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); 852 break; 853 default: 854 break; 855 } 856 857 return ret; 858} 859 860int smu_v13_0_system_features_control(struct smu_context *smu, 861 bool en) 862{ 863 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : 864 SMU_MSG_DisableAllSmuFeatures), NULL); 865} 866 867int smu_v13_0_notify_display_change(struct smu_context *smu) 868{ 869 int ret = 0; 870 871 if (!smu->pm_enabled) 872 return ret; 873 874 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 875 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) 876 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); 877 878 return ret; 879} 880 881 static int 882smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock, 883 enum smu_clk_type clock_select) 884{ 885 int ret = 0; 886 int clk_id; 887 888 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) || 889 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0)) 890 return 0; 891 892 clk_id = smu_cmn_to_asic_specific_index(smu, 893 CMN2ASIC_MAPPING_CLK, 894 clock_select); 895 if (clk_id < 0) 896 return -EINVAL; 897 898 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq, 899 clk_id << 16, clock); 900 if (ret) { 901 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!"); 902 return ret; 903 } 904 905 if (*clock != 0) 906 return 0; 907 908 /* if DC limit is zero, return AC limit */ 909 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, 910 clk_id << 16, clock); 911 if (ret) { 912 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!"); 913 return ret; 914 } 915 916 return 0; 917} 918 919int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu) 920{ 921 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks = 922 smu->smu_table.max_sustainable_clocks; 923 int ret = 0; 924 925 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; 926 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; 927 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; 928 max_sustainable_clocks->display_clock = 0xFFFFFFFF; 929 max_sustainable_clocks->phy_clock = 0xFFFFFFFF; 930 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; 931 932 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 933 ret = smu_v13_0_get_max_sustainable_clock(smu, 934 &(max_sustainable_clocks->uclock), 935 SMU_UCLK); 936 if (ret) { 937 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!", 938 __func__); 939 return ret; 940 } 941 } 942 943 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 944 ret = smu_v13_0_get_max_sustainable_clock(smu, 945 &(max_sustainable_clocks->soc_clock), 946 SMU_SOCCLK); 947 if (ret) { 948 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!", 949 __func__); 950 return ret; 951 } 952 } 953 954 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 955 ret = smu_v13_0_get_max_sustainable_clock(smu, 956 &(max_sustainable_clocks->dcef_clock), 957 SMU_DCEFCLK); 958 if (ret) { 959 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!", 960 __func__); 961 return ret; 962 } 963 964 ret = smu_v13_0_get_max_sustainable_clock(smu, 965 &(max_sustainable_clocks->display_clock), 966 SMU_DISPCLK); 967 if (ret) { 968 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!", 969 __func__); 970 return ret; 971 } 972 ret = smu_v13_0_get_max_sustainable_clock(smu, 973 &(max_sustainable_clocks->phy_clock), 974 SMU_PHYCLK); 975 if (ret) { 976 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!", 977 __func__); 978 return ret; 979 } 980 ret = smu_v13_0_get_max_sustainable_clock(smu, 981 &(max_sustainable_clocks->pixel_clock), 982 SMU_PIXCLK); 983 if (ret) { 984 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!", 985 __func__); 986 return ret; 987 } 988 } 989 990 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) 991 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; 992 993 return 0; 994} 995 996int smu_v13_0_get_current_power_limit(struct smu_context *smu, 997 uint32_t *power_limit) 998{ 999 int power_src; 1000 int ret = 0; 1001 1002 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 1003 return -EINVAL; 1004 1005 power_src = smu_cmn_to_asic_specific_index(smu, 1006 CMN2ASIC_MAPPING_PWR, 1007 smu->adev->pm.ac_power ? 1008 SMU_POWER_SOURCE_AC : 1009 SMU_POWER_SOURCE_DC); 1010 if (power_src < 0) 1011 return -EINVAL; 1012 1013 ret = smu_cmn_send_smc_msg_with_param(smu, 1014 SMU_MSG_GetPptLimit, 1015 power_src << 16, 1016 power_limit); 1017 if (ret) 1018 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); 1019 1020 return ret; 1021} 1022 1023int smu_v13_0_set_power_limit(struct smu_context *smu, 1024 enum smu_ppt_limit_type limit_type, 1025 uint32_t limit) 1026{ 1027 int ret = 0; 1028 1029 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 1030 return -EINVAL; 1031 1032 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1033 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 1034 return -EOPNOTSUPP; 1035 } 1036 1037 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL); 1038 if (ret) { 1039 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); 1040 return ret; 1041 } 1042 1043 smu->current_power_limit = limit; 1044 1045 return 0; 1046} 1047 1048static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu) 1049{ 1050 return smu_cmn_send_smc_msg(smu, 1051 SMU_MSG_AllowIHHostInterrupt, 1052 NULL); 1053} 1054 1055static int smu_v13_0_process_pending_interrupt(struct smu_context *smu) 1056{ 1057 int ret = 0; 1058 1059 if (smu->dc_controlled_by_gpio && 1060 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) 1061 ret = smu_v13_0_allow_ih_interrupt(smu); 1062 1063 return ret; 1064} 1065 1066int smu_v13_0_enable_thermal_alert(struct smu_context *smu) 1067{ 1068 int ret = 0; 1069 1070 if (!smu->irq_source.num_types) 1071 return 0; 1072 1073 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0); 1074 if (ret) 1075 return ret; 1076 1077 return smu_v13_0_process_pending_interrupt(smu); 1078} 1079 1080int smu_v13_0_disable_thermal_alert(struct smu_context *smu) 1081{ 1082 if (!smu->irq_source.num_types) 1083 return 0; 1084 1085 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); 1086} 1087 1088static uint16_t convert_to_vddc(uint8_t vid) 1089{ 1090 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE); 1091} 1092 1093int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value) 1094{ 1095 struct amdgpu_device *adev = smu->adev; 1096 uint32_t vdd = 0, val_vid = 0; 1097 1098 if (!value) 1099 return -EINVAL; 1100 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) & 1101 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> 1102 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; 1103 1104 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid); 1105 1106 *value = vdd; 1107 1108 return 0; 1109 1110} 1111 1112int 1113smu_v13_0_display_clock_voltage_request(struct smu_context *smu, 1114 struct pp_display_clock_request 1115 *clock_req) 1116{ 1117 enum amd_pp_clock_type clk_type = clock_req->clock_type; 1118 int ret = 0; 1119 enum smu_clk_type clk_select = 0; 1120 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1121 1122 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || 1123 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1124 switch (clk_type) { 1125 case amd_pp_dcef_clock: 1126 clk_select = SMU_DCEFCLK; 1127 break; 1128 case amd_pp_disp_clock: 1129 clk_select = SMU_DISPCLK; 1130 break; 1131 case amd_pp_pixel_clock: 1132 clk_select = SMU_PIXCLK; 1133 break; 1134 case amd_pp_phy_clock: 1135 clk_select = SMU_PHYCLK; 1136 break; 1137 case amd_pp_mem_clock: 1138 clk_select = SMU_UCLK; 1139 break; 1140 default: 1141 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__); 1142 ret = -EINVAL; 1143 break; 1144 } 1145 1146 if (ret) 1147 goto failed; 1148 1149 if (clk_select == SMU_UCLK && smu->disable_uclk_switch) 1150 return 0; 1151 1152 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); 1153 1154 if(clk_select == SMU_UCLK) 1155 smu->hard_min_uclk_req_from_dal = clk_freq; 1156 } 1157 1158failed: 1159 return ret; 1160} 1161 1162uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu) 1163{ 1164 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1165 return AMD_FAN_CTRL_MANUAL; 1166 else 1167 return AMD_FAN_CTRL_AUTO; 1168} 1169 1170 static int 1171smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control) 1172{ 1173 int ret = 0; 1174 1175 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1176 return 0; 1177 1178 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control); 1179 if (ret) 1180 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!", 1181 __func__, (auto_fan_control ? "Start" : "Stop")); 1182 1183 return ret; 1184} 1185 1186 static int 1187smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) 1188{ 1189 struct amdgpu_device *adev = smu->adev; 1190 1191 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2, 1192 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2), 1193 CG_FDO_CTRL2, TMIN, 0)); 1194 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2, 1195 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2), 1196 CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 1197 1198 return 0; 1199} 1200 1201int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu, 1202 uint32_t speed) 1203{ 1204 struct amdgpu_device *adev = smu->adev; 1205 uint32_t duty100, duty; 1206 uint64_t tmp64; 1207 1208 speed = MIN(speed, 255); 1209 1210 if (smu_v13_0_auto_fan_control(smu, 0)) 1211 return -EINVAL; 1212 1213 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1), 1214 CG_FDO_CTRL1, FMAX_DUTY100); 1215 if (!duty100) 1216 return -EINVAL; 1217 1218 tmp64 = (uint64_t)speed * duty100; 1219 do_div(tmp64, 255); 1220 duty = (uint32_t)tmp64; 1221 1222 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0, 1223 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0), 1224 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 1225 1226 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); 1227} 1228 1229 int 1230smu_v13_0_set_fan_control_mode(struct smu_context *smu, 1231 uint32_t mode) 1232{ 1233 int ret = 0; 1234 1235 switch (mode) { 1236 case AMD_FAN_CTRL_NONE: 1237 ret = smu_v13_0_set_fan_speed_pwm(smu, 255); 1238 break; 1239 case AMD_FAN_CTRL_MANUAL: 1240 ret = smu_v13_0_auto_fan_control(smu, 0); 1241 break; 1242 case AMD_FAN_CTRL_AUTO: 1243 ret = smu_v13_0_auto_fan_control(smu, 1); 1244 break; 1245 default: 1246 break; 1247 } 1248 1249 if (ret) { 1250 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__); 1251 return -EINVAL; 1252 } 1253 1254 return ret; 1255} 1256 1257int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, 1258 uint32_t speed) 1259{ 1260 struct amdgpu_device *adev = smu->adev; 1261 uint32_t tach_period, crystal_clock_freq; 1262 int ret; 1263 1264 if (!speed) 1265 return -EINVAL; 1266 1267 ret = smu_v13_0_auto_fan_control(smu, 0); 1268 if (ret) 1269 return ret; 1270 1271 crystal_clock_freq = amdgpu_asic_get_xclk(adev); 1272 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 1273 WREG32_SOC15(THM, 0, regCG_TACH_CTRL, 1274 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL), 1275 CG_TACH_CTRL, TARGET_PERIOD, 1276 tach_period)); 1277 1278 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); 1279} 1280 1281int smu_v13_0_set_xgmi_pstate(struct smu_context *smu, 1282 uint32_t pstate) 1283{ 1284 int ret = 0; 1285 ret = smu_cmn_send_smc_msg_with_param(smu, 1286 SMU_MSG_SetXgmiMode, 1287 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, 1288 NULL); 1289 return ret; 1290} 1291 1292static int smu_v13_0_set_irq_state(struct amdgpu_device *adev, 1293 struct amdgpu_irq_src *source, 1294 unsigned tyep, 1295 enum amdgpu_interrupt_state state) 1296{ 1297 struct smu_context *smu = adev->powerplay.pp_handle; 1298 uint32_t low, high; 1299 uint32_t val = 0; 1300 1301 switch (state) { 1302 case AMDGPU_IRQ_STATE_DISABLE: 1303 /* For THM irqs */ 1304 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 1305 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); 1306 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1); 1307 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val); 1308 1309 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0); 1310 1311 /* For MP1 SW irqs */ 1312 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 1313 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 1314 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 1315 1316 break; 1317 case AMDGPU_IRQ_STATE_ENABLE: 1318 /* For THM irqs */ 1319 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, 1320 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); 1321 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, 1322 smu->thermal_range.software_shutdown_temp); 1323 1324 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 1325 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 1326 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 1327 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); 1328 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); 1329 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); 1330 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); 1331 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1332 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val); 1333 1334 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); 1335 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 1336 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 1337 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val); 1338 1339 /* For MP1 SW irqs */ 1340 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); 1341 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 1342 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 1343 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); 1344 1345 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 1346 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 1347 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 1348 1349 break; 1350 default: 1351 break; 1352 } 1353 1354 return 0; 1355} 1356 1357static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu) 1358{ 1359 return smu_cmn_send_smc_msg(smu, 1360 SMU_MSG_ReenableAcDcInterrupt, 1361 NULL); 1362} 1363 1364#define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ 1365#define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ 1366#define SMUIO_11_0__SRCID__SMUIO_GPIO19 83 1367 1368static int smu_v13_0_irq_process(struct amdgpu_device *adev, 1369 struct amdgpu_irq_src *source, 1370 struct amdgpu_iv_entry *entry) 1371{ 1372 struct smu_context *smu = adev->powerplay.pp_handle; 1373 uint32_t client_id = entry->client_id; 1374 uint32_t src_id = entry->src_id; 1375 /* 1376 * ctxid is used to distinguish different 1377 * events for SMCToHost interrupt. 1378 */ 1379 uint32_t ctxid = entry->src_data[0]; 1380 uint32_t data; 1381 1382 if (client_id == SOC15_IH_CLIENTID_THM) { 1383 switch (src_id) { 1384 case THM_11_0__SRCID__THM_DIG_THERM_L2H: 1385 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1386 /* 1387 * SW CTF just occurred. 1388 * Try to do a graceful shutdown to prevent further damage. 1389 */ 1390 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1391 orderly_poweroff(true); 1392 break; 1393 case THM_11_0__SRCID__THM_DIG_THERM_H2L: 1394 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); 1395 break; 1396 default: 1397 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", 1398 src_id); 1399 break; 1400 } 1401 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) { 1402 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n"); 1403 /* 1404 * HW CTF just occurred. Shutdown to prevent further damage. 1405 */ 1406 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n"); 1407 orderly_poweroff(true); 1408 } else if (client_id == SOC15_IH_CLIENTID_MP1) { 1409 if (src_id == 0xfe) { 1410 /* ACK SMUToHost interrupt */ 1411 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 1412 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); 1413 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); 1414 1415 switch (ctxid) { 1416 case 0x3: 1417 dev_dbg(adev->dev, "Switched to AC mode!\n"); 1418 smu_v13_0_ack_ac_dc_interrupt(smu); 1419 break; 1420 case 0x4: 1421 dev_dbg(adev->dev, "Switched to DC mode!\n"); 1422 smu_v13_0_ack_ac_dc_interrupt(smu); 1423 break; 1424 case 0x7: 1425 /* 1426 * Increment the throttle interrupt counter 1427 */ 1428 atomic64_inc(&smu->throttle_int_counter); 1429 1430 if (!atomic_read(&adev->throttling_logging_enabled)) 1431 return 0; 1432 1433 if (__ratelimit(&adev->throttling_logging_rs)) 1434 schedule_work(&smu->throttling_logging_work); 1435 1436 break; 1437 } 1438 } 1439 } 1440 1441 return 0; 1442} 1443 1444static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = 1445{ 1446 .set = smu_v13_0_set_irq_state, 1447 .process = smu_v13_0_irq_process, 1448}; 1449 1450int smu_v13_0_register_irq_handler(struct smu_context *smu) 1451{ 1452 struct amdgpu_device *adev = smu->adev; 1453 struct amdgpu_irq_src *irq_src = &smu->irq_source; 1454 int ret = 0; 1455 1456 if (amdgpu_sriov_vf(adev)) 1457 return 0; 1458 1459 irq_src->num_types = 1; 1460 irq_src->funcs = &smu_v13_0_irq_funcs; 1461 1462 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1463 THM_11_0__SRCID__THM_DIG_THERM_L2H, 1464 irq_src); 1465 if (ret) 1466 return ret; 1467 1468 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1469 THM_11_0__SRCID__THM_DIG_THERM_H2L, 1470 irq_src); 1471 if (ret) 1472 return ret; 1473 1474 /* Register CTF(GPIO_19) interrupt */ 1475 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO, 1476 SMUIO_11_0__SRCID__SMUIO_GPIO19, 1477 irq_src); 1478 if (ret) 1479 return ret; 1480 1481 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, 1482 0xfe, 1483 irq_src); 1484 if (ret) 1485 return ret; 1486 1487 return ret; 1488} 1489 1490int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 1491 struct pp_smu_nv_clock_table *max_clocks) 1492{ 1493 struct smu_table_context *table_context = &smu->smu_table; 1494 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL; 1495 1496 if (!max_clocks || !table_context->max_sustainable_clocks) 1497 return -EINVAL; 1498 1499 sustainable_clocks = table_context->max_sustainable_clocks; 1500 1501 max_clocks->dcfClockInKhz = 1502 (unsigned int) sustainable_clocks->dcef_clock * 1000; 1503 max_clocks->displayClockInKhz = 1504 (unsigned int) sustainable_clocks->display_clock * 1000; 1505 max_clocks->phyClockInKhz = 1506 (unsigned int) sustainable_clocks->phy_clock * 1000; 1507 max_clocks->pixelClockInKhz = 1508 (unsigned int) sustainable_clocks->pixel_clock * 1000; 1509 max_clocks->uClockInKhz = 1510 (unsigned int) sustainable_clocks->uclock * 1000; 1511 max_clocks->socClockInKhz = 1512 (unsigned int) sustainable_clocks->soc_clock * 1000; 1513 max_clocks->dscClockInKhz = 0; 1514 max_clocks->dppClockInKhz = 0; 1515 max_clocks->fabricClockInKhz = 0; 1516 1517 return 0; 1518} 1519 1520int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu) 1521{ 1522 int ret = 0; 1523 1524 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL); 1525 1526 return ret; 1527} 1528 1529static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu, 1530 uint64_t event_arg) 1531{ 1532 int ret = 0; 1533 1534 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n"); 1535 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL); 1536 1537 return ret; 1538} 1539 1540int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1541 uint64_t event_arg) 1542{ 1543 int ret = -EINVAL; 1544 1545 switch (event) { 1546 case SMU_EVENT_RESET_COMPLETE: 1547 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg); 1548 break; 1549 default: 1550 break; 1551 } 1552 1553 return ret; 1554} 1555 1556int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 1557 uint32_t *min, uint32_t *max) 1558{ 1559 int ret = 0, clk_id = 0; 1560 uint32_t param = 0; 1561 uint32_t clock_limit; 1562 1563 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 1564 switch (clk_type) { 1565 case SMU_MCLK: 1566 case SMU_UCLK: 1567 clock_limit = smu->smu_table.boot_values.uclk; 1568 break; 1569 case SMU_GFXCLK: 1570 case SMU_SCLK: 1571 clock_limit = smu->smu_table.boot_values.gfxclk; 1572 break; 1573 case SMU_SOCCLK: 1574 clock_limit = smu->smu_table.boot_values.socclk; 1575 break; 1576 default: 1577 clock_limit = 0; 1578 break; 1579 } 1580 1581 /* clock in Mhz unit */ 1582 if (min) 1583 *min = clock_limit / 100; 1584 if (max) 1585 *max = clock_limit / 100; 1586 1587 return 0; 1588 } 1589 1590 clk_id = smu_cmn_to_asic_specific_index(smu, 1591 CMN2ASIC_MAPPING_CLK, 1592 clk_type); 1593 if (clk_id < 0) { 1594 ret = -EINVAL; 1595 goto failed; 1596 } 1597 param = (clk_id & 0xffff) << 16; 1598 1599 if (max) { 1600 if (smu->adev->pm.ac_power) 1601 ret = smu_cmn_send_smc_msg_with_param(smu, 1602 SMU_MSG_GetMaxDpmFreq, 1603 param, 1604 max); 1605 else 1606 ret = smu_cmn_send_smc_msg_with_param(smu, 1607 SMU_MSG_GetDcModeMaxDpmFreq, 1608 param, 1609 max); 1610 if (ret) 1611 goto failed; 1612 } 1613 1614 if (min) { 1615 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); 1616 if (ret) 1617 goto failed; 1618 } 1619 1620failed: 1621 return ret; 1622} 1623 1624int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, 1625 enum smu_clk_type clk_type, 1626 uint32_t min, 1627 uint32_t max) 1628{ 1629 int ret = 0, clk_id = 0; 1630 uint32_t param; 1631 1632 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1633 return 0; 1634 1635 clk_id = smu_cmn_to_asic_specific_index(smu, 1636 CMN2ASIC_MAPPING_CLK, 1637 clk_type); 1638 if (clk_id < 0) 1639 return clk_id; 1640 1641 if (max > 0) { 1642 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1643 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, 1644 param, NULL); 1645 if (ret) 1646 goto out; 1647 } 1648 1649 if (min > 0) { 1650 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1651 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, 1652 param, NULL); 1653 if (ret) 1654 goto out; 1655 } 1656 1657out: 1658 return ret; 1659} 1660 1661int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, 1662 enum smu_clk_type clk_type, 1663 uint32_t min, 1664 uint32_t max) 1665{ 1666 int ret = 0, clk_id = 0; 1667 uint32_t param; 1668 1669 if (min <= 0 && max <= 0) 1670 return -EINVAL; 1671 1672 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1673 return 0; 1674 1675 clk_id = smu_cmn_to_asic_specific_index(smu, 1676 CMN2ASIC_MAPPING_CLK, 1677 clk_type); 1678 if (clk_id < 0) 1679 return clk_id; 1680 1681 if (max > 0) { 1682 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1683 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, 1684 param, NULL); 1685 if (ret) 1686 return ret; 1687 } 1688 1689 if (min > 0) { 1690 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1691 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, 1692 param, NULL); 1693 if (ret) 1694 return ret; 1695 } 1696 1697 return ret; 1698} 1699 1700int smu_v13_0_set_performance_level(struct smu_context *smu, 1701 enum amd_dpm_forced_level level) 1702{ 1703 struct smu_13_0_dpm_context *dpm_context = 1704 smu->smu_dpm.dpm_context; 1705 struct smu_13_0_dpm_table *gfx_table = 1706 &dpm_context->dpm_tables.gfx_table; 1707 struct smu_13_0_dpm_table *mem_table = 1708 &dpm_context->dpm_tables.uclk_table; 1709 struct smu_13_0_dpm_table *soc_table = 1710 &dpm_context->dpm_tables.soc_table; 1711 struct smu_13_0_dpm_table *vclk_table = 1712 &dpm_context->dpm_tables.vclk_table; 1713 struct smu_13_0_dpm_table *dclk_table = 1714 &dpm_context->dpm_tables.dclk_table; 1715 struct smu_13_0_dpm_table *fclk_table = 1716 &dpm_context->dpm_tables.fclk_table; 1717 struct smu_umd_pstate_table *pstate_table = 1718 &smu->pstate_table; 1719 struct amdgpu_device *adev = smu->adev; 1720 uint32_t sclk_min = 0, sclk_max = 0; 1721 uint32_t mclk_min = 0, mclk_max = 0; 1722 uint32_t socclk_min = 0, socclk_max = 0; 1723 uint32_t vclk_min = 0, vclk_max = 0; 1724 uint32_t dclk_min = 0, dclk_max = 0; 1725 uint32_t fclk_min = 0, fclk_max = 0; 1726 int ret = 0, i; 1727 1728 switch (level) { 1729 case AMD_DPM_FORCED_LEVEL_HIGH: 1730 sclk_min = sclk_max = gfx_table->max; 1731 mclk_min = mclk_max = mem_table->max; 1732 socclk_min = socclk_max = soc_table->max; 1733 vclk_min = vclk_max = vclk_table->max; 1734 dclk_min = dclk_max = dclk_table->max; 1735 fclk_min = fclk_max = fclk_table->max; 1736 break; 1737 case AMD_DPM_FORCED_LEVEL_LOW: 1738 sclk_min = sclk_max = gfx_table->min; 1739 mclk_min = mclk_max = mem_table->min; 1740 socclk_min = socclk_max = soc_table->min; 1741 vclk_min = vclk_max = vclk_table->min; 1742 dclk_min = dclk_max = dclk_table->min; 1743 fclk_min = fclk_max = fclk_table->min; 1744 break; 1745 case AMD_DPM_FORCED_LEVEL_AUTO: 1746 sclk_min = gfx_table->min; 1747 sclk_max = gfx_table->max; 1748 mclk_min = mem_table->min; 1749 mclk_max = mem_table->max; 1750 socclk_min = soc_table->min; 1751 socclk_max = soc_table->max; 1752 vclk_min = vclk_table->min; 1753 vclk_max = vclk_table->max; 1754 dclk_min = dclk_table->min; 1755 dclk_max = dclk_table->max; 1756 fclk_min = fclk_table->min; 1757 fclk_max = fclk_table->max; 1758 break; 1759 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1760 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; 1761 mclk_min = mclk_max = pstate_table->uclk_pstate.standard; 1762 socclk_min = socclk_max = pstate_table->socclk_pstate.standard; 1763 vclk_min = vclk_max = pstate_table->vclk_pstate.standard; 1764 dclk_min = dclk_max = pstate_table->dclk_pstate.standard; 1765 fclk_min = fclk_max = pstate_table->fclk_pstate.standard; 1766 break; 1767 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1768 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; 1769 break; 1770 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1771 mclk_min = mclk_max = pstate_table->uclk_pstate.min; 1772 break; 1773 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1774 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; 1775 mclk_min = mclk_max = pstate_table->uclk_pstate.peak; 1776 socclk_min = socclk_max = pstate_table->socclk_pstate.peak; 1777 vclk_min = vclk_max = pstate_table->vclk_pstate.peak; 1778 dclk_min = dclk_max = pstate_table->dclk_pstate.peak; 1779 fclk_min = fclk_max = pstate_table->fclk_pstate.peak; 1780 break; 1781 case AMD_DPM_FORCED_LEVEL_MANUAL: 1782 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1783 return 0; 1784 default: 1785 dev_err(adev->dev, "Invalid performance level %d\n", level); 1786 return -EINVAL; 1787 } 1788 1789 /* 1790 * Unset those settings for SMU 13.0.2. As soft limits settings 1791 * for those clock domains are not supported. 1792 */ 1793 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) { 1794 mclk_min = mclk_max = 0; 1795 socclk_min = socclk_max = 0; 1796 vclk_min = vclk_max = 0; 1797 dclk_min = dclk_max = 0; 1798 fclk_min = fclk_max = 0; 1799 } 1800 1801 if (sclk_min && sclk_max) { 1802 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1803 SMU_GFXCLK, 1804 sclk_min, 1805 sclk_max); 1806 if (ret) 1807 return ret; 1808 1809 pstate_table->gfxclk_pstate.curr.min = sclk_min; 1810 pstate_table->gfxclk_pstate.curr.max = sclk_max; 1811 } 1812 1813 if (mclk_min && mclk_max) { 1814 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1815 SMU_MCLK, 1816 mclk_min, 1817 mclk_max); 1818 if (ret) 1819 return ret; 1820 1821 pstate_table->uclk_pstate.curr.min = mclk_min; 1822 pstate_table->uclk_pstate.curr.max = mclk_max; 1823 } 1824 1825 if (socclk_min && socclk_max) { 1826 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1827 SMU_SOCCLK, 1828 socclk_min, 1829 socclk_max); 1830 if (ret) 1831 return ret; 1832 1833 pstate_table->socclk_pstate.curr.min = socclk_min; 1834 pstate_table->socclk_pstate.curr.max = socclk_max; 1835 } 1836 1837 if (vclk_min && vclk_max) { 1838 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1839 if (adev->vcn.harvest_config & (1 << i)) 1840 continue; 1841 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1842 i ? SMU_VCLK1 : SMU_VCLK, 1843 vclk_min, 1844 vclk_max); 1845 if (ret) 1846 return ret; 1847 } 1848 pstate_table->vclk_pstate.curr.min = vclk_min; 1849 pstate_table->vclk_pstate.curr.max = vclk_max; 1850 } 1851 1852 if (dclk_min && dclk_max) { 1853 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1854 if (adev->vcn.harvest_config & (1 << i)) 1855 continue; 1856 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1857 i ? SMU_DCLK1 : SMU_DCLK, 1858 dclk_min, 1859 dclk_max); 1860 if (ret) 1861 return ret; 1862 } 1863 pstate_table->dclk_pstate.curr.min = dclk_min; 1864 pstate_table->dclk_pstate.curr.max = dclk_max; 1865 } 1866 1867 if (fclk_min && fclk_max) { 1868 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1869 SMU_FCLK, 1870 fclk_min, 1871 fclk_max); 1872 if (ret) 1873 return ret; 1874 1875 pstate_table->fclk_pstate.curr.min = fclk_min; 1876 pstate_table->fclk_pstate.curr.max = fclk_max; 1877 } 1878 1879 return ret; 1880} 1881 1882int smu_v13_0_set_power_source(struct smu_context *smu, 1883 enum smu_power_src_type power_src) 1884{ 1885 int pwr_source; 1886 1887 pwr_source = smu_cmn_to_asic_specific_index(smu, 1888 CMN2ASIC_MAPPING_PWR, 1889 (uint32_t)power_src); 1890 if (pwr_source < 0) 1891 return -EINVAL; 1892 1893 return smu_cmn_send_smc_msg_with_param(smu, 1894 SMU_MSG_NotifyPowerSource, 1895 pwr_source, 1896 NULL); 1897} 1898 1899static int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu, 1900 enum smu_clk_type clk_type, 1901 uint16_t level, 1902 uint32_t *value) 1903{ 1904 int ret = 0, clk_id = 0; 1905 uint32_t param; 1906 1907 if (!value) 1908 return -EINVAL; 1909 1910 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1911 return 0; 1912 1913 clk_id = smu_cmn_to_asic_specific_index(smu, 1914 CMN2ASIC_MAPPING_CLK, 1915 clk_type); 1916 if (clk_id < 0) 1917 return clk_id; 1918 1919 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); 1920 1921 ret = smu_cmn_send_smc_msg_with_param(smu, 1922 SMU_MSG_GetDpmFreqByIndex, 1923 param, 1924 value); 1925 if (ret) 1926 return ret; 1927 1928 *value = *value & 0x7fffffff; 1929 1930 return ret; 1931} 1932 1933static int smu_v13_0_get_dpm_level_count(struct smu_context *smu, 1934 enum smu_clk_type clk_type, 1935 uint32_t *value) 1936{ 1937 int ret; 1938 1939 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value); 1940 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */ 1941 if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value)) 1942 ++(*value); 1943 1944 return ret; 1945} 1946 1947static int smu_v13_0_get_fine_grained_status(struct smu_context *smu, 1948 enum smu_clk_type clk_type, 1949 bool *is_fine_grained_dpm) 1950{ 1951 int ret = 0, clk_id = 0; 1952 uint32_t param; 1953 uint32_t value; 1954 1955 if (!is_fine_grained_dpm) 1956 return -EINVAL; 1957 1958 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1959 return 0; 1960 1961 clk_id = smu_cmn_to_asic_specific_index(smu, 1962 CMN2ASIC_MAPPING_CLK, 1963 clk_type); 1964 if (clk_id < 0) 1965 return clk_id; 1966 1967 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff); 1968 1969 ret = smu_cmn_send_smc_msg_with_param(smu, 1970 SMU_MSG_GetDpmFreqByIndex, 1971 param, 1972 &value); 1973 if (ret) 1974 return ret; 1975 1976 /* 1977 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM 1978 * now, we un-support it 1979 */ 1980 *is_fine_grained_dpm = value & 0x80000000; 1981 1982 return 0; 1983} 1984 1985int smu_v13_0_set_single_dpm_table(struct smu_context *smu, 1986 enum smu_clk_type clk_type, 1987 struct smu_13_0_dpm_table *single_dpm_table) 1988{ 1989 int ret = 0; 1990 uint32_t clk; 1991 int i; 1992 1993 ret = smu_v13_0_get_dpm_level_count(smu, 1994 clk_type, 1995 &single_dpm_table->count); 1996 if (ret) { 1997 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); 1998 return ret; 1999 } 2000 2001 if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) { 2002 ret = smu_v13_0_get_fine_grained_status(smu, 2003 clk_type, 2004 &single_dpm_table->is_fine_grained); 2005 if (ret) { 2006 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__); 2007 return ret; 2008 } 2009 } 2010 2011 for (i = 0; i < single_dpm_table->count; i++) { 2012 ret = smu_v13_0_get_dpm_freq_by_index(smu, 2013 clk_type, 2014 i, 2015 &clk); 2016 if (ret) { 2017 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); 2018 return ret; 2019 } 2020 2021 single_dpm_table->dpm_levels[i].value = clk; 2022 single_dpm_table->dpm_levels[i].enabled = true; 2023 2024 if (i == 0) 2025 single_dpm_table->min = clk; 2026 else if (i == single_dpm_table->count - 1) 2027 single_dpm_table->max = clk; 2028 } 2029 2030 return 0; 2031} 2032 2033int smu_v13_0_get_dpm_level_range(struct smu_context *smu, 2034 enum smu_clk_type clk_type, 2035 uint32_t *min_value, 2036 uint32_t *max_value) 2037{ 2038 uint32_t level_count = 0; 2039 int ret = 0; 2040 2041 if (!min_value && !max_value) 2042 return -EINVAL; 2043 2044 if (min_value) { 2045 /* by default, level 0 clock value as min value */ 2046 ret = smu_v13_0_get_dpm_freq_by_index(smu, 2047 clk_type, 2048 0, 2049 min_value); 2050 if (ret) 2051 return ret; 2052 } 2053 2054 if (max_value) { 2055 ret = smu_v13_0_get_dpm_level_count(smu, 2056 clk_type, 2057 &level_count); 2058 if (ret) 2059 return ret; 2060 2061 ret = smu_v13_0_get_dpm_freq_by_index(smu, 2062 clk_type, 2063 level_count - 1, 2064 max_value); 2065 if (ret) 2066 return ret; 2067 } 2068 2069 return ret; 2070} 2071 2072int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu) 2073{ 2074 struct amdgpu_device *adev = smu->adev; 2075 2076 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 2077 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 2078 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 2079} 2080 2081int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu) 2082{ 2083 uint32_t width_level; 2084 2085 width_level = smu_v13_0_get_current_pcie_link_width_level(smu); 2086 if (width_level > LINK_WIDTH_MAX) 2087 width_level = 0; 2088 2089 return link_width[width_level]; 2090} 2091 2092int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu) 2093{ 2094 struct amdgpu_device *adev = smu->adev; 2095 2096 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 2097 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 2098 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2099} 2100 2101int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu) 2102{ 2103 uint32_t speed_level; 2104 2105 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu); 2106 if (speed_level > LINK_SPEED_MAX) 2107 speed_level = 0; 2108 2109 return link_speed[speed_level]; 2110} 2111 2112int smu_v13_0_set_vcn_enable(struct smu_context *smu, 2113 bool enable) 2114{ 2115 struct amdgpu_device *adev = smu->adev; 2116 int i, ret = 0; 2117 2118 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2119 if (adev->vcn.harvest_config & (1 << i)) 2120 continue; 2121 2122 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 2123 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 2124 i << 16U, NULL); 2125 if (ret) 2126 return ret; 2127 } 2128 2129 return ret; 2130} 2131 2132int smu_v13_0_set_jpeg_enable(struct smu_context *smu, 2133 bool enable) 2134{ 2135 return smu_cmn_send_smc_msg_with_param(smu, enable ? 2136 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg, 2137 0, NULL); 2138} 2139 2140int smu_v13_0_run_btc(struct smu_context *smu) 2141{ 2142 int res; 2143 2144 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 2145 if (res) 2146 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 2147 2148 return res; 2149} 2150 2151int smu_v13_0_deep_sleep_control(struct smu_context *smu, 2152 bool enablement) 2153{ 2154 struct amdgpu_device *adev = smu->adev; 2155 int ret = 0; 2156 2157 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { 2158 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); 2159 if (ret) { 2160 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); 2161 return ret; 2162 } 2163 } 2164 2165 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { 2166 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); 2167 if (ret) { 2168 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); 2169 return ret; 2170 } 2171 } 2172 2173 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { 2174 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); 2175 if (ret) { 2176 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); 2177 return ret; 2178 } 2179 } 2180 2181 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { 2182 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); 2183 if (ret) { 2184 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); 2185 return ret; 2186 } 2187 } 2188 2189 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { 2190 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); 2191 if (ret) { 2192 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); 2193 return ret; 2194 } 2195 } 2196 2197 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) { 2198 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement); 2199 if (ret) { 2200 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable"); 2201 return ret; 2202 } 2203 } 2204 2205 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) { 2206 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement); 2207 if (ret) { 2208 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable"); 2209 return ret; 2210 } 2211 } 2212 2213 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) { 2214 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement); 2215 if (ret) { 2216 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable"); 2217 return ret; 2218 } 2219 } 2220 2221 return ret; 2222} 2223 2224int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 2225 bool enablement) 2226{ 2227 int ret = 0; 2228 2229 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) 2230 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); 2231 2232 return ret; 2233} 2234 2235int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu, 2236 enum smu_baco_seq baco_seq) 2237{ 2238 return smu_cmn_send_smc_msg_with_param(smu, 2239 SMU_MSG_ArmD3, 2240 baco_seq, 2241 NULL); 2242} 2243 2244bool smu_v13_0_baco_is_support(struct smu_context *smu) 2245{ 2246 struct smu_baco_context *smu_baco = &smu->smu_baco; 2247 2248 if (amdgpu_sriov_vf(smu->adev) || 2249 !smu_baco->platform_support) 2250 return false; 2251 2252 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && 2253 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) 2254 return false; 2255 2256 return true; 2257} 2258 2259enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu) 2260{ 2261 struct smu_baco_context *smu_baco = &smu->smu_baco; 2262 2263 return smu_baco->state; 2264} 2265 2266int smu_v13_0_baco_set_state(struct smu_context *smu, 2267 enum smu_baco_state state) 2268{ 2269 struct smu_baco_context *smu_baco = &smu->smu_baco; 2270 struct amdgpu_device *adev = smu->adev; 2271 int ret = 0; 2272 2273 if (smu_v13_0_baco_get_state(smu) == state) 2274 return 0; 2275 2276 if (state == SMU_BACO_STATE_ENTER) { 2277 ret = smu_cmn_send_smc_msg_with_param(smu, 2278 SMU_MSG_EnterBaco, 2279 smu_baco->maco_support ? 2280 BACO_SEQ_BAMACO : BACO_SEQ_BACO, 2281 NULL); 2282 } else { 2283 ret = smu_cmn_send_smc_msg(smu, 2284 SMU_MSG_ExitBaco, 2285 NULL); 2286 if (ret) 2287 return ret; 2288 2289 /* clear vbios scratch 6 and 7 for coming asic reinit */ 2290 WREG32(adev->bios_scratch_reg_offset + 6, 0); 2291 WREG32(adev->bios_scratch_reg_offset + 7, 0); 2292 } 2293 2294 if (!ret) 2295 smu_baco->state = state; 2296 2297 return ret; 2298} 2299 2300int smu_v13_0_baco_enter(struct smu_context *smu) 2301{ 2302 int ret = 0; 2303 2304 ret = smu_v13_0_baco_set_state(smu, 2305 SMU_BACO_STATE_ENTER); 2306 if (ret) 2307 return ret; 2308 2309 drm_msleep(10); 2310 2311 return ret; 2312} 2313 2314int smu_v13_0_baco_exit(struct smu_context *smu) 2315{ 2316 return smu_v13_0_baco_set_state(smu, 2317 SMU_BACO_STATE_EXIT); 2318} 2319 2320int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu) 2321{ 2322 uint16_t index; 2323 2324 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2325 SMU_MSG_EnableGfxImu); 2326 /* Param 1 to tell PMFW to enable GFXOFF feature */ 2327 return smu_cmn_send_msg_without_waiting(smu, index, 1); 2328} 2329 2330int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, 2331 enum PP_OD_DPM_TABLE_COMMAND type, 2332 long input[], uint32_t size) 2333{ 2334 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 2335 int ret = 0; 2336 2337 /* Only allowed in manual mode */ 2338 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 2339 return -EINVAL; 2340 2341 switch (type) { 2342 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2343 if (size != 2) { 2344 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2345 return -EINVAL; 2346 } 2347 2348 if (input[0] == 0) { 2349 if (input[1] < smu->gfx_default_hard_min_freq) { 2350 dev_warn(smu->adev->dev, 2351 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 2352 input[1], smu->gfx_default_hard_min_freq); 2353 return -EINVAL; 2354 } 2355 smu->gfx_actual_hard_min_freq = input[1]; 2356 } else if (input[0] == 1) { 2357 if (input[1] > smu->gfx_default_soft_max_freq) { 2358 dev_warn(smu->adev->dev, 2359 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2360 input[1], smu->gfx_default_soft_max_freq); 2361 return -EINVAL; 2362 } 2363 smu->gfx_actual_soft_max_freq = input[1]; 2364 } else { 2365 return -EINVAL; 2366 } 2367 break; 2368 case PP_OD_RESTORE_DEFAULT_TABLE: 2369 if (size != 0) { 2370 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2371 return -EINVAL; 2372 } 2373 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 2374 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 2375 break; 2376 case PP_OD_COMMIT_DPM_TABLE: 2377 if (size != 0) { 2378 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2379 return -EINVAL; 2380 } 2381 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 2382 dev_err(smu->adev->dev, 2383 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 2384 smu->gfx_actual_hard_min_freq, 2385 smu->gfx_actual_soft_max_freq); 2386 return -EINVAL; 2387 } 2388 2389 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 2390 smu->gfx_actual_hard_min_freq, 2391 NULL); 2392 if (ret) { 2393 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 2394 return ret; 2395 } 2396 2397 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 2398 smu->gfx_actual_soft_max_freq, 2399 NULL); 2400 if (ret) { 2401 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 2402 return ret; 2403 } 2404 break; 2405 default: 2406 return -ENOSYS; 2407 } 2408 2409 return ret; 2410} 2411 2412int smu_v13_0_set_default_dpm_tables(struct smu_context *smu) 2413{ 2414 struct smu_table_context *smu_table = &smu->smu_table; 2415 2416 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, 2417 smu_table->clocks_table, false); 2418} 2419 2420void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu) 2421{ 2422 struct amdgpu_device *adev = smu->adev; 2423 2424 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2425 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2426 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2427} 2428 2429int smu_v13_0_mode1_reset(struct smu_context *smu) 2430{ 2431 int ret = 0; 2432 2433 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 2434 if (!ret) 2435 drm_msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 2436 2437 return ret; 2438} 2439