amdgpu_smu.h revision 1.5
1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22#ifndef __AMDGPU_SMU_H__ 23#define __AMDGPU_SMU_H__ 24 25#include "amdgpu.h" 26#include "kgd_pp_interface.h" 27#include "dm_pp_interface.h" 28#include "dm_pp_smu.h" 29#include "smu_types.h" 30#include "linux/firmware.h" 31 32#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 33#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 34#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 35#define SMU_FW_NAME_LEN 0x24 36 37#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 38#define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 39#define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 40 41// Power Throttlers 42#define SMU_THROTTLER_PPT0_BIT 0 43#define SMU_THROTTLER_PPT1_BIT 1 44#define SMU_THROTTLER_PPT2_BIT 2 45#define SMU_THROTTLER_PPT3_BIT 3 46#define SMU_THROTTLER_SPL_BIT 4 47#define SMU_THROTTLER_FPPT_BIT 5 48#define SMU_THROTTLER_SPPT_BIT 6 49#define SMU_THROTTLER_SPPT_APU_BIT 7 50 51// Current Throttlers 52#define SMU_THROTTLER_TDC_GFX_BIT 16 53#define SMU_THROTTLER_TDC_SOC_BIT 17 54#define SMU_THROTTLER_TDC_MEM_BIT 18 55#define SMU_THROTTLER_TDC_VDD_BIT 19 56#define SMU_THROTTLER_TDC_CVIP_BIT 20 57#define SMU_THROTTLER_EDC_CPU_BIT 21 58#define SMU_THROTTLER_EDC_GFX_BIT 22 59#define SMU_THROTTLER_APCC_BIT 23 60 61// Temperature 62#define SMU_THROTTLER_TEMP_GPU_BIT 32 63#define SMU_THROTTLER_TEMP_CORE_BIT 33 64#define SMU_THROTTLER_TEMP_MEM_BIT 34 65#define SMU_THROTTLER_TEMP_EDGE_BIT 35 66#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 67#define SMU_THROTTLER_TEMP_SOC_BIT 37 68#define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 69#define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 70#define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 71#define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 72#define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 73#define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 74#define SMU_THROTTLER_VRHOT0_BIT 44 75#define SMU_THROTTLER_VRHOT1_BIT 45 76#define SMU_THROTTLER_PROCHOT_CPU_BIT 46 77#define SMU_THROTTLER_PROCHOT_GFX_BIT 47 78 79// Other 80#define SMU_THROTTLER_PPM_BIT 56 81#define SMU_THROTTLER_FIT_BIT 57 82 83struct smu_hw_power_state { 84 unsigned int magic; 85}; 86 87struct smu_power_state; 88 89enum smu_state_ui_label { 90 SMU_STATE_UI_LABEL_NONE, 91 SMU_STATE_UI_LABEL_BATTERY, 92 SMU_STATE_UI_TABEL_MIDDLE_LOW, 93 SMU_STATE_UI_LABEL_BALLANCED, 94 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 95 SMU_STATE_UI_LABEL_PERFORMANCE, 96 SMU_STATE_UI_LABEL_BACO, 97}; 98 99enum smu_state_classification_flag { 100 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 101 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 102 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 103 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 104 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 105 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 106 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 107 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 108 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 109 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 111 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 112 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 113 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 114 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 115 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 116 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 117 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 118 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 119 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 120 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 121}; 122 123struct smu_state_classification_block { 124 enum smu_state_ui_label ui_label; 125 enum smu_state_classification_flag flags; 126 int bios_index; 127 bool temporary_state; 128 bool to_be_deleted; 129}; 130 131struct smu_state_pcie_block { 132 unsigned int lanes; 133}; 134 135enum smu_refreshrate_source { 136 SMU_REFRESHRATE_SOURCE_EDID, 137 SMU_REFRESHRATE_SOURCE_EXPLICIT 138}; 139 140struct smu_state_display_block { 141 bool disable_frame_modulation; 142 bool limit_refreshrate; 143 enum smu_refreshrate_source refreshrate_source; 144 int explicit_refreshrate; 145 int edid_refreshrate_index; 146 bool enable_vari_bright; 147}; 148 149struct smu_state_memory_block { 150 bool dll_off; 151 uint8_t m3arb; 152 uint8_t unused[3]; 153}; 154 155struct smu_state_software_algorithm_block { 156 bool disable_load_balancing; 157 bool enable_sleep_for_timestamps; 158}; 159 160struct smu_temperature_range { 161 int min; 162 int max; 163 int edge_emergency_max; 164 int hotspot_min; 165 int hotspot_crit_max; 166 int hotspot_emergency_max; 167 int mem_min; 168 int mem_crit_max; 169 int mem_emergency_max; 170 int software_shutdown_temp; 171 int software_shutdown_temp_offset; 172}; 173 174struct smu_state_validation_block { 175 bool single_display_only; 176 bool disallow_on_dc; 177 uint8_t supported_power_levels; 178}; 179 180struct smu_uvd_clocks { 181 uint32_t vclk; 182 uint32_t dclk; 183}; 184 185/** 186* Structure to hold a SMU Power State. 187*/ 188struct smu_power_state { 189 uint32_t id; 190 struct list_head ordered_list; 191 struct list_head all_states_list; 192 193 struct smu_state_classification_block classification; 194 struct smu_state_validation_block validation; 195 struct smu_state_pcie_block pcie; 196 struct smu_state_display_block display; 197 struct smu_state_memory_block memory; 198 struct smu_state_software_algorithm_block software; 199 struct smu_uvd_clocks uvd_clocks; 200 struct smu_hw_power_state hardware; 201}; 202 203enum smu_power_src_type 204{ 205 SMU_POWER_SOURCE_AC, 206 SMU_POWER_SOURCE_DC, 207 SMU_POWER_SOURCE_COUNT, 208}; 209 210enum smu_ppt_limit_type 211{ 212 SMU_DEFAULT_PPT_LIMIT = 0, 213 SMU_FAST_PPT_LIMIT, 214}; 215 216enum smu_ppt_limit_level 217{ 218 SMU_PPT_LIMIT_MIN = -1, 219 SMU_PPT_LIMIT_CURRENT, 220 SMU_PPT_LIMIT_DEFAULT, 221 SMU_PPT_LIMIT_MAX, 222}; 223 224enum smu_memory_pool_size 225{ 226 SMU_MEMORY_POOL_SIZE_ZERO = 0, 227 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 228 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 229 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 230 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 231}; 232 233struct smu_user_dpm_profile { 234 uint32_t fan_mode; 235 uint32_t power_limit; 236 uint32_t fan_speed_pwm; 237 uint32_t fan_speed_rpm; 238 uint32_t flags; 239 uint32_t user_od; 240 241 /* user clock state information */ 242 uint32_t clk_mask[SMU_CLK_COUNT]; 243 uint32_t clk_dependency; 244}; 245 246#define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 247 do { \ 248 tables[table_id].size = s; \ 249 tables[table_id].align = a; \ 250 tables[table_id].domain = d; \ 251 } while (0) 252 253struct smu_table { 254 uint64_t size; 255 uint32_t align; 256 uint8_t domain; 257 uint64_t mc_address; 258 void *cpu_addr; 259 struct amdgpu_bo *bo; 260}; 261 262enum smu_perf_level_designation { 263 PERF_LEVEL_ACTIVITY, 264 PERF_LEVEL_POWER_CONTAINMENT, 265}; 266 267struct smu_performance_level { 268 uint32_t core_clock; 269 uint32_t memory_clock; 270 uint32_t vddc; 271 uint32_t vddci; 272 uint32_t non_local_mem_freq; 273 uint32_t non_local_mem_width; 274}; 275 276struct smu_clock_info { 277 uint32_t min_mem_clk; 278 uint32_t max_mem_clk; 279 uint32_t min_eng_clk; 280 uint32_t max_eng_clk; 281 uint32_t min_bus_bandwidth; 282 uint32_t max_bus_bandwidth; 283}; 284 285struct smu_bios_boot_up_values 286{ 287 uint32_t revision; 288 uint32_t gfxclk; 289 uint32_t uclk; 290 uint32_t socclk; 291 uint32_t dcefclk; 292 uint32_t eclk; 293 uint32_t vclk; 294 uint32_t dclk; 295 uint16_t vddc; 296 uint16_t vddci; 297 uint16_t mvddc; 298 uint16_t vdd_gfx; 299 uint8_t cooling_id; 300 uint32_t pp_table_id; 301 uint32_t format_revision; 302 uint32_t content_revision; 303 uint32_t fclk; 304 uint32_t lclk; 305 uint32_t firmware_caps; 306}; 307 308enum smu_table_id 309{ 310 SMU_TABLE_PPTABLE = 0, 311 SMU_TABLE_WATERMARKS, 312 SMU_TABLE_CUSTOM_DPM, 313 SMU_TABLE_DPMCLOCKS, 314 SMU_TABLE_AVFS, 315 SMU_TABLE_AVFS_PSM_DEBUG, 316 SMU_TABLE_AVFS_FUSE_OVERRIDE, 317 SMU_TABLE_PMSTATUSLOG, 318 SMU_TABLE_SMU_METRICS, 319 SMU_TABLE_DRIVER_SMU_CONFIG, 320 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 321 SMU_TABLE_OVERDRIVE, 322 SMU_TABLE_I2C_COMMANDS, 323 SMU_TABLE_PACE, 324 SMU_TABLE_ECCINFO, 325 SMU_TABLE_COMBO_PPTABLE, 326 SMU_TABLE_COUNT, 327}; 328 329struct smu_table_context 330{ 331 void *power_play_table; 332 uint32_t power_play_table_size; 333 void *hardcode_pptable; 334 unsigned long metrics_time; 335 void *metrics_table; 336 void *clocks_table; 337 void *watermarks_table; 338 339 void *max_sustainable_clocks; 340 struct smu_bios_boot_up_values boot_values; 341 void *driver_pptable; 342 void *combo_pptable; 343 void *ecc_table; 344 void *driver_smu_config_table; 345 struct smu_table tables[SMU_TABLE_COUNT]; 346 /* 347 * The driver table is just a staging buffer for 348 * uploading/downloading content from the SMU. 349 * 350 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 351 * SMU_MSG_TransferTableDram2Smu instructs SMU 352 * which content driver is interested. 353 */ 354 struct smu_table driver_table; 355 struct smu_table memory_pool; 356 struct smu_table dummy_read_1_table; 357 uint8_t thermal_controller_type; 358 359 void *overdrive_table; 360 void *boot_overdrive_table; 361 void *user_overdrive_table; 362 363 uint32_t gpu_metrics_table_size; 364 void *gpu_metrics_table; 365}; 366 367struct smu_dpm_context { 368 uint32_t dpm_context_size; 369 void *dpm_context; 370 void *golden_dpm_context; 371 enum amd_dpm_forced_level dpm_level; 372 enum amd_dpm_forced_level saved_dpm_level; 373 enum amd_dpm_forced_level requested_dpm_level; 374 struct smu_power_state *dpm_request_power_state; 375 struct smu_power_state *dpm_current_power_state; 376 struct mclock_latency_table *mclk_latency_table; 377}; 378 379struct smu_power_gate { 380 bool uvd_gated; 381 bool vce_gated; 382 atomic_t vcn_gated; 383 atomic_t jpeg_gated; 384}; 385 386struct smu_power_context { 387 void *power_context; 388 uint32_t power_context_size; 389 struct smu_power_gate power_gate; 390}; 391 392#define SMU_FEATURE_MAX (64) 393struct smu_feature 394{ 395 uint32_t feature_num; 396 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 397 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 398}; 399 400struct smu_clocks { 401 uint32_t engine_clock; 402 uint32_t memory_clock; 403 uint32_t bus_bandwidth; 404 uint32_t engine_clock_in_sr; 405 uint32_t dcef_clock; 406 uint32_t dcef_clock_in_sr; 407}; 408 409#define MAX_REGULAR_DPM_NUM 16 410struct mclk_latency_entries { 411 uint32_t frequency; 412 uint32_t latency; 413}; 414struct mclock_latency_table { 415 uint32_t count; 416 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 417}; 418 419enum smu_reset_mode 420{ 421 SMU_RESET_MODE_0, 422 SMU_RESET_MODE_1, 423 SMU_RESET_MODE_2, 424}; 425 426enum smu_baco_state 427{ 428 SMU_BACO_STATE_ENTER = 0, 429 SMU_BACO_STATE_EXIT, 430}; 431 432struct smu_baco_context 433{ 434 uint32_t state; 435 bool platform_support; 436 bool maco_support; 437}; 438 439struct smu_freq_info { 440 uint32_t min; 441 uint32_t max; 442 uint32_t freq_level; 443}; 444 445struct pstates_clk_freq { 446 uint32_t min; 447 uint32_t standard; 448 uint32_t peak; 449 struct smu_freq_info custom; 450 struct smu_freq_info curr; 451}; 452 453struct smu_umd_pstate_table { 454 struct pstates_clk_freq gfxclk_pstate; 455 struct pstates_clk_freq socclk_pstate; 456 struct pstates_clk_freq uclk_pstate; 457 struct pstates_clk_freq vclk_pstate; 458 struct pstates_clk_freq dclk_pstate; 459 struct pstates_clk_freq fclk_pstate; 460}; 461 462struct cmn2asic_msg_mapping { 463 int valid_mapping; 464 int map_to; 465 int valid_in_vf; 466}; 467 468struct cmn2asic_mapping { 469 int valid_mapping; 470 int map_to; 471}; 472 473struct stb_context { 474 uint32_t stb_buf_size; 475 bool enabled; 476 spinlock_t lock; 477}; 478 479#define WORKLOAD_POLICY_MAX 7 480 481struct smu_context 482{ 483 struct amdgpu_device *adev; 484 struct amdgpu_irq_src irq_source; 485 486 const struct pptable_funcs *ppt_funcs; 487 const struct cmn2asic_msg_mapping *message_map; 488 const struct cmn2asic_mapping *clock_map; 489 const struct cmn2asic_mapping *feature_map; 490 const struct cmn2asic_mapping *table_map; 491 const struct cmn2asic_mapping *pwr_src_map; 492 const struct cmn2asic_mapping *workload_map; 493 struct rwlock message_lock; 494 uint64_t pool_size; 495 496 struct smu_table_context smu_table; 497 struct smu_dpm_context smu_dpm; 498 struct smu_power_context smu_power; 499 struct smu_feature smu_feature; 500 struct amd_pp_display_configuration *display_config; 501 struct smu_baco_context smu_baco; 502 struct smu_temperature_range thermal_range; 503 void *od_settings; 504 505 struct smu_umd_pstate_table pstate_table; 506 uint32_t pstate_sclk; 507 uint32_t pstate_mclk; 508 509 bool od_enabled; 510 uint32_t current_power_limit; 511 uint32_t default_power_limit; 512 uint32_t max_power_limit; 513 514 /* soft pptable */ 515 uint32_t ppt_offset_bytes; 516 uint32_t ppt_size_bytes; 517 uint8_t *ppt_start_addr; 518 519 bool support_power_containment; 520 bool disable_watermark; 521 522#define WATERMARKS_EXIST (1 << 0) 523#define WATERMARKS_LOADED (1 << 1) 524 uint32_t watermarks_bitmap; 525 uint32_t hard_min_uclk_req_from_dal; 526 bool disable_uclk_switch; 527 528 uint32_t workload_mask; 529 uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 530 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 531 uint32_t power_profile_mode; 532 uint32_t default_power_profile_mode; 533 bool pm_enabled; 534 bool is_apu; 535 536 uint32_t smc_driver_if_version; 537 uint32_t smc_fw_if_version; 538 uint32_t smc_fw_version; 539 540 bool uploading_custom_pp_table; 541 bool dc_controlled_by_gpio; 542 543 struct work_struct throttling_logging_work; 544 atomic64_t throttle_int_counter; 545 struct work_struct interrupt_work; 546 547 unsigned fan_max_rpm; 548 unsigned manual_fan_speed_pwm; 549 550 uint32_t gfx_default_hard_min_freq; 551 uint32_t gfx_default_soft_max_freq; 552 uint32_t gfx_actual_hard_min_freq; 553 uint32_t gfx_actual_soft_max_freq; 554 555 /* APU only */ 556 uint32_t cpu_default_soft_min_freq; 557 uint32_t cpu_default_soft_max_freq; 558 uint32_t cpu_actual_soft_min_freq; 559 uint32_t cpu_actual_soft_max_freq; 560 uint32_t cpu_core_id_select; 561 uint16_t cpu_core_num; 562 563 struct smu_user_dpm_profile user_dpm_profile; 564 565 struct stb_context stb_context; 566 567 struct firmware pptable_firmware; 568 569 u32 param_reg; 570 u32 msg_reg; 571 u32 resp_reg; 572 573 u32 debug_param_reg; 574 u32 debug_msg_reg; 575 u32 debug_resp_reg; 576 577 struct delayed_work swctf_delayed_work; 578}; 579 580struct i2c_adapter; 581 582/** 583 * struct pptable_funcs - Callbacks used to interact with the SMU. 584 */ 585struct pptable_funcs { 586 /** 587 * @run_btc: Calibrate voltage/frequency curve to fit the system's 588 * power delivery and voltage margins. Required for adaptive 589 * voltage frequency scaling (AVFS). 590 */ 591 int (*run_btc)(struct smu_context *smu); 592 593 /** 594 * @get_allowed_feature_mask: Get allowed feature mask. 595 * &feature_mask: Array to store feature mask. 596 * &num: Elements in &feature_mask. 597 */ 598 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 599 600 /** 601 * @get_current_power_state: Get the current power state. 602 * 603 * Return: Current power state on success, negative errno on failure. 604 */ 605 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 606 607 /** 608 * @set_default_dpm_table: Retrieve the default overdrive settings from 609 * the SMU. 610 */ 611 int (*set_default_dpm_table)(struct smu_context *smu); 612 613 int (*set_power_state)(struct smu_context *smu); 614 615 /** 616 * @populate_umd_state_clk: Populate the UMD power state table with 617 * defaults. 618 */ 619 int (*populate_umd_state_clk)(struct smu_context *smu); 620 621 /** 622 * @print_clk_levels: Print DPM clock levels for a clock domain 623 * to buffer. Star current level. 624 * 625 * Used for sysfs interfaces. 626 * Return: Number of characters written to the buffer 627 */ 628 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 629 630 /** 631 * @emit_clk_levels: Print DPM clock levels for a clock domain 632 * to buffer using sysfs_emit_at. Star current level. 633 * 634 * Used for sysfs interfaces. 635 * &buf: sysfs buffer 636 * &offset: offset within buffer to start printing, which is updated by the 637 * function. 638 * 639 * Return: 0 on Success or Negative to indicate an error occurred. 640 */ 641 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 642 643 /** 644 * @force_clk_levels: Set a range of allowed DPM levels for a clock 645 * domain. 646 * &clk_type: Clock domain. 647 * &mask: Range of allowed DPM levels. 648 */ 649 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 650 651 /** 652 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 653 * &type: Type of edit. 654 * &input: Edit parameters. 655 * &size: Size of &input. 656 */ 657 int (*od_edit_dpm_table)(struct smu_context *smu, 658 enum PP_OD_DPM_TABLE_COMMAND type, 659 long *input, uint32_t size); 660 661 /** 662 * @restore_user_od_settings: Restore the user customized 663 * OD settings on S3/S4/Runpm resume. 664 */ 665 int (*restore_user_od_settings)(struct smu_context *smu); 666 667 /** 668 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 669 * domain. 670 */ 671 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 672 enum smu_clk_type clk_type, 673 struct 674 pp_clock_levels_with_latency 675 *clocks); 676 /** 677 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 678 * domain. 679 */ 680 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 681 enum amd_pp_clock_type type, 682 struct 683 pp_clock_levels_with_voltage 684 *clocks); 685 686 /** 687 * @get_power_profile_mode: Print all power profile modes to 688 * buffer. Star current mode. 689 */ 690 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 691 692 /** 693 * @set_power_profile_mode: Set a power profile mode. Also used to 694 * create/set custom power profile modes. 695 * &input: Power profile mode parameters. 696 * &size: Size of &input. 697 */ 698 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 699 700 /** 701 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 702 * management. 703 */ 704 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 705 706 /** 707 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 708 * management. 709 */ 710 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 711 712 /** 713 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU 714 */ 715 int (*set_gfx_power_up_by_imu)(struct smu_context *smu); 716 717 /** 718 * @read_sensor: Read data from a sensor. 719 * &sensor: Sensor to read data from. 720 * &data: Sensor reading. 721 * &size: Size of &data. 722 */ 723 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 724 void *data, uint32_t *size); 725 726 /** 727 * @pre_display_config_changed: Prepare GPU for a display configuration 728 * change. 729 * 730 * Disable display tracking and pin memory clock speed to maximum. Used 731 * in display component synchronization. 732 */ 733 int (*pre_display_config_changed)(struct smu_context *smu); 734 735 /** 736 * @display_config_changed: Notify the SMU of the current display 737 * configuration. 738 * 739 * Allows SMU to properly track blanking periods for memory clock 740 * adjustment. Used in display component synchronization. 741 */ 742 int (*display_config_changed)(struct smu_context *smu); 743 744 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 745 746 /** 747 * @notify_smc_display_config: Applies display requirements to the 748 * current power state. 749 * 750 * Optimize deep sleep DCEFclk and mclk for the current display 751 * configuration. Used in display component synchronization. 752 */ 753 int (*notify_smc_display_config)(struct smu_context *smu); 754 755 /** 756 * @is_dpm_running: Check if DPM is running. 757 * 758 * Return: True if DPM is running, false otherwise. 759 */ 760 bool (*is_dpm_running)(struct smu_context *smu); 761 762 /** 763 * @get_fan_speed_pwm: Get the current fan speed in PWM. 764 */ 765 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 766 767 /** 768 * @get_fan_speed_rpm: Get the current fan speed in rpm. 769 */ 770 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 771 772 /** 773 * @set_watermarks_table: Configure and upload the watermarks tables to 774 * the SMU. 775 */ 776 int (*set_watermarks_table)(struct smu_context *smu, 777 struct pp_smu_wm_range_sets *clock_ranges); 778 779 /** 780 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 781 */ 782 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 783 784 /** 785 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 786 * &clocks_in_khz: Array of DPM levels. 787 * &num_states: Elements in &clocks_in_khz. 788 */ 789 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 790 791 /** 792 * @set_default_od_settings: Set the overdrive tables to defaults. 793 */ 794 int (*set_default_od_settings)(struct smu_context *smu); 795 796 /** 797 * @set_performance_level: Set a performance level. 798 */ 799 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 800 801 /** 802 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 803 * clock switching. 804 * 805 * Disabling this feature forces memory clock speed to maximum. 806 * Enabling sets the minimum memory clock capable of driving the 807 * current display configuration. 808 */ 809 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 810 811 /** 812 * @dump_pptable: Print the power play table to the system log. 813 */ 814 void (*dump_pptable)(struct smu_context *smu); 815 816 /** 817 * @get_power_limit: Get the device's power limits. 818 */ 819 int (*get_power_limit)(struct smu_context *smu, 820 uint32_t *current_power_limit, 821 uint32_t *default_power_limit, 822 uint32_t *max_power_limit); 823 824 /** 825 * @get_ppt_limit: Get the device's ppt limits. 826 */ 827 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 828 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 829 830 /** 831 * @set_df_cstate: Set data fabric cstate. 832 */ 833 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 834 835 /** 836 * @allow_xgmi_power_down: Enable/disable external global memory 837 * interconnect power down. 838 */ 839 int (*allow_xgmi_power_down)(struct smu_context *smu, bool en); 840 841 /** 842 * @update_pcie_parameters: Update and upload the system's PCIe 843 * capabilites to the SMU. 844 * &pcie_gen_cap: Maximum allowed PCIe generation. 845 * &pcie_width_cap: Maximum allowed PCIe width. 846 */ 847 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap); 848 849 /** 850 * @i2c_init: Initialize i2c. 851 * 852 * The i2c bus is used internally by the SMU voltage regulators and 853 * other devices. The i2c's EEPROM also stores bad page tables on boards 854 * with ECC. 855 */ 856 int (*i2c_init)(struct smu_context *smu); 857 858 /** 859 * @i2c_fini: Tear down i2c. 860 */ 861 void (*i2c_fini)(struct smu_context *smu); 862 863 /** 864 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 865 */ 866 void (*get_unique_id)(struct smu_context *smu); 867 868 /** 869 * @get_dpm_clock_table: Get a copy of the DPM clock table. 870 * 871 * Used by display component in bandwidth and watermark calculations. 872 */ 873 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 874 875 /** 876 * @init_microcode: Request the SMU's firmware from the kernel. 877 */ 878 int (*init_microcode)(struct smu_context *smu); 879 880 /** 881 * @load_microcode: Load firmware onto the SMU. 882 */ 883 int (*load_microcode)(struct smu_context *smu); 884 885 /** 886 * @fini_microcode: Release the SMU's firmware. 887 */ 888 void (*fini_microcode)(struct smu_context *smu); 889 890 /** 891 * @init_smc_tables: Initialize the SMU tables. 892 */ 893 int (*init_smc_tables)(struct smu_context *smu); 894 895 /** 896 * @fini_smc_tables: Release the SMU tables. 897 */ 898 int (*fini_smc_tables)(struct smu_context *smu); 899 900 /** 901 * @init_power: Initialize the power gate table context. 902 */ 903 int (*init_power)(struct smu_context *smu); 904 905 /** 906 * @fini_power: Release the power gate table context. 907 */ 908 int (*fini_power)(struct smu_context *smu); 909 910 /** 911 * @check_fw_status: Check the SMU's firmware status. 912 * 913 * Return: Zero if check passes, negative errno on failure. 914 */ 915 int (*check_fw_status)(struct smu_context *smu); 916 917 /** 918 * @set_mp1_state: put SMU into a correct state for comming 919 * resume from runpm or gpu reset. 920 */ 921 int (*set_mp1_state)(struct smu_context *smu, 922 enum pp_mp1_state mp1_state); 923 924 /** 925 * @setup_pptable: Initialize the power play table and populate it with 926 * default values. 927 */ 928 int (*setup_pptable)(struct smu_context *smu); 929 930 /** 931 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 932 */ 933 int (*get_vbios_bootup_values)(struct smu_context *smu); 934 935 /** 936 * @check_fw_version: Print driver and SMU interface versions to the 937 * system log. 938 * 939 * Interface mismatch is not a critical failure. 940 */ 941 int (*check_fw_version)(struct smu_context *smu); 942 943 /** 944 * @powergate_sdma: Power up/down system direct memory access. 945 */ 946 int (*powergate_sdma)(struct smu_context *smu, bool gate); 947 948 /** 949 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 950 * gating. 951 */ 952 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 953 954 /** 955 * @write_pptable: Write the power play table to the SMU. 956 */ 957 int (*write_pptable)(struct smu_context *smu); 958 959 /** 960 * @set_driver_table_location: Send the location of the driver table to 961 * the SMU. 962 */ 963 int (*set_driver_table_location)(struct smu_context *smu); 964 965 /** 966 * @set_tool_table_location: Send the location of the tool table to the 967 * SMU. 968 */ 969 int (*set_tool_table_location)(struct smu_context *smu); 970 971 /** 972 * @notify_memory_pool_location: Send the location of the memory pool to 973 * the SMU. 974 */ 975 int (*notify_memory_pool_location)(struct smu_context *smu); 976 977 /** 978 * @system_features_control: Enable/disable all SMU features. 979 */ 980 int (*system_features_control)(struct smu_context *smu, bool en); 981 982 /** 983 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 984 * &msg: Type of message. 985 * ¶m: Message parameter. 986 * &read_arg: SMU response (optional). 987 */ 988 int (*send_smc_msg_with_param)(struct smu_context *smu, 989 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 990 991 /** 992 * @send_smc_msg: Send a message to the SMU. 993 * &msg: Type of message. 994 * &read_arg: SMU response (optional). 995 */ 996 int (*send_smc_msg)(struct smu_context *smu, 997 enum smu_message_type msg, 998 uint32_t *read_arg); 999 1000 /** 1001 * @init_display_count: Notify the SMU of the number of display 1002 * components in current display configuration. 1003 */ 1004 int (*init_display_count)(struct smu_context *smu, uint32_t count); 1005 1006 /** 1007 * @set_allowed_mask: Notify the SMU of the features currently allowed 1008 * by the driver. 1009 */ 1010 int (*set_allowed_mask)(struct smu_context *smu); 1011 1012 /** 1013 * @get_enabled_mask: Get a mask of features that are currently enabled 1014 * on the SMU. 1015 * &feature_mask: Enabled feature mask. 1016 */ 1017 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1018 1019 /** 1020 * @feature_is_enabled: Test if a feature is enabled. 1021 * 1022 * Return: One if enabled, zero if disabled. 1023 */ 1024 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1025 1026 /** 1027 * @disable_all_features_with_exception: Disable all features with 1028 * exception to those in &mask. 1029 */ 1030 int (*disable_all_features_with_exception)(struct smu_context *smu, 1031 enum smu_feature_mask mask); 1032 1033 /** 1034 * @notify_display_change: Enable fast memory clock switching. 1035 * 1036 * Allows for fine grained memory clock switching but has more stringent 1037 * timing requirements. 1038 */ 1039 int (*notify_display_change)(struct smu_context *smu); 1040 1041 /** 1042 * @set_power_limit: Set power limit in watts. 1043 */ 1044 int (*set_power_limit)(struct smu_context *smu, 1045 enum smu_ppt_limit_type limit_type, 1046 uint32_t limit); 1047 1048 /** 1049 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1050 * table with values from the SMU. 1051 */ 1052 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1053 1054 /** 1055 * @enable_thermal_alert: Enable thermal alert interrupts. 1056 */ 1057 int (*enable_thermal_alert)(struct smu_context *smu); 1058 1059 /** 1060 * @disable_thermal_alert: Disable thermal alert interrupts. 1061 */ 1062 int (*disable_thermal_alert)(struct smu_context *smu); 1063 1064 /** 1065 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1066 * clock speed in MHz. 1067 */ 1068 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1069 1070 /** 1071 * @display_clock_voltage_request: Set a hard minimum frequency 1072 * for a clock domain. 1073 */ 1074 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1075 pp_display_clock_request 1076 *clock_req); 1077 1078 /** 1079 * @get_fan_control_mode: Get the current fan control mode. 1080 */ 1081 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1082 1083 /** 1084 * @set_fan_control_mode: Set the fan control mode. 1085 */ 1086 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1087 1088 /** 1089 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1090 */ 1091 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1092 1093 /** 1094 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1095 */ 1096 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1097 1098 /** 1099 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1100 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1101 */ 1102 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1103 1104 /** 1105 * @gfx_off_control: Enable/disable graphics engine poweroff. 1106 */ 1107 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1108 1109 1110 /** 1111 * @get_gfx_off_status: Get graphics engine poweroff status. 1112 * 1113 * Return: 1114 * 0 - GFXOFF(default). 1115 * 1 - Transition out of GFX State. 1116 * 2 - Not in GFXOFF. 1117 * 3 - Transition into GFXOFF. 1118 */ 1119 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1120 1121 /** 1122 * @gfx_off_entrycount: total GFXOFF entry count at the time of 1123 * query since system power-up 1124 */ 1125 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount); 1126 1127 /** 1128 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging 1129 */ 1130 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); 1131 1132 /** 1133 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval 1134 */ 1135 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency); 1136 1137 /** 1138 * @register_irq_handler: Register interupt request handlers. 1139 */ 1140 int (*register_irq_handler)(struct smu_context *smu); 1141 1142 /** 1143 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1144 */ 1145 int (*set_azalia_d3_pme)(struct smu_context *smu); 1146 1147 /** 1148 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1149 * clock speeds table. 1150 * 1151 * Provides a way for the display component (DC) to get the max 1152 * sustainable clocks from the SMU. 1153 */ 1154 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1155 1156 /** 1157 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off). 1158 */ 1159 bool (*baco_is_support)(struct smu_context *smu); 1160 1161 /** 1162 * @baco_get_state: Get the current BACO state. 1163 * 1164 * Return: Current BACO state. 1165 */ 1166 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1167 1168 /** 1169 * @baco_set_state: Enter/exit BACO. 1170 */ 1171 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1172 1173 /** 1174 * @baco_enter: Enter BACO. 1175 */ 1176 int (*baco_enter)(struct smu_context *smu); 1177 1178 /** 1179 * @baco_exit: Exit Baco. 1180 */ 1181 int (*baco_exit)(struct smu_context *smu); 1182 1183 /** 1184 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1185 */ 1186 bool (*mode1_reset_is_support)(struct smu_context *smu); 1187 /** 1188 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1189 */ 1190 bool (*mode2_reset_is_support)(struct smu_context *smu); 1191 1192 /** 1193 * @mode1_reset: Perform mode1 reset. 1194 * 1195 * Complete GPU reset. 1196 */ 1197 int (*mode1_reset)(struct smu_context *smu); 1198 1199 /** 1200 * @mode2_reset: Perform mode2 reset. 1201 * 1202 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1203 * IPs reset varies by asic. 1204 */ 1205 int (*mode2_reset)(struct smu_context *smu); 1206 1207 /** 1208 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1209 * domain in MHz. 1210 */ 1211 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1212 1213 /** 1214 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1215 * domain in MHz. 1216 */ 1217 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 1218 1219 /** 1220 * @set_power_source: Notify the SMU of the current power source. 1221 */ 1222 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1223 1224 /** 1225 * @log_thermal_throttling_event: Print a thermal throttling warning to 1226 * the system's log. 1227 */ 1228 void (*log_thermal_throttling_event)(struct smu_context *smu); 1229 1230 /** 1231 * @get_pp_feature_mask: Print a human readable table of enabled 1232 * features to buffer. 1233 */ 1234 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1235 1236 /** 1237 * @set_pp_feature_mask: Request the SMU enable/disable features to 1238 * match those enabled in &new_mask. 1239 */ 1240 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1241 1242 /** 1243 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1244 * 1245 * Return: Size of &table 1246 */ 1247 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1248 1249 /** 1250 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1251 */ 1252 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1253 1254 /** 1255 * @gfx_ulv_control: Enable/disable ultra low voltage. 1256 */ 1257 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1258 1259 /** 1260 * @deep_sleep_control: Enable/disable deep sleep. 1261 */ 1262 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1263 1264 /** 1265 * @get_fan_parameters: Get fan parameters. 1266 * 1267 * Get maximum fan speed from the power play table. 1268 */ 1269 int (*get_fan_parameters)(struct smu_context *smu); 1270 1271 /** 1272 * @post_init: Helper function for asic specific workarounds. 1273 */ 1274 int (*post_init)(struct smu_context *smu); 1275 1276 /** 1277 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1278 */ 1279 void (*interrupt_work)(struct smu_context *smu); 1280 1281 /** 1282 * @gpo_control: Enable/disable graphics power optimization if supported. 1283 */ 1284 int (*gpo_control)(struct smu_context *smu, bool enablement); 1285 1286 /** 1287 * @gfx_state_change_set: Send the current graphics state to the SMU. 1288 */ 1289 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1290 1291 /** 1292 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1293 * parameters to defaults. 1294 */ 1295 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1296 1297 /** 1298 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1299 */ 1300 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1301 1302 /** 1303 * @wait_for_event: Wait for events from SMU. 1304 */ 1305 int (*wait_for_event)(struct smu_context *smu, 1306 enum smu_event_type event, uint64_t event_arg); 1307 1308 /** 1309 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1310 * of SMUBUS table. 1311 */ 1312 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1313 1314 /** 1315 * @get_ecc_table: message SMU to get ECC INFO table. 1316 */ 1317 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1318 1319 1320 /** 1321 * @stb_collect_info: Collects Smart Trace Buffers data. 1322 */ 1323 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1324 1325 /** 1326 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1327 */ 1328 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1329 1330 /** 1331 * @set_config_table: Apply the input DriverSmuConfig table settings. 1332 */ 1333 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1334 1335 /** 1336 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1337 * of SMUBUS table. 1338 */ 1339 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1340 1341 /** 1342 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP 1343 */ 1344 int (*init_pptable_microcode)(struct smu_context *smu); 1345}; 1346 1347typedef enum { 1348 METRICS_CURR_GFXCLK, 1349 METRICS_CURR_SOCCLK, 1350 METRICS_CURR_UCLK, 1351 METRICS_CURR_VCLK, 1352 METRICS_CURR_VCLK1, 1353 METRICS_CURR_DCLK, 1354 METRICS_CURR_DCLK1, 1355 METRICS_CURR_FCLK, 1356 METRICS_CURR_DCEFCLK, 1357 METRICS_AVERAGE_CPUCLK, 1358 METRICS_AVERAGE_GFXCLK, 1359 METRICS_AVERAGE_SOCCLK, 1360 METRICS_AVERAGE_FCLK, 1361 METRICS_AVERAGE_UCLK, 1362 METRICS_AVERAGE_VCLK, 1363 METRICS_AVERAGE_DCLK, 1364 METRICS_AVERAGE_VCLK1, 1365 METRICS_AVERAGE_DCLK1, 1366 METRICS_AVERAGE_GFXACTIVITY, 1367 METRICS_AVERAGE_MEMACTIVITY, 1368 METRICS_AVERAGE_VCNACTIVITY, 1369 METRICS_AVERAGE_SOCKETPOWER, 1370 METRICS_TEMPERATURE_EDGE, 1371 METRICS_TEMPERATURE_HOTSPOT, 1372 METRICS_TEMPERATURE_MEM, 1373 METRICS_TEMPERATURE_VRGFX, 1374 METRICS_TEMPERATURE_VRSOC, 1375 METRICS_TEMPERATURE_VRMEM, 1376 METRICS_THROTTLER_STATUS, 1377 METRICS_CURR_FANSPEED, 1378 METRICS_VOLTAGE_VDDSOC, 1379 METRICS_VOLTAGE_VDDGFX, 1380 METRICS_SS_APU_SHARE, 1381 METRICS_SS_DGPU_SHARE, 1382 METRICS_UNIQUE_ID_UPPER32, 1383 METRICS_UNIQUE_ID_LOWER32, 1384 METRICS_PCIE_RATE, 1385 METRICS_PCIE_WIDTH, 1386 METRICS_CURR_FANPWM, 1387} MetricsMember_t; 1388 1389enum smu_cmn2asic_mapping_type { 1390 CMN2ASIC_MAPPING_MSG, 1391 CMN2ASIC_MAPPING_CLK, 1392 CMN2ASIC_MAPPING_FEATURE, 1393 CMN2ASIC_MAPPING_TABLE, 1394 CMN2ASIC_MAPPING_PWR, 1395 CMN2ASIC_MAPPING_WORKLOAD, 1396}; 1397 1398enum smu_baco_seq { 1399 BACO_SEQ_BACO = 0, 1400 BACO_SEQ_MSR, 1401 BACO_SEQ_BAMACO, 1402 BACO_SEQ_ULPS, 1403 BACO_SEQ_COUNT, 1404}; 1405 1406#define MSG_MAP(msg, index, valid_in_vf) \ 1407 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)} 1408 1409#define CLK_MAP(clk, index) \ 1410 [SMU_##clk] = {1, (index)} 1411 1412#define FEA_MAP(fea) \ 1413 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1414 1415#define FEA_MAP_REVERSE(fea) \ 1416 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1417 1418#define FEA_MAP_HALF_REVERSE(fea) \ 1419 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1420 1421#define TAB_MAP(tab) \ 1422 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1423 1424#define TAB_MAP_VALID(tab) \ 1425 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1426 1427#define TAB_MAP_INVALID(tab) \ 1428 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1429 1430#define PWR_MAP(tab) \ 1431 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1432 1433#define WORKLOAD_MAP(profile, workload) \ 1434 [profile] = {1, (workload)} 1435 1436/** 1437 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1438 * 1439 * @dst: Pointer to destination struct 1440 * @first_dst_member: The member name in @dst where the overwrite begins 1441 * @last_dst_member: The member name in @dst where the overwrite ends after 1442 * @src: Pointer to the source struct 1443 * @first_src_member: The member name in @src where the copy begins 1444 * 1445 */ 1446#define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1447 src, first_src_member) \ 1448({ \ 1449 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1450 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1451 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1452 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1453 __dst_offset; \ 1454 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1455 (u8 *)(src) + __src_offset, \ 1456 __dst_size); \ 1457}) 1458 1459#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1460int smu_get_power_limit(void *handle, 1461 uint32_t *limit, 1462 enum pp_power_limit_level pp_limit_level, 1463 enum pp_power_type pp_power_type); 1464 1465bool smu_mode1_reset_is_support(struct smu_context *smu); 1466bool smu_mode2_reset_is_support(struct smu_context *smu); 1467int smu_mode1_reset(struct smu_context *smu); 1468 1469extern const struct amd_ip_funcs smu_ip_funcs; 1470 1471bool is_support_sw_smu(struct amdgpu_device *adev); 1472bool is_support_cclk_dpm(struct amdgpu_device *adev); 1473int smu_write_watermarks_table(struct smu_context *smu); 1474 1475int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1476 uint32_t *min, uint32_t *max); 1477 1478int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1479 uint32_t min, uint32_t max); 1480 1481int smu_set_gfx_power_up_by_imu(struct smu_context *smu); 1482 1483int smu_set_ac_dc(struct smu_context *smu); 1484 1485int smu_allow_xgmi_power_down(struct smu_context *smu, bool en); 1486 1487int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); 1488 1489int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); 1490 1491int smu_set_residency_gfxoff(struct smu_context *smu, bool value); 1492 1493int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1494 1495int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1496 1497int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1498 uint64_t event_arg); 1499int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1500int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1501void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1502int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1503int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1504#endif 1505#endif 1506