1/* 2 * 3 * Copyright (C) 2016 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#ifndef SMU_6_0_SH_MASK_H 24#define SMU_6_0_SH_MASK_H 25 26#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03ffffffL 27#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000 28#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x000003f0L 29#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004 30#define GPIOPAD_A__GPIO_A_MASK 0x7fffffffL 31#define GPIOPAD_A__GPIO_A__SHIFT 0x00000000 32#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL 33#define GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000 34#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x00000020L 35#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x00000005 36#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x00000040L 37#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x00000006 38#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x0000001fL 39#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x00000000 40#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffffL 41#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x00000000 42#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L 43#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x0000001f 44#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffffL 45#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x00000000 46#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L 47#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x0000001f 48#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L 49#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x00000000 50#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L 51#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0x0000000a 52#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L 53#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0x0000000b 54#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L 55#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0x0000000c 56#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L 57#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0x0000000d 58#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L 59#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0x0000000e 60#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L 61#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0x0000000f 62#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L 63#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x00000010 64#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L 65#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x00000011 66#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L 67#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x00000012 68#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L 69#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x00000013 70#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L 71#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x00000001 72#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L 73#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x00000014 74#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L 75#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x00000015 76#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L 77#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x00000016 78#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L 79#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x00000017 80#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L 81#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x00000018 82#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L 83#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x00000019 84#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L 85#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x0000001a 86#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L 87#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x0000001b 88#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L 89#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x0000001c 90#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L 91#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x00000002 92#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L 93#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x00000003 94#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L 95#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x00000004 96#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L 97#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x00000005 98#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L 99#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x00000006 100#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L 101#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x00000007 102#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L 103#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x00000008 104#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L 105#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x00000009 106#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L 107#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x0000001f 108#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffffL 109#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x00000000 110#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L 111#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x0000001f 112#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffffL 113#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x00000000 114#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L 115#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x0000001f 116#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffffL 117#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x00000000 118#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L 119#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x0000001f 120#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffffL 121#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x00000000 122#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffffL 123#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x00000000 124#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L 125#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x00000000 126#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L 127#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0x0000000a 128#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L 129#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0x0000000b 130#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L 131#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0x0000000c 132#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L 133#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0x0000000d 134#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L 135#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0x0000000e 136#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L 137#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0x0000000f 138#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L 139#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x00000010 140#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L 141#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x00000011 142#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L 143#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x00000012 144#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L 145#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x00000013 146#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L 147#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x00000001 148#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L 149#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x00000014 150#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L 151#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x00000015 152#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L 153#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x00000016 154#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L 155#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x00000017 156#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L 157#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x00000018 158#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L 159#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x00000019 160#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L 161#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x0000001a 162#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L 163#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x0000001b 164#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L 165#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x0000001c 166#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L 167#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x0000001d 168#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L 169#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x00000002 170#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L 171#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x0000001e 172#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L 173#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x00000003 174#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L 175#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x00000004 176#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L 177#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x00000005 178#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L 179#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x00000006 180#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L 181#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x00000007 182#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L 183#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x00000008 184#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L 185#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x00000009 186#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffffL 187#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x00000000 188#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffffL 189#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x00000000 190#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0x0000000fL 191#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x00000000 192#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0x000000f0L 193#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x00000004 194#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L 195#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x00000000 196#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffffL 197#define GPIOPAD_Y__GPIO_Y__SHIFT 0x00000000 198#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x00000001L 199#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x00000000 200#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x0001fffeL 201#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x00000001 202#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffffL 203#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x00000000 204#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffffL 205#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x00000000 206#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x00000001L 207#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x00000000 208#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x0001fffeL 209#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x00000001 210#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffffL 211#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x00000000 212#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffffL 213#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x00000000 214#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x00000001L 215#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x00000000 216#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x0001fffeL 217#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x00000001 218#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffffL 219#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x00000000 220#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffffL 221#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x00000000 222#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x00000001L 223#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x00000000 224#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x0001fffeL 225#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x00000001 226#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffffL 227#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x00000000 228#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffffL 229#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x00000000 230#define LCAC_MC4_CNTL__MC4_ENABLE_MASK 0x00000001L 231#define LCAC_MC4_CNTL__MC4_ENABLE__SHIFT 0x00000000 232#define LCAC_MC4_CNTL__MC4_THRESHOLD_MASK 0x0001fffeL 233#define LCAC_MC4_CNTL__MC4_THRESHOLD__SHIFT 0x00000001 234#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL_MASK 0xffffffffL 235#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL__SHIFT 0x00000000 236#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL_MASK 0xffffffffL 237#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL__SHIFT 0x00000000 238#define LCAC_MC5_CNTL__MC5_ENABLE_MASK 0x00000001L 239#define LCAC_MC5_CNTL__MC5_ENABLE__SHIFT 0x00000000 240#define LCAC_MC5_CNTL__MC5_THRESHOLD_MASK 0x0001fffeL 241#define LCAC_MC5_CNTL__MC5_THRESHOLD__SHIFT 0x00000001 242#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL_MASK 0xffffffffL 243#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL__SHIFT 0x00000000 244#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL_MASK 0xffffffffL 245#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL__SHIFT 0x00000000 246#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x00000001L 247#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x00000000 248#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x00000100L 249#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x00000008 250#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x00010000L 251#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x00000010 252#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x01000000L 253#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x00000018 254#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffffL 255#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x00000000 256#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffffL 257#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x00000000 258#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffffL 259#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x00000000 260#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffffL 261#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x00000000 262#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffffL 263#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x00000000 264#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffffL 265#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x00000000 266#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffffL 267#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x00000000 268#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffffL 269#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x00000000 270#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffffL 271#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x00000000 272#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffffL 273#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x00000000 274#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffffffffL 275#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x00000000 276#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffffffffL 277#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x00000000 278#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffffffffL 279#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x00000000 280#define SMC_PC_C__smc_pc_c_MASK 0xffffffffL 281#define SMC_PC_C__smc_pc_c__SHIFT 0x00000000 282#define SMC_RESP_0__SMC_RESP_MASK 0xffffffffL 283#define SMC_RESP_0__SMC_RESP__SHIFT 0x00000000 284#define SMC_RESP_1__SMC_RESP_MASK 0xffffffffL 285#define SMC_RESP_1__SMC_RESP__SHIFT 0x00000000 286#define SMC_RESP_2__SMC_RESP_MASK 0xffffffffL 287#define SMC_RESP_2__SMC_RESP__SHIFT 0x00000000 288#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0x000ff000L 289#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0x0000000c 290#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x00000010L 291#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x00000004 292#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x00000008L 293#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x00000003 294#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x00000002L 295#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x00000001 296#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000L 297#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x0000001c 298#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x00000001L 299#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x00000000 300#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0x00000c00L 301#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0x0000000a 302#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x00000004L 303#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x00000002 304#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000L 305#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x0000001d 306#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0x0f000000L 307#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x00000018 308#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000L 309#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x0000001c 310#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x0000001fL 311#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x00000000 312#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0x0000ffe0L 313#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x00000005 314#define THM_TMON0_INT_DATA__TEMP_MASK 0x00fff000L 315#define THM_TMON0_INT_DATA__TEMP__SHIFT 0x0000000c 316#define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L 317#define THM_TMON0_INT_DATA__VALID__SHIFT 0x0000000b 318#define THM_TMON0_INT_DATA__Z_MASK 0x000007ffL 319#define THM_TMON0_INT_DATA__Z__SHIFT 0x00000000 320#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00fff000L 321#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0x0000000c 322#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L 323#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0x0000000b 324#define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007ffL 325#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x00000000 326#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00fff000L 327#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0x0000000c 328#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L 329#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0x0000000b 330#define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007ffL 331#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x00000000 332#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00fff000L 333#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0x0000000c 334#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L 335#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0x0000000b 336#define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007ffL 337#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x00000000 338#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00fff000L 339#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0x0000000c 340#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L 341#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0x0000000b 342#define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007ffL 343#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x00000000 344#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00fff000L 345#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0x0000000c 346#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L 347#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0x0000000b 348#define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007ffL 349#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x00000000 350#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00fff000L 351#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0x0000000c 352#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L 353#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0x0000000b 354#define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007ffL 355#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x00000000 356#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00fff000L 357#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0x0000000c 358#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L 359#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0x0000000b 360#define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007ffL 361#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x00000000 362#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00fff000L 363#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0x0000000c 364#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L 365#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0x0000000b 366#define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007ffL 367#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x00000000 368#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00fff000L 369#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0x0000000c 370#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L 371#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0x0000000b 372#define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007ffL 373#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x00000000 374#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00fff000L 375#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0x0000000c 376#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L 377#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0x0000000b 378#define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007ffL 379#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x00000000 380#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00fff000L 381#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0x0000000c 382#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L 383#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0x0000000b 384#define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007ffL 385#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x00000000 386#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00fff000L 387#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0x0000000c 388#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L 389#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0x0000000b 390#define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007ffL 391#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x00000000 392#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00fff000L 393#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0x0000000c 394#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L 395#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0x0000000b 396#define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007ffL 397#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x00000000 398#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00fff000L 399#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0x0000000c 400#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L 401#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0x0000000b 402#define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007ffL 403#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x00000000 404#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00fff000L 405#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0x0000000c 406#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L 407#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0x0000000b 408#define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007ffL 409#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x00000000 410#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00fff000L 411#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0x0000000c 412#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L 413#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0x0000000b 414#define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007ffL 415#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x00000000 416#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00fff000L 417#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0x0000000c 418#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L 419#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0x0000000b 420#define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007ffL 421#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x00000000 422#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00fff000L 423#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0x0000000c 424#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L 425#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0x0000000b 426#define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007ffL 427#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x00000000 428#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00fff000L 429#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0x0000000c 430#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L 431#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0x0000000b 432#define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007ffL 433#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x00000000 434#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00fff000L 435#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0x0000000c 436#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L 437#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0x0000000b 438#define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007ffL 439#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x00000000 440#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00fff000L 441#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0x0000000c 442#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L 443#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0x0000000b 444#define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007ffL 445#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x00000000 446#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00fff000L 447#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0x0000000c 448#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L 449#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0x0000000b 450#define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007ffL 451#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x00000000 452#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00fff000L 453#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0x0000000c 454#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L 455#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0x0000000b 456#define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007ffL 457#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x00000000 458#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00fff000L 459#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0x0000000c 460#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L 461#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0x0000000b 462#define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007ffL 463#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x00000000 464#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00fff000L 465#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0x0000000c 466#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L 467#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0x0000000b 468#define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007ffL 469#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x00000000 470#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00fff000L 471#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0x0000000c 472#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L 473#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0x0000000b 474#define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007ffL 475#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x00000000 476#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00fff000L 477#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0x0000000c 478#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L 479#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0x0000000b 480#define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007ffL 481#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x00000000 482#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00fff000L 483#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0x0000000c 484#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L 485#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0x0000000b 486#define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007ffL 487#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x00000000 488#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00fff000L 489#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0x0000000c 490#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L 491#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0x0000000b 492#define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007ffL 493#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x00000000 494#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00fff000L 495#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0x0000000c 496#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L 497#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0x0000000b 498#define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007ffL 499#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x00000000 500#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00fff000L 501#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0x0000000c 502#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L 503#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0x0000000b 504#define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007ffL 505#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x00000000 506#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00fff000L 507#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0x0000000c 508#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L 509#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0x0000000b 510#define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007ffL 511#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x00000000 512#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x0000001fL 513#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x00000000 514#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0x0000ffe0L 515#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x00000005 516#define THM_TMON1_INT_DATA__TEMP_MASK 0x00fff000L 517#define THM_TMON1_INT_DATA__TEMP__SHIFT 0x0000000c 518#define THM_TMON1_INT_DATA__VALID_MASK 0x00000800L 519#define THM_TMON1_INT_DATA__VALID__SHIFT 0x0000000b 520#define THM_TMON1_INT_DATA__Z_MASK 0x000007ffL 521#define THM_TMON1_INT_DATA__Z__SHIFT 0x00000000 522#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0x00fff000L 523#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0x0000000c 524#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x00000800L 525#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0x0000000b 526#define THM_TMON1_RDIL0_DATA__Z_MASK 0x000007ffL 527#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x00000000 528#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0x00fff000L 529#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0x0000000c 530#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x00000800L 531#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0x0000000b 532#define THM_TMON1_RDIL10_DATA__Z_MASK 0x000007ffL 533#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x00000000 534#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0x00fff000L 535#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0x0000000c 536#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x00000800L 537#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0x0000000b 538#define THM_TMON1_RDIL11_DATA__Z_MASK 0x000007ffL 539#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x00000000 540#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0x00fff000L 541#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0x0000000c 542#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x00000800L 543#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0x0000000b 544#define THM_TMON1_RDIL12_DATA__Z_MASK 0x000007ffL 545#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x00000000 546#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0x00fff000L 547#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0x0000000c 548#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x00000800L 549#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0x0000000b 550#define THM_TMON1_RDIL13_DATA__Z_MASK 0x000007ffL 551#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x00000000 552#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0x00fff000L 553#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0x0000000c 554#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x00000800L 555#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0x0000000b 556#define THM_TMON1_RDIL14_DATA__Z_MASK 0x000007ffL 557#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x00000000 558#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0x00fff000L 559#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0x0000000c 560#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x00000800L 561#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0x0000000b 562#define THM_TMON1_RDIL15_DATA__Z_MASK 0x000007ffL 563#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x00000000 564#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0x00fff000L 565#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0x0000000c 566#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x00000800L 567#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0x0000000b 568#define THM_TMON1_RDIL1_DATA__Z_MASK 0x000007ffL 569#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x00000000 570#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0x00fff000L 571#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0x0000000c 572#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x00000800L 573#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0x0000000b 574#define THM_TMON1_RDIL2_DATA__Z_MASK 0x000007ffL 575#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x00000000 576#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0x00fff000L 577#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0x0000000c 578#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x00000800L 579#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0x0000000b 580#define THM_TMON1_RDIL3_DATA__Z_MASK 0x000007ffL 581#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x00000000 582#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0x00fff000L 583#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0x0000000c 584#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x00000800L 585#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0x0000000b 586#define THM_TMON1_RDIL4_DATA__Z_MASK 0x000007ffL 587#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x00000000 588#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0x00fff000L 589#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0x0000000c 590#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x00000800L 591#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0x0000000b 592#define THM_TMON1_RDIL5_DATA__Z_MASK 0x000007ffL 593#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x00000000 594#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0x00fff000L 595#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0x0000000c 596#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x00000800L 597#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0x0000000b 598#define THM_TMON1_RDIL6_DATA__Z_MASK 0x000007ffL 599#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x00000000 600#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0x00fff000L 601#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0x0000000c 602#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x00000800L 603#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0x0000000b 604#define THM_TMON1_RDIL7_DATA__Z_MASK 0x000007ffL 605#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x00000000 606#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0x00fff000L 607#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0x0000000c 608#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x00000800L 609#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0x0000000b 610#define THM_TMON1_RDIL8_DATA__Z_MASK 0x000007ffL 611#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x00000000 612#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0x00fff000L 613#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0x0000000c 614#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x00000800L 615#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0x0000000b 616#define THM_TMON1_RDIL9_DATA__Z_MASK 0x000007ffL 617#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x00000000 618#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0x00fff000L 619#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0x0000000c 620#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x00000800L 621#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0x0000000b 622#define THM_TMON1_RDIR0_DATA__Z_MASK 0x000007ffL 623#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x00000000 624#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0x00fff000L 625#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0x0000000c 626#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x00000800L 627#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0x0000000b 628#define THM_TMON1_RDIR10_DATA__Z_MASK 0x000007ffL 629#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x00000000 630#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0x00fff000L 631#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0x0000000c 632#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x00000800L 633#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0x0000000b 634#define THM_TMON1_RDIR11_DATA__Z_MASK 0x000007ffL 635#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x00000000 636#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0x00fff000L 637#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0x0000000c 638#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x00000800L 639#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0x0000000b 640#define THM_TMON1_RDIR12_DATA__Z_MASK 0x000007ffL 641#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x00000000 642#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0x00fff000L 643#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0x0000000c 644#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x00000800L 645#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0x0000000b 646#define THM_TMON1_RDIR13_DATA__Z_MASK 0x000007ffL 647#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x00000000 648#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0x00fff000L 649#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0x0000000c 650#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x00000800L 651#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0x0000000b 652#define THM_TMON1_RDIR14_DATA__Z_MASK 0x000007ffL 653#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x00000000 654#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0x00fff000L 655#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0x0000000c 656#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x00000800L 657#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0x0000000b 658#define THM_TMON1_RDIR15_DATA__Z_MASK 0x000007ffL 659#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x00000000 660#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0x00fff000L 661#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0x0000000c 662#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x00000800L 663#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0x0000000b 664#define THM_TMON1_RDIR1_DATA__Z_MASK 0x000007ffL 665#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x00000000 666#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0x00fff000L 667#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0x0000000c 668#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x00000800L 669#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0x0000000b 670#define THM_TMON1_RDIR2_DATA__Z_MASK 0x000007ffL 671#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x00000000 672#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0x00fff000L 673#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0x0000000c 674#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x00000800L 675#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0x0000000b 676#define THM_TMON1_RDIR3_DATA__Z_MASK 0x000007ffL 677#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x00000000 678#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0x00fff000L 679#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0x0000000c 680#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x00000800L 681#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0x0000000b 682#define THM_TMON1_RDIR4_DATA__Z_MASK 0x000007ffL 683#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x00000000 684#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0x00fff000L 685#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0x0000000c 686#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x00000800L 687#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0x0000000b 688#define THM_TMON1_RDIR5_DATA__Z_MASK 0x000007ffL 689#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x00000000 690#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0x00fff000L 691#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0x0000000c 692#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x00000800L 693#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0x0000000b 694#define THM_TMON1_RDIR6_DATA__Z_MASK 0x000007ffL 695#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x00000000 696#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0x00fff000L 697#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0x0000000c 698#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x00000800L 699#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0x0000000b 700#define THM_TMON1_RDIR7_DATA__Z_MASK 0x000007ffL 701#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x00000000 702#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0x00fff000L 703#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0x0000000c 704#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x00000800L 705#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0x0000000b 706#define THM_TMON1_RDIR8_DATA__Z_MASK 0x000007ffL 707#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x00000000 708#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0x00fff000L 709#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0x0000000c 710#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x00000800L 711#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0x0000000b 712#define THM_TMON1_RDIR9_DATA__Z_MASK 0x000007ffL 713#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x00000000 714 715#endif 716