oss_3_0_1_sh_mask.h revision 1.1
1/* 2 * OSS_3_0_1 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef OSS_3_0_1_SH_MASK_H 25#define OSS_3_0_1_SH_MASK_H 26 27#define IH_VMID_0_LUT__PASID_MASK 0xffff 28#define IH_VMID_0_LUT__PASID__SHIFT 0x0 29#define IH_VMID_1_LUT__PASID_MASK 0xffff 30#define IH_VMID_1_LUT__PASID__SHIFT 0x0 31#define IH_VMID_2_LUT__PASID_MASK 0xffff 32#define IH_VMID_2_LUT__PASID__SHIFT 0x0 33#define IH_VMID_3_LUT__PASID_MASK 0xffff 34#define IH_VMID_3_LUT__PASID__SHIFT 0x0 35#define IH_VMID_4_LUT__PASID_MASK 0xffff 36#define IH_VMID_4_LUT__PASID__SHIFT 0x0 37#define IH_VMID_5_LUT__PASID_MASK 0xffff 38#define IH_VMID_5_LUT__PASID__SHIFT 0x0 39#define IH_VMID_6_LUT__PASID_MASK 0xffff 40#define IH_VMID_6_LUT__PASID__SHIFT 0x0 41#define IH_VMID_7_LUT__PASID_MASK 0xffff 42#define IH_VMID_7_LUT__PASID__SHIFT 0x0 43#define IH_VMID_8_LUT__PASID_MASK 0xffff 44#define IH_VMID_8_LUT__PASID__SHIFT 0x0 45#define IH_VMID_9_LUT__PASID_MASK 0xffff 46#define IH_VMID_9_LUT__PASID__SHIFT 0x0 47#define IH_VMID_10_LUT__PASID_MASK 0xffff 48#define IH_VMID_10_LUT__PASID__SHIFT 0x0 49#define IH_VMID_11_LUT__PASID_MASK 0xffff 50#define IH_VMID_11_LUT__PASID__SHIFT 0x0 51#define IH_VMID_12_LUT__PASID_MASK 0xffff 52#define IH_VMID_12_LUT__PASID__SHIFT 0x0 53#define IH_VMID_13_LUT__PASID_MASK 0xffff 54#define IH_VMID_13_LUT__PASID__SHIFT 0x0 55#define IH_VMID_14_LUT__PASID_MASK 0xffff 56#define IH_VMID_14_LUT__PASID__SHIFT 0x0 57#define IH_VMID_15_LUT__PASID_MASK 0xffff 58#define IH_VMID_15_LUT__PASID__SHIFT 0x0 59#define IH_RB_CNTL__RB_ENABLE_MASK 0x1 60#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 61#define IH_RB_CNTL__RB_SIZE_MASK 0x3e 62#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 63#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40 64#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6 65#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80 66#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 67#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 68#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 69#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00 70#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 71#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000 72#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 73#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 74#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 75#define IH_RB_BASE__ADDR_MASK 0xffffffff 76#define IH_RB_BASE__ADDR__SHIFT 0x0 77#define IH_RB_RPTR__OFFSET_MASK 0x3fffc 78#define IH_RB_RPTR__OFFSET__SHIFT 0x2 79#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1 80#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 81#define IH_RB_WPTR__OFFSET_MASK 0x3fffc 82#define IH_RB_WPTR__OFFSET__SHIFT 0x2 83#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000 84#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 85#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000 86#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 87#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff 88#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 89#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc 90#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 91#define IH_CNTL__ENABLE_INTR_MASK 0x1 92#define IH_CNTL__ENABLE_INTR__SHIFT 0x0 93#define IH_CNTL__MC_SWAP_MASK 0x6 94#define IH_CNTL__MC_SWAP__SHIFT 0x1 95#define IH_CNTL__RPTR_REARM_MASK 0x10 96#define IH_CNTL__RPTR_REARM__SHIFT 0x4 97#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300 98#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8 99#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00 100#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa 101#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000 102#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf 103#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000 104#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 105#define IH_CNTL__MC_VMID_MASK 0x1e000000 106#define IH_CNTL__MC_VMID__SHIFT 0x19 107#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1 108#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0 109#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4 110#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2 111#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8 112#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3 113#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10 114#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4 115#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20 116#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5 117#define IH_STATUS__IDLE_MASK 0x1 118#define IH_STATUS__IDLE__SHIFT 0x0 119#define IH_STATUS__INPUT_IDLE_MASK 0x2 120#define IH_STATUS__INPUT_IDLE__SHIFT 0x1 121#define IH_STATUS__RB_IDLE_MASK 0x4 122#define IH_STATUS__RB_IDLE__SHIFT 0x2 123#define IH_STATUS__RB_FULL_MASK 0x8 124#define IH_STATUS__RB_FULL__SHIFT 0x3 125#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10 126#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 127#define IH_STATUS__RB_OVERFLOW_MASK 0x20 128#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 129#define IH_STATUS__MC_WR_IDLE_MASK 0x40 130#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 131#define IH_STATUS__MC_WR_STALL_MASK 0x80 132#define IH_STATUS__MC_WR_STALL__SHIFT 0x7 133#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100 134#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 135#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200 136#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 137#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400 138#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa 139#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1 140#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 141#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2 142#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 143#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc 144#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 145#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100 146#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8 147#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200 148#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9 149#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 150#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa 151#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 152#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 153#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 154#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 155#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff 156#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 157#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff 158#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 159#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff 160#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 161#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1 162#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 163#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4 164#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 165#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8 166#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 167#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10 168#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 169#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20 170#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 171#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff 172#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 173#define IH_VERSION__VALUE_MASK 0xfff 174#define IH_VERSION__VALUE__SHIFT 0x0 175#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3 176#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 177#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc 178#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 179#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00 180#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 181#define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 182#define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 183#define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 184#define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 185#define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc 186#define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 187#define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x400 188#define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 189#define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x800 190#define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 191#define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0xff000 192#define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 193#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 194#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 195#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 196#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 197#define SEM_VF_ENABLE__VALUE_MASK 0x1 198#define SEM_VF_ENABLE__VALUE__SHIFT 0x0 199#define SEM_ACTIVE_FCN_ID__VFID_MASK 0xf 200#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0 201#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000 202#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f 203#define SEM_VIRT_RESET_REQ__VF_MASK 0xffff 204#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0 205#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000 206#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f 207#define SEM_STATUS__SEM_IDLE_MASK 0x1 208#define SEM_STATUS__SEM_IDLE__SHIFT 0x0 209#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2 210#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 211#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4 212#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 213#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8 214#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 215#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10 216#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 217#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20 218#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 219#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40 220#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 221#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80 222#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 223#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100 224#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 225#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200 226#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 227#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400 228#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa 229#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800 230#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb 231#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000 232#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc 233#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000 234#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd 235#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000 236#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe 237#define SEM_STATUS__ATC_REQ_PENDING_MASK 0x8000 238#define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0xf 239#define SEM_STATUS__SWITCH_READY_MASK 0x80000000 240#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f 241#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2 242#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 243#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7 244#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 245#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38 246#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 247#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0 248#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 249#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00 250#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 251#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000 252#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc 253#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000 254#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf 255#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000 256#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 257#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000 258#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 259#define SEM_MAILBOX__SIDEPORT_MASK 0xff 260#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0 261#define SEM_MAILBOX__HOSTPORT_MASK 0xff00 262#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8 263#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000 264#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10 265#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000 266#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18 267#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff 268#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0 269#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00 270#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8 271#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000 272#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10 273#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000 274#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18 275#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1 276#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 277#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2 278#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 279#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4 280#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 281#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18 282#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 283#define SEM_CHICKEN_BITS__SIGNAL_FAIL_MASK 0x20 284#define SEM_CHICKEN_BITS__SIGNAL_FAIL__SHIFT 0x5 285#define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x40 286#define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x6 287#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x80 288#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x7 289#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00 290#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 291#define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x3000 292#define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0xc 293#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f 294#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 295#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000 296#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10 297#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000 298#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11 299#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000 300#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12 301#define SRBM_CNTL__PWR_GFX3D_REQUEST_HALT_MASK 0x80000 302#define SRBM_CNTL__PWR_GFX3D_REQUEST_HALT__SHIFT 0x13 303#define SRBM_GFX_CNTL__PIPEID_MASK 0x3 304#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0 305#define SRBM_GFX_CNTL__MEID_MASK 0xc 306#define SRBM_GFX_CNTL__MEID__SHIFT 0x2 307#define SRBM_GFX_CNTL__VMID_MASK 0xf0 308#define SRBM_GFX_CNTL__VMID__SHIFT 0x4 309#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700 310#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 311#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff 312#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0 313#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1 314#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0 315#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2 316#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1 317#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4 318#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2 319#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8 320#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3 321#define SRBM_STATUS2__VP8_BUSY_MASK 0x10 322#define SRBM_STATUS2__VP8_BUSY__SHIFT 0x4 323#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20 324#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5 325#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40 326#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6 327#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80 328#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7 329#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100 330#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8 331#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200 332#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9 333#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400 334#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa 335#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800 336#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb 337#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000 338#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd 339#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000 340#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe 341#define SRBM_STATUS2__ODE_BUSY_MASK 0x8000 342#define SRBM_STATUS2__ODE_BUSY__SHIFT 0xf 343#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000 344#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10 345#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000 346#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11 347#define SRBM_STATUS2__VP8_RQ_PENDING_MASK 0x40000 348#define SRBM_STATUS2__VP8_RQ_PENDING__SHIFT 0x12 349#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000 350#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13 351#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000 352#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14 353#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2 354#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1 355#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4 356#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2 357#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8 358#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3 359#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10 360#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4 361#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20 362#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5 363#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40 364#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6 365#define SRBM_STATUS__VMC_BUSY_MASK 0x100 366#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8 367#define SRBM_STATUS__MCB_BUSY_MASK 0x200 368#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9 369#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400 370#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa 371#define SRBM_STATUS__MCC_BUSY_MASK 0x800 372#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb 373#define SRBM_STATUS__MCD_BUSY_MASK 0x1000 374#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc 375#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000 376#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd 377#define SRBM_STATUS__SEM_BUSY_MASK 0x4000 378#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe 379#define SRBM_STATUS__ACP_BUSY_MASK 0x10000 380#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10 381#define SRBM_STATUS__IH_BUSY_MASK 0x20000 382#define SRBM_STATUS__IH_BUSY__SHIFT 0x11 383#define SRBM_STATUS__UVD_BUSY_MASK 0x80000 384#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13 385#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000 386#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14 387#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000 388#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15 389#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000 390#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16 391#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000 392#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d 393#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1 394#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0 395#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2 396#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1 397#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4 398#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2 399#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8 400#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3 401#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10 402#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4 403#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20 404#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5 405#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40 406#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6 407#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80 408#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7 409#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100 410#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8 411#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200 412#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9 413#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400 414#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa 415#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800 416#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb 417#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000 418#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc 419#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000 420#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd 421#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000 422#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe 423#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000 424#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf 425#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1 426#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0 427#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2 428#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1 429#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4 430#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2 431#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8 432#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3 433#define SRBM_SOFT_RESET__SOFT_RESET_GIONB_MASK 0x10 434#define SRBM_SOFT_RESET__SOFT_RESET_GIONB__SHIFT 0x4 435#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20 436#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5 437#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40 438#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6 439#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100 440#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8 441#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200 442#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9 443#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400 444#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa 445#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800 446#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb 447#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000 448#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc 449#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000 450#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd 451#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000 452#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe 453#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000 454#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf 455#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000 456#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10 457#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000 458#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11 459#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000 460#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12 461#define SRBM_SOFT_RESET__SOFT_RESET_VP8_MASK 0x80000 462#define SRBM_SOFT_RESET__SOFT_RESET_VP8__SHIFT 0x13 463#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000 464#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14 465#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000 466#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15 467#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000 468#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16 469#define SRBM_SOFT_RESET__SOFT_RESET_ODE_MASK 0x800000 470#define SRBM_SOFT_RESET__SOFT_RESET_ODE__SHIFT 0x17 471#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000 472#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18 473#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000 474#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19 475#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000 476#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a 477#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000 478#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b 479#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000 480#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d 481#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000 482#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e 483#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000 484#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f 485#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f 486#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0 487#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff 488#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0 489#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff 490#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 491#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 492#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 493#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 494#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc 495#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 496#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 497#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 498#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 499#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 500#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 501#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 502#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 503#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 504#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 505#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 506#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 507#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 508#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 509#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 510#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 511#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 512#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 513#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 514#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 515#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 516#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 517#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 518#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 519#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 520#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 521#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 522#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 523#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 524#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 525#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 526#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 527#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 528#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 529#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 530#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 531#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 532#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 533#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 534#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 535#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1 536#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0 537#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2 538#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1 539#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4 540#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2 541#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10 542#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4 543#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20 544#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5 545#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40 546#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6 547#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80 548#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7 549#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100 550#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8 551#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200 552#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9 553#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400 554#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa 555#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE_MASK 0x800 556#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xb 557#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1 558#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0 559#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK 0x2 560#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT 0x1 561#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4 562#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2 563#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8 564#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3 565#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10 566#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4 567#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20 568#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5 569#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40 570#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6 571#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80 572#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7 573#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100 574#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8 575#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200 576#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9 577#define SRBM_DEBUG_SNAPSHOT__VP8_RDY_MASK 0x400 578#define SRBM_DEBUG_SNAPSHOT__VP8_RDY__SHIFT 0xa 579#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800 580#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb 581#define SRBM_DEBUG_SNAPSHOT__ODE_RDY_MASK 0x1000 582#define SRBM_DEBUG_SNAPSHOT__ODE_RDY__SHIFT 0xc 583#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000 584#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd 585#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000 586#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe 587#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000 588#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf 589#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000 590#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10 591#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000 592#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11 593#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000 594#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12 595#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000 596#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13 597#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000 598#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14 599#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000 600#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15 601#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000 602#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16 603#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000 604#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17 605#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000 606#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18 607#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000 608#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19 609#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000 610#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a 611#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000 612#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b 613#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000 614#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c 615#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000 616#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d 617#define SRBM_DEBUG_SNAPSHOT__RESERVED_MASK 0x40000000 618#define SRBM_DEBUG_SNAPSHOT__RESERVED__SHIFT 0x1e 619#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000 620#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f 621#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1 622#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0 623#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc 624#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 625#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000 626#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12 627#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000 628#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13 629#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000 630#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14 631#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000 632#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15 633#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000 634#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16 635#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000 636#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17 637#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000 638#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18 639#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000 640#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19 641#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000 642#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a 643#define SRBM_READ_ERROR__READ_REQUESTER_VP8_MASK 0x8000000 644#define SRBM_READ_ERROR__READ_REQUESTER_VP8__SHIFT 0x1b 645#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000 646#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c 647#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000 648#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d 649#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 650#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f 651#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1 652#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0 653#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2 654#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1 655#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4 656#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2 657#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000 658#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17 659#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000 660#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18 661#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1 662#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0 663#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2 664#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1 665#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1 666#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0 667#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2 668#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1 669#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1 670#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0 671#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2 672#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1 673#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1 674#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0 675#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2 676#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1 677#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VP8_MASK 0x4 678#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VP8__SHIFT 0x2 679#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8 680#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3 681#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20 682#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5 683#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40 684#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6 685#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80 686#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7 687#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100 688#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8 689#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200 690#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9 691#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400 692#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa 693#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800 694#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb 695#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000 696#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc 697#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000 698#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd 699#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000 700#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe 701#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000 702#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf 703#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000 704#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10 705#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000 706#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11 707#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000 708#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12 709#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000 710#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13 711#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000 712#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14 713#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000 714#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18 715#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000 716#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19 717#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000 718#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a 719#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000 720#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b 721#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000 722#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c 723#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc 724#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2 725#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000 726#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13 727#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000 728#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14 729#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000 730#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f 731#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff 732#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0 733#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000 734#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10 735#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff 736#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0 737#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff 738#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0 739#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000 740#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10 741#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff 742#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0 743#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf 744#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 745#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 746#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 747#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 748#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa 749#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f 750#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 751#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f 752#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 753#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff 754#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0 755#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff 756#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0 757#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff 758#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0 759#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff 760#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0 761#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3 762#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 763#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff 764#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 765#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 766#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 767#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 768#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 769#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 770#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 771#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 772#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 773#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 774#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 775#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 776#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 777#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 778#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 779#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff 780#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 781#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 782#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 783#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff 784#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 785#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 786#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 787#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff 788#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 789#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 790#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 791#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff 792#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 793#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 794#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 795#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 796#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 797#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 798#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 799#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 800#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 801#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 802#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 803#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 804#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 805#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 806#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 807#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff 808#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 809#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 810#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 811#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff 812#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 813#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 814#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 815#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff 816#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 817#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 818#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 819#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff 820#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 821#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 822#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 823#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 824#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 825#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 826#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 827#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 828#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 829#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 830#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 831#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 832#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 833#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 834#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 835#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff 836#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 837#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 838#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 839#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 840#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 841#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 842#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 843#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 844#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 845#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 846#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 847#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 848#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 849#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 850#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 851#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 852#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 853#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 854#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 855#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 856#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 857#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 858#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 859#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 860#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 861#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 862#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 863#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 864#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 865#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 866#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 867#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 868#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 869#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 870#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 871#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 872#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 873#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 874#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 875#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 876#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 877#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 878#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 879#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf 880#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0 881#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff 882#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0 883#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00 884#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8 885#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000 886#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10 887#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000 888#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d 889#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 890#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e 891#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000 892#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f 893#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf 894#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0 895#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3 896#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0 897#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc 898#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2 899#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0 900#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4 901#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700 902#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8 903#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1 904#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0 905#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1 906#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0 907#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff 908#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0 909#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000 910#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f 911#define SDMA0_UCODE_ADDR__VALUE_MASK 0x1fff 912#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 913#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff 914#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 915#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 916#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 917#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200 918#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 919#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400 920#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 921#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800 922#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 923#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000 924#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 925#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf 926#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 927#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 928#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 929#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 930#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 931#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 932#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 933#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 934#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 935#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 936#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 937#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 938#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 939#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 940#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 941#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 942#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 943#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 944#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 945#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1 946#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 947#define SDMA0_CNTL__ATC_L1_ENABLE_MASK 0x2 948#define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT 0x1 949#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 950#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 951#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8 952#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 953#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 954#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 955#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20 956#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 957#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 958#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb 959#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000 960#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 961#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 962#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 963#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 964#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 965#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 966#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 967#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 968#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 969#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 970#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 971#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 972#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 973#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 974#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 975#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 976#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 977#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 978#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 979#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 980#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 981#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 982#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 983#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 984#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 985#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 986#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 987#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 988#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 989#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 990#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 991#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7 992#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0 993#define SDMA0_HASH__BANK_BITS_MASK 0x70 994#define SDMA0_HASH__BANK_BITS__SHIFT 0x4 995#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700 996#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 997#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000 998#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc 999#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff 1000#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 1001#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc 1002#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 1003#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc 1004#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 1005#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff 1006#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 1007#define SDMA0_STATUS_REG__IDLE_MASK 0x1 1008#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 1009#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2 1010#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 1011#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4 1012#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 1013#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8 1014#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 1015#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10 1016#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 1017#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20 1018#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 1019#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40 1020#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 1021#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80 1022#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 1023#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100 1024#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 1025#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200 1026#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 1027#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400 1028#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 1029#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 1030#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 1031#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000 1032#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 1033#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000 1034#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 1035#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000 1036#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 1037#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 1038#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 1039#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 1040#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 1041#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 1042#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 1043#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 1044#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 1045#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000 1046#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 1047#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 1048#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 1049#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 1050#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 1051#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 1052#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 1053#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 1054#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 1055#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000 1056#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 1057#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 1058#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 1059#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 1060#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 1061#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000 1062#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 1063#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 1064#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 1065#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 1066#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 1067#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2 1068#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 1069#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 1070#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 1071#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 1072#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 1073#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 1074#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 1075#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20 1076#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 1077#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40 1078#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 1079#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 1080#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 1081#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 1082#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 1083#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 1084#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 1085#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 1086#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 1087#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000 1088#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 1089#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000 1090#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 1091#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x3 1092#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 1093#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 1094#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1095#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 1096#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1097#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc 1098#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1099#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x400 1100#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1101#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x800 1102#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1103#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xff000 1104#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1105#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 1106#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1107#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 1108#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1109#define SDMA0_F32_CNTL__HALT_MASK 0x1 1110#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 1111#define SDMA0_F32_CNTL__STEP_MASK 0x2 1112#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 1113#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc 1114#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 1115#define SDMA0_FREEZE__FREEZE_MASK 0x10 1116#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 1117#define SDMA0_FREEZE__FROZEN_MASK 0x20 1118#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 1119#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40 1120#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 1121#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf 1122#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 1123#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 1124#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 1125#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000 1126#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 1127#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf 1128#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 1129#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 1130#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 1131#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000 1132#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 1133#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1 1134#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0 1135#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2 1136#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1 1137#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4 1138#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2 1139#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30 1140#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 1141#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40 1142#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6 1143#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80 1144#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7 1145#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00 1146#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8 1147#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000 1148#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14 1149#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff 1150#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 1151#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 1152#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 1153#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200 1154#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 1155#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400 1156#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 1157#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800 1158#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 1159#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000 1160#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 1161#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000 1162#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 1163#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 1164#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 1165#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 1166#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 1167#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff 1168#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 1169#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff 1170#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 1171#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2 1172#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 1173#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 1174#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 1175#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff 1176#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 1177#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 1178#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 1179#define SDMA0_ID__DEVICE_ID_MASK 0xff 1180#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 1181#define SDMA0_VERSION__VALUE_MASK 0xffff 1182#define SDMA0_VERSION__VALUE__SHIFT 0x0 1183#define SDMA0_VM_CNTL__CMD_MASK 0xf 1184#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 1185#define SDMA0_VM_CTX_LO__ADDR_MASK 0xfffffffc 1186#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 1187#define SDMA0_VM_CTX_HI__ADDR_MASK 0xffffffff 1188#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 1189#define SDMA0_STATUS2_REG__ID_MASK 0x3 1190#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 1191#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc 1192#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 1193#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000 1194#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 1195#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0xf 1196#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 1197#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000 1198#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 1199#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x1 1200#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 1201#define SDMA0_VM_CTX_CNTL__VMID_MASK 0xf0 1202#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 1203#define SDMA0_VIRT_RESET_REQ__VF_MASK 0xffff 1204#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 1205#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000 1206#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 1207#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x1 1208#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 1209#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff 1210#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 1211#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000 1212#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 1213#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff 1214#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 1215#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff 1216#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 1217#define SDMA0_ATCL1_CNTL__REDO_ENABLE_MASK 0x1 1218#define SDMA0_ATCL1_CNTL__REDO_ENABLE__SHIFT 0x0 1219#define SDMA0_ATCL1_CNTL__REDO_DELAY_MASK 0x7fe 1220#define SDMA0_ATCL1_CNTL__REDO_DELAY__SHIFT 0x1 1221#define SDMA0_ATCL1_CNTL__REDO_WATERMK_MASK 0x3800 1222#define SDMA0_ATCL1_CNTL__REDO_WATERMK__SHIFT 0xb 1223#define SDMA0_ATCL1_CNTL__INVACK_DELAY_MASK 0xffc000 1224#define SDMA0_ATCL1_CNTL__INVACK_DELAY__SHIFT 0xe 1225#define SDMA0_ATCL1_CNTL__REQL2_CREDIT_MASK 0xf000000 1226#define SDMA0_ATCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 1227#define SDMA0_ATCL1_CNTL__VADDR_WATERMK_MASK 0x70000000 1228#define SDMA0_ATCL1_CNTL__VADDR_WATERMK__SHIFT 0x1c 1229#define SDMA0_ATCL1_WATERMK__REQMC_WATERMK_MASK 0x3ff 1230#define SDMA0_ATCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 1231#define SDMA0_ATCL1_WATERMK__REQPG_WATERMK_MASK 0x3fc00 1232#define SDMA0_ATCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 1233#define SDMA0_ATCL1_WATERMK__INVREQ_WATERMK_MASK 0xfc0000 1234#define SDMA0_ATCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 1235#define SDMA0_ATCL1_WATERMK__XNACK_WATERMK_MASK 0x7f000000 1236#define SDMA0_ATCL1_WATERMK__XNACK_WATERMK__SHIFT 0x18 1237#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1 1238#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 1239#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2 1240#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 1241#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4 1242#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 1243#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8 1244#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 1245#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10 1246#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 1247#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20 1248#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 1249#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40 1250#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 1251#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80 1252#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 1253#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100 1254#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 1255#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200 1256#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 1257#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400 1258#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 1259#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x800 1260#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 1261#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000 1262#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 1263#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000 1264#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 1265#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000 1266#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 1267#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000 1268#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 1269#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000 1270#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 1271#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000 1272#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 1273#define SDMA0_ATCL1_RD_STATUS__ALL_IDLE_MASK 0x40000 1274#define SDMA0_ATCL1_RD_STATUS__ALL_IDLE__SHIFT 0x12 1275#define SDMA0_ATCL1_RD_STATUS__REQL2_IDLE_MASK 0x80000 1276#define SDMA0_ATCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x13 1277#define SDMA0_ATCL1_RD_STATUS__REQMC_IDLE_MASK 0x100000 1278#define SDMA0_ATCL1_RD_STATUS__REQMC_IDLE__SHIFT 0x14 1279#define SDMA0_ATCL1_RD_STATUS__CE_L1_STALL_MASK 0x200000 1280#define SDMA0_ATCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 1281#define SDMA0_ATCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x3c00000 1282#define SDMA0_ATCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 1283#define SDMA0_ATCL1_RD_STATUS__MERGE_STATE_MASK 0x1c000000 1284#define SDMA0_ATCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 1285#define SDMA0_ATCL1_RD_STATUS__RESERVED_MASK 0xe0000000 1286#define SDMA0_ATCL1_RD_STATUS__RESERVED__SHIFT 0x1d 1287#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1 1288#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 1289#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2 1290#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 1291#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4 1292#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 1293#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8 1294#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 1295#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10 1296#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 1297#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20 1298#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 1299#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40 1300#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 1301#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80 1302#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 1303#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100 1304#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 1305#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200 1306#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 1307#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400 1308#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 1309#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x800 1310#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 1311#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000 1312#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 1313#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000 1314#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 1315#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000 1316#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 1317#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000 1318#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 1319#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000 1320#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 1321#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000 1322#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 1323#define SDMA0_ATCL1_WR_STATUS__ALL_IDLE_MASK 0x40000 1324#define SDMA0_ATCL1_WR_STATUS__ALL_IDLE__SHIFT 0x12 1325#define SDMA0_ATCL1_WR_STATUS__REQL2_IDLE_MASK 0x80000 1326#define SDMA0_ATCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x13 1327#define SDMA0_ATCL1_WR_STATUS__REQMC_IDLE_MASK 0x100000 1328#define SDMA0_ATCL1_WR_STATUS__REQMC_IDLE__SHIFT 0x14 1329#define SDMA0_ATCL1_WR_STATUS__F32_WR_RTR_MASK 0x200000 1330#define SDMA0_ATCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 1331#define SDMA0_ATCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x3c00000 1332#define SDMA0_ATCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 1333#define SDMA0_ATCL1_WR_STATUS__MERGE_STATE_MASK 0x1c000000 1334#define SDMA0_ATCL1_WR_STATUS__MERGE_STATE__SHIFT 0x1a 1335#define SDMA0_ATCL1_WR_STATUS__RESERVED_MASK 0xe0000000 1336#define SDMA0_ATCL1_WR_STATUS__RESERVED__SHIFT 0x1d 1337#define SDMA0_ATCL1_INV0__INV_MIDDLE_MASK 0x1 1338#define SDMA0_ATCL1_INV0__INV_MIDDLE__SHIFT 0x0 1339#define SDMA0_ATCL1_INV0__RD_TIMEOUT_MASK 0x2 1340#define SDMA0_ATCL1_INV0__RD_TIMEOUT__SHIFT 0x1 1341#define SDMA0_ATCL1_INV0__WR_TIMEOUT_MASK 0x4 1342#define SDMA0_ATCL1_INV0__WR_TIMEOUT__SHIFT 0x2 1343#define SDMA0_ATCL1_INV0__RD_IN_INVADR_MASK 0x8 1344#define SDMA0_ATCL1_INV0__RD_IN_INVADR__SHIFT 0x3 1345#define SDMA0_ATCL1_INV0__WR_IN_INVADR_MASK 0x10 1346#define SDMA0_ATCL1_INV0__WR_IN_INVADR__SHIFT 0x4 1347#define SDMA0_ATCL1_INV0__RD_WT_INVADR_MASK 0x20 1348#define SDMA0_ATCL1_INV0__RD_WT_INVADR__SHIFT 0x5 1349#define SDMA0_ATCL1_INV0__WR_WT_INVADR_MASK 0x40 1350#define SDMA0_ATCL1_INV0__WR_WT_INVADR__SHIFT 0x6 1351#define SDMA0_ATCL1_INV0__RD_INV_EN_MASK 0x80 1352#define SDMA0_ATCL1_INV0__RD_INV_EN__SHIFT 0x7 1353#define SDMA0_ATCL1_INV0__WR_INV_EN_MASK 0x100 1354#define SDMA0_ATCL1_INV0__WR_INV_EN__SHIFT 0x8 1355#define SDMA0_ATCL1_INV0__RD_INV_IDLE_MASK 0x200 1356#define SDMA0_ATCL1_INV0__RD_INV_IDLE__SHIFT 0x9 1357#define SDMA0_ATCL1_INV0__WR_INV_IDLE_MASK 0x400 1358#define SDMA0_ATCL1_INV0__WR_INV_IDLE__SHIFT 0xa 1359#define SDMA0_ATCL1_INV0__INV_FLUSHTYPE_MASK 0x800 1360#define SDMA0_ATCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 1361#define SDMA0_ATCL1_INV0__INV_VMID_VEC_MASK 0xffff000 1362#define SDMA0_ATCL1_INV0__INV_VMID_VEC__SHIFT 0xc 1363#define SDMA0_ATCL1_INV0__INV_ADDR_HI_MASK 0xf0000000 1364#define SDMA0_ATCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 1365#define SDMA0_ATCL1_INV1__INV_ADDR_LO_MASK 0xffffffff 1366#define SDMA0_ATCL1_INV1__INV_ADDR_LO__SHIFT 0x0 1367#define SDMA0_ATCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xffff 1368#define SDMA0_ATCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 1369#define SDMA0_ATCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff 1370#define SDMA0_ATCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 1371#define SDMA0_ATCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0xf 1372#define SDMA0_ATCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 1373#define SDMA0_ATCL1_RD_XNACK1__XNACK_VMID_MASK 0xf0 1374#define SDMA0_ATCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 1375#define SDMA0_ATCL1_RD_XNACK1__IS_XNACK_MASK 0x100 1376#define SDMA0_ATCL1_RD_XNACK1__IS_XNACK__SHIFT 0x8 1377#define SDMA0_ATCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff 1378#define SDMA0_ATCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 1379#define SDMA0_ATCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0xf 1380#define SDMA0_ATCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 1381#define SDMA0_ATCL1_WR_XNACK1__XNACK_VMID_MASK 0xf0 1382#define SDMA0_ATCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 1383#define SDMA0_ATCL1_WR_XNACK1__IS_XNACK_MASK 0x100 1384#define SDMA0_ATCL1_WR_XNACK1__IS_XNACK__SHIFT 0x8 1385#define SDMA0_ATCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0xffff 1386#define SDMA0_ATCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 1387#define SDMA0_ATCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xffff0000 1388#define SDMA0_ATCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 1389#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0xffff 1390#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 1391#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0xff0000 1392#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 1393#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xff000000 1394#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 1395#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK 0x1 1396#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL__SHIFT 0x0 1397#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK 0x2 1398#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x1 1399#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT_MASK 0x4 1400#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x2 1401#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8 1402#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3 1403#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x1 1404#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 1405#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x2 1406#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 1407#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x4 1408#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 1409#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x8 1410#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 1411#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x10 1412#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x4 1413#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x20 1414#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5 1415#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40 1416#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6 1417#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80 1418#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7 1419#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x100 1420#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 1421#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x200 1422#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 1423#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x400 1424#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 1425#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x800 1426#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 1427#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x1000 1428#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 1429#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x2000 1430#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 1431#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x4000 1432#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 1433#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x8000 1434#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 1435#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x10000 1436#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 1437#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x20000 1438#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 1439#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x40000 1440#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 1441#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x80000 1442#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 1443#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR_MASK 0x80 1444#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR__SHIFT 0x7 1445#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL_MASK 0x100 1446#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL__SHIFT 0x8 1447#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x200 1448#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 1449#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x400 1450#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 1451#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1_MASK 0x800 1452#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1__SHIFT 0xb 1453#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x1000 1454#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 1455#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x2000 1456#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 1457#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x4000 1458#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 1459#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x8000 1460#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 1461#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x10000 1462#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 1463#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x20000 1464#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 1465#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000 1466#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12 1467#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x1 1468#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 1469#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x2 1470#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 1471#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x4 1472#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 1473#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x8 1474#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 1475#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x10 1476#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 1477#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x20 1478#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 1479#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x40 1480#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 1481#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x80 1482#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 1483#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x100 1484#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 1485#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x200 1486#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 1487#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xfffffc00 1488#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 1489#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x1 1490#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 1491#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x2 1492#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 1493#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x4 1494#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2 1495#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x8 1496#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x3 1497#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10 1498#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x4 1499#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20 1500#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x5 1501#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG_MASK 0x40 1502#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG__SHIFT 0x6 1503#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH_MASK 0x80 1504#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH__SHIFT 0x7 1505#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200 1506#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9 1507#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH_MASK 0x400 1508#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH__SHIFT 0xa 1509#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH_MASK 0x800 1510#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH__SHIFT 0xb 1511#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM_MASK 0x1000 1512#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM__SHIFT 0xc 1513#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG_MASK 0x2000 1514#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG__SHIFT 0xd 1515#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG_MASK 0x4000 1516#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG__SHIFT 0xe 1517#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL_MASK 0x8000 1518#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL__SHIFT 0xf 1519#define SDMA0_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000 1520#define SDMA0_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10 1521#define SDMA0_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000 1522#define SDMA0_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11 1523#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL_MASK 0x40000 1524#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL__SHIFT 0x12 1525#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE_MASK 0x80000 1526#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE__SHIFT 0x13 1527#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM_MASK 0x100000 1528#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM__SHIFT 0x14 1529#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM_MASK 0x200000 1530#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM__SHIFT 0x15 1531#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING_MASK 0x400000 1532#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING__SHIFT 0x16 1533#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG_MASK 0x800000 1534#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG__SHIFT 0x17 1535#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE_MASK 0x1000000 1536#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE__SHIFT 0x18 1537#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ_MASK 0x2000000 1538#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ__SHIFT 0x19 1539#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG_MASK 0x4000000 1540#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG__SHIFT 0x1a 1541#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD_MASK 0x8000000 1542#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD__SHIFT 0x1b 1543#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID_MASK 0x10000000 1544#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID__SHIFT 0x1c 1545#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION_MASK 0x20000000 1546#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION__SHIFT 0x1d 1547#define SDMA0_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000 1548#define SDMA0_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e 1549#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK 0x1 1550#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL__SHIFT 0x0 1551#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK 0x2 1552#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT 0x1 1553#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI_MASK 0x4 1554#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT 0x2 1555#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x8 1556#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x3 1557#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID_MASK 0x10 1558#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID__SHIFT 0x4 1559#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL_MASK 0x20 1560#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL__SHIFT 0x5 1561#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ_MASK 0x40 1562#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ__SHIFT 0x6 1563#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE_MASK 0x80 1564#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE__SHIFT 0x7 1565#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x100 1566#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x8 1567#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x200 1568#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x9 1569#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x400 1570#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0xa 1571#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_CNTL_MASK 0x800 1572#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_CNTL__SHIFT 0xb 1573#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_WATERMK_MASK 0x1000 1574#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_WATERMK__SHIFT 0xc 1575#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_TIMEOUT_MASK 0x2000 1576#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_TIMEOUT__SHIFT 0xd 1577#define SDMA0_PUB_REG_TYPE1__RESERVED_MASK 0xffffc000 1578#define SDMA0_PUB_REG_TYPE1__RESERVED__SHIFT 0xe 1579#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 1580#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1581#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e 1582#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1583#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 1584#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1585#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 1586#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1587#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 1588#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1589#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 1590#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1591#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 1592#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1593#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 1594#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1595#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff 1596#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1597#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff 1598#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1599#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc 1600#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2 1601#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc 1602#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2 1603#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 1604#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1605#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 1606#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1607#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 1608#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1609#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 1610#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1611#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 1612#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1613#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 1614#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1615#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 1616#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1617#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 1618#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1619#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 1620#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1621#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 1622#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1623#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 1624#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1625#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 1626#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1627#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 1628#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1629#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc 1630#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1631#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc 1632#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1633#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 1634#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1635#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff 1636#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1637#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff 1638#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1639#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 1640#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1641#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 1642#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1643#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 1644#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1645#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 1646#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1647#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 1648#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1649#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 1650#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1651#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 1652#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1653#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 1654#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1655#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 1656#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1657#define SDMA0_GFX_DOORBELL__OFFSET_MASK 0x1fffff 1658#define SDMA0_GFX_DOORBELL__OFFSET__SHIFT 0x0 1659#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000 1660#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1661#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000 1662#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1663#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 1664#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1665#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 1666#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 1667#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 1668#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 1669#define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2 1670#define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1 1671#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 1672#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 1673#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 1674#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 1675#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 1676#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 1677#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff 1678#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0 1679#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 1680#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 1681#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1 1682#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1683#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc 1684#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1685#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff 1686#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1687#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 1688#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1689#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 1690#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1691#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff 1692#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1693#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff 1694#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1695#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 1696#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1697#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff 1698#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1699#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff 1700#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1701#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff 1702#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1703#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff 1704#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1705#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff 1706#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1707#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff 1708#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1709#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff 1710#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1711#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xffffffff 1712#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1713#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xffffffff 1714#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1715#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xffffffff 1716#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1717#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1 1718#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1719#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2 1720#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1721#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 1722#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1723#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 1724#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1725#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 1726#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1727#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e 1728#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1729#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 1730#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1731#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 1732#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1733#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 1734#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1735#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 1736#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1737#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 1738#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1739#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 1740#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1741#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff 1742#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1743#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff 1744#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1745#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc 1746#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 1747#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc 1748#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 1749#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 1750#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1751#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 1752#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1753#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 1754#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1755#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 1756#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1757#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 1758#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1759#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 1760#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1761#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 1762#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1763#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 1764#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1765#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 1766#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1767#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 1768#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1769#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 1770#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1771#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 1772#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1773#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 1774#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1775#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc 1776#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1777#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc 1778#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1779#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 1780#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1781#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff 1782#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1783#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff 1784#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1785#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 1786#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1787#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 1788#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1789#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 1790#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1791#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 1792#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1793#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 1794#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1795#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 1796#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1797#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 1798#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1799#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 1800#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1801#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 1802#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1803#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff 1804#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0 1805#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000 1806#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1807#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 1808#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1809#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 1810#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 1811#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2 1812#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1 1813#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 1814#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 1815#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 1816#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 1817#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 1818#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 1819#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff 1820#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0 1821#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 1822#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 1823#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 1824#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1825#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc 1826#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1827#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff 1828#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1829#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 1830#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1831#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 1832#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1833#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff 1834#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1835#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff 1836#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1837#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 1838#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1839#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff 1840#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1841#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff 1842#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1843#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff 1844#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1845#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff 1846#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1847#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff 1848#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1849#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff 1850#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1851#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff 1852#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1853#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xffffffff 1854#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1855#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xffffffff 1856#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1857#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xffffffff 1858#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1859#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1 1860#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1861#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2 1862#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1863#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 1864#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1865#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 1866#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1867#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 1868#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1869#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e 1870#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1871#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 1872#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1873#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 1874#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1875#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 1876#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1877#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 1878#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1879#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 1880#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1881#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 1882#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1883#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff 1884#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1885#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff 1886#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1887#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc 1888#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 1889#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc 1890#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 1891#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 1892#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1893#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 1894#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1895#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 1896#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1897#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 1898#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1899#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 1900#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1901#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 1902#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1903#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 1904#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1905#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 1906#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1907#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 1908#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1909#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 1910#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1911#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 1912#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1913#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 1914#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1915#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 1916#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1917#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc 1918#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1919#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc 1920#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1921#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 1922#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1923#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff 1924#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1925#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff 1926#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1927#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 1928#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1929#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 1930#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1931#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 1932#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1933#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 1934#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1935#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 1936#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1937#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 1938#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1939#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 1940#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1941#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 1942#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1943#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 1944#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1945#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff 1946#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0 1947#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000 1948#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1949#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 1950#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1951#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 1952#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 1953#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2 1954#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1 1955#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 1956#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 1957#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 1958#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 1959#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 1960#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 1961#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff 1962#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0 1963#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 1964#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 1965#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 1966#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1967#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc 1968#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1969#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff 1970#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1971#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 1972#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1973#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 1974#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1975#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff 1976#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1977#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff 1978#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1979#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 1980#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1981#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff 1982#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1983#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff 1984#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1985#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff 1986#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1987#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff 1988#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1989#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff 1990#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1991#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff 1992#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1993#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff 1994#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1995#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xffffffff 1996#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1997#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xffffffff 1998#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1999#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xffffffff 2000#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 2001#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1 2002#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2003#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2 2004#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2005#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 2006#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2007#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 2008#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2009#define SDMA1_UCODE_ADDR__VALUE_MASK 0x1fff 2010#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 2011#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff 2012#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 2013#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 2014#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 2015#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200 2016#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 2017#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400 2018#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 2019#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800 2020#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 2021#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000 2022#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 2023#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf 2024#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 2025#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 2026#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2027#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 2028#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 2029#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 2030#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 2031#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 2032#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 2033#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 2034#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 2035#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 2036#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 2037#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 2038#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 2039#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 2040#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 2041#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 2042#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 2043#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1 2044#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 2045#define SDMA1_CNTL__ATC_L1_ENABLE_MASK 0x2 2046#define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT 0x1 2047#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 2048#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 2049#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8 2050#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 2051#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 2052#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 2053#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20 2054#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 2055#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 2056#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb 2057#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000 2058#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 2059#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 2060#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 2061#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 2062#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 2063#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 2064#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 2065#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 2066#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 2067#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 2068#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 2069#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 2070#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 2071#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 2072#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 2073#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 2074#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 2075#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 2076#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 2077#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 2078#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 2079#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 2080#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 2081#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 2082#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 2083#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 2084#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 2085#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 2086#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 2087#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 2088#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 2089#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7 2090#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0 2091#define SDMA1_HASH__BANK_BITS_MASK 0x70 2092#define SDMA1_HASH__BANK_BITS__SHIFT 0x4 2093#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700 2094#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 2095#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000 2096#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc 2097#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff 2098#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 2099#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc 2100#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 2101#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc 2102#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 2103#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff 2104#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 2105#define SDMA1_STATUS_REG__IDLE_MASK 0x1 2106#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 2107#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2 2108#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 2109#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4 2110#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 2111#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8 2112#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 2113#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10 2114#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 2115#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20 2116#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 2117#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40 2118#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 2119#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80 2120#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 2121#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100 2122#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 2123#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200 2124#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 2125#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400 2126#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 2127#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 2128#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 2129#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000 2130#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc 2131#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000 2132#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 2133#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000 2134#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe 2135#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 2136#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 2137#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 2138#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 2139#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 2140#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 2141#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 2142#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 2143#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000 2144#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 2145#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 2146#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 2147#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 2148#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 2149#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 2150#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 2151#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 2152#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 2153#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000 2154#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a 2155#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 2156#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 2157#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 2158#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 2159#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000 2160#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e 2161#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 2162#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 2163#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 2164#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 2165#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 2166#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 2167#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 2168#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 2169#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 2170#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 2171#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 2172#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 2173#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20 2174#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 2175#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40 2176#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 2177#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 2178#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 2179#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 2180#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 2181#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 2182#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 2183#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 2184#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 2185#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000 2186#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 2187#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000 2188#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 2189#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x3 2190#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 2191#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 2192#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 2193#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 2194#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 2195#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc 2196#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 2197#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x400 2198#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 2199#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x800 2200#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 2201#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xff000 2202#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 2203#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 2204#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 2205#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 2206#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 2207#define SDMA1_F32_CNTL__HALT_MASK 0x1 2208#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 2209#define SDMA1_F32_CNTL__STEP_MASK 0x2 2210#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 2211#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc 2212#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 2213#define SDMA1_FREEZE__FREEZE_MASK 0x10 2214#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 2215#define SDMA1_FREEZE__FROZEN_MASK 0x20 2216#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 2217#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40 2218#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 2219#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf 2220#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 2221#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00 2222#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 2223#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000 2224#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 2225#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf 2226#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 2227#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00 2228#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 2229#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000 2230#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 2231#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2 2232#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 2233#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 2234#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 2235#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff 2236#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 2237#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 2238#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 2239#define SDMA1_ID__DEVICE_ID_MASK 0xff 2240#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 2241#define SDMA1_VERSION__VALUE_MASK 0xffff 2242#define SDMA1_VERSION__VALUE__SHIFT 0x0 2243#define SDMA1_VM_CNTL__CMD_MASK 0xf 2244#define SDMA1_VM_CNTL__CMD__SHIFT 0x0 2245#define SDMA1_VM_CTX_LO__ADDR_MASK 0xfffffffc 2246#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 2247#define SDMA1_VM_CTX_HI__ADDR_MASK 0xffffffff 2248#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 2249#define SDMA1_STATUS2_REG__ID_MASK 0x3 2250#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 2251#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc 2252#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 2253#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000 2254#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 2255#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0xf 2256#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 2257#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000 2258#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 2259#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x1 2260#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 2261#define SDMA1_VM_CTX_CNTL__VMID_MASK 0xf0 2262#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 2263#define SDMA1_VIRT_RESET_REQ__VF_MASK 0xffff 2264#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 2265#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000 2266#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f 2267#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x1 2268#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 2269#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff 2270#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 2271#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000 2272#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 2273#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff 2274#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 2275#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff 2276#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 2277#define SDMA1_ATCL1_CNTL__REDO_ENABLE_MASK 0x1 2278#define SDMA1_ATCL1_CNTL__REDO_ENABLE__SHIFT 0x0 2279#define SDMA1_ATCL1_CNTL__REDO_DELAY_MASK 0x7fe 2280#define SDMA1_ATCL1_CNTL__REDO_DELAY__SHIFT 0x1 2281#define SDMA1_ATCL1_CNTL__REDO_WATERMK_MASK 0x3800 2282#define SDMA1_ATCL1_CNTL__REDO_WATERMK__SHIFT 0xb 2283#define SDMA1_ATCL1_CNTL__INVACK_DELAY_MASK 0xffc000 2284#define SDMA1_ATCL1_CNTL__INVACK_DELAY__SHIFT 0xe 2285#define SDMA1_ATCL1_CNTL__REQL2_CREDIT_MASK 0xf000000 2286#define SDMA1_ATCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 2287#define SDMA1_ATCL1_CNTL__VADDR_WATERMK_MASK 0x70000000 2288#define SDMA1_ATCL1_CNTL__VADDR_WATERMK__SHIFT 0x1c 2289#define SDMA1_ATCL1_WATERMK__REQMC_WATERMK_MASK 0x3ff 2290#define SDMA1_ATCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 2291#define SDMA1_ATCL1_WATERMK__REQPG_WATERMK_MASK 0x3fc00 2292#define SDMA1_ATCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 2293#define SDMA1_ATCL1_WATERMK__INVREQ_WATERMK_MASK 0xfc0000 2294#define SDMA1_ATCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 2295#define SDMA1_ATCL1_WATERMK__XNACK_WATERMK_MASK 0x7f000000 2296#define SDMA1_ATCL1_WATERMK__XNACK_WATERMK__SHIFT 0x18 2297#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1 2298#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 2299#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2 2300#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 2301#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4 2302#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 2303#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8 2304#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 2305#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10 2306#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 2307#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20 2308#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 2309#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40 2310#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 2311#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80 2312#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 2313#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100 2314#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 2315#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200 2316#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 2317#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400 2318#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 2319#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x800 2320#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 2321#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000 2322#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 2323#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000 2324#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 2325#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000 2326#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 2327#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000 2328#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 2329#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000 2330#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 2331#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000 2332#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 2333#define SDMA1_ATCL1_RD_STATUS__ALL_IDLE_MASK 0x40000 2334#define SDMA1_ATCL1_RD_STATUS__ALL_IDLE__SHIFT 0x12 2335#define SDMA1_ATCL1_RD_STATUS__REQL2_IDLE_MASK 0x80000 2336#define SDMA1_ATCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x13 2337#define SDMA1_ATCL1_RD_STATUS__REQMC_IDLE_MASK 0x100000 2338#define SDMA1_ATCL1_RD_STATUS__REQMC_IDLE__SHIFT 0x14 2339#define SDMA1_ATCL1_RD_STATUS__CE_L1_STALL_MASK 0x200000 2340#define SDMA1_ATCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 2341#define SDMA1_ATCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x3c00000 2342#define SDMA1_ATCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 2343#define SDMA1_ATCL1_RD_STATUS__MERGE_STATE_MASK 0x1c000000 2344#define SDMA1_ATCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 2345#define SDMA1_ATCL1_RD_STATUS__RESERVED_MASK 0xe0000000 2346#define SDMA1_ATCL1_RD_STATUS__RESERVED__SHIFT 0x1d 2347#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1 2348#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 2349#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2 2350#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 2351#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4 2352#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 2353#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8 2354#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 2355#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10 2356#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 2357#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20 2358#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 2359#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40 2360#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 2361#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80 2362#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 2363#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100 2364#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 2365#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200 2366#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 2367#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400 2368#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 2369#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x800 2370#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 2371#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000 2372#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 2373#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000 2374#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 2375#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000 2376#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 2377#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000 2378#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 2379#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000 2380#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 2381#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000 2382#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 2383#define SDMA1_ATCL1_WR_STATUS__ALL_IDLE_MASK 0x40000 2384#define SDMA1_ATCL1_WR_STATUS__ALL_IDLE__SHIFT 0x12 2385#define SDMA1_ATCL1_WR_STATUS__REQL2_IDLE_MASK 0x80000 2386#define SDMA1_ATCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x13 2387#define SDMA1_ATCL1_WR_STATUS__REQMC_IDLE_MASK 0x100000 2388#define SDMA1_ATCL1_WR_STATUS__REQMC_IDLE__SHIFT 0x14 2389#define SDMA1_ATCL1_WR_STATUS__F32_WR_RTR_MASK 0x200000 2390#define SDMA1_ATCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 2391#define SDMA1_ATCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x3c00000 2392#define SDMA1_ATCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 2393#define SDMA1_ATCL1_WR_STATUS__MERGE_STATE_MASK 0x1c000000 2394#define SDMA1_ATCL1_WR_STATUS__MERGE_STATE__SHIFT 0x1a 2395#define SDMA1_ATCL1_WR_STATUS__RESERVED_MASK 0xe0000000 2396#define SDMA1_ATCL1_WR_STATUS__RESERVED__SHIFT 0x1d 2397#define SDMA1_ATCL1_INV0__INV_MIDDLE_MASK 0x1 2398#define SDMA1_ATCL1_INV0__INV_MIDDLE__SHIFT 0x0 2399#define SDMA1_ATCL1_INV0__RD_TIMEOUT_MASK 0x2 2400#define SDMA1_ATCL1_INV0__RD_TIMEOUT__SHIFT 0x1 2401#define SDMA1_ATCL1_INV0__WR_TIMEOUT_MASK 0x4 2402#define SDMA1_ATCL1_INV0__WR_TIMEOUT__SHIFT 0x2 2403#define SDMA1_ATCL1_INV0__RD_IN_INVADR_MASK 0x8 2404#define SDMA1_ATCL1_INV0__RD_IN_INVADR__SHIFT 0x3 2405#define SDMA1_ATCL1_INV0__WR_IN_INVADR_MASK 0x10 2406#define SDMA1_ATCL1_INV0__WR_IN_INVADR__SHIFT 0x4 2407#define SDMA1_ATCL1_INV0__RD_WT_INVADR_MASK 0x20 2408#define SDMA1_ATCL1_INV0__RD_WT_INVADR__SHIFT 0x5 2409#define SDMA1_ATCL1_INV0__WR_WT_INVADR_MASK 0x40 2410#define SDMA1_ATCL1_INV0__WR_WT_INVADR__SHIFT 0x6 2411#define SDMA1_ATCL1_INV0__RD_INV_EN_MASK 0x80 2412#define SDMA1_ATCL1_INV0__RD_INV_EN__SHIFT 0x7 2413#define SDMA1_ATCL1_INV0__WR_INV_EN_MASK 0x100 2414#define SDMA1_ATCL1_INV0__WR_INV_EN__SHIFT 0x8 2415#define SDMA1_ATCL1_INV0__RD_INV_IDLE_MASK 0x200 2416#define SDMA1_ATCL1_INV0__RD_INV_IDLE__SHIFT 0x9 2417#define SDMA1_ATCL1_INV0__WR_INV_IDLE_MASK 0x400 2418#define SDMA1_ATCL1_INV0__WR_INV_IDLE__SHIFT 0xa 2419#define SDMA1_ATCL1_INV0__INV_FLUSHTYPE_MASK 0x800 2420#define SDMA1_ATCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 2421#define SDMA1_ATCL1_INV0__INV_VMID_VEC_MASK 0xffff000 2422#define SDMA1_ATCL1_INV0__INV_VMID_VEC__SHIFT 0xc 2423#define SDMA1_ATCL1_INV0__INV_ADDR_HI_MASK 0xf0000000 2424#define SDMA1_ATCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 2425#define SDMA1_ATCL1_INV1__INV_ADDR_LO_MASK 0xffffffff 2426#define SDMA1_ATCL1_INV1__INV_ADDR_LO__SHIFT 0x0 2427#define SDMA1_ATCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xffff 2428#define SDMA1_ATCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 2429#define SDMA1_ATCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff 2430#define SDMA1_ATCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 2431#define SDMA1_ATCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0xf 2432#define SDMA1_ATCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 2433#define SDMA1_ATCL1_RD_XNACK1__XNACK_VMID_MASK 0xf0 2434#define SDMA1_ATCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 2435#define SDMA1_ATCL1_RD_XNACK1__IS_XNACK_MASK 0x100 2436#define SDMA1_ATCL1_RD_XNACK1__IS_XNACK__SHIFT 0x8 2437#define SDMA1_ATCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff 2438#define SDMA1_ATCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 2439#define SDMA1_ATCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0xf 2440#define SDMA1_ATCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 2441#define SDMA1_ATCL1_WR_XNACK1__XNACK_VMID_MASK 0xf0 2442#define SDMA1_ATCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 2443#define SDMA1_ATCL1_WR_XNACK1__IS_XNACK_MASK 0x100 2444#define SDMA1_ATCL1_WR_XNACK1__IS_XNACK__SHIFT 0x8 2445#define SDMA1_ATCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0xffff 2446#define SDMA1_ATCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 2447#define SDMA1_ATCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xffff0000 2448#define SDMA1_ATCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 2449#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0xffff 2450#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 2451#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0xff0000 2452#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 2453#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xff000000 2454#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 2455#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK 0x1 2456#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL__SHIFT 0x0 2457#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK 0x2 2458#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x1 2459#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT_MASK 0x4 2460#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x2 2461#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8 2462#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3 2463#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x1 2464#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 2465#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x2 2466#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 2467#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x4 2468#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 2469#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x8 2470#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 2471#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x10 2472#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x4 2473#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x20 2474#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5 2475#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40 2476#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6 2477#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80 2478#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7 2479#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x100 2480#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 2481#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x200 2482#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 2483#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x400 2484#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa 2485#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x800 2486#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb 2487#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x1000 2488#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc 2489#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x2000 2490#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd 2491#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x4000 2492#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe 2493#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x8000 2494#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf 2495#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x10000 2496#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 2497#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x20000 2498#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 2499#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x40000 2500#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 2501#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x80000 2502#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 2503#define SDMA1_CONTEXT_REG_TYPE0__RESERVED_MASK 0xfff00000 2504#define SDMA1_CONTEXT_REG_TYPE0__RESERVED__SHIFT 0x14 2505#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0_MASK 0x7f 2506#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0__SHIFT 0x0 2507#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR_MASK 0x80 2508#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR__SHIFT 0x7 2509#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL_MASK 0x100 2510#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL__SHIFT 0x8 2511#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x200 2512#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 2513#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x400 2514#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa 2515#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x800 2516#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xb 2517#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x1000 2518#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc 2519#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x2000 2520#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd 2521#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3_MASK 0x4000 2522#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3__SHIFT 0xe 2523#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x8000 2524#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf 2525#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x10000 2526#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 2527#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x20000 2528#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 2529#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000 2530#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12 2531#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x1 2532#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 2533#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x2 2534#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 2535#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x4 2536#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 2537#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x8 2538#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 2539#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x10 2540#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 2541#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x20 2542#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 2543#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x40 2544#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 2545#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x80 2546#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 2547#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x100 2548#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 2549#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x200 2550#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 2551#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xfffffc00 2552#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 2553#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x1 2554#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 2555#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x2 2556#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 2557#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x4 2558#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x2 2559#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x8 2560#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x3 2561#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10 2562#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x4 2563#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20 2564#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x5 2565#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG_MASK 0x40 2566#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG__SHIFT 0x6 2567#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH_MASK 0x80 2568#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH__SHIFT 0x7 2569#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200 2570#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9 2571#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH_MASK 0x400 2572#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH__SHIFT 0xa 2573#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH_MASK 0x800 2574#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH__SHIFT 0xb 2575#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM_MASK 0x1000 2576#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM__SHIFT 0xc 2577#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG_MASK 0x2000 2578#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG__SHIFT 0xd 2579#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG_MASK 0x4000 2580#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG__SHIFT 0xe 2581#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL_MASK 0x8000 2582#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL__SHIFT 0xf 2583#define SDMA1_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000 2584#define SDMA1_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10 2585#define SDMA1_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000 2586#define SDMA1_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11 2587#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL_MASK 0x40000 2588#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL__SHIFT 0x12 2589#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE_MASK 0x80000 2590#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE__SHIFT 0x13 2591#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM_MASK 0x100000 2592#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM__SHIFT 0x14 2593#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM_MASK 0x200000 2594#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM__SHIFT 0x15 2595#define SDMA1_PUB_REG_TYPE0__VOID_REG0_MASK 0x3c00000 2596#define SDMA1_PUB_REG_TYPE0__VOID_REG0__SHIFT 0x16 2597#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG_MASK 0x4000000 2598#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG__SHIFT 0x1a 2599#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD_MASK 0x8000000 2600#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD__SHIFT 0x1b 2601#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID_MASK 0x10000000 2602#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID__SHIFT 0x1c 2603#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION_MASK 0x20000000 2604#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION__SHIFT 0x1d 2605#define SDMA1_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000 2606#define SDMA1_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e 2607#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK 0x1 2608#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL__SHIFT 0x0 2609#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK 0x2 2610#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT 0x1 2611#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI_MASK 0x4 2612#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT 0x2 2613#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x8 2614#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x3 2615#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID_MASK 0x10 2616#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID__SHIFT 0x4 2617#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL_MASK 0x20 2618#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL__SHIFT 0x5 2619#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ_MASK 0x40 2620#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ__SHIFT 0x6 2621#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE_MASK 0x80 2622#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE__SHIFT 0x7 2623#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x100 2624#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x8 2625#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x200 2626#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x9 2627#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x400 2628#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0xa 2629#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_CNTL_MASK 0x800 2630#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_CNTL__SHIFT 0xb 2631#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_WATERMK_MASK 0x1000 2632#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_WATERMK__SHIFT 0xc 2633#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_TIMEOUT_MASK 0x2000 2634#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_TIMEOUT__SHIFT 0xd 2635#define SDMA1_PUB_REG_TYPE1__RESERVED_MASK 0xffffc000 2636#define SDMA1_PUB_REG_TYPE1__RESERVED__SHIFT 0xe 2637#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 2638#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 2639#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e 2640#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 2641#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 2642#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2643#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 2644#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2645#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 2646#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2647#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 2648#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2649#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 2650#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 2651#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 2652#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 2653#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff 2654#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 2655#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff 2656#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 2657#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc 2658#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2 2659#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc 2660#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2 2661#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 2662#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2663#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 2664#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2665#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 2666#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2667#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 2668#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2669#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 2670#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2671#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 2672#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2673#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 2674#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2675#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 2676#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2677#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 2678#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2679#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 2680#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 2681#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 2682#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2683#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 2684#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2685#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 2686#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 2687#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc 2688#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 2689#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc 2690#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 2691#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 2692#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 2693#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff 2694#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 2695#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff 2696#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 2697#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 2698#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2699#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 2700#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2701#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 2702#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 2703#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 2704#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2705#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 2706#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2707#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 2708#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2709#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 2710#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2711#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 2712#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2713#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 2714#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2715#define SDMA1_GFX_DOORBELL__OFFSET_MASK 0x1fffff 2716#define SDMA1_GFX_DOORBELL__OFFSET__SHIFT 0x0 2717#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000 2718#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c 2719#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000 2720#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 2721#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 2722#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 2723#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 2724#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 2725#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 2726#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 2727#define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2 2728#define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1 2729#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 2730#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 2731#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 2732#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 2733#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 2734#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 2735#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff 2736#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0 2737#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 2738#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 2739#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1 2740#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2741#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc 2742#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 2743#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff 2744#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2745#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 2746#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2747#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 2748#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 2749#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff 2750#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 2751#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff 2752#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2753#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 2754#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 2755#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff 2756#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 2757#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff 2758#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 2759#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff 2760#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 2761#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff 2762#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 2763#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff 2764#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 2765#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff 2766#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 2767#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff 2768#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 2769#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xffffffff 2770#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 2771#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xffffffff 2772#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 2773#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xffffffff 2774#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 2775#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1 2776#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2777#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2 2778#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2779#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 2780#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2781#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 2782#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2783#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 2784#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 2785#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e 2786#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 2787#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 2788#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2789#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 2790#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2791#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 2792#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2793#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 2794#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2795#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 2796#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 2797#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 2798#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 2799#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff 2800#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 2801#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff 2802#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 2803#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc 2804#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 2805#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc 2806#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 2807#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 2808#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2809#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 2810#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2811#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 2812#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2813#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 2814#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2815#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 2816#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2817#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 2818#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2819#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 2820#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2821#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 2822#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2823#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 2824#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2825#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 2826#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 2827#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 2828#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2829#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 2830#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2831#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 2832#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 2833#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc 2834#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 2835#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc 2836#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 2837#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 2838#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 2839#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff 2840#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 2841#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff 2842#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 2843#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 2844#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2845#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 2846#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2847#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 2848#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 2849#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 2850#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2851#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 2852#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2853#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 2854#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2855#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 2856#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2857#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 2858#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2859#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 2860#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2861#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff 2862#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0 2863#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000 2864#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 2865#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 2866#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 2867#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 2868#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 2869#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2 2870#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1 2871#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 2872#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 2873#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 2874#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 2875#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 2876#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 2877#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff 2878#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0 2879#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 2880#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 2881#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 2882#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2883#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc 2884#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 2885#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff 2886#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2887#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 2888#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2889#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 2890#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 2891#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff 2892#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 2893#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff 2894#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2895#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 2896#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 2897#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff 2898#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 2899#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff 2900#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 2901#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff 2902#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 2903#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff 2904#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 2905#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff 2906#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 2907#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff 2908#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 2909#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff 2910#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 2911#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xffffffff 2912#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 2913#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xffffffff 2914#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 2915#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xffffffff 2916#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 2917#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1 2918#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2919#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2 2920#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2921#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 2922#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2923#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 2924#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2925#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 2926#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 2927#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e 2928#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 2929#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 2930#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2931#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 2932#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2933#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 2934#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2935#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 2936#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2937#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 2938#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 2939#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 2940#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 2941#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff 2942#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 2943#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff 2944#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 2945#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc 2946#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 2947#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc 2948#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 2949#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 2950#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2951#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 2952#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2953#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 2954#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2955#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 2956#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2957#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 2958#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2959#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 2960#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2961#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 2962#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2963#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 2964#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2965#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 2966#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2967#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 2968#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 2969#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 2970#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2971#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 2972#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2973#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 2974#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 2975#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc 2976#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 2977#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc 2978#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 2979#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 2980#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 2981#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff 2982#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 2983#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff 2984#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 2985#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 2986#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2987#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 2988#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2989#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 2990#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 2991#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 2992#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2993#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 2994#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2995#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 2996#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2997#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 2998#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2999#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 3000#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 3001#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 3002#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 3003#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff 3004#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0 3005#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000 3006#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 3007#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 3008#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 3009#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 3010#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 3011#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2 3012#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1 3013#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 3014#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 3015#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 3016#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 3017#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 3018#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 3019#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff 3020#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0 3021#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 3022#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 3023#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 3024#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 3025#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc 3026#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 3027#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff 3028#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 3029#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 3030#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 3031#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 3032#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 3033#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff 3034#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 3035#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff 3036#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 3037#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 3038#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 3039#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff 3040#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 3041#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff 3042#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 3043#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff 3044#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 3045#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff 3046#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 3047#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff 3048#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 3049#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff 3050#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 3051#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff 3052#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 3053#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xffffffff 3054#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 3055#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xffffffff 3056#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 3057#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xffffffff 3058#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 3059#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1 3060#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 3061#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2 3062#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 3063#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 3064#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 3065#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 3066#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 3067#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7 3068#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0 3069#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8 3070#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3 3071#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600 3072#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 3073#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800 3074#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb 3075#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000 3076#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 3077#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000 3078#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 3079#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000 3080#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16 3081#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000 3082#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17 3083#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000 3084#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18 3085#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000 3086#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d 3087#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000 3088#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e 3089#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000 3090#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f 3091#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff 3092#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0 3093#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1 3094#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0 3095#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e 3096#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1 3097#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60 3098#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5 3099#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380 3100#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7 3101#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00 3102#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa 3103#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000 3104#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd 3105#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000 3106#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf 3107#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000 3108#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10 3109#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000 3110#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11 3111#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000 3112#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14 3113#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000 3114#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16 3115#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000 3116#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18 3117#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000 3118#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a 3119#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000 3120#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c 3121#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000 3122#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f 3123#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff 3124#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0 3125#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800 3126#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb 3127#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1 3128#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 3129#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2 3130#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 3131#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1 3132#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 3133#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2 3134#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 3135#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff 3136#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 3137#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 3138#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0 3139#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f 3140#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 3141#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe 3142#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1 3143#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30 3144#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4 3145#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0 3146#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6 3147#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700 3148#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8 3149#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800 3150#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb 3151#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000 3152#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe 3153#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7 3154#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0 3155#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18 3156#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3 3157#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff 3158#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 3159#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00 3160#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 3161#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7 3162#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 3163#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 3164#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 3165#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 3166#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 3167#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 3168#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 3169#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 3170#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 3171#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 3172#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 3173#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 3174#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 3175#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 3176#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 3177#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 3178#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 3179#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1 3180#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 3181#define HDP_MISC_CNTL__VM_ID_MASK 0x1e 3182#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1 3183#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20 3184#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 3185#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40 3186#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 3187#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780 3188#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7 3189#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800 3190#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb 3191#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000 3192#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc 3193#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000 3194#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 3195#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000 3196#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13 3197#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000 3198#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14 3199#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000 3200#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 3201#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE_MASK 0x400000 3202#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE__SHIFT 0x16 3203#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE_MASK 0x800000 3204#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE__SHIFT 0x17 3205#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1 3206#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 3207#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e 3208#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1 3209#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80 3210#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 3211#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7 3212#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0 3213#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38 3214#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3 3215#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0 3216#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6 3217#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00 3218#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9 3219#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000 3220#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b 3221#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1 3222#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 3223#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2 3224#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 3225#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c 3226#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 3227#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40 3228#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 3229#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80 3230#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 3231#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00 3232#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 3233#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000 3234#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe 3235#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000 3236#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf 3237#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x10000 3238#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 3239#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x1e0000 3240#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 3241#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff 3242#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 3243#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1 3244#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 3245#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2 3246#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 3247#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4 3248#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 3249#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8 3250#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 3251#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff 3252#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 3253#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff 3254#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 3255#define HDP_VF_ENABLE__VF_EN_MASK 0x1 3256#define HDP_VF_ENABLE__VF_EN__SHIFT 0x0 3257#define HDP_VF_ENABLE__VF_NUM_MASK 0xffff0000 3258#define HDP_VF_ENABLE__VF_NUM__SHIFT 0x10 3259#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff 3260#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 3261#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf 3262#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 3263#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0 3264#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 3265#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700 3266#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 3267#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800 3268#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb 3269#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000 3270#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 3271#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000 3272#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11 3273#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000 3274#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 3275#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000 3276#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 3277#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000 3278#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 3279#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff 3280#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 3281#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000 3282#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 3283#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000 3284#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 3285#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff 3286#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 3287#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff 3288#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 3289#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff 3290#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 3291#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff 3292#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 3293#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff 3294#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 3295#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff 3296#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 3297#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff 3298#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 3299#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff 3300#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 3301#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff 3302#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 3303#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff 3304#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 3305#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff 3306#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 3307#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff 3308#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 3309#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff 3310#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 3311#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff 3312#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 3313#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff 3314#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 3315#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff 3316#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 3317#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff 3318#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 3319#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff 3320#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 3321#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff 3322#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 3323#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff 3324#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 3325#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff 3326#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 3327#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff 3328#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 3329#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff 3330#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 3331#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff 3332#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 3333#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff 3334#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 3335#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff 3336#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 3337#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff 3338#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 3339#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff 3340#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 3341#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff 3342#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 3343#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff 3344#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 3345#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff 3346#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 3347#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff 3348#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 3349#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff 3350#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 3351#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf 3352#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 3353#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30 3354#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 3355#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff 3356#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 3357#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1 3358#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 3359#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe 3360#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1 3361#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000 3362#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15 3363#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1 3364#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 3365#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe 3366#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1 3367#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000 3368#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15 3369#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1 3370#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 3371#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe 3372#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1 3373#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000 3374#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15 3375#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1 3376#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 3377#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe 3378#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1 3379#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000 3380#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15 3381#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1 3382#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 3383#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe 3384#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1 3385#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000 3386#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15 3387#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1 3388#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 3389#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe 3390#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1 3391#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000 3392#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15 3393#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1 3394#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 3395#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe 3396#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1 3397#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000 3398#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15 3399#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1 3400#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0 3401#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6 3402#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1 3403#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8 3404#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3 3405#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0 3406#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4 3407#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1 3408#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0 3409#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6 3410#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1 3411#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8 3412#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3 3413#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10 3414#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4 3415#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60 3416#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5 3417#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80 3418#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7 3419#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00 3420#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8 3421#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000 3422#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe 3423#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000 3424#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14 3425#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000 3426#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17 3427#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000 3428#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b 3429#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1 3430#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 3431#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6 3432#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 3433#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1 3434#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0 3435#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6 3436#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1 3437#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18 3438#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3 3439#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f 3440#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 3441#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0 3442#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 3443#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000 3444#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc 3445#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000 3446#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd 3447#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f 3448#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0 3449#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40 3450#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6 3451#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80 3452#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7 3453#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf 3454#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0 3455#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0 3456#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4 3457#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000 3458#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc 3459#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000 3460#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e 3461#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000 3462#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f 3463#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff 3464#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 3465#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000 3466#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 3467#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000 3468#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 3469#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff 3470#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 3471#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000 3472#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 3473#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000 3474#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 3475#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff 3476#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 3477#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000 3478#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 3479#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000 3480#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 3481#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff 3482#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 3483#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000 3484#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 3485#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000 3486#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 3487#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff 3488#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 3489#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000 3490#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 3491#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000 3492#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 3493#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff 3494#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 3495#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000 3496#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 3497#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000 3498#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 3499#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff 3500#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 3501#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000 3502#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 3503#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000 3504#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 3505#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff 3506#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 3507#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000 3508#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 3509#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000 3510#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 3511#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff 3512#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 3513#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff 3514#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 3515#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff 3516#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 3517#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff 3518#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 3519#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000 3520#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 3521#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff 3522#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 3523#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00 3524#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 3525#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000 3526#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 3527#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000 3528#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 3529#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff 3530#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0 3531#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000 3532#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10 3533#define HDP_XDP_DBG_DATA__STS_MASK 0xffff 3534#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0 3535#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000 3536#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10 3537#define HDP_XDP_DBG_MASK__STS_MASK 0xffff 3538#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0 3539#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000 3540#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10 3541#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf 3542#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 3543#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0 3544#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 3545#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00 3546#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 3547#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000 3548#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc 3549#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000 3550#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 3551#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000 3552#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 3553#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000 3554#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 3555#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000 3556#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c 3557 3558#endif /* OSS_3_0_1_SH_MASK_H */ 3559