gc_9_4_1_sh_mask.h revision 1.2
1/* 2 * Copyright (C) 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _gc_9_4_1_SH_MASK_HEADER 22#define _gc_9_4_1_SH_MASK_HEADER 23 24// addressBlock: gc_cppdec2 25//CPF_EDC_TAG_CNT 26#define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0 27#define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2 28#define CPF_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L 29#define CPF_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL 30//CPF_EDC_ROQ_CNT 31#define CPF_EDC_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0 32#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2 33#define CPF_EDC_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4 34#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6 35#define CPF_EDC_ROQ_CNT__DED_COUNT_ME1_MASK 0x00000003L 36#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1_MASK 0x0000000CL 37#define CPF_EDC_ROQ_CNT__DED_COUNT_ME2_MASK 0x00000030L 38#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2_MASK 0x000000C0L 39//CPG_EDC_TAG_CNT 40#define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0 41#define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2 42#define CPG_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L 43#define CPG_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL 44//CPG_EDC_DMA_CNT 45#define CPG_EDC_DMA_CNT__ROQ_DED_COUNT__SHIFT 0x0 46#define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT__SHIFT 0x2 47#define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT 0x4 48#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT 0x6 49#define CPG_EDC_DMA_CNT__ROQ_DED_COUNT_MASK 0x00000003L 50#define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT_MASK 0x0000000CL 51#define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK 0x00000030L 52#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK 0x000000C0L 53//CPC_EDC_SCRATCH_CNT 54#define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT 0x0 55#define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT 0x2 56#define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK 0x00000003L 57#define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK 0x0000000CL 58//CPC_EDC_UCODE_CNT 59#define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT 0x0 60#define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT 0x2 61#define CPC_EDC_UCODE_CNT__DED_COUNT_MASK 0x00000003L 62#define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK 0x0000000CL 63//DC_EDC_STATE_CNT 64#define DC_EDC_STATE_CNT__DED_COUNT_ME1__SHIFT 0x0 65#define DC_EDC_STATE_CNT__SEC_COUNT_ME1__SHIFT 0x2 66#define DC_EDC_STATE_CNT__DED_COUNT_ME1_MASK 0x00000003L 67#define DC_EDC_STATE_CNT__SEC_COUNT_ME1_MASK 0x0000000CL 68//DC_EDC_CSINVOC_CNT 69#define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1__SHIFT 0x0 70#define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1__SHIFT 0x2 71#define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1__SHIFT 0x4 72#define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1__SHIFT 0x6 73#define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1_MASK 0x00000003L 74#define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1_MASK 0x0000000CL 75#define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1_MASK 0x00000030L 76#define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1_MASK 0x000000C0L 77//DC_EDC_RESTORE_CNT 78#define DC_EDC_RESTORE_CNT__DED_COUNT_ME1__SHIFT 0x0 79#define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1__SHIFT 0x2 80#define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1__SHIFT 0x4 81#define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1__SHIFT 0x6 82#define DC_EDC_RESTORE_CNT__DED_COUNT_ME1_MASK 0x00000003L 83#define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1_MASK 0x0000000CL 84#define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1_MASK 0x00000030L 85#define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1_MASK 0x000000C0L 86 87// addressBlock: gc_gdsdec 88//GDS_EDC_CNT 89#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 90#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 91#define GDS_EDC_CNT__UNUSED__SHIFT 0x6 92#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L 93#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L 94#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L 95//GDS_EDC_GRBM_CNT 96#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 97#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 98#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 99#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L 100#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL 101#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L 102//GDS_EDC_OA_DED 103#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 104#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 105#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 106#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 107#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 108#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 109#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 110#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 111#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 112#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 113#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa 114#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb 115#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc 116#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L 117#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L 118#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L 119#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L 120#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L 121#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L 122#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L 123#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L 124#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L 125#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L 126#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L 127#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L 128#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L 129//GDS_EDC_OA_PHY_CNT 130#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 131#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 132#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 133#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 134#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC__SHIFT 0x8 135#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED__SHIFT 0xa 136#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xc 137#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L 138#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL 139#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L 140#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L 141#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC_MASK 0x00000300L 142#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED_MASK 0x00000C00L 143#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFF000L 144//GDS_EDC_OA_PIPE_CNT 145#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 146#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 147#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 148#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 149#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 150#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa 151#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc 152#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe 153#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 154#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L 155#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL 156#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L 157#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L 158#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L 159#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L 160#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L 161#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L 162#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L 163 164// addressBlock: gc_shsdec 165//SPI_EDC_CNT 166#define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT__SHIFT 0x0 167#define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT__SHIFT 0x2 168#define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT__SHIFT 0x4 169#define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT__SHIFT 0x6 170#define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT__SHIFT 0x8 171#define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT__SHIFT 0xa 172#define SPI_EDC_CNT__SPI_WB_GRANT_61_SEC_COUNT__SHIFT 0xc 173#define SPI_EDC_CNT__SPI_WB_GRANT_61_DED_COUNT__SHIFT 0xe 174#define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT__SHIFT 0x10 175#define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT__SHIFT 0x12 176#define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT_MASK 0x00000003L 177#define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT_MASK 0x0000000CL 178#define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT_MASK 0x00000030L 179#define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT_MASK 0x000000C0L 180#define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT_MASK 0x00000300L 181#define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT_MASK 0x00000C00L 182#define SPI_EDC_CNT__SPI_WB_GRANT_61_SEC_COUNT_MASK 0x00003000L 183#define SPI_EDC_CNT__SPI_WB_GRANT_61_DED_COUNT_MASK 0x0000C000L 184#define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT_MASK 0x00030000L 185#define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT_MASK 0x000C0000L 186 187// addressBlock: gc_sqdec 188//SQC_EDC_CNT2 189#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0 190#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2 191#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4 192#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6 193#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8 194#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa 195#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc 196#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe 197#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x10 198#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x12 199#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L 200#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL 201#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L 202#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L 203#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L 204#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L 205#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L 206#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L 207#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x00030000L 208#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x000C0000L 209//SQC_EDC_CNT3 210#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0 211#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2 212#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4 213#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6 214#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8 215#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa 216#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc 217#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe 218#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L 219#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL 220#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L 221#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L 222#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L 223#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L 224#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L 225#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L 226//SQC_EDC_PARITY_CNT3 227#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT 0x0 228#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT__SHIFT 0x2 229#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT__SHIFT 0x4 230#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT__SHIFT 0x6 231#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT__SHIFT 0x8 232#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT__SHIFT 0xa 233#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT__SHIFT 0xc 234#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT__SHIFT 0xe 235#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT 0x10 236#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT__SHIFT 0x12 237#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x14 238#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT__SHIFT 0x16 239#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT__SHIFT 0x18 240#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT__SHIFT 0x1a 241#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x1c 242#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT__SHIFT 0x1e 243#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT_MASK 0x00000003L 244#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT_MASK 0x0000000CL 245#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT_MASK 0x00000030L 246#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT_MASK 0x000000C0L 247#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT_MASK 0x00000300L 248#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT_MASK 0x00000C00L 249#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT_MASK 0x00003000L 250#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT_MASK 0x0000C000L 251#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT_MASK 0x00030000L 252#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT_MASK 0x000C0000L 253#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT_MASK 0x00300000L 254#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT_MASK 0x00C00000L 255#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT_MASK 0x03000000L 256#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT_MASK 0x0C000000L 257#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT_MASK 0x30000000L 258#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT_MASK 0xC0000000L 259//SQC_EDC_CNT 260#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0 261#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2 262#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4 263#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6 264#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8 265#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa 266#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc 267#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe 268#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10 269#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12 270#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14 271#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16 272#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18 273#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a 274#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c 275#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e 276#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L 277#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL 278#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L 279#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L 280#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L 281#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L 282#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L 283#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L 284#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L 285#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L 286#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L 287#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L 288#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L 289#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L 290#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L 291#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L 292//SQ_EDC_SEC_CNT 293#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 294#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 295#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 296#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL 297#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L 298#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L 299//SQ_EDC_DED_CNT 300#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 301#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 302#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 303#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL 304#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L 305#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L 306//SQ_EDC_INFO 307#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 308#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 309#define SQ_EDC_INFO__SOURCE__SHIFT 0x6 310#define SQ_EDC_INFO__VM_ID__SHIFT 0x9 311#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL 312#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L 313#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L 314#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L 315//SQ_EDC_CNT 316#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0 317#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2 318#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4 319#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6 320#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8 321#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa 322#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc 323#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe 324#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10 325#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12 326#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14 327#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16 328#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18 329#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a 330#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L 331#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL 332#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L 333#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L 334#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L 335#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L 336#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L 337#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L 338#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L 339#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L 340#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L 341#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L 342#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L 343#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L 344 345// addressBlock: gc_tpdec 346//TA_EDC_CNT 347#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT 0x0 348#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT 0x2 349#define TA_EDC_CNT__TA_FS_AFIFO_SEC_COUNT__SHIFT 0x4 350#define TA_EDC_CNT__TA_FS_AFIFO_DED_COUNT__SHIFT 0x6 351#define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT__SHIFT 0x8 352#define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT__SHIFT 0xa 353#define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT__SHIFT 0xc 354#define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT__SHIFT 0xe 355#define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT__SHIFT 0x10 356#define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT__SHIFT 0x12 357#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK 0x00000003L 358#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK 0x0000000CL 359#define TA_EDC_CNT__TA_FS_AFIFO_SEC_COUNT_MASK 0x00000030L 360#define TA_EDC_CNT__TA_FS_AFIFO_DED_COUNT_MASK 0x000000C0L 361#define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT_MASK 0x00000300L 362#define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT_MASK 0x00000C00L 363#define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT_MASK 0x00003000L 364#define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT_MASK 0x0000C000L 365#define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT_MASK 0x00030000L 366#define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT_MASK 0x000C0000L 367 368// addressBlock: gc_tcdec 369//TCP_EDC_CNT 370#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 371#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 372#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 373#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL 374#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L 375#define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L 376//TCP_EDC_CNT_NEW 377#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT 0x0 378#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT 0x2 379#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT 0x4 380#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT 0x6 381#define TCP_EDC_CNT_NEW__CMD_FIFO_SEC_COUNT__SHIFT 0x8 382#define TCP_EDC_CNT_NEW__CMD_FIFO_DED_COUNT__SHIFT 0xa 383#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT 0xc 384#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT 0xe 385#define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT__SHIFT 0x10 386#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT 0x12 387#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT 0x14 388#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT 0x16 389#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT 0x18 390#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK 0x00000003L 391#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK 0x0000000CL 392#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK 0x00000030L 393#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK 0x000000C0L 394#define TCP_EDC_CNT_NEW__CMD_FIFO_SEC_COUNT_MASK 0x00000300L 395#define TCP_EDC_CNT_NEW__CMD_FIFO_DED_COUNT_MASK 0x00000C00L 396#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK 0x00003000L 397#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK 0x0000C000L 398#define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT_MASK 0x00030000L 399#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK 0x000C0000L 400#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK 0x00300000L 401#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK 0x00C00000L 402#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK 0x03000000L 403//TCP_ATC_EDC_GATCL1_CNT 404#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 405#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL 406//TCI_EDC_CNT 407#define TCI_EDC_CNT__WRITE_RAM_SEC_COUNT__SHIFT 0x0 408#define TCI_EDC_CNT__WRITE_RAM_DED_COUNT__SHIFT 0x2 409#define TCI_EDC_CNT__WRITE_RAM_SEC_COUNT_MASK 0x00000003L 410#define TCI_EDC_CNT__WRITE_RAM_DED_COUNT_MASK 0x0000000CL 411//TCA_EDC_CNT 412#define TCA_EDC_CNT__HOLE_FIFO_SEC_COUNT__SHIFT 0x0 413#define TCA_EDC_CNT__HOLE_FIFO_DED_COUNT__SHIFT 0x2 414#define TCA_EDC_CNT__REQ_FIFO_SEC_COUNT__SHIFT 0x4 415#define TCA_EDC_CNT__REQ_FIFO_DED_COUNT__SHIFT 0x6 416#define TCA_EDC_CNT__HOLE_FIFO_SEC_COUNT_MASK 0x00000003L 417#define TCA_EDC_CNT__HOLE_FIFO_DED_COUNT_MASK 0x0000000CL 418#define TCA_EDC_CNT__REQ_FIFO_SEC_COUNT_MASK 0x00000030L 419#define TCA_EDC_CNT__REQ_FIFO_DED_COUNT_MASK 0x000000C0L 420//TCC_EDC_CNT 421#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0 422#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2 423#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4 424#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6 425#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8 426#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa 427#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc 428#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe 429#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10 430#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12 431#define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT__SHIFT 0x14 432#define TCC_EDC_CNT__LATENCY_FIFO_DED_COUNT__SHIFT 0x16 433#define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_SEC_COUNT__SHIFT 0x18 434#define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_DED_COUNT__SHIFT 0x1a 435#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L 436#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL 437#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L 438#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L 439#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L 440#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L 441#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L 442#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L 443#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L 444#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L 445#define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT_MASK 0x00300000L 446#define TCC_EDC_CNT__LATENCY_FIFO_DED_COUNT_MASK 0x00C00000L 447#define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_SEC_COUNT_MASK 0x03000000L 448#define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_DED_COUNT_MASK 0x0C000000L 449//TCC_EDC_CNT2 450#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SEC_COUNT__SHIFT 0x0 451#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_DED_COUNT__SHIFT 0x2 452#define TCC_EDC_CNT2__UC_ATOMIC_FIFO_SEC_COUNT__SHIFT 0x4 453#define TCC_EDC_CNT2__UC_ATOMIC_FIFO_DED_COUNT__SHIFT 0x6 454#define TCC_EDC_CNT2__WRITE_CACHE_READ_SEC_COUNT__SHIFT 0x8 455#define TCC_EDC_CNT2__WRITE_CACHE_READ_DED_COUNT__SHIFT 0xa 456#define TCC_EDC_CNT2__RETURN_CONTROL_SEC_COUNT__SHIFT 0xc 457#define TCC_EDC_CNT2__RETURN_CONTROL_DED_COUNT__SHIFT 0xe 458#define TCC_EDC_CNT2__IN_USE_TRANSFER_SEC_COUNT__SHIFT 0x10 459#define TCC_EDC_CNT2__IN_USE_TRANSFER_DED_COUNT__SHIFT 0x12 460#define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT__SHIFT 0x14 461#define TCC_EDC_CNT2__IN_USE_DEC_DED_COUNT__SHIFT 0x16 462#define TCC_EDC_CNT2__WRITE_RETURN_SEC_COUNT__SHIFT 0x18 463#define TCC_EDC_CNT2__WRITE_RETURN_DED_COUNT__SHIFT 0x1a 464#define TCC_EDC_CNT2__RETURN_DATA_SEC_COUNT__SHIFT 0x1c 465#define TCC_EDC_CNT2__RETURN_DATA_DED_COUNT__SHIFT 0x1e 466#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SEC_COUNT_MASK 0x00000003L 467#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_DED_COUNT_MASK 0x0000000CL 468#define TCC_EDC_CNT2__UC_ATOMIC_FIFO_SEC_COUNT_MASK 0x00000030L 469#define TCC_EDC_CNT2__UC_ATOMIC_FIFO_DED_COUNT_MASK 0x000000C0L 470#define TCC_EDC_CNT2__WRITE_CACHE_READ_SEC_COUNT_MASK 0x00000300L 471#define TCC_EDC_CNT2__WRITE_CACHE_READ_DED_COUNT_MASK 0x00000C00L 472#define TCC_EDC_CNT2__RETURN_CONTROL_SEC_COUNT_MASK 0x00003000L 473#define TCC_EDC_CNT2__RETURN_CONTROL_DED_COUNT_MASK 0x0000C000L 474#define TCC_EDC_CNT2__IN_USE_TRANSFER_SEC_COUNT_MASK 0x00030000L 475#define TCC_EDC_CNT2__IN_USE_TRANSFER_DED_COUNT_MASK 0x000C0000L 476#define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT_MASK 0x00300000L 477#define TCC_EDC_CNT2__IN_USE_DEC_DED_COUNT_MASK 0x00C00000L 478#define TCC_EDC_CNT2__WRITE_RETURN_SEC_COUNT_MASK 0x03000000L 479#define TCC_EDC_CNT2__WRITE_RETURN_DED_COUNT_MASK 0x0C000000L 480#define TCC_EDC_CNT2__RETURN_DATA_SEC_COUNT_MASK 0x30000000L 481#define TCC_EDC_CNT2__RETURN_DATA_DED_COUNT_MASK 0xC0000000L 482 483// addressBlock: gc_tpdec 484//TD_EDC_CNT 485#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT 0x0 486#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT 0x2 487#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT 0x4 488#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT 0x6 489#define TD_EDC_CNT__CS_FIFO_SEC_COUNT__SHIFT 0x8 490#define TD_EDC_CNT__CS_FIFO_DED_COUNT__SHIFT 0xa 491#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK 0x00000003L 492#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK 0x0000000CL 493#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK 0x00000030L 494#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK 0x000000C0L 495#define TD_EDC_CNT__CS_FIFO_SEC_COUNT_MASK 0x00000300L 496#define TD_EDC_CNT__CS_FIFO_DED_COUNT_MASK 0x00000C00L 497//TA_EDC_CNT 498#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT 0x0 499#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT 0x2 500#define TA_EDC_CNT__TA_FS_AFIFO_SEC_COUNT__SHIFT 0x4 501#define TA_EDC_CNT__TA_FS_AFIFO_DED_COUNT__SHIFT 0x6 502#define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT__SHIFT 0x8 503#define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT__SHIFT 0xa 504#define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT__SHIFT 0xc 505#define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT__SHIFT 0xe 506#define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT__SHIFT 0x10 507#define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT__SHIFT 0x12 508#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK 0x00000003L 509#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK 0x0000000CL 510#define TA_EDC_CNT__TA_FS_AFIFO_SEC_COUNT_MASK 0x00000030L 511#define TA_EDC_CNT__TA_FS_AFIFO_DED_COUNT_MASK 0x000000C0L 512#define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT_MASK 0x00000300L 513#define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT_MASK 0x00000C00L 514#define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT_MASK 0x00003000L 515#define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT_MASK 0x0000C000L 516#define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT_MASK 0x00030000L 517#define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT_MASK 0x000C0000L 518 519// addressBlock: gc_ea_gceadec2 520//GCEA_EDC_CNT 521#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 522#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 523#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 524#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 525#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 526#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 527#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 528#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 529#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 530#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 531#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 532#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 533#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 534#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 535#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 536#define GCEA_EDC_CNT__MAM_AFMEM_SEC_COUNT__SHIFT 0x1e 537#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 538#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 539#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 540#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 541#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 542#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 543#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 544#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 545#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 546#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 547#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 548#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 549#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 550#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 551#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 552#define GCEA_EDC_CNT__MAM_AFMEM_SEC_COUNT_MASK 0xC0000000L 553//GCEA_EDC_CNT2 554#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 555#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 556#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 557#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 558#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 559#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 560#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 561#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 562#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 563#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 564#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 565#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 566#define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 567#define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 568#define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 569#define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 570#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 571#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 572#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 573#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 574#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 575#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 576#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 577#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 578#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 579#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 580#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 581#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 582#define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 583#define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 584#define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 585#define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 586//GCEA_EDC_CNT3 587#define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 588#define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 589#define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 590#define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 591#define GCEA_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 592#define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa 593#define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc 594#define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT__SHIFT 0xe 595#define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT__SHIFT 0x10 596#define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT__SHIFT 0x12 597#define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT__SHIFT 0x14 598#define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT__SHIFT 0x16 599#define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT__SHIFT 0x18 600#define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT__SHIFT 0x1a 601#define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT__SHIFT 0x1c 602#define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT__SHIFT 0x1e 603#define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 604#define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 605#define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 606#define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 607#define GCEA_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L 608#define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L 609#define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L 610#define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT_MASK 0x0000C000L 611#define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT_MASK 0x00030000L 612#define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT_MASK 0x000C0000L 613#define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT_MASK 0x00300000L 614#define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT_MASK 0x00C00000L 615#define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT_MASK 0x03000000L 616#define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT_MASK 0x0C000000L 617#define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT_MASK 0x30000000L 618#define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT_MASK 0xC0000000L 619 620//GCEA_ERR_STATUS 621#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 622#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 623#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 624#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 625#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 626#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 627#define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd 628#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 629#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 630#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 631#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 632#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 633#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 634#define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 635 636// addressBlock: gc_gfxudec 637//GRBM_GFX_INDEX 638#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 639#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 640#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 641#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d 642#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e 643#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f 644#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL 645#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L 646#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L 647#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L 648#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L 649#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L 650 651// addressBlock: gc_utcl2_atcl2dec 652//ATC_L2_CNTL 653//ATC_L2_CACHE_4K_DSM_INDEX 654#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0 655#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL 656//ATC_L2_CACHE_2M_DSM_INDEX 657#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0 658#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL 659//ATC_L2_CACHE_4K_DSM_CNTL 660#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd 661#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf 662#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L 663#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L 664//ATC_L2_CACHE_2M_DSM_CNTL 665#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd 666#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf 667#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L 668#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L 669 670// addressBlock: gc_utcl2_vml2pfdec 671//VML2_MEM_ECC_INDEX 672#define VML2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 673#define VML2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL 674//VML2_WALKER_MEM_ECC_INDEX 675#define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0 676#define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL 677//UTCL2_MEM_ECC_INDEX 678#define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 679#define UTCL2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL 680//VML2_MEM_ECC_CNTL 681#define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc 682#define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe 683#define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L 684#define VML2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L 685//VML2_WALKER_MEM_ECC_CNTL 686#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc 687#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe 688#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L 689#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L 690//UTCL2_MEM_ECC_CNTL 691#define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc 692#define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe 693#define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L 694#define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L 695 696// addressBlock: gc_rlcpdec 697//RLC_EDC_CNT 698#define RLC_EDC_CNT__RLCG_INSTR_RAM_SEC_COUNT__SHIFT 0x0 699#define RLC_EDC_CNT__RLCG_INSTR_RAM_DED_COUNT__SHIFT 0x2 700#define RLC_EDC_CNT__RLCG_SCRATCH_RAM_SEC_COUNT__SHIFT 0x4 701#define RLC_EDC_CNT__RLCG_SCRATCH_RAM_DED_COUNT__SHIFT 0x6 702#define RLC_EDC_CNT__RLCV_INSTR_RAM_SEC_COUNT__SHIFT 0x8 703#define RLC_EDC_CNT__RLCV_INSTR_RAM_DED_COUNT__SHIFT 0xa 704#define RLC_EDC_CNT__RLCV_SCRATCH_RAM_SEC_COUNT__SHIFT 0xc 705#define RLC_EDC_CNT__RLCV_SCRATCH_RAM_DED_COUNT__SHIFT 0xe 706#define RLC_EDC_CNT__RLC_TCTAG_RAM_SEC_COUNT__SHIFT 0x10 707#define RLC_EDC_CNT__RLC_TCTAG_RAM_DED_COUNT__SHIFT 0x12 708#define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT__SHIFT 0x14 709#define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_DED_COUNT__SHIFT 0x16 710#define RLC_EDC_CNT__RLC_SRM_DATA_RAM_SEC_COUNT__SHIFT 0x18 711#define RLC_EDC_CNT__RLC_SRM_DATA_RAM_DED_COUNT__SHIFT 0x1a 712#define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_SEC_COUNT__SHIFT 0x1c 713#define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_DED_COUNT__SHIFT 0x1e 714#define RLC_EDC_CNT__RLCG_INSTR_RAM_SEC_COUNT_MASK 0x00000003L 715#define RLC_EDC_CNT__RLCG_INSTR_RAM_DED_COUNT_MASK 0x0000000CL 716#define RLC_EDC_CNT__RLCG_SCRATCH_RAM_SEC_COUNT_MASK 0x00000030L 717#define RLC_EDC_CNT__RLCG_SCRATCH_RAM_DED_COUNT_MASK 0x000000C0L 718#define RLC_EDC_CNT__RLCV_INSTR_RAM_SEC_COUNT_MASK 0x00000300L 719#define RLC_EDC_CNT__RLCV_INSTR_RAM_DED_COUNT_MASK 0x00000C00L 720#define RLC_EDC_CNT__RLCV_SCRATCH_RAM_SEC_COUNT_MASK 0x00003000L 721#define RLC_EDC_CNT__RLCV_SCRATCH_RAM_DED_COUNT_MASK 0x0000C000L 722#define RLC_EDC_CNT__RLC_TCTAG_RAM_SEC_COUNT_MASK 0x00030000L 723#define RLC_EDC_CNT__RLC_TCTAG_RAM_DED_COUNT_MASK 0x000C0000L 724#define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT_MASK 0x00300000L 725#define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_DED_COUNT_MASK 0x00C00000L 726#define RLC_EDC_CNT__RLC_SRM_DATA_RAM_SEC_COUNT_MASK 0x03000000L 727#define RLC_EDC_CNT__RLC_SRM_DATA_RAM_DED_COUNT_MASK 0x0C000000L 728#define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_SEC_COUNT_MASK 0x30000000L 729#define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_DED_COUNT_MASK 0xC0000000L 730//RLC_EDC_CNT2 731#define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT__SHIFT 0x0 732#define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT__SHIFT 0x2 733#define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT__SHIFT 0x4 734#define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT__SHIFT 0x6 735#define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT__SHIFT 0x8 736#define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT__SHIFT 0xa 737#define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT__SHIFT 0xc 738#define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT__SHIFT 0xe 739#define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT__SHIFT 0x10 740#define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT__SHIFT 0x12 741#define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT__SHIFT 0x14 742#define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT__SHIFT 0x16 743#define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT__SHIFT 0x18 744#define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT__SHIFT 0x1a 745#define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT__SHIFT 0x1c 746#define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT__SHIFT 0x1e 747#define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT_MASK 0x00000003L 748#define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT_MASK 0x0000000CL 749#define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT_MASK 0x00000030L 750#define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT_MASK 0x000000C0L 751#define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT_MASK 0x00000300L 752#define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT_MASK 0x00000C00L 753#define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT_MASK 0x00003000L 754#define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT_MASK 0x0000C000L 755#define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT_MASK 0x00030000L 756#define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT_MASK 0x000C0000L 757#define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT_MASK 0x00300000L 758#define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT_MASK 0x00C00000L 759#define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT_MASK 0x03000000L 760#define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT_MASK 0x0C000000L 761#define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT_MASK 0x30000000L 762#define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT_MASK 0xC0000000L 763 764#endif 765