dcn_3_1_6_offset.h revision 1.1
1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef _dcn_3_1_6_OFFSET_HEADER 25#define _dcn_3_1_6_OFFSET_HEADER 26 27 28 29// addressBlock: dce_dc_hda_azcontroller_azdec 30// base address: 0x1300000 31#define regAZCONTROLLER0_GLOBAL_CAPABILITIES 0x4b7000 32#define regAZCONTROLLER0_GLOBAL_CAPABILITIES_BASE_IDX 3 33#define regAZCONTROLLER0_MINOR_VERSION 0x4b7000 34#define regAZCONTROLLER0_MINOR_VERSION_BASE_IDX 3 35#define regAZCONTROLLER0_MAJOR_VERSION 0x4b7000 36#define regAZCONTROLLER0_MAJOR_VERSION_BASE_IDX 3 37#define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY 0x4b7001 38#define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 39#define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY 0x4b7001 40#define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 41#define regAZCONTROLLER0_GLOBAL_CONTROL 0x4b7002 42#define regAZCONTROLLER0_GLOBAL_CONTROL_BASE_IDX 3 43#define regAZCONTROLLER0_WAKE_ENABLE 0x4b7003 44#define regAZCONTROLLER0_WAKE_ENABLE_BASE_IDX 3 45#define regAZCONTROLLER0_STATE_CHANGE_STATUS 0x4b7003 46#define regAZCONTROLLER0_STATE_CHANGE_STATUS_BASE_IDX 3 47#define regAZCONTROLLER0_GLOBAL_STATUS 0x4b7004 48#define regAZCONTROLLER0_GLOBAL_STATUS_BASE_IDX 3 49#define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 50#define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 51#define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 52#define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 53#define regAZCONTROLLER0_INTERRUPT_CONTROL 0x4b7008 54#define regAZCONTROLLER0_INTERRUPT_CONTROL_BASE_IDX 3 55#define regAZCONTROLLER0_INTERRUPT_STATUS 0x4b7009 56#define regAZCONTROLLER0_INTERRUPT_STATUS_BASE_IDX 3 57#define regAZCONTROLLER0_WALL_CLOCK_COUNTER 0x4b700c 58#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_BASE_IDX 3 59#define regAZCONTROLLER0_STREAM_SYNCHRONIZATION 0x4b700e 60#define regAZCONTROLLER0_STREAM_SYNCHRONIZATION_BASE_IDX 3 61#define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS 0x4b7010 62#define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS_BASE_IDX 3 63#define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS 0x4b7011 64#define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS_BASE_IDX 3 65#define regAZCONTROLLER0_CORB_WRITE_POINTER 0x4b7012 66#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 3 67#define regAZCONTROLLER0_CORB_READ_POINTER 0x4b7012 68#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 3 69#define regAZCONTROLLER0_CORB_CONTROL 0x4b7013 70#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 3 71#define regAZCONTROLLER0_CORB_STATUS 0x4b7013 72#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 3 73#define regAZCONTROLLER0_CORB_SIZE 0x4b7013 74#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 3 75#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x4b7014 76#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 77#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x4b7015 78#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 79#define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x4b7016 80#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 3 81#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x4b7016 82#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3 83#define regAZCONTROLLER0_RIRB_CONTROL 0x4b7017 84#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 3 85#define regAZCONTROLLER0_RIRB_STATUS 0x4b7017 86#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 3 87#define regAZCONTROLLER0_RIRB_SIZE 0x4b7017 88#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 3 89#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 90#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 91#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 92#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 93#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 94#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 95#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 96#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 97#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x4b701a 98#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3 99#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c 100#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 101#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d 102#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 103#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x4b780c 104#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3 105 106 107// addressBlock: dce_dc_hda_azendpoint_azdec 108// base address: 0x1300000 109#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 110#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 111#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 112#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 113 114 115// addressBlock: dce_dc_hda_azinputendpoint_azdec 116// base address: 0x1300000 117#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 118#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 119#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 120#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 121 122 123// addressBlock: dce_dc_hda_azroot_azdec 124// base address: 0x1300000 125#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 126#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 127#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 128#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 129 130 131// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] 132// base address: 0x48 133#define regVGA_MEM_WRITE_PAGE_ADDR 0x0000 134#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 135#define regVGA_MEM_READ_PAGE_ADDR 0x0001 136#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 137 138 139// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] 140// base address: 0x3b4 141#define regCRTC8_IDX 0x002d 142#define regCRTC8_IDX_BASE_IDX 1 143#define regCRTC8_DATA 0x002d 144#define regCRTC8_DATA_BASE_IDX 1 145#define regGENFC_WT 0x002e 146#define regGENFC_WT_BASE_IDX 1 147#define regGENS1 0x002e 148#define regGENS1_BASE_IDX 1 149#define regATTRDW 0x0030 150#define regATTRDW_BASE_IDX 1 151#define regATTRX 0x0030 152#define regATTRX_BASE_IDX 1 153#define regATTRDR 0x0030 154#define regATTRDR_BASE_IDX 1 155#define regGENMO_WT 0x0030 156#define regGENMO_WT_BASE_IDX 1 157#define regGENS0 0x0030 158#define regGENS0_BASE_IDX 1 159#define regGENENB 0x0030 160#define regGENENB_BASE_IDX 1 161#define regSEQ8_IDX 0x0031 162#define regSEQ8_IDX_BASE_IDX 1 163#define regSEQ8_DATA 0x0031 164#define regSEQ8_DATA_BASE_IDX 1 165#define regDAC_MASK 0x0031 166#define regDAC_MASK_BASE_IDX 1 167#define regDAC_R_INDEX 0x0031 168#define regDAC_R_INDEX_BASE_IDX 1 169#define regDAC_W_INDEX 0x0032 170#define regDAC_W_INDEX_BASE_IDX 1 171#define regDAC_DATA 0x0032 172#define regDAC_DATA_BASE_IDX 1 173#define regGENFC_RD 0x0032 174#define regGENFC_RD_BASE_IDX 1 175#define regGENMO_RD 0x0033 176#define regGENMO_RD_BASE_IDX 1 177#define regGRPH8_IDX 0x0033 178#define regGRPH8_IDX_BASE_IDX 1 179#define regGRPH8_DATA 0x0033 180#define regGRPH8_DATA_BASE_IDX 1 181#define regCRTC8_IDX_1 0x0035 182#define regCRTC8_IDX_1_BASE_IDX 1 183#define regCRTC8_DATA_1 0x0035 184#define regCRTC8_DATA_1_BASE_IDX 1 185#define regGENFC_WT_1 0x0036 186#define regGENFC_WT_1_BASE_IDX 1 187#define regGENS1_1 0x0036 188#define regGENS1_1_BASE_IDX 1 189 190 191// addressBlock: dce_dc_hda_azcontroller_azdec 192// base address: 0x0 193#define regAZCONTROLLER1_CORB_WRITE_POINTER 0x0000 194#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 0 195#define regAZCONTROLLER1_CORB_READ_POINTER 0x0000 196#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 0 197#define regAZCONTROLLER1_CORB_CONTROL 0x0001 198#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 0 199#define regAZCONTROLLER1_CORB_STATUS 0x0001 200#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 0 201#define regAZCONTROLLER1_CORB_SIZE 0x0001 202#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 0 203#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x0002 204#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 205#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x0003 206#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 207#define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x0004 208#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 0 209#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x0004 210#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0 211#define regAZCONTROLLER1_RIRB_CONTROL 0x0005 212#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 0 213#define regAZCONTROLLER1_RIRB_STATUS 0x0005 214#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 0 215#define regAZCONTROLLER1_RIRB_SIZE 0x0005 216#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 0 217#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 218#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 219#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 220#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 221#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 222#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 223#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 224#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 225#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x0008 226#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0 227#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a 228#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 229#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b 230#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 231#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS 0x074c 232#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 233 234 235// addressBlock: dce_dc_hda_azendpoint_azdec 236// base address: 0x0 237#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 238#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 239#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 240#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 241 242 243// addressBlock: dce_dc_hda_azinputendpoint_azdec 244// base address: 0x0 245#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 246#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 247#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 248#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 249 250 251// addressBlock: dce_dc_hda_azroot_azdec 252// base address: 0x0 253#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 254#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 255#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 256#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 257 258 259// addressBlock: dce_dc_hda_azstream0_azdec 260// base address: 0x0 261#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e 262#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 263#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f 264#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 265#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010 266#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 267#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011 268#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 269#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012 270#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 271#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012 272#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 273#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014 274#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 275#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015 276#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 277#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761 278#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 279 280 281// addressBlock: dce_dc_hda_azstream1_azdec 282// base address: 0x20 283#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016 284#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 285#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017 286#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 287#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018 288#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 289#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019 290#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 291#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a 292#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 293#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a 294#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 295#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c 296#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 297#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d 298#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 299#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769 300#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 301 302 303// addressBlock: dce_dc_hda_azstream2_azdec 304// base address: 0x40 305#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e 306#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 307#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f 308#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 309#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020 310#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 311#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021 312#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 313#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022 314#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 315#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022 316#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 317#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024 318#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 319#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025 320#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 321#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771 322#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 323 324 325// addressBlock: dce_dc_hda_azstream3_azdec 326// base address: 0x60 327#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026 328#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 329#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027 330#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 331#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028 332#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 333#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029 334#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 335#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a 336#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 337#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a 338#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 339#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c 340#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 341#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d 342#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 343#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779 344#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 345 346 347// addressBlock: dce_dc_hda_azstream4_azdec 348// base address: 0x80 349#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e 350#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 351#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f 352#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 353#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030 354#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 355#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031 356#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 357#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032 358#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 359#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032 360#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 361#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034 362#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 363#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035 364#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 365#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781 366#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 367 368 369// addressBlock: dce_dc_hda_azstream5_azdec 370// base address: 0xa0 371#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036 372#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 373#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037 374#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 375#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038 376#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 377#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039 378#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 379#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a 380#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 381#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a 382#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 383#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c 384#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 385#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d 386#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 387#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789 388#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 389 390 391// addressBlock: dce_dc_hda_azstream6_azdec 392// base address: 0xc0 393#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e 394#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 395#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f 396#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 397#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040 398#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 399#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041 400#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 401#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042 402#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 403#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042 404#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 405#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044 406#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 407#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045 408#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 409#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791 410#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 411 412 413// addressBlock: dce_dc_hda_azstream7_azdec 414// base address: 0xe0 415#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046 416#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 417#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047 418#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 419#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048 420#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 421#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049 422#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 423#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a 424#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 425#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a 426#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 427#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c 428#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 429#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d 430#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 431#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799 432#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 433 434 435// addressBlock: dce_dc_dccg_dccg_dfs_dispdec 436// base address: 0x0 437#define regDENTIST_DISPCLK_CNTL 0x0064 438#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 439 440 441// addressBlock: dce_dc_dccg_dccg_dispdec 442// base address: 0x0 443#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 444#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 445#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 446#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 447#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 448#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 449#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 450#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 451#define regDP_DTO_DBUF_EN 0x0044 452#define regDP_DTO_DBUF_EN_BASE_IDX 1 453#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 454#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 455#define regDCCG_GATE_DISABLE_CNTL4 0x0049 456#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 457#define regDPSTREAMCLK_CNTL 0x004a 458#define regDPSTREAMCLK_CNTL_BASE_IDX 1 459#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b 460#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 461#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c 462#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 463#define regDCCG_PERFMON_CNTL2 0x004e 464#define regDCCG_PERFMON_CNTL2_BASE_IDX 1 465#define regDCCG_DS_DTO_INCR 0x0053 466#define regDCCG_DS_DTO_INCR_BASE_IDX 1 467#define regDCCG_DS_DTO_MODULO 0x0054 468#define regDCCG_DS_DTO_MODULO_BASE_IDX 1 469#define regDCCG_DS_CNTL 0x0055 470#define regDCCG_DS_CNTL_BASE_IDX 1 471#define regDCCG_DS_HW_CAL_INTERVAL 0x0056 472#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 473#define regDPREFCLK_CNTL 0x0058 474#define regDPREFCLK_CNTL_BASE_IDX 1 475#define regDCE_VERSION 0x005e 476#define regDCE_VERSION_BASE_IDX 1 477#define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f 478#define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 479#define regDCCG_GTC_CNTL 0x0060 480#define regDCCG_GTC_CNTL_BASE_IDX 1 481#define regDCCG_GTC_DTO_INCR 0x0061 482#define regDCCG_GTC_DTO_INCR_BASE_IDX 1 483#define regDCCG_GTC_DTO_MODULO 0x0062 484#define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 485#define regDCCG_GTC_CURRENT 0x0063 486#define regDCCG_GTC_CURRENT_BASE_IDX 1 487#define regSYMCLK32_SE_CNTL 0x0065 488#define regSYMCLK32_SE_CNTL_BASE_IDX 1 489#define regSYMCLK32_LE_CNTL 0x0066 490#define regSYMCLK32_LE_CNTL_BASE_IDX 1 491#define regDSCCLK0_DTO_PARAM 0x006c 492#define regDSCCLK0_DTO_PARAM_BASE_IDX 1 493#define regDSCCLK1_DTO_PARAM 0x006d 494#define regDSCCLK1_DTO_PARAM_BASE_IDX 1 495#define regDSCCLK2_DTO_PARAM 0x006e 496#define regDSCCLK2_DTO_PARAM_BASE_IDX 1 497#define regMILLISECOND_TIME_BASE_DIV 0x0070 498#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 499#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 500#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 501#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 502#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 503#define regDCCG_PERFMON_CNTL 0x0073 504#define regDCCG_PERFMON_CNTL_BASE_IDX 1 505#define regDCCG_GATE_DISABLE_CNTL 0x0074 506#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 507#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 508#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 509#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 510#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 511#define regDCCG_CAC_STATUS 0x0077 512#define regDCCG_CAC_STATUS_BASE_IDX 1 513#define regMICROSECOND_TIME_BASE_DIV 0x007b 514#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 515#define regDCCG_GATE_DISABLE_CNTL2 0x007c 516#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 517#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d 518#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 519#define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e 520#define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 521#define regDCCG_DISP_CNTL_REG 0x007f 522#define regDCCG_DISP_CNTL_REG_BASE_IDX 1 523#define regOTG0_PIXEL_RATE_CNTL 0x0080 524#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 525#define regDP_DTO0_PHASE 0x0081 526#define regDP_DTO0_PHASE_BASE_IDX 1 527#define regDP_DTO0_MODULO 0x0082 528#define regDP_DTO0_MODULO_BASE_IDX 1 529#define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 530#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 531#define regOTG1_PIXEL_RATE_CNTL 0x0084 532#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 533#define regDP_DTO1_PHASE 0x0085 534#define regDP_DTO1_PHASE_BASE_IDX 1 535#define regDP_DTO1_MODULO 0x0086 536#define regDP_DTO1_MODULO_BASE_IDX 1 537#define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 538#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 539#define regOTG2_PIXEL_RATE_CNTL 0x0088 540#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 541#define regDP_DTO2_PHASE 0x0089 542#define regDP_DTO2_PHASE_BASE_IDX 1 543#define regDP_DTO2_MODULO 0x008a 544#define regDP_DTO2_MODULO_BASE_IDX 1 545#define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b 546#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 547#define regOTG3_PIXEL_RATE_CNTL 0x008c 548#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 549#define regDP_DTO3_PHASE 0x008d 550#define regDP_DTO3_PHASE_BASE_IDX 1 551#define regDP_DTO3_MODULO 0x008e 552#define regDP_DTO3_MODULO_BASE_IDX 1 553#define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f 554#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 555#define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 556#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 557#define regDPPCLK0_DTO_PARAM 0x0099 558#define regDPPCLK0_DTO_PARAM_BASE_IDX 1 559#define regDPPCLK1_DTO_PARAM 0x009a 560#define regDPPCLK1_DTO_PARAM_BASE_IDX 1 561#define regDPPCLK2_DTO_PARAM 0x009b 562#define regDPPCLK2_DTO_PARAM_BASE_IDX 1 563#define regDPPCLK3_DTO_PARAM 0x009c 564#define regDPPCLK3_DTO_PARAM_BASE_IDX 1 565#define regDCCG_CAC_STATUS2 0x009f 566#define regDCCG_CAC_STATUS2_BASE_IDX 1 567#define regSYMCLKA_CLOCK_ENABLE 0x00a0 568#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 569#define regSYMCLKB_CLOCK_ENABLE 0x00a1 570#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 571#define regSYMCLKC_CLOCK_ENABLE 0x00a2 572#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 573#define regSYMCLKD_CLOCK_ENABLE 0x00a3 574#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 575#define regSYMCLKE_CLOCK_ENABLE 0x00a4 576#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 577#define regDCCG_SOFT_RESET 0x00a6 578#define regDCCG_SOFT_RESET_BASE_IDX 1 579#define regDSCCLK_DTO_CTRL 0x00a7 580#define regDSCCLK_DTO_CTRL_BASE_IDX 1 581#define regDCCG_AUDIO_DTO_SOURCE 0x00ab 582#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 583#define regDCCG_AUDIO_DTO0_PHASE 0x00ac 584#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 585#define regDCCG_AUDIO_DTO0_MODULE 0x00ad 586#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 587#define regDCCG_AUDIO_DTO1_PHASE 0x00ae 588#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 589#define regDCCG_AUDIO_DTO1_MODULE 0x00af 590#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 591#define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 592#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 593#define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 594#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 595#define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 596#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 597#define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 598#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 599#define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 600#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 601#define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 602#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 603#define regDPPCLK_DTO_CTRL 0x00b6 604#define regDPPCLK_DTO_CTRL_BASE_IDX 1 605#define regDCCG_VSYNC_CNT_CTRL 0x00b8 606#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 607#define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 608#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 609#define regFORCE_SYMCLK_DISABLE 0x00ba 610#define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 611#define regDCCG_TEST_CLK_SEL 0x00be 612#define regDCCG_TEST_CLK_SEL_BASE_IDX 1 613#define regDTBCLK_DTO0_PHASE 0x0018 614#define regDTBCLK_DTO0_PHASE_BASE_IDX 2 615#define regDTBCLK_DTO1_PHASE 0x0019 616#define regDTBCLK_DTO1_PHASE_BASE_IDX 2 617#define regDTBCLK_DTO2_PHASE 0x001a 618#define regDTBCLK_DTO2_PHASE_BASE_IDX 2 619#define regDTBCLK_DTO3_PHASE 0x001b 620#define regDTBCLK_DTO3_PHASE_BASE_IDX 2 621#define regDTBCLK_DTO0_MODULO 0x001f 622#define regDTBCLK_DTO0_MODULO_BASE_IDX 2 623#define regDTBCLK_DTO1_MODULO 0x0020 624#define regDTBCLK_DTO1_MODULO_BASE_IDX 2 625#define regDTBCLK_DTO2_MODULO 0x0021 626#define regDTBCLK_DTO2_MODULO_BASE_IDX 2 627#define regDTBCLK_DTO3_MODULO 0x0022 628#define regDTBCLK_DTO3_MODULO_BASE_IDX 2 629#define regPHYASYMCLK_CLOCK_CNTL 0x0052 630#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 631#define regPHYBSYMCLK_CLOCK_CNTL 0x0053 632#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 633#define regPHYCSYMCLK_CLOCK_CNTL 0x0054 634#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 635#define regPHYDSYMCLK_CLOCK_CNTL 0x0055 636#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 637#define regPHYESYMCLK_CLOCK_CNTL 0x0056 638#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 639#define regPHYFSYMCLK_CLOCK_CNTL 0x0057 640#define regPHYFSYMCLK_CLOCK_CNTL_BASE_IDX 2 641#define regDCCG_GATE_DISABLE_CNTL3 0x005a 642#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 643#define regHDMISTREAMCLK0_DTO_PARAM 0x005b 644#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 645#define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 646#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 647#define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 648#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 649#define regDTBCLK_DTO_DBUF_EN 0x0063 650#define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 651 652 653// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec 654// base address: 0x0 655#define regDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 656#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 657#define regDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 658#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 659#define regDC_PERFMON0_PERFCOUNTER_STATE 0x0002 660#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 661#define regDC_PERFMON0_PERFMON_CNTL 0x0003 662#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 663#define regDC_PERFMON0_PERFMON_CNTL2 0x0004 664#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 665#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 666#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 667#define regDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 668#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 669#define regDC_PERFMON0_PERFMON_HI 0x0007 670#define regDC_PERFMON0_PERFMON_HI_BASE_IDX 2 671#define regDC_PERFMON0_PERFMON_LOW 0x0008 672#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 673 674 675// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec 676// base address: 0x30 677#define regDC_PERFMON1_PERFCOUNTER_CNTL 0x000c 678#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 679#define regDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d 680#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 681#define regDC_PERFMON1_PERFCOUNTER_STATE 0x000e 682#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 683#define regDC_PERFMON1_PERFMON_CNTL 0x000f 684#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 685#define regDC_PERFMON1_PERFMON_CNTL2 0x0010 686#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 687#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 688#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 689#define regDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 690#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 691#define regDC_PERFMON1_PERFMON_HI 0x0013 692#define regDC_PERFMON1_PERFMON_HI_BASE_IDX 2 693#define regDC_PERFMON1_PERFMON_LOW 0x0014 694#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 695 696 697// addressBlock: dce_dc_dmu_dmcu_dispdec 698// base address: 0x0 699#define regDMCU_CTRL 0x00da 700#define regDMCU_CTRL_BASE_IDX 2 701#define regDMCU_STATUS 0x00db 702#define regDMCU_STATUS_BASE_IDX 2 703#define regDMCU_PC_START_ADDR 0x00dc 704#define regDMCU_PC_START_ADDR_BASE_IDX 2 705#define regDMCU_FW_START_ADDR 0x00dd 706#define regDMCU_FW_START_ADDR_BASE_IDX 2 707#define regDMCU_FW_END_ADDR 0x00de 708#define regDMCU_FW_END_ADDR_BASE_IDX 2 709#define regDMCU_FW_ISR_START_ADDR 0x00df 710#define regDMCU_FW_ISR_START_ADDR_BASE_IDX 2 711#define regDMCU_FW_CS_HI 0x00e0 712#define regDMCU_FW_CS_HI_BASE_IDX 2 713#define regDMCU_FW_CS_LO 0x00e1 714#define regDMCU_FW_CS_LO_BASE_IDX 2 715#define regDMCU_RAM_ACCESS_CTRL 0x00e2 716#define regDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 717#define regDMCU_ERAM_WR_CTRL 0x00e3 718#define regDMCU_ERAM_WR_CTRL_BASE_IDX 2 719#define regDMCU_ERAM_WR_DATA 0x00e4 720#define regDMCU_ERAM_WR_DATA_BASE_IDX 2 721#define regDMCU_ERAM_RD_CTRL 0x00e5 722#define regDMCU_ERAM_RD_CTRL_BASE_IDX 2 723#define regDMCU_ERAM_RD_DATA 0x00e6 724#define regDMCU_ERAM_RD_DATA_BASE_IDX 2 725#define regDMCU_IRAM_WR_CTRL 0x00e7 726#define regDMCU_IRAM_WR_CTRL_BASE_IDX 2 727#define regDMCU_IRAM_WR_DATA 0x00e8 728#define regDMCU_IRAM_WR_DATA_BASE_IDX 2 729#define regDMCU_IRAM_RD_CTRL 0x00e9 730#define regDMCU_IRAM_RD_CTRL_BASE_IDX 2 731#define regDMCU_IRAM_RD_DATA 0x00ea 732#define regDMCU_IRAM_RD_DATA_BASE_IDX 2 733#define regDMCU_EVENT_TRIGGER 0x00eb 734#define regDMCU_EVENT_TRIGGER_BASE_IDX 2 735#define regDMCU_UC_INTERNAL_INT_STATUS 0x00ec 736#define regDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 737#define regDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed 738#define regDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 739#define regDMCU_INTERRUPT_STATUS 0x00ee 740#define regDMCU_INTERRUPT_STATUS_BASE_IDX 2 741#define regDMCU_INTERRUPT_STATUS_1 0x00ef 742#define regDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 743#define regDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 744#define regDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 745#define regDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 746#define regDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 747#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 748#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 749#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 750#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 751#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 752#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 753#define regDC_DMCU_SCRATCH 0x00f5 754#define regDC_DMCU_SCRATCH_BASE_IDX 2 755#define regDMCU_INT_CNT 0x00f6 756#define regDMCU_INT_CNT_BASE_IDX 2 757#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 758#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 759#define regDMCU_UC_CLK_GATING_CNTL 0x00f8 760#define regDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 761#define regMASTER_COMM_DATA_REG1 0x00f9 762#define regMASTER_COMM_DATA_REG1_BASE_IDX 2 763#define regMASTER_COMM_DATA_REG2 0x00fa 764#define regMASTER_COMM_DATA_REG2_BASE_IDX 2 765#define regMASTER_COMM_DATA_REG3 0x00fb 766#define regMASTER_COMM_DATA_REG3_BASE_IDX 2 767#define regMASTER_COMM_CMD_REG 0x00fc 768#define regMASTER_COMM_CMD_REG_BASE_IDX 2 769#define regMASTER_COMM_CNTL_REG 0x00fd 770#define regMASTER_COMM_CNTL_REG_BASE_IDX 2 771#define regSLAVE_COMM_DATA_REG1 0x00fe 772#define regSLAVE_COMM_DATA_REG1_BASE_IDX 2 773#define regSLAVE_COMM_DATA_REG2 0x00ff 774#define regSLAVE_COMM_DATA_REG2_BASE_IDX 2 775#define regSLAVE_COMM_DATA_REG3 0x0100 776#define regSLAVE_COMM_DATA_REG3_BASE_IDX 2 777#define regSLAVE_COMM_CMD_REG 0x0101 778#define regSLAVE_COMM_CMD_REG_BASE_IDX 2 779#define regSLAVE_COMM_CNTL_REG 0x0102 780#define regSLAVE_COMM_CNTL_REG_BASE_IDX 2 781#define regDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 782#define regDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 783#define regDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 784#define regDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 785#define regDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 786#define regDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 787#define regDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 788#define regDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 789#define regDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 790#define regDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 791#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a 792#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 793#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b 794#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 795#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c 796#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 797#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d 798#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 799#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e 800#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 801#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f 802#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 803#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 804#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 805#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 806#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 807#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 808#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 809#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 810#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 811#define regDMCU_DPRX_INTERRUPT_STATUS1 0x0114 812#define regDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 813#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 814#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 815#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 816#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 817#define regDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 818#define regDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 819#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a 820#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 821#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b 822#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 823#define regDMCU_INT_CNT_CONTINUE 0x011c 824#define regDMCU_INT_CNT_CONTINUE_BASE_IDX 2 825#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d 826#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 827#define regDMCU_INTERRUPT_STATUS_2 0x011e 828#define regDMCU_INTERRUPT_STATUS_2_BASE_IDX 2 829#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f 830#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 831#define regDMCU_INT_CNT_CONT2 0x0120 832#define regDMCU_INT_CNT_CONT2_BASE_IDX 2 833#define regDMCU_INT_CNT_CONT3 0x0121 834#define regDMCU_INT_CNT_CONT3_BASE_IDX 2 835 836 837// addressBlock: dce_dc_dmu_fgsec_dispdec 838// base address: 0x0 839#define regDMCUB_RBBMIF_SEC_CNTL 0x017a 840#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 841 842 843// addressBlock: dce_dc_dmu_rbbmif_dispdec 844// base address: 0x0 845#define regRBBMIF_TIMEOUT 0x017f 846#define regRBBMIF_TIMEOUT_BASE_IDX 2 847#define regRBBMIF_STATUS 0x0180 848#define regRBBMIF_STATUS_BASE_IDX 2 849#define regRBBMIF_STATUS_2 0x0181 850#define regRBBMIF_STATUS_2_BASE_IDX 2 851#define regRBBMIF_INT_STATUS 0x0182 852#define regRBBMIF_INT_STATUS_BASE_IDX 2 853#define regRBBMIF_TIMEOUT_DIS 0x0183 854#define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 855#define regRBBMIF_TIMEOUT_DIS_2 0x0184 856#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 857#define regRBBMIF_STATUS_FLAG 0x0185 858#define regRBBMIF_STATUS_FLAG_BASE_IDX 2 859 860 861// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec 862// base address: 0x2f8 863#define regDC_PERFMON2_PERFCOUNTER_CNTL 0x00be 864#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 865#define regDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf 866#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 867#define regDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 868#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 869#define regDC_PERFMON2_PERFMON_CNTL 0x00c1 870#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 871#define regDC_PERFMON2_PERFMON_CNTL2 0x00c2 872#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 873#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 874#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 875#define regDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 876#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 877#define regDC_PERFMON2_PERFMON_HI 0x00c5 878#define regDC_PERFMON2_PERFMON_HI_BASE_IDX 2 879#define regDC_PERFMON2_PERFMON_LOW 0x00c6 880#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 881 882 883// addressBlock: dce_dc_dmu_ihc_dispdec 884// base address: 0x0 885#define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 886#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 887#define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 888#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 889#define regDC_GPU_TIMER_READ 0x0128 890#define regDC_GPU_TIMER_READ_BASE_IDX 2 891#define regDC_GPU_TIMER_READ_CNTL 0x0129 892#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 893#define regDISP_INTERRUPT_STATUS 0x012a 894#define regDISP_INTERRUPT_STATUS_BASE_IDX 2 895#define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b 896#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 897#define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c 898#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 899#define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d 900#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 901#define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e 902#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 903#define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f 904#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 905#define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 906#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 907#define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 908#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 909#define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 910#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 911#define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 912#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 913#define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 914#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 915#define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 916#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 917#define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 918#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 919#define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 920#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 921#define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 922#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 923#define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 924#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 925#define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a 926#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 927#define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b 928#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 929#define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c 930#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 931#define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d 932#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 933#define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e 934#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 935#define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f 936#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 937#define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 938#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 939#define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 940#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 941#define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 942#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 943#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 944#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 945#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 946#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 947#define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 948#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 949#define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 950#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 951#define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 952#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 953#define regDCCG_INTERRUPT_DEST 0x0148 954#define regDCCG_INTERRUPT_DEST_BASE_IDX 2 955#define regDMU_INTERRUPT_DEST 0x0149 956#define regDMU_INTERRUPT_DEST_BASE_IDX 2 957#define regDMU_INTERRUPT_DEST2 0x014a 958#define regDMU_INTERRUPT_DEST2_BASE_IDX 2 959#define regDCPG_INTERRUPT_DEST 0x014b 960#define regDCPG_INTERRUPT_DEST_BASE_IDX 2 961#define regDCPG_INTERRUPT_DEST2 0x014c 962#define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 963#define regMMHUBBUB_INTERRUPT_DEST 0x014d 964#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 965#define regWB_INTERRUPT_DEST 0x014e 966#define regWB_INTERRUPT_DEST_BASE_IDX 2 967#define regDCHUB_INTERRUPT_DEST 0x014f 968#define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 969#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 970#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 971#define regDCHUB_INTERRUPT_DEST2 0x0151 972#define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 973#define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 974#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 975#define regMPC_INTERRUPT_DEST 0x0153 976#define regMPC_INTERRUPT_DEST_BASE_IDX 2 977#define regOPP_INTERRUPT_DEST 0x0154 978#define regOPP_INTERRUPT_DEST_BASE_IDX 2 979#define regOPTC_INTERRUPT_DEST 0x0155 980#define regOPTC_INTERRUPT_DEST_BASE_IDX 2 981#define regOTG0_INTERRUPT_DEST 0x0156 982#define regOTG0_INTERRUPT_DEST_BASE_IDX 2 983#define regOTG1_INTERRUPT_DEST 0x0157 984#define regOTG1_INTERRUPT_DEST_BASE_IDX 2 985#define regOTG2_INTERRUPT_DEST 0x0158 986#define regOTG2_INTERRUPT_DEST_BASE_IDX 2 987#define regOTG3_INTERRUPT_DEST 0x0159 988#define regOTG3_INTERRUPT_DEST_BASE_IDX 2 989#define regOTG4_INTERRUPT_DEST 0x015a 990#define regOTG4_INTERRUPT_DEST_BASE_IDX 2 991#define regOTG5_INTERRUPT_DEST 0x015b 992#define regOTG5_INTERRUPT_DEST_BASE_IDX 2 993#define regDIG_INTERRUPT_DEST 0x015c 994#define regDIG_INTERRUPT_DEST_BASE_IDX 2 995#define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d 996#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 997#define regDIO_INTERRUPT_DEST 0x015f 998#define regDIO_INTERRUPT_DEST_BASE_IDX 2 999#define regDCIO_INTERRUPT_DEST 0x0160 1000#define regDCIO_INTERRUPT_DEST_BASE_IDX 2 1001#define regHPD_INTERRUPT_DEST 0x0161 1002#define regHPD_INTERRUPT_DEST_BASE_IDX 2 1003#define regAZ_INTERRUPT_DEST 0x0162 1004#define regAZ_INTERRUPT_DEST_BASE_IDX 2 1005#define regAUX_INTERRUPT_DEST 0x0163 1006#define regAUX_INTERRUPT_DEST_BASE_IDX 2 1007#define regDSC_INTERRUPT_DEST 0x0164 1008#define regDSC_INTERRUPT_DEST_BASE_IDX 2 1009#define regHPO_INTERRUPT_DEST 0x0165 1010#define regHPO_INTERRUPT_DEST_BASE_IDX 2 1011 1012 1013// addressBlock: dce_dc_dmu_dmu_misc_dispdec 1014// base address: 0x0 1015#define regCC_DC_PIPE_DIS 0x00ca 1016#define regCC_DC_PIPE_DIS_BASE_IDX 2 1017#define regDMU_CLK_CNTL 0x00cb 1018#define regDMU_CLK_CNTL_BASE_IDX 2 1019#define regDMU_MEM_PWR_CNTL 0x00cc 1020#define regDMU_MEM_PWR_CNTL_BASE_IDX 2 1021#define regDMCU_SMU_INTERRUPT_CNTL 0x00cd 1022#define regDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 1023#define regSMU_INTERRUPT_CONTROL 0x00ce 1024#define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 1025#define regZSC_CNTL 0x00cf 1026#define regZSC_CNTL_BASE_IDX 2 1027#define regZSC_CNTL2 0x00d0 1028#define regZSC_CNTL2_BASE_IDX 2 1029#define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 1030#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 1031#define regZSC_STATUS 0x00d7 1032#define regZSC_STATUS_BASE_IDX 2 1033 1034 1035// addressBlock: dce_dc_dmu_dc_pg_dispdec 1036// base address: 0x0 1037#define regDOMAIN0_PG_CONFIG 0x0080 1038#define regDOMAIN0_PG_CONFIG_BASE_IDX 2 1039#define regDOMAIN0_PG_STATUS 0x0081 1040#define regDOMAIN0_PG_STATUS_BASE_IDX 2 1041#define regDOMAIN1_PG_CONFIG 0x0082 1042#define regDOMAIN1_PG_CONFIG_BASE_IDX 2 1043#define regDOMAIN1_PG_STATUS 0x0083 1044#define regDOMAIN1_PG_STATUS_BASE_IDX 2 1045#define regDOMAIN2_PG_CONFIG 0x0084 1046#define regDOMAIN2_PG_CONFIG_BASE_IDX 2 1047#define regDOMAIN2_PG_STATUS 0x0085 1048#define regDOMAIN2_PG_STATUS_BASE_IDX 2 1049#define regDOMAIN3_PG_CONFIG 0x0086 1050#define regDOMAIN3_PG_CONFIG_BASE_IDX 2 1051#define regDOMAIN3_PG_STATUS 0x0087 1052#define regDOMAIN3_PG_STATUS_BASE_IDX 2 1053#define regDOMAIN16_PG_CONFIG 0x0089 1054#define regDOMAIN16_PG_CONFIG_BASE_IDX 2 1055#define regDOMAIN16_PG_STATUS 0x008a 1056#define regDOMAIN16_PG_STATUS_BASE_IDX 2 1057#define regDOMAIN17_PG_CONFIG 0x008b 1058#define regDOMAIN17_PG_CONFIG_BASE_IDX 2 1059#define regDOMAIN17_PG_STATUS 0x008c 1060#define regDOMAIN17_PG_STATUS_BASE_IDX 2 1061#define regDOMAIN18_PG_CONFIG 0x008d 1062#define regDOMAIN18_PG_CONFIG_BASE_IDX 2 1063#define regDOMAIN18_PG_STATUS 0x008e 1064#define regDOMAIN18_PG_STATUS_BASE_IDX 2 1065#define regDCPG_INTERRUPT_STATUS 0x008f 1066#define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 1067#define regDCPG_INTERRUPT_STATUS_2 0x0090 1068#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 1069#define regDCPG_INTERRUPT_CONTROL_1 0x0091 1070#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 1071#define regDCPG_INTERRUPT_CONTROL_3 0x0092 1072#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 1073#define regDC_IP_REQUEST_CNTL 0x0093 1074#define regDC_IP_REQUEST_CNTL_BASE_IDX 2 1075 1076 1077// addressBlock: dce_dc_dmu_dmcub_dispdec 1078// base address: 0x0 1079#define regDMCUB_REGION0_OFFSET 0x018e 1080#define regDMCUB_REGION0_OFFSET_BASE_IDX 2 1081#define regDMCUB_REGION0_OFFSET_HIGH 0x018f 1082#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 1083#define regDMCUB_REGION1_OFFSET 0x0190 1084#define regDMCUB_REGION1_OFFSET_BASE_IDX 2 1085#define regDMCUB_REGION1_OFFSET_HIGH 0x0191 1086#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 1087#define regDMCUB_REGION2_OFFSET 0x0192 1088#define regDMCUB_REGION2_OFFSET_BASE_IDX 2 1089#define regDMCUB_REGION2_OFFSET_HIGH 0x0193 1090#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 1091#define regDMCUB_REGION4_OFFSET 0x0196 1092#define regDMCUB_REGION4_OFFSET_BASE_IDX 2 1093#define regDMCUB_REGION4_OFFSET_HIGH 0x0197 1094#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 1095#define regDMCUB_REGION5_OFFSET 0x0198 1096#define regDMCUB_REGION5_OFFSET_BASE_IDX 2 1097#define regDMCUB_REGION5_OFFSET_HIGH 0x0199 1098#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 1099#define regDMCUB_REGION6_OFFSET 0x019a 1100#define regDMCUB_REGION6_OFFSET_BASE_IDX 2 1101#define regDMCUB_REGION6_OFFSET_HIGH 0x019b 1102#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 1103#define regDMCUB_REGION7_OFFSET 0x019c 1104#define regDMCUB_REGION7_OFFSET_BASE_IDX 2 1105#define regDMCUB_REGION7_OFFSET_HIGH 0x019d 1106#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 1107#define regDMCUB_REGION0_TOP_ADDRESS 0x019e 1108#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 1109#define regDMCUB_REGION1_TOP_ADDRESS 0x019f 1110#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 1111#define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 1112#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 1113#define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 1114#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 1115#define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 1116#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 1117#define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 1118#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 1119#define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 1120#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 1121#define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 1122#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 1123#define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 1124#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 1125#define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 1126#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 1127#define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 1128#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 1129#define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 1130#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 1131#define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa 1132#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 1133#define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab 1134#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 1135#define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac 1136#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 1137#define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad 1138#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 1139#define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae 1140#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 1141#define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af 1142#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 1143#define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 1144#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 1145#define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 1146#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 1147#define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 1148#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 1149#define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 1150#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 1151#define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 1152#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 1153#define regDMCUB_REGION3_CW0_OFFSET 0x01b5 1154#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 1155#define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 1156#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 1157#define regDMCUB_REGION3_CW1_OFFSET 0x01b7 1158#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 1159#define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 1160#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 1161#define regDMCUB_REGION3_CW2_OFFSET 0x01b9 1162#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 1163#define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba 1164#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 1165#define regDMCUB_REGION3_CW3_OFFSET 0x01bb 1166#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 1167#define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc 1168#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 1169#define regDMCUB_REGION3_CW4_OFFSET 0x01bd 1170#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 1171#define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be 1172#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 1173#define regDMCUB_REGION3_CW5_OFFSET 0x01bf 1174#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 1175#define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 1176#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 1177#define regDMCUB_REGION3_CW6_OFFSET 0x01c1 1178#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 1179#define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 1180#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 1181#define regDMCUB_REGION3_CW7_OFFSET 0x01c3 1182#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 1183#define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 1184#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 1185#define regDMCUB_INTERRUPT_ENABLE 0x01c5 1186#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 1187#define regDMCUB_INTERRUPT_ACK 0x01c6 1188#define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 1189#define regDMCUB_INTERRUPT_STATUS 0x01c7 1190#define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 1191#define regDMCUB_INTERRUPT_TYPE 0x01c8 1192#define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 1193#define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 1194#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 1195#define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca 1196#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 1197#define regDMCUB_EXT_INTERRUPT_ACK 0x01cb 1198#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 1199#define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc 1200#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 1201#define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd 1202#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 1203#define regDMCUB_SEC_CNTL 0x01ce 1204#define regDMCUB_SEC_CNTL_BASE_IDX 2 1205#define regDMCUB_MEM_CNTL 0x01cf 1206#define regDMCUB_MEM_CNTL_BASE_IDX 2 1207#define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 1208#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 1209#define regDMCUB_INBOX0_SIZE 0x01d1 1210#define regDMCUB_INBOX0_SIZE_BASE_IDX 2 1211#define regDMCUB_INBOX0_WPTR 0x01d2 1212#define regDMCUB_INBOX0_WPTR_BASE_IDX 2 1213#define regDMCUB_INBOX0_RPTR 0x01d3 1214#define regDMCUB_INBOX0_RPTR_BASE_IDX 2 1215#define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 1216#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 1217#define regDMCUB_INBOX1_SIZE 0x01d5 1218#define regDMCUB_INBOX1_SIZE_BASE_IDX 2 1219#define regDMCUB_INBOX1_WPTR 0x01d6 1220#define regDMCUB_INBOX1_WPTR_BASE_IDX 2 1221#define regDMCUB_INBOX1_RPTR 0x01d7 1222#define regDMCUB_INBOX1_RPTR_BASE_IDX 2 1223#define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 1224#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 1225#define regDMCUB_OUTBOX0_SIZE 0x01d9 1226#define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 1227#define regDMCUB_OUTBOX0_WPTR 0x01da 1228#define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 1229#define regDMCUB_OUTBOX0_RPTR 0x01db 1230#define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 1231#define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc 1232#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 1233#define regDMCUB_OUTBOX1_SIZE 0x01dd 1234#define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 1235#define regDMCUB_OUTBOX1_WPTR 0x01de 1236#define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 1237#define regDMCUB_OUTBOX1_RPTR 0x01df 1238#define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 1239#define regDMCUB_TIMER_TRIGGER0 0x01e0 1240#define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 1241#define regDMCUB_TIMER_TRIGGER1 0x01e1 1242#define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 1243#define regDMCUB_TIMER_WINDOW 0x01e2 1244#define regDMCUB_TIMER_WINDOW_BASE_IDX 2 1245#define regDMCUB_SCRATCH0 0x01e3 1246#define regDMCUB_SCRATCH0_BASE_IDX 2 1247#define regDMCUB_SCRATCH1 0x01e4 1248#define regDMCUB_SCRATCH1_BASE_IDX 2 1249#define regDMCUB_SCRATCH2 0x01e5 1250#define regDMCUB_SCRATCH2_BASE_IDX 2 1251#define regDMCUB_SCRATCH3 0x01e6 1252#define regDMCUB_SCRATCH3_BASE_IDX 2 1253#define regDMCUB_SCRATCH4 0x01e7 1254#define regDMCUB_SCRATCH4_BASE_IDX 2 1255#define regDMCUB_SCRATCH5 0x01e8 1256#define regDMCUB_SCRATCH5_BASE_IDX 2 1257#define regDMCUB_SCRATCH6 0x01e9 1258#define regDMCUB_SCRATCH6_BASE_IDX 2 1259#define regDMCUB_SCRATCH7 0x01ea 1260#define regDMCUB_SCRATCH7_BASE_IDX 2 1261#define regDMCUB_SCRATCH8 0x01eb 1262#define regDMCUB_SCRATCH8_BASE_IDX 2 1263#define regDMCUB_SCRATCH9 0x01ec 1264#define regDMCUB_SCRATCH9_BASE_IDX 2 1265#define regDMCUB_SCRATCH10 0x01ed 1266#define regDMCUB_SCRATCH10_BASE_IDX 2 1267#define regDMCUB_SCRATCH11 0x01ee 1268#define regDMCUB_SCRATCH11_BASE_IDX 2 1269#define regDMCUB_SCRATCH12 0x01ef 1270#define regDMCUB_SCRATCH12_BASE_IDX 2 1271#define regDMCUB_SCRATCH13 0x01f0 1272#define regDMCUB_SCRATCH13_BASE_IDX 2 1273#define regDMCUB_SCRATCH14 0x01f1 1274#define regDMCUB_SCRATCH14_BASE_IDX 2 1275#define regDMCUB_SCRATCH15 0x01f2 1276#define regDMCUB_SCRATCH15_BASE_IDX 2 1277#define regDMCUB_CNTL 0x01f6 1278#define regDMCUB_CNTL_BASE_IDX 2 1279#define regDMCUB_GPINT_DATAIN0 0x01f7 1280#define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 1281#define regDMCUB_GPINT_DATAIN1 0x01f8 1282#define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 1283#define regDMCUB_GPINT_DATAOUT 0x01f9 1284#define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 1285#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa 1286#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 1287#define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb 1288#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 1289#define regDMCUB_MEM_PWR_CNTL 0x01fc 1290#define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 1291#define regDMCUB_TIMER_CURRENT 0x01fd 1292#define regDMCUB_TIMER_CURRENT_BASE_IDX 2 1293#define regDMCUB_PROC_ID 0x01ff 1294#define regDMCUB_PROC_ID_BASE_IDX 2 1295#define regDMCUB_CNTL2 0x0200 1296#define regDMCUB_CNTL2_BASE_IDX 2 1297 1298 1299// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec 1300// base address: 0x0 1301#define regDWB_ENABLE_CLK_CTRL 0x3228 1302#define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 1303#define regDWB_MEM_PWR_CTRL 0x3229 1304#define regDWB_MEM_PWR_CTRL_BASE_IDX 2 1305#define regFC_MODE_CTRL 0x322a 1306#define regFC_MODE_CTRL_BASE_IDX 2 1307#define regFC_FLOW_CTRL 0x322b 1308#define regFC_FLOW_CTRL_BASE_IDX 2 1309#define regFC_WINDOW_START 0x322c 1310#define regFC_WINDOW_START_BASE_IDX 2 1311#define regFC_WINDOW_SIZE 0x322d 1312#define regFC_WINDOW_SIZE_BASE_IDX 2 1313#define regFC_SOURCE_SIZE 0x322e 1314#define regFC_SOURCE_SIZE_BASE_IDX 2 1315#define regDWB_UPDATE_CTRL 0x322f 1316#define regDWB_UPDATE_CTRL_BASE_IDX 2 1317#define regDWB_CRC_CTRL 0x3230 1318#define regDWB_CRC_CTRL_BASE_IDX 2 1319#define regDWB_CRC_MASK_R_G 0x3231 1320#define regDWB_CRC_MASK_R_G_BASE_IDX 2 1321#define regDWB_CRC_MASK_B_A 0x3232 1322#define regDWB_CRC_MASK_B_A_BASE_IDX 2 1323#define regDWB_CRC_VAL_R_G 0x3233 1324#define regDWB_CRC_VAL_R_G_BASE_IDX 2 1325#define regDWB_CRC_VAL_B_A 0x3234 1326#define regDWB_CRC_VAL_B_A_BASE_IDX 2 1327#define regDWB_OUT_CTRL 0x3235 1328#define regDWB_OUT_CTRL_BASE_IDX 2 1329#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 1330#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 1331#define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 1332#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 1333#define regDWB_HOST_READ_CONTROL 0x3238 1334#define regDWB_HOST_READ_CONTROL_BASE_IDX 2 1335#define regDWB_OVERFLOW_STATUS 0x3239 1336#define regDWB_OVERFLOW_STATUS_BASE_IDX 2 1337#define regDWB_OVERFLOW_COUNTER 0x323a 1338#define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 1339#define regDWB_SOFT_RESET 0x323b 1340#define regDWB_SOFT_RESET_BASE_IDX 2 1341#define regDWB_DEBUG_CTRL 0x323c 1342#define regDWB_DEBUG_CTRL_BASE_IDX 2 1343 1344 1345// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec 1346// base address: 0x0 1347#define regDWB_HDR_MULT_COEF 0x3294 1348#define regDWB_HDR_MULT_COEF_BASE_IDX 2 1349#define regDWB_GAMUT_REMAP_MODE 0x3295 1350#define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 1351#define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 1352#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 1353#define regDWB_GAMUT_REMAPA_C11_C12 0x3297 1354#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 1355#define regDWB_GAMUT_REMAPA_C13_C14 0x3298 1356#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 1357#define regDWB_GAMUT_REMAPA_C21_C22 0x3299 1358#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 1359#define regDWB_GAMUT_REMAPA_C23_C24 0x329a 1360#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 1361#define regDWB_GAMUT_REMAPA_C31_C32 0x329b 1362#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 1363#define regDWB_GAMUT_REMAPA_C33_C34 0x329c 1364#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 1365#define regDWB_GAMUT_REMAPB_C11_C12 0x329d 1366#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 1367#define regDWB_GAMUT_REMAPB_C13_C14 0x329e 1368#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 1369#define regDWB_GAMUT_REMAPB_C21_C22 0x329f 1370#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 1371#define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 1372#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 1373#define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 1374#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 1375#define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 1376#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 1377#define regDWB_OGAM_CONTROL 0x32a3 1378#define regDWB_OGAM_CONTROL_BASE_IDX 2 1379#define regDWB_OGAM_LUT_INDEX 0x32a4 1380#define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 1381#define regDWB_OGAM_LUT_DATA 0x32a5 1382#define regDWB_OGAM_LUT_DATA_BASE_IDX 2 1383#define regDWB_OGAM_LUT_CONTROL 0x32a6 1384#define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 1385#define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 1386#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 1387#define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 1388#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 1389#define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 1390#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 1391#define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa 1392#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 1393#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab 1394#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 1395#define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac 1396#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 1397#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad 1398#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 1399#define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae 1400#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 1401#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af 1402#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 1403#define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 1404#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 1405#define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 1406#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 1407#define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 1408#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 1409#define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 1410#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 1411#define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 1412#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 1413#define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 1414#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 1415#define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 1416#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 1417#define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 1418#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 1419#define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 1420#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 1421#define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 1422#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 1423#define regDWB_OGAM_RAMA_REGION_2_3 0x32ba 1424#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 1425#define regDWB_OGAM_RAMA_REGION_4_5 0x32bb 1426#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 1427#define regDWB_OGAM_RAMA_REGION_6_7 0x32bc 1428#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 1429#define regDWB_OGAM_RAMA_REGION_8_9 0x32bd 1430#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 1431#define regDWB_OGAM_RAMA_REGION_10_11 0x32be 1432#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 1433#define regDWB_OGAM_RAMA_REGION_12_13 0x32bf 1434#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 1435#define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 1436#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 1437#define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 1438#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 1439#define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 1440#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 1441#define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 1442#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 1443#define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 1444#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 1445#define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 1446#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 1447#define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 1448#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 1449#define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 1450#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 1451#define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 1452#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 1453#define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 1454#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 1455#define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca 1456#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 1457#define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb 1458#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 1459#define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc 1460#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 1461#define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd 1462#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 1463#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce 1464#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 1465#define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf 1466#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 1467#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 1468#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 1469#define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 1470#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 1471#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 1472#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 1473#define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 1474#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 1475#define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 1476#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 1477#define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 1478#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 1479#define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 1480#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 1481#define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 1482#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 1483#define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 1484#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 1485#define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 1486#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 1487#define regDWB_OGAM_RAMB_OFFSET_G 0x32da 1488#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 1489#define regDWB_OGAM_RAMB_OFFSET_R 0x32db 1490#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 1491#define regDWB_OGAM_RAMB_REGION_0_1 0x32dc 1492#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 1493#define regDWB_OGAM_RAMB_REGION_2_3 0x32dd 1494#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 1495#define regDWB_OGAM_RAMB_REGION_4_5 0x32de 1496#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 1497#define regDWB_OGAM_RAMB_REGION_6_7 0x32df 1498#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 1499#define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 1500#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 1501#define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 1502#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 1503#define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 1504#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 1505#define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 1506#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 1507#define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 1508#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 1509#define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 1510#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 1511#define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 1512#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 1513#define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 1514#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 1515#define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 1516#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 1517#define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 1518#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 1519#define regDWB_OGAM_RAMB_REGION_28_29 0x32ea 1520#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 1521#define regDWB_OGAM_RAMB_REGION_30_31 0x32eb 1522#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 1523#define regDWB_OGAM_RAMB_REGION_32_33 0x32ec 1524#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 1525 1526 1527// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec 1528// base address: 0xca20 1529#define regDC_PERFMON3_PERFCOUNTER_CNTL 0x3288 1530#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 1531#define regDC_PERFMON3_PERFCOUNTER_CNTL2 0x3289 1532#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 1533#define regDC_PERFMON3_PERFCOUNTER_STATE 0x328a 1534#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 1535#define regDC_PERFMON3_PERFMON_CNTL 0x328b 1536#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 1537#define regDC_PERFMON3_PERFMON_CNTL2 0x328c 1538#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 1539#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x328d 1540#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1541#define regDC_PERFMON3_PERFMON_CVALUE_LOW 0x328e 1542#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 1543#define regDC_PERFMON3_PERFMON_HI 0x328f 1544#define regDC_PERFMON3_PERFMON_HI_BASE_IDX 2 1545#define regDC_PERFMON3_PERFMON_LOW 0x3290 1546#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 1547 1548 1549// addressBlock: dce_dc_mmhubbub_vga_dispdec 1550// base address: 0x0 1551#define regVGA_RENDER_CONTROL 0x0000 1552#define regVGA_RENDER_CONTROL_BASE_IDX 1 1553#define regVGA_SEQUENCER_RESET_CONTROL 0x0001 1554#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 1555#define regVGA_MODE_CONTROL 0x0002 1556#define regVGA_MODE_CONTROL_BASE_IDX 1 1557#define regVGA_SURFACE_PITCH_SELECT 0x0003 1558#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 1559#define regVGA_MEMORY_BASE_ADDRESS 0x0004 1560#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 1561#define regVGA_TEST_DEBUG_INDEX 0x0005 1562#define regVGA_TEST_DEBUG_INDEX_BASE_IDX 1 1563#define regVGA_DISPBUF1_SURFACE_ADDR 0x0006 1564#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 1565#define regVGA_TEST_DEBUG_DATA 0x0007 1566#define regVGA_TEST_DEBUG_DATA_BASE_IDX 1 1567#define regVGA_DISPBUF2_SURFACE_ADDR 0x0008 1568#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 1569#define regVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 1570#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 1571#define regVGA_HDP_CONTROL 0x000a 1572#define regVGA_HDP_CONTROL_BASE_IDX 1 1573#define regVGA_CACHE_CONTROL 0x000b 1574#define regVGA_CACHE_CONTROL_BASE_IDX 1 1575#define regD1VGA_CONTROL 0x000c 1576#define regD1VGA_CONTROL_BASE_IDX 1 1577#define regVGA_SECURITY_LEVEL 0x000d 1578#define regVGA_SECURITY_LEVEL_BASE_IDX 1 1579#define regD2VGA_CONTROL 0x000e 1580#define regD2VGA_CONTROL_BASE_IDX 1 1581#define regVGA_HW_DEBUG 0x000f 1582#define regVGA_HW_DEBUG_BASE_IDX 1 1583#define regVGA_STATUS 0x0010 1584#define regVGA_STATUS_BASE_IDX 1 1585#define regVGA_INTERRUPT_CONTROL 0x0011 1586#define regVGA_INTERRUPT_CONTROL_BASE_IDX 1 1587#define regVGA_STATUS_CLEAR 0x0012 1588#define regVGA_STATUS_CLEAR_BASE_IDX 1 1589#define regVGA_INTERRUPT_STATUS 0x0013 1590#define regVGA_INTERRUPT_STATUS_BASE_IDX 1 1591#define regVGA_MAIN_CONTROL 0x0014 1592#define regVGA_MAIN_CONTROL_BASE_IDX 1 1593#define regVGA_TEST_CONTROL 0x0015 1594#define regVGA_TEST_CONTROL_BASE_IDX 1 1595#define regVGA_DEBUG_READBACK_INDEX 0x0016 1596#define regVGA_DEBUG_READBACK_INDEX_BASE_IDX 1 1597#define regVGA_DEBUG_READBACK_DATA 0x0017 1598#define regVGA_DEBUG_READBACK_DATA_BASE_IDX 1 1599#define regVGA_QOS_CTRL 0x0018 1600#define regVGA_QOS_CTRL_BASE_IDX 1 1601#define regD3VGA_CONTROL 0x0038 1602#define regD3VGA_CONTROL_BASE_IDX 1 1603#define regD4VGA_CONTROL 0x0039 1604#define regD4VGA_CONTROL_BASE_IDX 1 1605#define regD5VGA_CONTROL 0x003a 1606#define regD5VGA_CONTROL_BASE_IDX 1 1607#define regD6VGA_CONTROL 0x003b 1608#define regD6VGA_CONTROL_BASE_IDX 1 1609#define regVGA_SOURCE_SELECT 0x003c 1610#define regVGA_SOURCE_SELECT_BASE_IDX 1 1611 1612 1613// addressBlock: dce_dc_mmhubbub_vgaif_dispdec 1614// base address: 0x0 1615#define regMCIF_CONTROL 0x034a 1616#define regMCIF_CONTROL_BASE_IDX 2 1617#define regMCIF_WRITE_COMBINE_CONTROL 0x034b 1618#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 1619#define regMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e 1620#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1621#define regMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f 1622#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1623#define regMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 1624#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 1625 1626 1627// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec 1628// base address: 0x0 1629#define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 1630#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 1631#define regMCIF_WB_BUFMGR_STATUS 0x0274 1632#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 1633#define regMCIF_WB_BUF_PITCH 0x0275 1634#define regMCIF_WB_BUF_PITCH_BASE_IDX 2 1635#define regMCIF_WB_BUF_1_STATUS 0x0276 1636#define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 1637#define regMCIF_WB_BUF_1_STATUS2 0x0277 1638#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 1639#define regMCIF_WB_BUF_2_STATUS 0x0278 1640#define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 1641#define regMCIF_WB_BUF_2_STATUS2 0x0279 1642#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 1643#define regMCIF_WB_BUF_3_STATUS 0x027a 1644#define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 1645#define regMCIF_WB_BUF_3_STATUS2 0x027b 1646#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 1647#define regMCIF_WB_BUF_4_STATUS 0x027c 1648#define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 1649#define regMCIF_WB_BUF_4_STATUS2 0x027d 1650#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 1651#define regMCIF_WB_ARBITRATION_CONTROL 0x027e 1652#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 1653#define regMCIF_WB_SCLK_CHANGE 0x027f 1654#define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 1655#define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 1656#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 1657#define regMCIF_WB_TEST_DEBUG_DATA 0x0281 1658#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 1659#define regMCIF_WB_BUF_1_ADDR_Y 0x0282 1660#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 1661#define regMCIF_WB_BUF_1_ADDR_C 0x0284 1662#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 1663#define regMCIF_WB_BUF_2_ADDR_Y 0x0286 1664#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 1665#define regMCIF_WB_BUF_2_ADDR_C 0x0288 1666#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 1667#define regMCIF_WB_BUF_3_ADDR_Y 0x028a 1668#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 1669#define regMCIF_WB_BUF_3_ADDR_C 0x028c 1670#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 1671#define regMCIF_WB_BUF_4_ADDR_Y 0x028e 1672#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 1673#define regMCIF_WB_BUF_4_ADDR_C 0x0290 1674#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 1675#define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 1676#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 1677#define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 1678#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 1679#define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 1680#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 1681#define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 1682#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 1683#define regMULTI_LEVEL_QOS_CTRL 0x0297 1684#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 1685#define regMCIF_WB_BUF_LUMA_SIZE 0x0299 1686#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 1687#define regMCIF_WB_BUF_CHROMA_SIZE 0x029a 1688#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 1689#define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b 1690#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 1691#define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c 1692#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 1693#define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d 1694#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 1695#define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e 1696#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 1697#define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f 1698#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 1699#define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 1700#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 1701#define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 1702#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 1703#define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 1704#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 1705#define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 1706#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 1707#define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 1708#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 1709#define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 1710#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 1711#define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 1712#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 1713#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7 1714#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2 1715#define regMCIF_WB_VMID_CONTROL 0x02a8 1716#define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 1717#define regMCIF_WB_MIN_TTO 0x02a9 1718#define regMCIF_WB_MIN_TTO_BASE_IDX 2 1719 1720 1721// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec 1722// base address: 0xd48 1723#define regDC_PERFMON4_PERFCOUNTER_CNTL 0x0352 1724#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 1725#define regDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353 1726#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 1727#define regDC_PERFMON4_PERFCOUNTER_STATE 0x0354 1728#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 1729#define regDC_PERFMON4_PERFMON_CNTL 0x0355 1730#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 1731#define regDC_PERFMON4_PERFMON_CNTL2 0x0356 1732#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 1733#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357 1734#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1735#define regDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358 1736#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 1737#define regDC_PERFMON4_PERFMON_HI 0x0359 1738#define regDC_PERFMON4_PERFMON_HI_BASE_IDX 2 1739#define regDC_PERFMON4_PERFMON_LOW 0x035a 1740#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 1741 1742 1743// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec 1744// base address: 0x0 1745#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa 1746#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 1747#define regMCIF_WB_WATERMARK 0x02ab 1748#define regMCIF_WB_WATERMARK_BASE_IDX 2 1749#define regMMHUBBUB_WARMUP_CONFIG 0x02ac 1750#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 1751#define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad 1752#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 1753#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae 1754#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 1755#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af 1756#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 1757#define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 1758#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 1759#define regMMHUBBUB_MIN_TTO 0x02b1 1760#define regMMHUBBUB_MIN_TTO_BASE_IDX 2 1761#define regMMHUBBUB_CTRL 0x0333 1762#define regMMHUBBUB_CTRL_BASE_IDX 2 1763#define regWBIF_SMU_WM_CONTROL 0x0334 1764#define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 1765#define regWBIF0_MISC_CTRL 0x0335 1766#define regWBIF0_MISC_CTRL_BASE_IDX 2 1767#define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 1768#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1769#define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 1770#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1771#define regVGA_SRC_SPLIT_CNTL 0x033e 1772#define regVGA_SRC_SPLIT_CNTL_BASE_IDX 2 1773#define regMMHUBBUB_MEM_PWR_STATUS 0x033f 1774#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 1775#define regMMHUBBUB_MEM_PWR_CNTL 0x0340 1776#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 1777#define regMMHUBBUB_CLOCK_CNTL 0x0341 1778#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 1779#define regMMHUBBUB_SOFT_RESET 0x0342 1780#define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 1781#define regDMU_IF_ERR_STATUS 0x0346 1782#define regDMU_IF_ERR_STATUS_BASE_IDX 2 1783#define regMMHUBBUB_CLIENT_UNIT_ID 0x0347 1784#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 1785#define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0349 1786#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 1787 1788 1789// addressBlock: dce_dc_hda_azf0controller_dispdec 1790// base address: 0x0 1791#define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 1792#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 1793#define regAZALIA_AUDIO_DTO 0x03c3 1794#define regAZALIA_AUDIO_DTO_BASE_IDX 2 1795#define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 1796#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 1797#define regAZALIA_SOCCLK_CONTROL 0x03c5 1798#define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 1799#define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 1800#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 1801#define regAZALIA_DATA_DMA_CONTROL 0x03c7 1802#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 1803#define regAZALIA_BDL_DMA_CONTROL 0x03c8 1804#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 1805#define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 1806#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 1807#define regAZALIA_CORB_DMA_CONTROL 0x03ca 1808#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 1809#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 1810#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 1811#define regAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 1812#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 1813#define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 1814#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 1815#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 1816#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1817#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 1818#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 1819#define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 1820#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1821#define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 1822#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 1823#define regAZALIA_INPUT_CRC0_CONTROL1 0x03da 1824#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 1825#define regAZALIA_INPUT_CRC0_CONTROL2 0x03db 1826#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 1827#define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc 1828#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 1829#define regAZALIA_INPUT_CRC0_RESULT 0x03dd 1830#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 1831#define regAZALIA_INPUT_CRC1_CONTROL0 0x03de 1832#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 1833#define regAZALIA_INPUT_CRC1_CONTROL1 0x03df 1834#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 1835#define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 1836#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 1837#define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 1838#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 1839#define regAZALIA_INPUT_CRC1_RESULT 0x03e2 1840#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 1841#define regAZALIA_CRC0_CONTROL0 0x03e3 1842#define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 1843#define regAZALIA_CRC0_CONTROL1 0x03e4 1844#define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 1845#define regAZALIA_CRC0_CONTROL2 0x03e5 1846#define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 1847#define regAZALIA_CRC0_CONTROL3 0x03e6 1848#define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 1849#define regAZALIA_CRC0_RESULT 0x03e7 1850#define regAZALIA_CRC0_RESULT_BASE_IDX 2 1851#define regAZALIA_CRC1_CONTROL0 0x03e8 1852#define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 1853#define regAZALIA_CRC1_CONTROL1 0x03e9 1854#define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 1855#define regAZALIA_CRC1_CONTROL2 0x03ea 1856#define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 1857#define regAZALIA_CRC1_CONTROL3 0x03eb 1858#define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 1859#define regAZALIA_CRC1_RESULT 0x03ec 1860#define regAZALIA_CRC1_RESULT_BASE_IDX 2 1861#define regAZALIA_MEM_PWR_CTRL 0x03ee 1862#define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 1863#define regAZALIA_MEM_PWR_STATUS 0x03ef 1864#define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 1865 1866 1867// addressBlock: dce_dc_hda_azf0root_dispdec 1868// base address: 0x0 1869#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 1870#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 1871#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 1872#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 1873#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 1874#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 1875#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 1876#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 1877#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 1878#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 1879#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 1880#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 1881#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 1882#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 1883#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 1884#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 1885#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 1886#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 1887#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 1888#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 1889#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 1890#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 1891#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 1892#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 1893#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 1894#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1895#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 1896#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1897#define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 1898#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 1899#define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 1900#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 1901#define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 1902#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 1903#define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 1904#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 1905#define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 1906#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 1907#define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a 1908#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 1909#define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b 1910#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 1911#define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 1912#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1913#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 1914#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1915 1916 1917// addressBlock: dce_dc_hda_az_misc_dispdec 1918// base address: 0x0 1919#define regAZ_CLOCK_CNTL 0x0372 1920#define regAZ_CLOCK_CNTL_BASE_IDX 2 1921 1922 1923// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec 1924// base address: 0xde8 1925#define regDC_PERFMON5_PERFCOUNTER_CNTL 0x037a 1926#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 1927#define regDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b 1928#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 1929#define regDC_PERFMON5_PERFCOUNTER_STATE 0x037c 1930#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 1931#define regDC_PERFMON5_PERFMON_CNTL 0x037d 1932#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 1933#define regDC_PERFMON5_PERFMON_CNTL2 0x037e 1934#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 1935#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f 1936#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1937#define regDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380 1938#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 1939#define regDC_PERFMON5_PERFMON_HI 0x0381 1940#define regDC_PERFMON5_PERFMON_HI_BASE_IDX 2 1941#define regDC_PERFMON5_PERFMON_LOW 0x0382 1942#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 1943 1944 1945// addressBlock: dce_dc_hda_azf0stream0_dispdec 1946// base address: 0x0 1947#define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 1948#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 1949#define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 1950#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 1951 1952 1953// addressBlock: dce_dc_hda_azf0stream1_dispdec 1954// base address: 0x8 1955#define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 1956#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 1957#define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 1958#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 1959 1960 1961// addressBlock: dce_dc_hda_azf0stream2_dispdec 1962// base address: 0x10 1963#define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 1964#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 1965#define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 1966#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 1967 1968 1969// addressBlock: dce_dc_hda_azf0stream3_dispdec 1970// base address: 0x18 1971#define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 1972#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 1973#define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 1974#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 1975 1976 1977// addressBlock: dce_dc_hda_azf0stream4_dispdec 1978// base address: 0x20 1979#define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 1980#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 1981#define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 1982#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 1983 1984 1985// addressBlock: dce_dc_hda_azf0stream5_dispdec 1986// base address: 0x28 1987#define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 1988#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 1989#define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 1990#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 1991 1992 1993// addressBlock: dce_dc_hda_azf0stream6_dispdec 1994// base address: 0x30 1995#define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 1996#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 1997#define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 1998#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 1999 2000 2001// addressBlock: dce_dc_hda_azf0stream7_dispdec 2002// base address: 0x38 2003#define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 2004#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 2005#define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 2006#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 2007 2008 2009// addressBlock: dce_dc_hda_azf0stream8_dispdec 2010// base address: 0x320 2011#define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 2012#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 2013#define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 2014#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 2015 2016 2017// addressBlock: dce_dc_hda_azf0stream9_dispdec 2018// base address: 0x328 2019#define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 2020#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 2021#define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 2022#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 2023 2024 2025// addressBlock: dce_dc_hda_azf0stream10_dispdec 2026// base address: 0x330 2027#define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 2028#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 2029#define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 2030#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 2031 2032 2033// addressBlock: dce_dc_hda_azf0stream11_dispdec 2034// base address: 0x338 2035#define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 2036#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 2037#define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 2038#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 2039 2040 2041// addressBlock: dce_dc_hda_azf0stream12_dispdec 2042// base address: 0x340 2043#define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 2044#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 2045#define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 2046#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 2047 2048 2049// addressBlock: dce_dc_hda_azf0stream13_dispdec 2050// base address: 0x348 2051#define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 2052#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 2053#define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 2054#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 2055 2056 2057// addressBlock: dce_dc_hda_azf0stream14_dispdec 2058// base address: 0x350 2059#define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 2060#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 2061#define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 2062#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 2063 2064 2065// addressBlock: dce_dc_hda_azf0stream15_dispdec 2066// base address: 0x358 2067#define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 2068#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 2069#define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 2070#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 2071 2072 2073// addressBlock: dce_dc_hda_azf0endpoint0_dispdec 2074// base address: 0x0 2075#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 2076#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2077#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 2078#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2079 2080 2081// addressBlock: dce_dc_hda_azf0endpoint1_dispdec 2082// base address: 0x18 2083#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 2084#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2085#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 2086#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2087 2088 2089// addressBlock: dce_dc_hda_azf0endpoint2_dispdec 2090// base address: 0x30 2091#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 2092#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2093#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 2094#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2095 2096 2097// addressBlock: dce_dc_hda_azf0endpoint3_dispdec 2098// base address: 0x48 2099#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 2100#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2101#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 2102#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2103 2104 2105// addressBlock: dce_dc_hda_azf0endpoint4_dispdec 2106// base address: 0x60 2107#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 2108#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2109#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 2110#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2111 2112 2113// addressBlock: dce_dc_hda_azf0endpoint5_dispdec 2114// base address: 0x78 2115#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 2116#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2117#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 2118#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2119 2120 2121// addressBlock: dce_dc_hda_azf0endpoint6_dispdec 2122// base address: 0x90 2123#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 2124#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2125#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 2126#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2127 2128 2129// addressBlock: dce_dc_hda_azf0endpoint7_dispdec 2130// base address: 0xa8 2131#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 2132#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2133#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 2134#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2135 2136 2137// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec 2138// base address: 0x0 2139#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 2140#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2141#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 2142#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2143 2144 2145// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec 2146// base address: 0x10 2147#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 2148#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2149#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 2150#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2151 2152 2153// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec 2154// base address: 0x20 2155#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 2156#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2157#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 2158#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2159 2160 2161// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec 2162// base address: 0x30 2163#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 2164#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2165#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 2166#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2167 2168 2169// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec 2170// base address: 0x40 2171#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 2172#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2173#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 2174#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2175 2176 2177// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec 2178// base address: 0x50 2179#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 2180#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2181#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 2182#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2183 2184 2185// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec 2186// base address: 0x60 2187#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 2188#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2189#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 2190#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2191 2192 2193// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec 2194// base address: 0x70 2195#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 2196#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2197#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 2198#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2199 2200 2201// addressBlock: dce_dc_dchubbubl_hubbub_dispdec 2202// base address: 0x0 2203#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 2204#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 2205#define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa 2206#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 2207#define regDCHUBBUB_ARB_QOS_FORCE 0x04fb 2208#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 2209#define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc 2210#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 2211#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fd 2212#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 2213#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x04fe 2214#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 2215#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x04ff 2216#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 2217#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0x0500 2218#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX 2 2219#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0501 2220#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 2221#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0x0502 2222#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX 2 2223#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x0503 2224#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 2225#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0504 2226#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 2227#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0505 2228#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 2229#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0506 2230#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 2231#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0507 2232#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 2233#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0508 2234#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 2235#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0x0509 2236#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX 2 2237#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050a 2238#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 2239#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0x050b 2240#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX 2 2241#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x050c 2242#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 2243#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x050d 2244#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 2245#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x050e 2246#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 2247#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x050f 2248#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 2249#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0510 2250#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 2251#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0511 2252#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 2253#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0x0512 2254#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX 2 2255#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0513 2256#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 2257#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0x0514 2258#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX 2 2259#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0515 2260#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 2261#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0516 2262#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 2263#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0517 2264#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 2265#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 2266#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 2267#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 2268#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 2269#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a 2270#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 2271#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0x051b 2272#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX 2 2273#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051c 2274#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 2275#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0x051d 2276#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX 2 2277#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051e 2278#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 2279#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x051f 2280#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 2281#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0520 2282#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 2283#define regDCHUBBUB_ARB_HOSTVM_CNTL 0x0521 2284#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 2285#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0522 2286#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 2287#define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0523 2288#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 2289#define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0524 2290#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 2291#define regSURFACE_CHECK0_ADDRESS_LSB 0x0525 2292#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 2293#define regSURFACE_CHECK0_ADDRESS_MSB 0x0526 2294#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 2295#define regSURFACE_CHECK1_ADDRESS_LSB 0x0527 2296#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 2297#define regSURFACE_CHECK1_ADDRESS_MSB 0x0528 2298#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 2299#define regSURFACE_CHECK2_ADDRESS_LSB 0x0529 2300#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 2301#define regSURFACE_CHECK2_ADDRESS_MSB 0x052a 2302#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 2303#define regSURFACE_CHECK3_ADDRESS_LSB 0x052b 2304#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 2305#define regSURFACE_CHECK3_ADDRESS_MSB 0x052c 2306#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 2307#define regVTG0_CONTROL 0x052d 2308#define regVTG0_CONTROL_BASE_IDX 2 2309#define regVTG1_CONTROL 0x052e 2310#define regVTG1_CONTROL_BASE_IDX 2 2311#define regVTG2_CONTROL 0x052f 2312#define regVTG2_CONTROL_BASE_IDX 2 2313#define regVTG3_CONTROL 0x0530 2314#define regVTG3_CONTROL_BASE_IDX 2 2315#define regDCHUBBUB_SOFT_RESET 0x0531 2316#define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 2317#define regDCHUBBUB_CLOCK_CNTL 0x0532 2318#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 2319#define regDCFCLK_CNTL 0x0533 2320#define regDCFCLK_CNTL_BASE_IDX 2 2321#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0534 2322#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 2323#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0535 2324#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 2325#define regDCHUBBUB_VLINE_SNAPSHOT 0x0536 2326#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 2327#define regDCHUBBUB_CTRL_STATUS 0x0537 2328#define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 2329#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053d 2330#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 2331#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053e 2332#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 2333#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053f 2334#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 2335#define regFMON_CTRL 0x0540 2336#define regFMON_CTRL_BASE_IDX 2 2337#define regDCHUBBUB_TEST_DEBUG_INDEX 0x0541 2338#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 2339#define regDCHUBBUB_TEST_DEBUG_DATA 0x0542 2340#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 2341 2342 2343// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec 2344// base address: 0x0 2345#define regDCHUBBUB_SDPIF_CFG0 0x046f 2346#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 2347#define regDCHUBBUB_SDPIF_CFG1 0x0470 2348#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 2349#define regDCHUBBUB_SDPIF_CFG2 0x0471 2350#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 2351#define regVM_REQUEST_PHYSICAL 0x0472 2352#define regVM_REQUEST_PHYSICAL_BASE_IDX 2 2353#define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 2354#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 2355#define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 2356#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 2357#define regDCN_VM_FB_LOCATION_BASE 0x0475 2358#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 2359#define regDCN_VM_FB_LOCATION_TOP 0x0476 2360#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 2361#define regDCN_VM_FB_OFFSET 0x0477 2362#define regDCN_VM_FB_OFFSET_BASE_IDX 2 2363#define regDCN_VM_AGP_BOT 0x0478 2364#define regDCN_VM_AGP_BOT_BASE_IDX 2 2365#define regDCN_VM_AGP_TOP 0x0479 2366#define regDCN_VM_AGP_TOP_BASE_IDX 2 2367#define regDCN_VM_AGP_BASE 0x047a 2368#define regDCN_VM_AGP_BASE_BASE_IDX 2 2369#define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b 2370#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 2371#define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c 2372#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 2373#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d 2374#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 2375#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x047e 2376#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 2377#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x047f 2378#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 2379#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0483 2380#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 2381#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0484 2382#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 2383 2384 2385// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec 2386// base address: 0x0 2387#define regDCHUBBUB_RET_PATH_DCC_CFG 0x04af 2388#define regDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 2389#define regDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04b0 2390#define regDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 2391#define regDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04b1 2392#define regDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 2393#define regDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04b2 2394#define regDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 2395#define regDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04b3 2396#define regDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 2397#define regDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04b4 2398#define regDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 2399#define regDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04b5 2400#define regDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 2401#define regDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04b6 2402#define regDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 2403#define regDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04b7 2404#define regDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 2405#define regDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04b8 2406#define regDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 2407#define regDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04b9 2408#define regDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 2409#define regDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04ba 2410#define regDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 2411#define regDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04bb 2412#define regDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 2413#define regDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04bc 2414#define regDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 2415#define regDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04bd 2416#define regDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 2417#define regDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04be 2418#define regDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 2419#define regDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04bf 2420#define regDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 2421#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04c0 2422#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 2423#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04c1 2424#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 2425#define regDCHUBBUB_CRC_CTRL 0x04c2 2426#define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 2427#define regDCHUBBUB_CRC0_VAL_R_G 0x04c3 2428#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 2429#define regDCHUBBUB_CRC0_VAL_B_A 0x04c4 2430#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 2431#define regDCHUBBUB_CRC1_VAL_R_G 0x04c5 2432#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 2433#define regDCHUBBUB_CRC1_VAL_B_A 0x04c6 2434#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 2435#define regDCHUBBUB_DCC_STAT_CNTL 0x04c7 2436#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 2437#define regDCHUBBUB_DCC_STAT0 0x04c8 2438#define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 2439#define regDCHUBBUB_DCC_STAT1 0x04c9 2440#define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 2441#define regDCHUBBUB_DCC_STAT2 0x04ca 2442#define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 2443#define regDCHUBBUB_COMPBUF_CTRL 0x04cb 2444#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 2445#define regDCHUBBUB_DET0_CTRL 0x04cc 2446#define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 2447#define regDCHUBBUB_DET1_CTRL 0x04cd 2448#define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 2449#define regDCHUBBUB_DET2_CTRL 0x04ce 2450#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 2451#define regDCHUBBUB_DET3_CTRL 0x04cf 2452#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 2453#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04d1 2454#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 2455#define regCOMPBUF_MEM_PWR_CTRL_1 0x04d2 2456#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 2457#define regCOMPBUF_MEM_PWR_CTRL_2 0x04d3 2458#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 2459#define regDCHUBBUB_MEM_PWR_STATUS 0x04d4 2460#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 2461#define regCOMPBUF_RESERVED_SPACE 0x04d5 2462#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 2463 2464 2465// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec 2466// base address: 0x0 2467#define regDCN_VM_CONTEXT0_CNTL 0x0559 2468#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 2469#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a 2470#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2471#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b 2472#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2473#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c 2474#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2475#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d 2476#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2477#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e 2478#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2479#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f 2480#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2481#define regDCN_VM_CONTEXT1_CNTL 0x0560 2482#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 2483#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 2484#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2485#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 2486#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2487#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 2488#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2489#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 2490#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2491#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 2492#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2493#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 2494#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2495#define regDCN_VM_CONTEXT2_CNTL 0x0567 2496#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 2497#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 2498#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2499#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 2500#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2501#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a 2502#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2503#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b 2504#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2505#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c 2506#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2507#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d 2508#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2509#define regDCN_VM_CONTEXT3_CNTL 0x056e 2510#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 2511#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f 2512#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2513#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 2514#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2515#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 2516#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2517#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 2518#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2519#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 2520#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2521#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 2522#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2523#define regDCN_VM_CONTEXT4_CNTL 0x0575 2524#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 2525#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 2526#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2527#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 2528#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2529#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 2530#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2531#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 2532#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2533#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a 2534#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2535#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b 2536#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2537#define regDCN_VM_CONTEXT5_CNTL 0x057c 2538#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 2539#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d 2540#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2541#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e 2542#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2543#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f 2544#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2545#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 2546#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2547#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 2548#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2549#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 2550#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2551#define regDCN_VM_CONTEXT6_CNTL 0x0583 2552#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 2553#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 2554#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2555#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 2556#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2557#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 2558#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2559#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 2560#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2561#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 2562#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2563#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 2564#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2565#define regDCN_VM_CONTEXT7_CNTL 0x058a 2566#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 2567#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b 2568#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2569#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c 2570#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2571#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d 2572#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2573#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e 2574#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2575#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f 2576#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2577#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 2578#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2579#define regDCN_VM_CONTEXT8_CNTL 0x0591 2580#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 2581#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 2582#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2583#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 2584#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2585#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 2586#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2587#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 2588#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2589#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 2590#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2591#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 2592#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2593#define regDCN_VM_CONTEXT9_CNTL 0x0598 2594#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 2595#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 2596#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2597#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a 2598#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2599#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b 2600#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2601#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c 2602#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2603#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d 2604#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2605#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e 2606#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2607#define regDCN_VM_CONTEXT10_CNTL 0x059f 2608#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 2609#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 2610#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2611#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 2612#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2613#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 2614#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2615#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 2616#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2617#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 2618#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2619#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 2620#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2621#define regDCN_VM_CONTEXT11_CNTL 0x05a6 2622#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 2623#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 2624#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2625#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 2626#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2627#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 2628#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2629#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa 2630#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2631#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab 2632#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2633#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac 2634#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2635#define regDCN_VM_CONTEXT12_CNTL 0x05ad 2636#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 2637#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae 2638#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2639#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af 2640#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2641#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 2642#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2643#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 2644#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2645#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 2646#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2647#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 2648#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2649#define regDCN_VM_CONTEXT13_CNTL 0x05b4 2650#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 2651#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 2652#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2653#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 2654#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2655#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 2656#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2657#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 2658#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2659#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 2660#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2661#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba 2662#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2663#define regDCN_VM_CONTEXT14_CNTL 0x05bb 2664#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 2665#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc 2666#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2667#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd 2668#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2669#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be 2670#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2671#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf 2672#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2673#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 2674#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2675#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 2676#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2677#define regDCN_VM_CONTEXT15_CNTL 0x05c2 2678#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 2679#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 2680#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2681#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 2682#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2683#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 2684#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2685#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 2686#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2687#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 2688#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2689#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 2690#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2691#define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 2692#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 2693#define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca 2694#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 2695#define regDCN_VM_FAULT_CNTL 0x05cb 2696#define regDCN_VM_FAULT_CNTL_BASE_IDX 2 2697#define regDCN_VM_FAULT_STATUS 0x05cc 2698#define regDCN_VM_FAULT_STATUS_BASE_IDX 2 2699#define regDCN_VM_FAULT_ADDR_MSB 0x05cd 2700#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 2701#define regDCN_VM_FAULT_ADDR_LSB 0x05ce 2702#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 2703 2704 2705// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec 2706// base address: 0x1534 2707#define regDC_PERFMON6_PERFCOUNTER_CNTL 0x054d 2708#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 2709#define regDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e 2710#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 2711#define regDC_PERFMON6_PERFCOUNTER_STATE 0x054f 2712#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 2713#define regDC_PERFMON6_PERFMON_CNTL 0x0550 2714#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 2715#define regDC_PERFMON6_PERFMON_CNTL2 0x0551 2716#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 2717#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552 2718#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2719#define regDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553 2720#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 2721#define regDC_PERFMON6_PERFMON_HI 0x0554 2722#define regDC_PERFMON6_PERFMON_HI_BASE_IDX 2 2723#define regDC_PERFMON6_PERFMON_LOW 0x0555 2724#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 2725 2726 2727// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec 2728// base address: 0x0 2729#define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 2730#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2731#define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 2732#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 2733#define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 2734#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 2735#define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 2736#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2737#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea 2738#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2739#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb 2740#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2741#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec 2742#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2743#define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed 2744#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2745#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee 2746#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2747#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef 2748#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2749#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 2750#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2751#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 2752#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2753#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 2754#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2755#define regHUBP0_DCHUBP_CNTL 0x05f3 2756#define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 2757#define regHUBP0_HUBP_CLK_CNTL 0x05f4 2758#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 2759#define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 2760#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2761#define regHUBP0_HUBPREQ_DEBUG_DB 0x05f6 2762#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 2763#define regHUBP0_HUBPREQ_DEBUG 0x05f7 2764#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 2765#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb 2766#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2767#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc 2768#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2769 2770 2771// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 2772// base address: 0x0 2773#define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 2774#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 2775#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 2776#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2777#define regHUBPREQ0_VMID_SETTINGS_0 0x0609 2778#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 2779#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 2780#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2781#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 2782#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2783#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 2784#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2785#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 2786#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2787#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 2788#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2789#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 2790#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2791#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 2792#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2793#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 2794#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2795#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 2796#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2797#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 2798#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2799#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 2800#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2801#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 2802#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2803#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 2804#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2805#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 2806#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2807#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 2808#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2809#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 2810#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2811#define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a 2812#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2813#define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b 2814#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 2815#define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c 2816#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2817#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 2818#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2819#define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 2820#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 2821#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 2822#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2823#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 2824#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2825#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 2826#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2827#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 2828#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2829#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 2830#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2831#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 2832#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2833#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 2834#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2835#define regHUBPREQ0_DCN_EXPANSION_MODE 0x0629 2836#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 2837#define regHUBPREQ0_DCN_TTU_QOS_WM 0x062a 2838#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 2839#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b 2840#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2841#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c 2842#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2843#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d 2844#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2845#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e 2846#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2847#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f 2848#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2849#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630 2850#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2851#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631 2852#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2853#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632 2854#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2855#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633 2856#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2857#define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634 2858#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2859#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635 2860#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2861#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636 2862#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2863#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643 2864#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2865#define regHUBPREQ0_BLANK_OFFSET_0 0x0644 2866#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 2867#define regHUBPREQ0_BLANK_OFFSET_1 0x0645 2868#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 2869#define regHUBPREQ0_DST_DIMENSIONS 0x0646 2870#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 2871#define regHUBPREQ0_DST_AFTER_SCALER 0x0647 2872#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 2873#define regHUBPREQ0_PREFETCH_SETTINGS 0x0648 2874#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 2875#define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0649 2876#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 2877#define regHUBPREQ0_VBLANK_PARAMETERS_0 0x064a 2878#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 2879#define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064b 2880#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 2881#define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064c 2882#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 2883#define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064d 2884#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 2885#define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064e 2886#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 2887#define regHUBPREQ0_FLIP_PARAMETERS_0 0x064f 2888#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 2889#define regHUBPREQ0_FLIP_PARAMETERS_1 0x0650 2890#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 2891#define regHUBPREQ0_FLIP_PARAMETERS_2 0x0651 2892#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 2893#define regHUBPREQ0_NOM_PARAMETERS_0 0x0652 2894#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 2895#define regHUBPREQ0_NOM_PARAMETERS_1 0x0653 2896#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 2897#define regHUBPREQ0_NOM_PARAMETERS_2 0x0654 2898#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 2899#define regHUBPREQ0_NOM_PARAMETERS_3 0x0655 2900#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 2901#define regHUBPREQ0_NOM_PARAMETERS_4 0x0656 2902#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 2903#define regHUBPREQ0_NOM_PARAMETERS_5 0x0657 2904#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 2905#define regHUBPREQ0_NOM_PARAMETERS_6 0x0658 2906#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 2907#define regHUBPREQ0_NOM_PARAMETERS_7 0x0659 2908#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 2909#define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a 2910#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2911#define regHUBPREQ0_PER_LINE_DELIVERY 0x065b 2912#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 2913#define regHUBPREQ0_CURSOR_SETTINGS 0x065c 2914#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 2915#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d 2916#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2917#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e 2918#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2919#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f 2920#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2921#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660 2922#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2923#define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0663 2924#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 2925#define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0664 2926#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 2927#define regHUBPREQ0_FLIP_PARAMETERS_3 0x0665 2928#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 2929#define regHUBPREQ0_FLIP_PARAMETERS_4 0x0666 2930#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 2931#define regHUBPREQ0_FLIP_PARAMETERS_5 0x0667 2932#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 2933#define regHUBPREQ0_FLIP_PARAMETERS_6 0x0668 2934#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 2935 2936 2937// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec 2938// base address: 0x0 2939#define regHUBPRET0_HUBPRET_CONTROL 0x066c 2940#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 2941#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d 2942#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2943#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e 2944#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2945#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f 2946#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2947#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 2948#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2949#define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 2950#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 2951#define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 2952#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 2953#define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 2954#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 2955#define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 2956#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2957#define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 2958#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2959 2960 2961// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec 2962// base address: 0x0 2963#define regCURSOR0_0_CURSOR_CONTROL 0x0678 2964#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 2965#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 2966#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2967#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a 2968#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2969#define regCURSOR0_0_CURSOR_SIZE 0x067b 2970#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 2971#define regCURSOR0_0_CURSOR_POSITION 0x067c 2972#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 2973#define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d 2974#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 2975#define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e 2976#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 2977#define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f 2978#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 2979#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 2980#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2981#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 2982#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2983#define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 2984#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2985#define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 2986#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 2987#define regCURSOR0_0_DMDATA_CNTL 0x0684 2988#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 2989#define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 2990#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 2991#define regCURSOR0_0_DMDATA_STATUS 0x0686 2992#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 2993#define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 2994#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 2995#define regCURSOR0_0_DMDATA_SW_DATA 0x0688 2996#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 2997 2998 2999// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3000// base address: 0x1a74 3001#define regDC_PERFMON7_PERFCOUNTER_CNTL 0x069d 3002#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 3003#define regDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e 3004#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 3005#define regDC_PERFMON7_PERFCOUNTER_STATE 0x069f 3006#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 3007#define regDC_PERFMON7_PERFMON_CNTL 0x06a0 3008#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 3009#define regDC_PERFMON7_PERFMON_CNTL2 0x06a1 3010#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 3011#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2 3012#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3013#define regDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3 3014#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 3015#define regDC_PERFMON7_PERFMON_HI 0x06a4 3016#define regDC_PERFMON7_PERFMON_HI_BASE_IDX 2 3017#define regDC_PERFMON7_PERFMON_LOW 0x06a5 3018#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 3019 3020 3021// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec 3022// base address: 0x370 3023#define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 3024#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3025#define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 3026#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 3027#define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 3028#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 3029#define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 3030#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3031#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 3032#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3033#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 3034#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3035#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 3036#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3037#define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 3038#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3039#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca 3040#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3041#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb 3042#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3043#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc 3044#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3045#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd 3046#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3047#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce 3048#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3049#define regHUBP1_DCHUBP_CNTL 0x06cf 3050#define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 3051#define regHUBP1_HUBP_CLK_CNTL 0x06d0 3052#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 3053#define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 3054#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3055#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d2 3056#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 3057#define regHUBP1_HUBPREQ_DEBUG 0x06d3 3058#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 3059#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 3060#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3061#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 3062#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3063 3064 3065// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec 3066// base address: 0x370 3067#define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 3068#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 3069#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 3070#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3071#define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 3072#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 3073#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 3074#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3075#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 3076#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3077#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 3078#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3079#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 3080#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3081#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 3082#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3083#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 3084#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3085#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 3086#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3087#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 3088#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3089#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee 3090#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3091#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef 3092#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3093#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 3094#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3095#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 3096#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3097#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 3098#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3099#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 3100#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3101#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 3102#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3103#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 3104#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3105#define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 3106#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3107#define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 3108#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 3109#define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 3110#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3111#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc 3112#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3113#define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd 3114#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 3115#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe 3116#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3117#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff 3118#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3119#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 3120#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3121#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 3122#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3123#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 3124#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3125#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 3126#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3127#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 3128#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3129#define regHUBPREQ1_DCN_EXPANSION_MODE 0x0705 3130#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 3131#define regHUBPREQ1_DCN_TTU_QOS_WM 0x0706 3132#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 3133#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707 3134#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3135#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708 3136#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3137#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709 3138#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3139#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a 3140#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3141#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b 3142#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3143#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c 3144#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3145#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d 3146#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3147#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e 3148#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3149#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f 3150#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3151#define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710 3152#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3153#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711 3154#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3155#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712 3156#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3157#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f 3158#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3159#define regHUBPREQ1_BLANK_OFFSET_0 0x0720 3160#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 3161#define regHUBPREQ1_BLANK_OFFSET_1 0x0721 3162#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 3163#define regHUBPREQ1_DST_DIMENSIONS 0x0722 3164#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 3165#define regHUBPREQ1_DST_AFTER_SCALER 0x0723 3166#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 3167#define regHUBPREQ1_PREFETCH_SETTINGS 0x0724 3168#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 3169#define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0725 3170#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 3171#define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0726 3172#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 3173#define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0727 3174#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 3175#define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0728 3176#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 3177#define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0729 3178#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 3179#define regHUBPREQ1_VBLANK_PARAMETERS_4 0x072a 3180#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 3181#define regHUBPREQ1_FLIP_PARAMETERS_0 0x072b 3182#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 3183#define regHUBPREQ1_FLIP_PARAMETERS_1 0x072c 3184#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 3185#define regHUBPREQ1_FLIP_PARAMETERS_2 0x072d 3186#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 3187#define regHUBPREQ1_NOM_PARAMETERS_0 0x072e 3188#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 3189#define regHUBPREQ1_NOM_PARAMETERS_1 0x072f 3190#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 3191#define regHUBPREQ1_NOM_PARAMETERS_2 0x0730 3192#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 3193#define regHUBPREQ1_NOM_PARAMETERS_3 0x0731 3194#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 3195#define regHUBPREQ1_NOM_PARAMETERS_4 0x0732 3196#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 3197#define regHUBPREQ1_NOM_PARAMETERS_5 0x0733 3198#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 3199#define regHUBPREQ1_NOM_PARAMETERS_6 0x0734 3200#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 3201#define regHUBPREQ1_NOM_PARAMETERS_7 0x0735 3202#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 3203#define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736 3204#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3205#define regHUBPREQ1_PER_LINE_DELIVERY 0x0737 3206#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 3207#define regHUBPREQ1_CURSOR_SETTINGS 0x0738 3208#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 3209#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739 3210#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3211#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a 3212#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3213#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b 3214#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3215#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c 3216#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3217#define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073f 3218#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 3219#define regHUBPREQ1_VBLANK_PARAMETERS_6 0x0740 3220#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 3221#define regHUBPREQ1_FLIP_PARAMETERS_3 0x0741 3222#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 3223#define regHUBPREQ1_FLIP_PARAMETERS_4 0x0742 3224#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 3225#define regHUBPREQ1_FLIP_PARAMETERS_5 0x0743 3226#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 3227#define regHUBPREQ1_FLIP_PARAMETERS_6 0x0744 3228#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 3229 3230 3231// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec 3232// base address: 0x370 3233#define regHUBPRET1_HUBPRET_CONTROL 0x0748 3234#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 3235#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 3236#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3237#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a 3238#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3239#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b 3240#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3241#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c 3242#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3243#define regHUBPRET1_HUBPRET_READ_LINE0 0x074d 3244#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 3245#define regHUBPRET1_HUBPRET_READ_LINE1 0x074e 3246#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 3247#define regHUBPRET1_HUBPRET_INTERRUPT 0x074f 3248#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 3249#define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 3250#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3251#define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 3252#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3253 3254 3255// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec 3256// base address: 0x370 3257#define regCURSOR0_1_CURSOR_CONTROL 0x0754 3258#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 3259#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 3260#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3261#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 3262#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3263#define regCURSOR0_1_CURSOR_SIZE 0x0757 3264#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 3265#define regCURSOR0_1_CURSOR_POSITION 0x0758 3266#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 3267#define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 3268#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 3269#define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a 3270#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 3271#define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b 3272#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 3273#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c 3274#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3275#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d 3276#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3277#define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e 3278#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3279#define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f 3280#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 3281#define regCURSOR0_1_DMDATA_CNTL 0x0760 3282#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 3283#define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 3284#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 3285#define regCURSOR0_1_DMDATA_STATUS 0x0762 3286#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 3287#define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 3288#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 3289#define regCURSOR0_1_DMDATA_SW_DATA 0x0764 3290#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 3291 3292 3293// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3294// base address: 0x1de4 3295#define regDC_PERFMON8_PERFCOUNTER_CNTL 0x0779 3296#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 3297#define regDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a 3298#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 3299#define regDC_PERFMON8_PERFCOUNTER_STATE 0x077b 3300#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 3301#define regDC_PERFMON8_PERFMON_CNTL 0x077c 3302#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 3303#define regDC_PERFMON8_PERFMON_CNTL2 0x077d 3304#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 3305#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e 3306#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3307#define regDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f 3308#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 3309#define regDC_PERFMON8_PERFMON_HI 0x0780 3310#define regDC_PERFMON8_PERFMON_HI_BASE_IDX 2 3311#define regDC_PERFMON8_PERFMON_LOW 0x0781 3312#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 3313 3314 3315// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec 3316// base address: 0x6e0 3317#define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d 3318#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3319#define regHUBP2_DCSURF_ADDR_CONFIG 0x079e 3320#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 3321#define regHUBP2_DCSURF_TILING_CONFIG 0x079f 3322#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 3323#define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 3324#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3325#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 3326#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3327#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 3328#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3329#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 3330#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3331#define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 3332#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3333#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 3334#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3335#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 3336#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3337#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 3338#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3339#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 3340#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3341#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa 3342#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3343#define regHUBP2_DCHUBP_CNTL 0x07ab 3344#define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 3345#define regHUBP2_HUBP_CLK_CNTL 0x07ac 3346#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 3347#define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad 3348#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3349#define regHUBP2_HUBPREQ_DEBUG_DB 0x07ae 3350#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 3351#define regHUBP2_HUBPREQ_DEBUG 0x07af 3352#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 3353#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3 3354#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3355#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4 3356#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3357 3358 3359// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec 3360// base address: 0x6e0 3361#define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf 3362#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 3363#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 3364#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3365#define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 3366#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 3367#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 3368#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3369#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 3370#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3371#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 3372#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3373#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 3374#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3375#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 3376#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3377#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 3378#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3379#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 3380#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3381#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 3382#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3383#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca 3384#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3385#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb 3386#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3387#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc 3388#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3389#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd 3390#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3391#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce 3392#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3393#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf 3394#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3395#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 3396#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3397#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 3398#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3399#define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 3400#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3401#define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 3402#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 3403#define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 3404#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3405#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8 3406#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3407#define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9 3408#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 3409#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da 3410#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3411#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db 3412#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3413#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc 3414#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3415#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd 3416#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3417#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de 3418#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3419#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df 3420#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3421#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0 3422#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3423#define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e1 3424#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 3425#define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e2 3426#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 3427#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e3 3428#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3429#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e4 3430#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3431#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e5 3432#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3433#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e6 3434#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3435#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e7 3436#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3437#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e8 3438#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3439#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e9 3440#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3441#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ea 3442#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3443#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07eb 3444#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3445#define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07ec 3446#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3447#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ed 3448#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3449#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ee 3450#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3451#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fb 3452#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3453#define regHUBPREQ2_BLANK_OFFSET_0 0x07fc 3454#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 3455#define regHUBPREQ2_BLANK_OFFSET_1 0x07fd 3456#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 3457#define regHUBPREQ2_DST_DIMENSIONS 0x07fe 3458#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 3459#define regHUBPREQ2_DST_AFTER_SCALER 0x07ff 3460#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 3461#define regHUBPREQ2_PREFETCH_SETTINGS 0x0800 3462#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 3463#define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0801 3464#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 3465#define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0802 3466#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 3467#define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0803 3468#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 3469#define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0804 3470#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 3471#define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0805 3472#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 3473#define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0806 3474#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 3475#define regHUBPREQ2_FLIP_PARAMETERS_0 0x0807 3476#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 3477#define regHUBPREQ2_FLIP_PARAMETERS_1 0x0808 3478#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 3479#define regHUBPREQ2_FLIP_PARAMETERS_2 0x0809 3480#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 3481#define regHUBPREQ2_NOM_PARAMETERS_0 0x080a 3482#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 3483#define regHUBPREQ2_NOM_PARAMETERS_1 0x080b 3484#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 3485#define regHUBPREQ2_NOM_PARAMETERS_2 0x080c 3486#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 3487#define regHUBPREQ2_NOM_PARAMETERS_3 0x080d 3488#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 3489#define regHUBPREQ2_NOM_PARAMETERS_4 0x080e 3490#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 3491#define regHUBPREQ2_NOM_PARAMETERS_5 0x080f 3492#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 3493#define regHUBPREQ2_NOM_PARAMETERS_6 0x0810 3494#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 3495#define regHUBPREQ2_NOM_PARAMETERS_7 0x0811 3496#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 3497#define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0812 3498#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3499#define regHUBPREQ2_PER_LINE_DELIVERY 0x0813 3500#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 3501#define regHUBPREQ2_CURSOR_SETTINGS 0x0814 3502#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 3503#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0815 3504#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3505#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0816 3506#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3507#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0817 3508#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3509#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0818 3510#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3511#define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081b 3512#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 3513#define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081c 3514#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 3515#define regHUBPREQ2_FLIP_PARAMETERS_3 0x081d 3516#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 3517#define regHUBPREQ2_FLIP_PARAMETERS_4 0x081e 3518#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 3519#define regHUBPREQ2_FLIP_PARAMETERS_5 0x081f 3520#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 3521#define regHUBPREQ2_FLIP_PARAMETERS_6 0x0820 3522#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 3523 3524 3525// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec 3526// base address: 0x6e0 3527#define regHUBPRET2_HUBPRET_CONTROL 0x0824 3528#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 3529#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 3530#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3531#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 3532#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3533#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 3534#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3535#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 3536#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3537#define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 3538#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 3539#define regHUBPRET2_HUBPRET_READ_LINE1 0x082a 3540#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 3541#define regHUBPRET2_HUBPRET_INTERRUPT 0x082b 3542#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 3543#define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c 3544#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3545#define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d 3546#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3547 3548 3549// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec 3550// base address: 0x6e0 3551#define regCURSOR0_2_CURSOR_CONTROL 0x0830 3552#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 3553#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 3554#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3555#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 3556#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3557#define regCURSOR0_2_CURSOR_SIZE 0x0833 3558#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 3559#define regCURSOR0_2_CURSOR_POSITION 0x0834 3560#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 3561#define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 3562#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 3563#define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 3564#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 3565#define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 3566#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 3567#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 3568#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3569#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 3570#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3571#define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a 3572#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3573#define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b 3574#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 3575#define regCURSOR0_2_DMDATA_CNTL 0x083c 3576#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 3577#define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d 3578#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 3579#define regCURSOR0_2_DMDATA_STATUS 0x083e 3580#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 3581#define regCURSOR0_2_DMDATA_SW_CNTL 0x083f 3582#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 3583#define regCURSOR0_2_DMDATA_SW_DATA 0x0840 3584#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 3585 3586 3587// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3588// base address: 0x2154 3589#define regDC_PERFMON9_PERFCOUNTER_CNTL 0x0855 3590#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 3591#define regDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856 3592#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 3593#define regDC_PERFMON9_PERFCOUNTER_STATE 0x0857 3594#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 3595#define regDC_PERFMON9_PERFMON_CNTL 0x0858 3596#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 3597#define regDC_PERFMON9_PERFMON_CNTL2 0x0859 3598#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 3599#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a 3600#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3601#define regDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b 3602#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 3603#define regDC_PERFMON9_PERFMON_HI 0x085c 3604#define regDC_PERFMON9_PERFMON_HI_BASE_IDX 2 3605#define regDC_PERFMON9_PERFMON_LOW 0x085d 3606#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 3607 3608 3609// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec 3610// base address: 0xa50 3611#define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 3612#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3613#define regHUBP3_DCSURF_ADDR_CONFIG 0x087a 3614#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 3615#define regHUBP3_DCSURF_TILING_CONFIG 0x087b 3616#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 3617#define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d 3618#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3619#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e 3620#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3621#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f 3622#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3623#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 3624#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3625#define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 3626#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3627#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 3628#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3629#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 3630#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3631#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 3632#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3633#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 3634#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3635#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 3636#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3637#define regHUBP3_DCHUBP_CNTL 0x0887 3638#define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 3639#define regHUBP3_HUBP_CLK_CNTL 0x0888 3640#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 3641#define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 3642#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3643#define regHUBP3_HUBPREQ_DEBUG_DB 0x088a 3644#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 3645#define regHUBP3_HUBPREQ_DEBUG 0x088b 3646#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 3647#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f 3648#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3649#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890 3650#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3651 3652 3653// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec 3654// base address: 0xa50 3655#define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b 3656#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 3657#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c 3658#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3659#define regHUBPREQ3_VMID_SETTINGS_0 0x089d 3660#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 3661#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e 3662#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3663#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f 3664#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3665#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 3666#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3667#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 3668#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3669#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 3670#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3671#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 3672#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3673#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 3674#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3675#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 3676#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3677#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 3678#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3679#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 3680#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3681#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 3682#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3683#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 3684#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3685#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa 3686#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3687#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab 3688#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3689#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac 3690#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3691#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad 3692#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3693#define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae 3694#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3695#define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af 3696#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 3697#define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 3698#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3699#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4 3700#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3701#define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5 3702#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 3703#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6 3704#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3705#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7 3706#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3707#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8 3708#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3709#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9 3710#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3711#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba 3712#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3713#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb 3714#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3715#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc 3716#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3717#define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bd 3718#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 3719#define regHUBPREQ3_DCN_TTU_QOS_WM 0x08be 3720#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 3721#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08bf 3722#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3723#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c0 3724#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3725#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c1 3726#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3727#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c2 3728#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3729#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c3 3730#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3731#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c4 3732#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3733#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c5 3734#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3735#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c6 3736#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3737#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c7 3738#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3739#define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c8 3740#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3741#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c9 3742#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3743#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08ca 3744#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3745#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d7 3746#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3747#define regHUBPREQ3_BLANK_OFFSET_0 0x08d8 3748#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 3749#define regHUBPREQ3_BLANK_OFFSET_1 0x08d9 3750#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 3751#define regHUBPREQ3_DST_DIMENSIONS 0x08da 3752#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 3753#define regHUBPREQ3_DST_AFTER_SCALER 0x08db 3754#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 3755#define regHUBPREQ3_PREFETCH_SETTINGS 0x08dc 3756#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 3757#define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dd 3758#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 3759#define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08de 3760#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 3761#define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08df 3762#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 3763#define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08e0 3764#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 3765#define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e1 3766#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 3767#define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e2 3768#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 3769#define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e3 3770#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 3771#define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e4 3772#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 3773#define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e5 3774#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 3775#define regHUBPREQ3_NOM_PARAMETERS_0 0x08e6 3776#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 3777#define regHUBPREQ3_NOM_PARAMETERS_1 0x08e7 3778#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 3779#define regHUBPREQ3_NOM_PARAMETERS_2 0x08e8 3780#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 3781#define regHUBPREQ3_NOM_PARAMETERS_3 0x08e9 3782#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 3783#define regHUBPREQ3_NOM_PARAMETERS_4 0x08ea 3784#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 3785#define regHUBPREQ3_NOM_PARAMETERS_5 0x08eb 3786#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 3787#define regHUBPREQ3_NOM_PARAMETERS_6 0x08ec 3788#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 3789#define regHUBPREQ3_NOM_PARAMETERS_7 0x08ed 3790#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 3791#define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ee 3792#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3793#define regHUBPREQ3_PER_LINE_DELIVERY 0x08ef 3794#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 3795#define regHUBPREQ3_CURSOR_SETTINGS 0x08f0 3796#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 3797#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f1 3798#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3799#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f2 3800#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3801#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f3 3802#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3803#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f4 3804#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3805#define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f7 3806#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 3807#define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f8 3808#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 3809#define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f9 3810#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 3811#define regHUBPREQ3_FLIP_PARAMETERS_4 0x08fa 3812#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 3813#define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fb 3814#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 3815#define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fc 3816#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 3817 3818 3819// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec 3820// base address: 0xa50 3821#define regHUBPRET3_HUBPRET_CONTROL 0x0900 3822#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 3823#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 3824#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3825#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 3826#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3827#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 3828#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3829#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 3830#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3831#define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 3832#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 3833#define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 3834#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 3835#define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 3836#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 3837#define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 3838#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3839#define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 3840#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3841 3842 3843// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec 3844// base address: 0xa50 3845#define regCURSOR0_3_CURSOR_CONTROL 0x090c 3846#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 3847#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d 3848#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3849#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e 3850#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3851#define regCURSOR0_3_CURSOR_SIZE 0x090f 3852#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 3853#define regCURSOR0_3_CURSOR_POSITION 0x0910 3854#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 3855#define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 3856#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 3857#define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 3858#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 3859#define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 3860#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 3861#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 3862#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3863#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 3864#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3865#define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 3866#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3867#define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 3868#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 3869#define regCURSOR0_3_DMDATA_CNTL 0x0918 3870#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 3871#define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 3872#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 3873#define regCURSOR0_3_DMDATA_STATUS 0x091a 3874#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 3875#define regCURSOR0_3_DMDATA_SW_CNTL 0x091b 3876#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 3877#define regCURSOR0_3_DMDATA_SW_DATA 0x091c 3878#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 3879 3880 3881// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3882// base address: 0x24c4 3883#define regDC_PERFMON10_PERFCOUNTER_CNTL 0x0931 3884#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 3885#define regDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932 3886#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 3887#define regDC_PERFMON10_PERFCOUNTER_STATE 0x0933 3888#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 3889#define regDC_PERFMON10_PERFMON_CNTL 0x0934 3890#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 3891#define regDC_PERFMON10_PERFMON_CNTL2 0x0935 3892#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 3893#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936 3894#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3895#define regDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937 3896#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 3897#define regDC_PERFMON10_PERFMON_HI 0x0938 3898#define regDC_PERFMON10_PERFMON_HI_BASE_IDX 2 3899#define regDC_PERFMON10_PERFMON_LOW 0x0939 3900#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 3901 3902 3903// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec 3904// base address: 0x0 3905#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 3906#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3907#define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 3908#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 3909#define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 3910#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 3911#define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 3912#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 3913#define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 3914#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 3915#define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 3916#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 3917#define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 3918#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 3919#define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 3920#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 3921#define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 3922#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 3923#define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 3924#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 3925#define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 3926#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 3927#define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 3928#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 3929#define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 3930#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 3931#define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 3932#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 3933#define regCNVC_CFG0_PRE_DEALPHA 0x0cde 3934#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 3935#define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf 3936#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 3937#define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 3938#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 3939#define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 3940#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 3941#define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 3942#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 3943#define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 3944#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 3945#define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 3946#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 3947#define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 3948#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 3949#define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 3950#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 3951#define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 3952#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 3953#define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 3954#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 3955#define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 3956#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 3957#define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea 3958#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 3959#define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb 3960#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 3961#define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec 3962#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 3963#define regCNVC_CFG0_PRE_DEGAM 0x0ced 3964#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 3965#define regCNVC_CFG0_PRE_REALPHA 0x0cee 3966#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 3967 3968 3969// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec 3970// base address: 0x0 3971#define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 3972#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 3973#define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 3974#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 3975#define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 3976#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 3977#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 3978#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3979 3980 3981// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec 3982// base address: 0x0 3983#define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 3984#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3985#define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa 3986#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3987#define regDSCL0_SCL_MODE 0x0cfb 3988#define regDSCL0_SCL_MODE_BASE_IDX 2 3989#define regDSCL0_SCL_TAP_CONTROL 0x0cfc 3990#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 3991#define regDSCL0_DSCL_CONTROL 0x0cfd 3992#define regDSCL0_DSCL_CONTROL_BASE_IDX 2 3993#define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe 3994#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 3995#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff 3996#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3997#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 3998#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3999#define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 4000#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4001#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 4002#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4003#define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 4004#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4005#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 4006#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4007#define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 4008#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 4009#define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 4010#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4011#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 4012#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4013#define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 4014#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4015#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 4016#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4017#define regDSCL0_SCL_BLACK_COLOR 0x0d0a 4018#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 4019#define regDSCL0_DSCL_UPDATE 0x0d0b 4020#define regDSCL0_DSCL_UPDATE_BASE_IDX 2 4021#define regDSCL0_DSCL_AUTOCAL 0x0d0c 4022#define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 4023#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d 4024#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4025#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e 4026#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4027#define regDSCL0_OTG_H_BLANK 0x0d0f 4028#define regDSCL0_OTG_H_BLANK_BASE_IDX 2 4029#define regDSCL0_OTG_V_BLANK 0x0d10 4030#define regDSCL0_OTG_V_BLANK_BASE_IDX 2 4031#define regDSCL0_RECOUT_START 0x0d11 4032#define regDSCL0_RECOUT_START_BASE_IDX 2 4033#define regDSCL0_RECOUT_SIZE 0x0d12 4034#define regDSCL0_RECOUT_SIZE_BASE_IDX 2 4035#define regDSCL0_MPC_SIZE 0x0d13 4036#define regDSCL0_MPC_SIZE_BASE_IDX 2 4037#define regDSCL0_LB_DATA_FORMAT 0x0d14 4038#define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 4039#define regDSCL0_LB_MEMORY_CTRL 0x0d15 4040#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 4041#define regDSCL0_LB_V_COUNTER 0x0d16 4042#define regDSCL0_LB_V_COUNTER_BASE_IDX 2 4043#define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 4044#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4045#define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 4046#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4047#define regDSCL0_OBUF_CONTROL 0x0d19 4048#define regDSCL0_OBUF_CONTROL_BASE_IDX 2 4049#define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a 4050#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4051 4052 4053// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec 4054// base address: 0x0 4055#define regCM0_CM_CONTROL 0x0d20 4056#define regCM0_CM_CONTROL_BASE_IDX 2 4057#define regCM0_CM_POST_CSC_CONTROL 0x0d21 4058#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 4059#define regCM0_CM_POST_CSC_C11_C12 0x0d22 4060#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 4061#define regCM0_CM_POST_CSC_C13_C14 0x0d23 4062#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 4063#define regCM0_CM_POST_CSC_C21_C22 0x0d24 4064#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 4065#define regCM0_CM_POST_CSC_C23_C24 0x0d25 4066#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 4067#define regCM0_CM_POST_CSC_C31_C32 0x0d26 4068#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 4069#define regCM0_CM_POST_CSC_C33_C34 0x0d27 4070#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 4071#define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 4072#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4073#define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 4074#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4075#define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a 4076#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4077#define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b 4078#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4079#define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c 4080#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4081#define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d 4082#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4083#define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e 4084#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4085#define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f 4086#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4087#define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 4088#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4089#define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 4090#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4091#define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 4092#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4093#define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 4094#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4095#define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 4096#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4097#define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 4098#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4099#define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 4100#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4101#define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 4102#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4103#define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 4104#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4105#define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 4106#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4107#define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a 4108#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4109#define regCM0_CM_BIAS_CR_R 0x0d3b 4110#define regCM0_CM_BIAS_CR_R_BASE_IDX 2 4111#define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c 4112#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4113#define regCM0_CM_GAMCOR_CONTROL 0x0d3d 4114#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 4115#define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e 4116#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4117#define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f 4118#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4119#define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 4120#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4121#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 4122#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4123#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 4124#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4125#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 4126#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4127#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 4128#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4129#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 4130#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4131#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 4132#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4133#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 4134#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4135#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 4136#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4137#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 4138#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4139#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a 4140#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4141#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b 4142#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4143#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c 4144#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4145#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d 4146#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4147#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e 4148#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4149#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f 4150#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4151#define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 4152#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4153#define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 4154#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4155#define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 4156#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4157#define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 4158#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4159#define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 4160#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4161#define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 4162#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4163#define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 4164#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4165#define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 4166#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4167#define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 4168#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4169#define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 4170#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4171#define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a 4172#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4173#define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b 4174#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4175#define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c 4176#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4177#define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d 4178#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4179#define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e 4180#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4181#define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f 4182#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4183#define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 4184#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4185#define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 4186#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4187#define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 4188#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4189#define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 4190#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4191#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 4192#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4193#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 4194#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4195#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 4196#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4197#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 4198#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4199#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 4200#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4201#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 4202#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4203#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a 4204#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4205#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b 4206#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4207#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c 4208#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4209#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d 4210#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4211#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e 4212#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4213#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f 4214#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4215#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 4216#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4217#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 4218#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4219#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 4220#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4221#define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 4222#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4223#define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 4224#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4225#define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 4226#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4227#define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 4228#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4229#define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 4230#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4231#define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 4232#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4233#define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 4234#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4235#define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a 4236#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4237#define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b 4238#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4239#define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c 4240#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4241#define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d 4242#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4243#define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e 4244#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4245#define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f 4246#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4247#define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 4248#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4249#define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 4250#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4251#define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 4252#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4253#define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 4254#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4255#define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 4256#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4257#define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 4258#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4259#define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 4260#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4261#define regCM0_CM_BLNDGAM_CONTROL 0x0d87 4262#define regCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 4263#define regCM0_CM_BLNDGAM_LUT_INDEX 0x0d88 4264#define regCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 4265#define regCM0_CM_BLNDGAM_LUT_DATA 0x0d89 4266#define regCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 4267#define regCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a 4268#define regCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 4269#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b 4270#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 4271#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c 4272#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 4273#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d 4274#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 4275#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e 4276#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4277#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f 4278#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4279#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90 4280#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4281#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91 4282#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4283#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92 4284#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4285#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93 4286#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4287#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94 4288#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4289#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95 4290#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4291#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96 4292#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4293#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97 4294#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4295#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98 4296#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4297#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99 4298#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4299#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a 4300#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 4301#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b 4302#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 4303#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c 4304#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 4305#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d 4306#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 4307#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e 4308#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 4309#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f 4310#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 4311#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0 4312#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 4313#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1 4314#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 4315#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2 4316#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 4317#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3 4318#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 4319#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4 4320#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 4321#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5 4322#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 4323#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6 4324#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 4325#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7 4326#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 4327#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8 4328#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 4329#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9 4330#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 4331#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa 4332#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 4333#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab 4334#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 4335#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac 4336#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 4337#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad 4338#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 4339#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae 4340#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 4341#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf 4342#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 4343#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0 4344#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 4345#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1 4346#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4347#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2 4348#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4349#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3 4350#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4351#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4 4352#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4353#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5 4354#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4355#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6 4356#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4357#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7 4358#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4359#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8 4360#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4361#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9 4362#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4363#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba 4364#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4365#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb 4366#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4367#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc 4368#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4369#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd 4370#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 4371#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe 4372#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 4373#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf 4374#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 4375#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0 4376#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 4377#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1 4378#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 4379#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2 4380#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 4381#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3 4382#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 4383#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4 4384#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 4385#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5 4386#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 4387#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6 4388#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 4389#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7 4390#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 4391#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8 4392#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 4393#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9 4394#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 4395#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca 4396#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 4397#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb 4398#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 4399#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc 4400#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 4401#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd 4402#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 4403#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce 4404#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 4405#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf 4406#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 4407#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0 4408#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 4409#define regCM0_CM_HDR_MULT_COEF 0x0dd1 4410#define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 4411#define regCM0_CM_MEM_PWR_CTRL 0x0dd2 4412#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 4413#define regCM0_CM_MEM_PWR_STATUS 0x0dd3 4414#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 4415#define regCM0_CM_DEALPHA 0x0dd5 4416#define regCM0_CM_DEALPHA_BASE_IDX 2 4417#define regCM0_CM_COEF_FORMAT 0x0dd6 4418#define regCM0_CM_COEF_FORMAT_BASE_IDX 2 4419#define regCM0_CM_SHAPER_CONTROL 0x0dd7 4420#define regCM0_CM_SHAPER_CONTROL_BASE_IDX 2 4421#define regCM0_CM_SHAPER_OFFSET_R 0x0dd8 4422#define regCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 4423#define regCM0_CM_SHAPER_OFFSET_G 0x0dd9 4424#define regCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 4425#define regCM0_CM_SHAPER_OFFSET_B 0x0dda 4426#define regCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 4427#define regCM0_CM_SHAPER_SCALE_R 0x0ddb 4428#define regCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 4429#define regCM0_CM_SHAPER_SCALE_G_B 0x0ddc 4430#define regCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 4431#define regCM0_CM_SHAPER_LUT_INDEX 0x0ddd 4432#define regCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 4433#define regCM0_CM_SHAPER_LUT_DATA 0x0dde 4434#define regCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 4435#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf 4436#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 4437#define regCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0 4438#define regCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 4439#define regCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1 4440#define regCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 4441#define regCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2 4442#define regCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 4443#define regCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3 4444#define regCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 4445#define regCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4 4446#define regCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 4447#define regCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5 4448#define regCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 4449#define regCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6 4450#define regCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 4451#define regCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7 4452#define regCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 4453#define regCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8 4454#define regCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 4455#define regCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9 4456#define regCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 4457#define regCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea 4458#define regCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 4459#define regCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb 4460#define regCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 4461#define regCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec 4462#define regCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 4463#define regCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded 4464#define regCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 4465#define regCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee 4466#define regCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 4467#define regCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def 4468#define regCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 4469#define regCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0 4470#define regCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 4471#define regCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1 4472#define regCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 4473#define regCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2 4474#define regCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 4475#define regCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3 4476#define regCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 4477#define regCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4 4478#define regCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 4479#define regCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5 4480#define regCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 4481#define regCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6 4482#define regCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 4483#define regCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7 4484#define regCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 4485#define regCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8 4486#define regCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 4487#define regCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9 4488#define regCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 4489#define regCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa 4490#define regCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 4491#define regCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb 4492#define regCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 4493#define regCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc 4494#define regCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 4495#define regCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd 4496#define regCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 4497#define regCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe 4498#define regCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 4499#define regCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff 4500#define regCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 4501#define regCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00 4502#define regCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 4503#define regCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01 4504#define regCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 4505#define regCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02 4506#define regCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 4507#define regCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03 4508#define regCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 4509#define regCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04 4510#define regCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 4511#define regCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05 4512#define regCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 4513#define regCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06 4514#define regCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 4515#define regCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07 4516#define regCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 4517#define regCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08 4518#define regCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 4519#define regCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09 4520#define regCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 4521#define regCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a 4522#define regCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 4523#define regCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b 4524#define regCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 4525#define regCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c 4526#define regCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 4527#define regCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d 4528#define regCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 4529#define regCM0_CM_MEM_PWR_CTRL2 0x0e0e 4530#define regCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 4531#define regCM0_CM_MEM_PWR_STATUS2 0x0e0f 4532#define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 4533#define regCM0_CM_3DLUT_MODE 0x0e10 4534#define regCM0_CM_3DLUT_MODE_BASE_IDX 2 4535#define regCM0_CM_3DLUT_INDEX 0x0e11 4536#define regCM0_CM_3DLUT_INDEX_BASE_IDX 2 4537#define regCM0_CM_3DLUT_DATA 0x0e12 4538#define regCM0_CM_3DLUT_DATA_BASE_IDX 2 4539#define regCM0_CM_3DLUT_DATA_30BIT 0x0e13 4540#define regCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 4541#define regCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14 4542#define regCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 4543#define regCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15 4544#define regCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 4545#define regCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16 4546#define regCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 4547#define regCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17 4548#define regCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 4549#define regCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18 4550#define regCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 4551#define regCM0_CM_TEST_DEBUG_INDEX 0x0e19 4552#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4553#define regCM0_CM_TEST_DEBUG_DATA 0x0e1a 4554#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 4555 4556 4557// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec 4558// base address: 0x0 4559#define regDPP_TOP0_DPP_CONTROL 0x0cc5 4560#define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 4561#define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 4562#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 4563#define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 4564#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 4565#define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 4566#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 4567#define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 4568#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 4569#define regDPP_TOP0_HOST_READ_CONTROL 0x0cca 4570#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 4571 4572 4573// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 4574// base address: 0x3890 4575#define regDC_PERFMON11_PERFCOUNTER_CNTL 0x0e24 4576#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 4577#define regDC_PERFMON11_PERFCOUNTER_CNTL2 0x0e25 4578#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 4579#define regDC_PERFMON11_PERFCOUNTER_STATE 0x0e26 4580#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 4581#define regDC_PERFMON11_PERFMON_CNTL 0x0e27 4582#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 4583#define regDC_PERFMON11_PERFMON_CNTL2 0x0e28 4584#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 4585#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0e29 4586#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4587#define regDC_PERFMON11_PERFMON_CVALUE_LOW 0x0e2a 4588#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 4589#define regDC_PERFMON11_PERFMON_HI 0x0e2b 4590#define regDC_PERFMON11_PERFMON_HI_BASE_IDX 2 4591#define regDC_PERFMON11_PERFMON_LOW 0x0e2c 4592#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 4593 4594 4595// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec 4596// base address: 0x5ac 4597#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 4598#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4599#define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b 4600#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 4601#define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 4602#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 4603#define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 4604#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 4605#define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 4606#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 4607#define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 4608#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 4609#define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 4610#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 4611#define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 4612#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 4613#define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 4614#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 4615#define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 4616#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 4617#define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 4618#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 4619#define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 4620#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 4621#define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 4622#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 4623#define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 4624#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 4625#define regCNVC_CFG1_PRE_DEALPHA 0x0e49 4626#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 4627#define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a 4628#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 4629#define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b 4630#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 4631#define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c 4632#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 4633#define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d 4634#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 4635#define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e 4636#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 4637#define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f 4638#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 4639#define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 4640#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 4641#define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 4642#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 4643#define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 4644#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 4645#define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 4646#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 4647#define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 4648#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 4649#define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 4650#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 4651#define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 4652#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 4653#define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 4654#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 4655#define regCNVC_CFG1_PRE_DEGAM 0x0e58 4656#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 4657#define regCNVC_CFG1_PRE_REALPHA 0x0e59 4658#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 4659 4660 4661// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec 4662// base address: 0x5ac 4663#define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c 4664#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 4665#define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d 4666#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 4667#define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e 4668#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 4669#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f 4670#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4671 4672 4673// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec 4674// base address: 0x5ac 4675#define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 4676#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4677#define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 4678#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4679#define regDSCL1_SCL_MODE 0x0e66 4680#define regDSCL1_SCL_MODE_BASE_IDX 2 4681#define regDSCL1_SCL_TAP_CONTROL 0x0e67 4682#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 4683#define regDSCL1_DSCL_CONTROL 0x0e68 4684#define regDSCL1_DSCL_CONTROL_BASE_IDX 2 4685#define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 4686#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 4687#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a 4688#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4689#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b 4690#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4691#define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c 4692#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4693#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d 4694#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4695#define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e 4696#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4697#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f 4698#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4699#define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 4700#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 4701#define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 4702#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4703#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 4704#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4705#define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 4706#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4707#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 4708#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4709#define regDSCL1_SCL_BLACK_COLOR 0x0e75 4710#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 4711#define regDSCL1_DSCL_UPDATE 0x0e76 4712#define regDSCL1_DSCL_UPDATE_BASE_IDX 2 4713#define regDSCL1_DSCL_AUTOCAL 0x0e77 4714#define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 4715#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 4716#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4717#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 4718#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4719#define regDSCL1_OTG_H_BLANK 0x0e7a 4720#define regDSCL1_OTG_H_BLANK_BASE_IDX 2 4721#define regDSCL1_OTG_V_BLANK 0x0e7b 4722#define regDSCL1_OTG_V_BLANK_BASE_IDX 2 4723#define regDSCL1_RECOUT_START 0x0e7c 4724#define regDSCL1_RECOUT_START_BASE_IDX 2 4725#define regDSCL1_RECOUT_SIZE 0x0e7d 4726#define regDSCL1_RECOUT_SIZE_BASE_IDX 2 4727#define regDSCL1_MPC_SIZE 0x0e7e 4728#define regDSCL1_MPC_SIZE_BASE_IDX 2 4729#define regDSCL1_LB_DATA_FORMAT 0x0e7f 4730#define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 4731#define regDSCL1_LB_MEMORY_CTRL 0x0e80 4732#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 4733#define regDSCL1_LB_V_COUNTER 0x0e81 4734#define regDSCL1_LB_V_COUNTER_BASE_IDX 2 4735#define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 4736#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4737#define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 4738#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4739#define regDSCL1_OBUF_CONTROL 0x0e84 4740#define regDSCL1_OBUF_CONTROL_BASE_IDX 2 4741#define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 4742#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4743 4744 4745// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec 4746// base address: 0x5ac 4747#define regCM1_CM_CONTROL 0x0e8b 4748#define regCM1_CM_CONTROL_BASE_IDX 2 4749#define regCM1_CM_POST_CSC_CONTROL 0x0e8c 4750#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 4751#define regCM1_CM_POST_CSC_C11_C12 0x0e8d 4752#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 4753#define regCM1_CM_POST_CSC_C13_C14 0x0e8e 4754#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 4755#define regCM1_CM_POST_CSC_C21_C22 0x0e8f 4756#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 4757#define regCM1_CM_POST_CSC_C23_C24 0x0e90 4758#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 4759#define regCM1_CM_POST_CSC_C31_C32 0x0e91 4760#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 4761#define regCM1_CM_POST_CSC_C33_C34 0x0e92 4762#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 4763#define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 4764#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4765#define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 4766#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4767#define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 4768#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4769#define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 4770#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4771#define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 4772#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4773#define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 4774#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4775#define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 4776#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4777#define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a 4778#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4779#define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b 4780#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4781#define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c 4782#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4783#define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d 4784#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4785#define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e 4786#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4787#define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f 4788#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4789#define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 4790#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4791#define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 4792#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4793#define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 4794#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4795#define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 4796#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4797#define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 4798#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4799#define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 4800#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4801#define regCM1_CM_BIAS_CR_R 0x0ea6 4802#define regCM1_CM_BIAS_CR_R_BASE_IDX 2 4803#define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 4804#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4805#define regCM1_CM_GAMCOR_CONTROL 0x0ea8 4806#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 4807#define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 4808#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4809#define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa 4810#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4811#define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab 4812#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4813#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac 4814#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4815#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead 4816#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4817#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae 4818#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4819#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf 4820#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4821#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 4822#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4823#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 4824#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4825#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 4826#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4827#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 4828#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4829#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 4830#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4831#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 4832#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4833#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 4834#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4835#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 4836#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4837#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 4838#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4839#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 4840#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4841#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba 4842#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4843#define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb 4844#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4845#define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc 4846#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4847#define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd 4848#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4849#define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe 4850#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4851#define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf 4852#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4853#define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 4854#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4855#define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 4856#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4857#define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 4858#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4859#define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 4860#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4861#define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 4862#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4863#define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 4864#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4865#define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 4866#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4867#define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 4868#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4869#define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 4870#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4871#define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 4872#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4873#define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca 4874#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4875#define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb 4876#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4877#define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc 4878#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4879#define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd 4880#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4881#define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece 4882#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4883#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf 4884#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4885#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 4886#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4887#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 4888#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4889#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 4890#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4891#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 4892#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4893#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 4894#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4895#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 4896#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4897#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 4898#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4899#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 4900#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4901#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 4902#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4903#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 4904#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4905#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda 4906#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4907#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb 4908#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4909#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc 4910#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4911#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd 4912#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4913#define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede 4914#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4915#define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf 4916#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4917#define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 4918#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4919#define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 4920#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4921#define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 4922#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4923#define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 4924#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4925#define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 4926#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4927#define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 4928#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4929#define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 4930#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4931#define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 4932#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4933#define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 4934#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4935#define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 4936#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4937#define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea 4938#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4939#define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb 4940#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4941#define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec 4942#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4943#define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed 4944#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4945#define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee 4946#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4947#define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef 4948#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4949#define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 4950#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4951#define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 4952#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4953#define regCM1_CM_BLNDGAM_CONTROL 0x0ef2 4954#define regCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 4955#define regCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3 4956#define regCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 4957#define regCM1_CM_BLNDGAM_LUT_DATA 0x0ef4 4958#define regCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 4959#define regCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5 4960#define regCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 4961#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6 4962#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 4963#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7 4964#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 4965#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8 4966#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 4967#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9 4968#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4969#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa 4970#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4971#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb 4972#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4973#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc 4974#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4975#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd 4976#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4977#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe 4978#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4979#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff 4980#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4981#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00 4982#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4983#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01 4984#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4985#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02 4986#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4987#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03 4988#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4989#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04 4990#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4991#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05 4992#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 4993#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06 4994#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 4995#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07 4996#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 4997#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08 4998#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 4999#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09 5000#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 5001#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a 5002#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 5003#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b 5004#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 5005#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c 5006#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 5007#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d 5008#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 5009#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e 5010#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 5011#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f 5012#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 5013#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10 5014#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 5015#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11 5016#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 5017#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12 5018#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 5019#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13 5020#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 5021#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14 5022#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 5023#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15 5024#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 5025#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16 5026#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 5027#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17 5028#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 5029#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18 5030#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 5031#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19 5032#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 5033#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a 5034#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 5035#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b 5036#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 5037#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c 5038#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5039#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d 5040#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5041#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e 5042#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5043#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f 5044#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5045#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20 5046#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5047#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21 5048#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5049#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22 5050#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5051#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23 5052#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5053#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24 5054#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5055#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25 5056#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5057#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26 5058#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5059#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27 5060#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5061#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28 5062#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 5063#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29 5064#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 5065#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a 5066#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 5067#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b 5068#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 5069#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c 5070#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 5071#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d 5072#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 5073#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e 5074#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 5075#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f 5076#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 5077#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30 5078#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 5079#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31 5080#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 5081#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32 5082#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 5083#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33 5084#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 5085#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34 5086#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 5087#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35 5088#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 5089#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36 5090#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 5091#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37 5092#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 5093#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38 5094#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 5095#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39 5096#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 5097#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a 5098#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 5099#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b 5100#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 5101#define regCM1_CM_HDR_MULT_COEF 0x0f3c 5102#define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 5103#define regCM1_CM_MEM_PWR_CTRL 0x0f3d 5104#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 5105#define regCM1_CM_MEM_PWR_STATUS 0x0f3e 5106#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 5107#define regCM1_CM_DEALPHA 0x0f40 5108#define regCM1_CM_DEALPHA_BASE_IDX 2 5109#define regCM1_CM_COEF_FORMAT 0x0f41 5110#define regCM1_CM_COEF_FORMAT_BASE_IDX 2 5111#define regCM1_CM_SHAPER_CONTROL 0x0f42 5112#define regCM1_CM_SHAPER_CONTROL_BASE_IDX 2 5113#define regCM1_CM_SHAPER_OFFSET_R 0x0f43 5114#define regCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 5115#define regCM1_CM_SHAPER_OFFSET_G 0x0f44 5116#define regCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 5117#define regCM1_CM_SHAPER_OFFSET_B 0x0f45 5118#define regCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 5119#define regCM1_CM_SHAPER_SCALE_R 0x0f46 5120#define regCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 5121#define regCM1_CM_SHAPER_SCALE_G_B 0x0f47 5122#define regCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 5123#define regCM1_CM_SHAPER_LUT_INDEX 0x0f48 5124#define regCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 5125#define regCM1_CM_SHAPER_LUT_DATA 0x0f49 5126#define regCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 5127#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a 5128#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 5129#define regCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b 5130#define regCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 5131#define regCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c 5132#define regCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 5133#define regCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d 5134#define regCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 5135#define regCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e 5136#define regCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 5137#define regCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f 5138#define regCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 5139#define regCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50 5140#define regCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 5141#define regCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51 5142#define regCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 5143#define regCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52 5144#define regCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 5145#define regCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53 5146#define regCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 5147#define regCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54 5148#define regCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 5149#define regCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55 5150#define regCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 5151#define regCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56 5152#define regCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 5153#define regCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57 5154#define regCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 5155#define regCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58 5156#define regCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 5157#define regCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59 5158#define regCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 5159#define regCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a 5160#define regCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 5161#define regCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b 5162#define regCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 5163#define regCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c 5164#define regCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 5165#define regCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d 5166#define regCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 5167#define regCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e 5168#define regCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 5169#define regCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f 5170#define regCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 5171#define regCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60 5172#define regCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 5173#define regCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61 5174#define regCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 5175#define regCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62 5176#define regCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 5177#define regCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63 5178#define regCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 5179#define regCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64 5180#define regCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 5181#define regCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65 5182#define regCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 5183#define regCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66 5184#define regCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 5185#define regCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67 5186#define regCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 5187#define regCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68 5188#define regCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 5189#define regCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69 5190#define regCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 5191#define regCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a 5192#define regCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 5193#define regCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b 5194#define regCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 5195#define regCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c 5196#define regCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 5197#define regCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d 5198#define regCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 5199#define regCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e 5200#define regCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 5201#define regCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f 5202#define regCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 5203#define regCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70 5204#define regCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 5205#define regCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71 5206#define regCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 5207#define regCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72 5208#define regCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 5209#define regCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73 5210#define regCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 5211#define regCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74 5212#define regCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 5213#define regCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75 5214#define regCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 5215#define regCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76 5216#define regCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 5217#define regCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77 5218#define regCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 5219#define regCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78 5220#define regCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 5221#define regCM1_CM_MEM_PWR_CTRL2 0x0f79 5222#define regCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 5223#define regCM1_CM_MEM_PWR_STATUS2 0x0f7a 5224#define regCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 5225#define regCM1_CM_3DLUT_MODE 0x0f7b 5226#define regCM1_CM_3DLUT_MODE_BASE_IDX 2 5227#define regCM1_CM_3DLUT_INDEX 0x0f7c 5228#define regCM1_CM_3DLUT_INDEX_BASE_IDX 2 5229#define regCM1_CM_3DLUT_DATA 0x0f7d 5230#define regCM1_CM_3DLUT_DATA_BASE_IDX 2 5231#define regCM1_CM_3DLUT_DATA_30BIT 0x0f7e 5232#define regCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5233#define regCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f 5234#define regCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5235#define regCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80 5236#define regCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5237#define regCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81 5238#define regCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5239#define regCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82 5240#define regCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5241#define regCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83 5242#define regCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5243#define regCM1_CM_TEST_DEBUG_INDEX 0x0f84 5244#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5245#define regCM1_CM_TEST_DEBUG_DATA 0x0f85 5246#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 5247 5248 5249// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec 5250// base address: 0x5ac 5251#define regDPP_TOP1_DPP_CONTROL 0x0e30 5252#define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 5253#define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 5254#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 5255#define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 5256#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 5257#define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 5258#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 5259#define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 5260#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 5261#define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 5262#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 5263 5264 5265// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5266// base address: 0x3e3c 5267#define regDC_PERFMON12_PERFCOUNTER_CNTL 0x0f8f 5268#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 5269#define regDC_PERFMON12_PERFCOUNTER_CNTL2 0x0f90 5270#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 5271#define regDC_PERFMON12_PERFCOUNTER_STATE 0x0f91 5272#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 5273#define regDC_PERFMON12_PERFMON_CNTL 0x0f92 5274#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 5275#define regDC_PERFMON12_PERFMON_CNTL2 0x0f93 5276#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 5277#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0f94 5278#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5279#define regDC_PERFMON12_PERFMON_CVALUE_LOW 0x0f95 5280#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 5281#define regDC_PERFMON12_PERFMON_HI 0x0f96 5282#define regDC_PERFMON12_PERFMON_HI_BASE_IDX 2 5283#define regDC_PERFMON12_PERFMON_LOW 0x0f97 5284#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 5285 5286 5287// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec 5288// base address: 0xb58 5289#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 5290#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5291#define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 5292#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 5293#define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 5294#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 5295#define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 5296#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 5297#define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 5298#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 5299#define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa 5300#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 5301#define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab 5302#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 5303#define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac 5304#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 5305#define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad 5306#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 5307#define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae 5308#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 5309#define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf 5310#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 5311#define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 5312#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 5313#define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 5314#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 5315#define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 5316#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 5317#define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 5318#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 5319#define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 5320#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 5321#define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 5322#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 5323#define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 5324#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 5325#define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 5326#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 5327#define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 5328#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 5329#define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba 5330#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 5331#define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb 5332#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 5333#define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc 5334#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 5335#define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd 5336#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 5337#define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe 5338#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 5339#define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf 5340#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 5341#define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 5342#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 5343#define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 5344#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 5345#define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 5346#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 5347#define regCNVC_CFG2_PRE_DEGAM 0x0fc3 5348#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 5349#define regCNVC_CFG2_PRE_REALPHA 0x0fc4 5350#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 5351 5352 5353// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec 5354// base address: 0xb58 5355#define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 5356#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 5357#define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 5358#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 5359#define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 5360#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 5361#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca 5362#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 5363 5364 5365// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec 5366// base address: 0xb58 5367#define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf 5368#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 5369#define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 5370#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 5371#define regDSCL2_SCL_MODE 0x0fd1 5372#define regDSCL2_SCL_MODE_BASE_IDX 2 5373#define regDSCL2_SCL_TAP_CONTROL 0x0fd2 5374#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 5375#define regDSCL2_DSCL_CONTROL 0x0fd3 5376#define regDSCL2_DSCL_CONTROL_BASE_IDX 2 5377#define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 5378#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 5379#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 5380#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 5381#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 5382#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 5383#define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 5384#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 5385#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 5386#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 5387#define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 5388#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 5389#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda 5390#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 5391#define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb 5392#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 5393#define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc 5394#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 5395#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd 5396#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 5397#define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde 5398#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 5399#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf 5400#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 5401#define regDSCL2_SCL_BLACK_COLOR 0x0fe0 5402#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 5403#define regDSCL2_DSCL_UPDATE 0x0fe1 5404#define regDSCL2_DSCL_UPDATE_BASE_IDX 2 5405#define regDSCL2_DSCL_AUTOCAL 0x0fe2 5406#define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 5407#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 5408#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 5409#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 5410#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 5411#define regDSCL2_OTG_H_BLANK 0x0fe5 5412#define regDSCL2_OTG_H_BLANK_BASE_IDX 2 5413#define regDSCL2_OTG_V_BLANK 0x0fe6 5414#define regDSCL2_OTG_V_BLANK_BASE_IDX 2 5415#define regDSCL2_RECOUT_START 0x0fe7 5416#define regDSCL2_RECOUT_START_BASE_IDX 2 5417#define regDSCL2_RECOUT_SIZE 0x0fe8 5418#define regDSCL2_RECOUT_SIZE_BASE_IDX 2 5419#define regDSCL2_MPC_SIZE 0x0fe9 5420#define regDSCL2_MPC_SIZE_BASE_IDX 2 5421#define regDSCL2_LB_DATA_FORMAT 0x0fea 5422#define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 5423#define regDSCL2_LB_MEMORY_CTRL 0x0feb 5424#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 5425#define regDSCL2_LB_V_COUNTER 0x0fec 5426#define regDSCL2_LB_V_COUNTER_BASE_IDX 2 5427#define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed 5428#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 5429#define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee 5430#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 5431#define regDSCL2_OBUF_CONTROL 0x0fef 5432#define regDSCL2_OBUF_CONTROL_BASE_IDX 2 5433#define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 5434#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 5435 5436 5437// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec 5438// base address: 0xb58 5439#define regCM2_CM_CONTROL 0x0ff6 5440#define regCM2_CM_CONTROL_BASE_IDX 2 5441#define regCM2_CM_POST_CSC_CONTROL 0x0ff7 5442#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 5443#define regCM2_CM_POST_CSC_C11_C12 0x0ff8 5444#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 5445#define regCM2_CM_POST_CSC_C13_C14 0x0ff9 5446#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 5447#define regCM2_CM_POST_CSC_C21_C22 0x0ffa 5448#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 5449#define regCM2_CM_POST_CSC_C23_C24 0x0ffb 5450#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 5451#define regCM2_CM_POST_CSC_C31_C32 0x0ffc 5452#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 5453#define regCM2_CM_POST_CSC_C33_C34 0x0ffd 5454#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 5455#define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe 5456#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 5457#define regCM2_CM_POST_CSC_B_C13_C14 0x0fff 5458#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5459#define regCM2_CM_POST_CSC_B_C21_C22 0x1000 5460#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5461#define regCM2_CM_POST_CSC_B_C23_C24 0x1001 5462#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5463#define regCM2_CM_POST_CSC_B_C31_C32 0x1002 5464#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5465#define regCM2_CM_POST_CSC_B_C33_C34 0x1003 5466#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5467#define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 5468#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5469#define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 5470#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5471#define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 5472#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5473#define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 5474#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5475#define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 5476#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5477#define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 5478#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5479#define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a 5480#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5481#define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b 5482#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5483#define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c 5484#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5485#define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d 5486#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5487#define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e 5488#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5489#define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f 5490#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5491#define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 5492#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5493#define regCM2_CM_BIAS_CR_R 0x1011 5494#define regCM2_CM_BIAS_CR_R_BASE_IDX 2 5495#define regCM2_CM_BIAS_Y_G_CB_B 0x1012 5496#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5497#define regCM2_CM_GAMCOR_CONTROL 0x1013 5498#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 5499#define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 5500#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5501#define regCM2_CM_GAMCOR_LUT_DATA 0x1015 5502#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5503#define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 5504#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5505#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 5506#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5507#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 5508#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5509#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 5510#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5511#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a 5512#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5513#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b 5514#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5515#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c 5516#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5517#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d 5518#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5519#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e 5520#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5521#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f 5522#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5523#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 5524#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5525#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 5526#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5527#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 5528#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5529#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 5530#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5531#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 5532#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5533#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 5534#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5535#define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 5536#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5537#define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 5538#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5539#define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 5540#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5541#define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 5542#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5543#define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a 5544#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5545#define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b 5546#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5547#define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c 5548#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5549#define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d 5550#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5551#define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e 5552#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5553#define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f 5554#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5555#define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 5556#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5557#define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 5558#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5559#define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 5560#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5561#define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 5562#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5563#define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 5564#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5565#define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 5566#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5567#define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 5568#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5569#define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 5570#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5571#define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 5572#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5573#define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 5574#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5575#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a 5576#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5577#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b 5578#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5579#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c 5580#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5581#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d 5582#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5583#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e 5584#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5585#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f 5586#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5587#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 5588#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5589#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 5590#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5591#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 5592#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5593#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 5594#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5595#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 5596#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5597#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 5598#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5599#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 5600#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5601#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 5602#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5603#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 5604#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5605#define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 5606#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5607#define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a 5608#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5609#define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b 5610#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5611#define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c 5612#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5613#define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d 5614#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5615#define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e 5616#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5617#define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f 5618#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5619#define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 5620#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5621#define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 5622#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5623#define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 5624#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5625#define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 5626#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5627#define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 5628#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5629#define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 5630#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5631#define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 5632#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5633#define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 5634#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 5635#define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 5636#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 5637#define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 5638#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 5639#define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a 5640#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 5641#define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b 5642#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 5643#define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c 5644#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 5645#define regCM2_CM_BLNDGAM_CONTROL 0x105d 5646#define regCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2 5647#define regCM2_CM_BLNDGAM_LUT_INDEX 0x105e 5648#define regCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 5649#define regCM2_CM_BLNDGAM_LUT_DATA 0x105f 5650#define regCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 5651#define regCM2_CM_BLNDGAM_LUT_CONTROL 0x1060 5652#define regCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 5653#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x1061 5654#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 5655#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x1062 5656#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 5657#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x1063 5658#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 5659#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x1064 5660#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5661#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x1065 5662#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5663#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x1066 5664#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5665#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x1067 5666#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5667#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x1068 5668#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5669#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x1069 5670#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5671#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x106a 5672#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 5673#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x106b 5674#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 5675#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x106c 5676#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 5677#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x106d 5678#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 5679#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x106e 5680#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 5681#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x106f 5682#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 5683#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B 0x1070 5684#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 5685#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G 0x1071 5686#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 5687#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R 0x1072 5688#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 5689#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1073 5690#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 5691#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x1074 5692#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 5693#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x1075 5694#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 5695#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x1076 5696#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 5697#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x1077 5698#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 5699#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x1078 5700#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 5701#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x1079 5702#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 5703#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x107a 5704#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 5705#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x107b 5706#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 5707#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x107c 5708#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 5709#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x107d 5710#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 5711#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x107e 5712#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 5713#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x107f 5714#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 5715#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1080 5716#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 5717#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1081 5718#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 5719#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1082 5720#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 5721#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1083 5722#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 5723#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x1084 5724#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 5725#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x1085 5726#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 5727#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x1086 5728#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 5729#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x1087 5730#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5731#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x1088 5732#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5733#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x1089 5734#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5735#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x108a 5736#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5737#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x108b 5738#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5739#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x108c 5740#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5741#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x108d 5742#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5743#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x108e 5744#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5745#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x108f 5746#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5747#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1090 5748#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5749#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1091 5750#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5751#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1092 5752#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5753#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B 0x1093 5754#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 5755#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G 0x1094 5756#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 5757#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R 0x1095 5758#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 5759#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1096 5760#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 5761#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1097 5762#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 5763#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1098 5764#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 5765#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1099 5766#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 5767#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x109a 5768#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 5769#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x109b 5770#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 5771#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x109c 5772#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 5773#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x109d 5774#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 5775#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x109e 5776#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 5777#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x109f 5778#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 5779#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x10a0 5780#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 5781#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x10a1 5782#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 5783#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x10a2 5784#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 5785#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x10a3 5786#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 5787#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x10a4 5788#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 5789#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x10a5 5790#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 5791#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x10a6 5792#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 5793#define regCM2_CM_HDR_MULT_COEF 0x10a7 5794#define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 5795#define regCM2_CM_MEM_PWR_CTRL 0x10a8 5796#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 5797#define regCM2_CM_MEM_PWR_STATUS 0x10a9 5798#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 5799#define regCM2_CM_DEALPHA 0x10ab 5800#define regCM2_CM_DEALPHA_BASE_IDX 2 5801#define regCM2_CM_COEF_FORMAT 0x10ac 5802#define regCM2_CM_COEF_FORMAT_BASE_IDX 2 5803#define regCM2_CM_SHAPER_CONTROL 0x10ad 5804#define regCM2_CM_SHAPER_CONTROL_BASE_IDX 2 5805#define regCM2_CM_SHAPER_OFFSET_R 0x10ae 5806#define regCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2 5807#define regCM2_CM_SHAPER_OFFSET_G 0x10af 5808#define regCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2 5809#define regCM2_CM_SHAPER_OFFSET_B 0x10b0 5810#define regCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2 5811#define regCM2_CM_SHAPER_SCALE_R 0x10b1 5812#define regCM2_CM_SHAPER_SCALE_R_BASE_IDX 2 5813#define regCM2_CM_SHAPER_SCALE_G_B 0x10b2 5814#define regCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2 5815#define regCM2_CM_SHAPER_LUT_INDEX 0x10b3 5816#define regCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2 5817#define regCM2_CM_SHAPER_LUT_DATA 0x10b4 5818#define regCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2 5819#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x10b5 5820#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 5821#define regCM2_CM_SHAPER_RAMA_START_CNTL_B 0x10b6 5822#define regCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 5823#define regCM2_CM_SHAPER_RAMA_START_CNTL_G 0x10b7 5824#define regCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 5825#define regCM2_CM_SHAPER_RAMA_START_CNTL_R 0x10b8 5826#define regCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 5827#define regCM2_CM_SHAPER_RAMA_END_CNTL_B 0x10b9 5828#define regCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 5829#define regCM2_CM_SHAPER_RAMA_END_CNTL_G 0x10ba 5830#define regCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 5831#define regCM2_CM_SHAPER_RAMA_END_CNTL_R 0x10bb 5832#define regCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 5833#define regCM2_CM_SHAPER_RAMA_REGION_0_1 0x10bc 5834#define regCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 5835#define regCM2_CM_SHAPER_RAMA_REGION_2_3 0x10bd 5836#define regCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 5837#define regCM2_CM_SHAPER_RAMA_REGION_4_5 0x10be 5838#define regCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 5839#define regCM2_CM_SHAPER_RAMA_REGION_6_7 0x10bf 5840#define regCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 5841#define regCM2_CM_SHAPER_RAMA_REGION_8_9 0x10c0 5842#define regCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 5843#define regCM2_CM_SHAPER_RAMA_REGION_10_11 0x10c1 5844#define regCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 5845#define regCM2_CM_SHAPER_RAMA_REGION_12_13 0x10c2 5846#define regCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 5847#define regCM2_CM_SHAPER_RAMA_REGION_14_15 0x10c3 5848#define regCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 5849#define regCM2_CM_SHAPER_RAMA_REGION_16_17 0x10c4 5850#define regCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 5851#define regCM2_CM_SHAPER_RAMA_REGION_18_19 0x10c5 5852#define regCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 5853#define regCM2_CM_SHAPER_RAMA_REGION_20_21 0x10c6 5854#define regCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 5855#define regCM2_CM_SHAPER_RAMA_REGION_22_23 0x10c7 5856#define regCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 5857#define regCM2_CM_SHAPER_RAMA_REGION_24_25 0x10c8 5858#define regCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 5859#define regCM2_CM_SHAPER_RAMA_REGION_26_27 0x10c9 5860#define regCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 5861#define regCM2_CM_SHAPER_RAMA_REGION_28_29 0x10ca 5862#define regCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 5863#define regCM2_CM_SHAPER_RAMA_REGION_30_31 0x10cb 5864#define regCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 5865#define regCM2_CM_SHAPER_RAMA_REGION_32_33 0x10cc 5866#define regCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 5867#define regCM2_CM_SHAPER_RAMB_START_CNTL_B 0x10cd 5868#define regCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 5869#define regCM2_CM_SHAPER_RAMB_START_CNTL_G 0x10ce 5870#define regCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 5871#define regCM2_CM_SHAPER_RAMB_START_CNTL_R 0x10cf 5872#define regCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 5873#define regCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10d0 5874#define regCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 5875#define regCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10d1 5876#define regCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 5877#define regCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10d2 5878#define regCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 5879#define regCM2_CM_SHAPER_RAMB_REGION_0_1 0x10d3 5880#define regCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 5881#define regCM2_CM_SHAPER_RAMB_REGION_2_3 0x10d4 5882#define regCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 5883#define regCM2_CM_SHAPER_RAMB_REGION_4_5 0x10d5 5884#define regCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 5885#define regCM2_CM_SHAPER_RAMB_REGION_6_7 0x10d6 5886#define regCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 5887#define regCM2_CM_SHAPER_RAMB_REGION_8_9 0x10d7 5888#define regCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 5889#define regCM2_CM_SHAPER_RAMB_REGION_10_11 0x10d8 5890#define regCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 5891#define regCM2_CM_SHAPER_RAMB_REGION_12_13 0x10d9 5892#define regCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 5893#define regCM2_CM_SHAPER_RAMB_REGION_14_15 0x10da 5894#define regCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 5895#define regCM2_CM_SHAPER_RAMB_REGION_16_17 0x10db 5896#define regCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 5897#define regCM2_CM_SHAPER_RAMB_REGION_18_19 0x10dc 5898#define regCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 5899#define regCM2_CM_SHAPER_RAMB_REGION_20_21 0x10dd 5900#define regCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 5901#define regCM2_CM_SHAPER_RAMB_REGION_22_23 0x10de 5902#define regCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 5903#define regCM2_CM_SHAPER_RAMB_REGION_24_25 0x10df 5904#define regCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 5905#define regCM2_CM_SHAPER_RAMB_REGION_26_27 0x10e0 5906#define regCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 5907#define regCM2_CM_SHAPER_RAMB_REGION_28_29 0x10e1 5908#define regCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 5909#define regCM2_CM_SHAPER_RAMB_REGION_30_31 0x10e2 5910#define regCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 5911#define regCM2_CM_SHAPER_RAMB_REGION_32_33 0x10e3 5912#define regCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 5913#define regCM2_CM_MEM_PWR_CTRL2 0x10e4 5914#define regCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2 5915#define regCM2_CM_MEM_PWR_STATUS2 0x10e5 5916#define regCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2 5917#define regCM2_CM_3DLUT_MODE 0x10e6 5918#define regCM2_CM_3DLUT_MODE_BASE_IDX 2 5919#define regCM2_CM_3DLUT_INDEX 0x10e7 5920#define regCM2_CM_3DLUT_INDEX_BASE_IDX 2 5921#define regCM2_CM_3DLUT_DATA 0x10e8 5922#define regCM2_CM_3DLUT_DATA_BASE_IDX 2 5923#define regCM2_CM_3DLUT_DATA_30BIT 0x10e9 5924#define regCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5925#define regCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ea 5926#define regCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5927#define regCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10eb 5928#define regCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5929#define regCM2_CM_3DLUT_OUT_OFFSET_R 0x10ec 5930#define regCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5931#define regCM2_CM_3DLUT_OUT_OFFSET_G 0x10ed 5932#define regCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5933#define regCM2_CM_3DLUT_OUT_OFFSET_B 0x10ee 5934#define regCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5935#define regCM2_CM_TEST_DEBUG_INDEX 0x10ef 5936#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5937#define regCM2_CM_TEST_DEBUG_DATA 0x10f0 5938#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 5939 5940 5941// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec 5942// base address: 0xb58 5943#define regDPP_TOP2_DPP_CONTROL 0x0f9b 5944#define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 5945#define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c 5946#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 5947#define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d 5948#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 5949#define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e 5950#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 5951#define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f 5952#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 5953#define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 5954#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 5955 5956 5957// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5958// base address: 0x43e8 5959#define regDC_PERFMON13_PERFCOUNTER_CNTL 0x10fa 5960#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 5961#define regDC_PERFMON13_PERFCOUNTER_CNTL2 0x10fb 5962#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 5963#define regDC_PERFMON13_PERFCOUNTER_STATE 0x10fc 5964#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 5965#define regDC_PERFMON13_PERFMON_CNTL 0x10fd 5966#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 5967#define regDC_PERFMON13_PERFMON_CNTL2 0x10fe 5968#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 5969#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x10ff 5970#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5971#define regDC_PERFMON13_PERFMON_CVALUE_LOW 0x1100 5972#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 5973#define regDC_PERFMON13_PERFMON_HI 0x1101 5974#define regDC_PERFMON13_PERFMON_HI_BASE_IDX 2 5975#define regDC_PERFMON13_PERFMON_LOW 0x1102 5976#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 5977 5978 5979// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec 5980// base address: 0x1104 5981#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 5982#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5983#define regCNVC_CFG3_FORMAT_CONTROL 0x1111 5984#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 5985#define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 5986#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 5987#define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 5988#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 5989#define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 5990#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 5991#define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 5992#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 5993#define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 5994#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 5995#define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 5996#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 5997#define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 5998#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 5999#define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 6000#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 6001#define regCNVC_CFG3_COLOR_KEYER_RED 0x111a 6002#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 6003#define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b 6004#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 6005#define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c 6006#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 6007#define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e 6008#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 6009#define regCNVC_CFG3_PRE_DEALPHA 0x111f 6010#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 6011#define regCNVC_CFG3_PRE_CSC_MODE 0x1120 6012#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 6013#define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 6014#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 6015#define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 6016#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 6017#define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 6018#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 6019#define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 6020#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 6021#define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 6022#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 6023#define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 6024#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 6025#define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 6026#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 6027#define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 6028#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 6029#define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 6030#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 6031#define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a 6032#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 6033#define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b 6034#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 6035#define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c 6036#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 6037#define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d 6038#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 6039#define regCNVC_CFG3_PRE_DEGAM 0x112e 6040#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 6041#define regCNVC_CFG3_PRE_REALPHA 0x112f 6042#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 6043 6044 6045// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec 6046// base address: 0x1104 6047#define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 6048#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 6049#define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 6050#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 6051#define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 6052#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 6053#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 6054#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 6055 6056 6057// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec 6058// base address: 0x1104 6059#define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a 6060#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 6061#define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b 6062#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 6063#define regDSCL3_SCL_MODE 0x113c 6064#define regDSCL3_SCL_MODE_BASE_IDX 2 6065#define regDSCL3_SCL_TAP_CONTROL 0x113d 6066#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 6067#define regDSCL3_DSCL_CONTROL 0x113e 6068#define regDSCL3_DSCL_CONTROL_BASE_IDX 2 6069#define regDSCL3_DSCL_2TAP_CONTROL 0x113f 6070#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 6071#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 6072#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 6073#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 6074#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 6075#define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 6076#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 6077#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 6078#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 6079#define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 6080#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 6081#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 6082#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 6083#define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 6084#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 6085#define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 6086#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 6087#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 6088#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 6089#define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 6090#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 6091#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a 6092#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 6093#define regDSCL3_SCL_BLACK_COLOR 0x114b 6094#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 6095#define regDSCL3_DSCL_UPDATE 0x114c 6096#define regDSCL3_DSCL_UPDATE_BASE_IDX 2 6097#define regDSCL3_DSCL_AUTOCAL 0x114d 6098#define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 6099#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e 6100#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 6101#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f 6102#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 6103#define regDSCL3_OTG_H_BLANK 0x1150 6104#define regDSCL3_OTG_H_BLANK_BASE_IDX 2 6105#define regDSCL3_OTG_V_BLANK 0x1151 6106#define regDSCL3_OTG_V_BLANK_BASE_IDX 2 6107#define regDSCL3_RECOUT_START 0x1152 6108#define regDSCL3_RECOUT_START_BASE_IDX 2 6109#define regDSCL3_RECOUT_SIZE 0x1153 6110#define regDSCL3_RECOUT_SIZE_BASE_IDX 2 6111#define regDSCL3_MPC_SIZE 0x1154 6112#define regDSCL3_MPC_SIZE_BASE_IDX 2 6113#define regDSCL3_LB_DATA_FORMAT 0x1155 6114#define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 6115#define regDSCL3_LB_MEMORY_CTRL 0x1156 6116#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 6117#define regDSCL3_LB_V_COUNTER 0x1157 6118#define regDSCL3_LB_V_COUNTER_BASE_IDX 2 6119#define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 6120#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 6121#define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 6122#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 6123#define regDSCL3_OBUF_CONTROL 0x115a 6124#define regDSCL3_OBUF_CONTROL_BASE_IDX 2 6125#define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b 6126#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 6127 6128 6129// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec 6130// base address: 0x1104 6131#define regCM3_CM_CONTROL 0x1161 6132#define regCM3_CM_CONTROL_BASE_IDX 2 6133#define regCM3_CM_POST_CSC_CONTROL 0x1162 6134#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 6135#define regCM3_CM_POST_CSC_C11_C12 0x1163 6136#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 6137#define regCM3_CM_POST_CSC_C13_C14 0x1164 6138#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 6139#define regCM3_CM_POST_CSC_C21_C22 0x1165 6140#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 6141#define regCM3_CM_POST_CSC_C23_C24 0x1166 6142#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 6143#define regCM3_CM_POST_CSC_C31_C32 0x1167 6144#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 6145#define regCM3_CM_POST_CSC_C33_C34 0x1168 6146#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 6147#define regCM3_CM_POST_CSC_B_C11_C12 0x1169 6148#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 6149#define regCM3_CM_POST_CSC_B_C13_C14 0x116a 6150#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 6151#define regCM3_CM_POST_CSC_B_C21_C22 0x116b 6152#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 6153#define regCM3_CM_POST_CSC_B_C23_C24 0x116c 6154#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 6155#define regCM3_CM_POST_CSC_B_C31_C32 0x116d 6156#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 6157#define regCM3_CM_POST_CSC_B_C33_C34 0x116e 6158#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 6159#define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f 6160#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 6161#define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 6162#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 6163#define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 6164#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 6165#define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 6166#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 6167#define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 6168#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 6169#define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 6170#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 6171#define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 6172#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 6173#define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 6174#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 6175#define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 6176#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 6177#define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 6178#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 6179#define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 6180#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 6181#define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a 6182#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 6183#define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b 6184#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 6185#define regCM3_CM_BIAS_CR_R 0x117c 6186#define regCM3_CM_BIAS_CR_R_BASE_IDX 2 6187#define regCM3_CM_BIAS_Y_G_CB_B 0x117d 6188#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 6189#define regCM3_CM_GAMCOR_CONTROL 0x117e 6190#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 6191#define regCM3_CM_GAMCOR_LUT_INDEX 0x117f 6192#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 6193#define regCM3_CM_GAMCOR_LUT_DATA 0x1180 6194#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 6195#define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 6196#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 6197#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 6198#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 6199#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 6200#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 6201#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 6202#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 6203#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 6204#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6205#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 6206#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6207#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 6208#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6209#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 6210#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6211#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 6212#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6213#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a 6214#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6215#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b 6216#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 6217#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c 6218#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 6219#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d 6220#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 6221#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e 6222#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 6223#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f 6224#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 6225#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 6226#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 6227#define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 6228#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 6229#define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 6230#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 6231#define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 6232#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 6233#define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 6234#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 6235#define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 6236#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 6237#define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 6238#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 6239#define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 6240#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 6241#define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 6242#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 6243#define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 6244#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 6245#define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a 6246#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 6247#define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b 6248#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 6249#define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c 6250#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 6251#define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d 6252#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 6253#define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e 6254#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 6255#define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f 6256#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 6257#define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 6258#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 6259#define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 6260#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 6261#define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 6262#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 6263#define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 6264#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 6265#define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 6266#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 6267#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 6268#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 6269#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 6270#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 6271#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 6272#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 6273#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 6274#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6275#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 6276#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6277#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa 6278#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6279#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab 6280#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6281#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac 6282#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6283#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad 6284#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6285#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae 6286#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 6287#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af 6288#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 6289#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 6290#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 6291#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 6292#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 6293#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 6294#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 6295#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 6296#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 6297#define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 6298#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 6299#define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 6300#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 6301#define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 6302#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 6303#define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 6304#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 6305#define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 6306#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 6307#define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 6308#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 6309#define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba 6310#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 6311#define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb 6312#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 6313#define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc 6314#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 6315#define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd 6316#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 6317#define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be 6318#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 6319#define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf 6320#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 6321#define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 6322#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 6323#define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 6324#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 6325#define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 6326#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 6327#define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 6328#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 6329#define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 6330#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 6331#define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 6332#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 6333#define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 6334#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 6335#define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 6336#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 6337#define regCM3_CM_BLNDGAM_CONTROL 0x11c8 6338#define regCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2 6339#define regCM3_CM_BLNDGAM_LUT_INDEX 0x11c9 6340#define regCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 6341#define regCM3_CM_BLNDGAM_LUT_DATA 0x11ca 6342#define regCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 6343#define regCM3_CM_BLNDGAM_LUT_CONTROL 0x11cb 6344#define regCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 6345#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11cc 6346#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 6347#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11cd 6348#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 6349#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11ce 6350#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 6351#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x11cf 6352#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6353#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x11d0 6354#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6355#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x11d1 6356#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6357#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x11d2 6358#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6359#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x11d3 6360#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6361#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x11d4 6362#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6363#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11d5 6364#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 6365#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11d6 6366#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 6367#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11d7 6368#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 6369#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11d8 6370#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 6371#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11d9 6372#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 6373#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11da 6374#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 6375#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B 0x11db 6376#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 6377#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G 0x11dc 6378#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 6379#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R 0x11dd 6380#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 6381#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11de 6382#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 6383#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11df 6384#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 6385#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11e0 6386#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 6387#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11e1 6388#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 6389#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11e2 6390#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 6391#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11e3 6392#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 6393#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11e4 6394#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 6395#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11e5 6396#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 6397#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11e6 6398#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 6399#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11e7 6400#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 6401#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11e8 6402#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 6403#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11e9 6404#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 6405#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11ea 6406#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 6407#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11eb 6408#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 6409#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11ec 6410#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 6411#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11ed 6412#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 6413#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11ee 6414#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 6415#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11ef 6416#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 6417#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11f0 6418#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 6419#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11f1 6420#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 6421#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x11f2 6422#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6423#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x11f3 6424#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6425#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x11f4 6426#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6427#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x11f5 6428#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6429#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x11f6 6430#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6431#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x11f7 6432#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6433#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11f8 6434#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 6435#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11f9 6436#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 6437#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11fa 6438#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 6439#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11fb 6440#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 6441#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11fc 6442#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 6443#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11fd 6444#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 6445#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B 0x11fe 6446#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 6447#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G 0x11ff 6448#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 6449#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R 0x1200 6450#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 6451#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x1201 6452#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 6453#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x1202 6454#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 6455#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x1203 6456#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 6457#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x1204 6458#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 6459#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x1205 6460#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 6461#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x1206 6462#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 6463#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x1207 6464#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 6465#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x1208 6466#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 6467#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x1209 6468#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 6469#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x120a 6470#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 6471#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x120b 6472#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 6473#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x120c 6474#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 6475#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x120d 6476#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 6477#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x120e 6478#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 6479#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x120f 6480#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 6481#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x1210 6482#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 6483#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x1211 6484#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 6485#define regCM3_CM_HDR_MULT_COEF 0x1212 6486#define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 6487#define regCM3_CM_MEM_PWR_CTRL 0x1213 6488#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 6489#define regCM3_CM_MEM_PWR_STATUS 0x1214 6490#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 6491#define regCM3_CM_DEALPHA 0x1216 6492#define regCM3_CM_DEALPHA_BASE_IDX 2 6493#define regCM3_CM_COEF_FORMAT 0x1217 6494#define regCM3_CM_COEF_FORMAT_BASE_IDX 2 6495#define regCM3_CM_SHAPER_CONTROL 0x1218 6496#define regCM3_CM_SHAPER_CONTROL_BASE_IDX 2 6497#define regCM3_CM_SHAPER_OFFSET_R 0x1219 6498#define regCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2 6499#define regCM3_CM_SHAPER_OFFSET_G 0x121a 6500#define regCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2 6501#define regCM3_CM_SHAPER_OFFSET_B 0x121b 6502#define regCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2 6503#define regCM3_CM_SHAPER_SCALE_R 0x121c 6504#define regCM3_CM_SHAPER_SCALE_R_BASE_IDX 2 6505#define regCM3_CM_SHAPER_SCALE_G_B 0x121d 6506#define regCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2 6507#define regCM3_CM_SHAPER_LUT_INDEX 0x121e 6508#define regCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2 6509#define regCM3_CM_SHAPER_LUT_DATA 0x121f 6510#define regCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2 6511#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x1220 6512#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 6513#define regCM3_CM_SHAPER_RAMA_START_CNTL_B 0x1221 6514#define regCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 6515#define regCM3_CM_SHAPER_RAMA_START_CNTL_G 0x1222 6516#define regCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 6517#define regCM3_CM_SHAPER_RAMA_START_CNTL_R 0x1223 6518#define regCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 6519#define regCM3_CM_SHAPER_RAMA_END_CNTL_B 0x1224 6520#define regCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 6521#define regCM3_CM_SHAPER_RAMA_END_CNTL_G 0x1225 6522#define regCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 6523#define regCM3_CM_SHAPER_RAMA_END_CNTL_R 0x1226 6524#define regCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 6525#define regCM3_CM_SHAPER_RAMA_REGION_0_1 0x1227 6526#define regCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 6527#define regCM3_CM_SHAPER_RAMA_REGION_2_3 0x1228 6528#define regCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 6529#define regCM3_CM_SHAPER_RAMA_REGION_4_5 0x1229 6530#define regCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 6531#define regCM3_CM_SHAPER_RAMA_REGION_6_7 0x122a 6532#define regCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 6533#define regCM3_CM_SHAPER_RAMA_REGION_8_9 0x122b 6534#define regCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 6535#define regCM3_CM_SHAPER_RAMA_REGION_10_11 0x122c 6536#define regCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 6537#define regCM3_CM_SHAPER_RAMA_REGION_12_13 0x122d 6538#define regCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 6539#define regCM3_CM_SHAPER_RAMA_REGION_14_15 0x122e 6540#define regCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 6541#define regCM3_CM_SHAPER_RAMA_REGION_16_17 0x122f 6542#define regCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 6543#define regCM3_CM_SHAPER_RAMA_REGION_18_19 0x1230 6544#define regCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 6545#define regCM3_CM_SHAPER_RAMA_REGION_20_21 0x1231 6546#define regCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 6547#define regCM3_CM_SHAPER_RAMA_REGION_22_23 0x1232 6548#define regCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 6549#define regCM3_CM_SHAPER_RAMA_REGION_24_25 0x1233 6550#define regCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 6551#define regCM3_CM_SHAPER_RAMA_REGION_26_27 0x1234 6552#define regCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 6553#define regCM3_CM_SHAPER_RAMA_REGION_28_29 0x1235 6554#define regCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 6555#define regCM3_CM_SHAPER_RAMA_REGION_30_31 0x1236 6556#define regCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 6557#define regCM3_CM_SHAPER_RAMA_REGION_32_33 0x1237 6558#define regCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 6559#define regCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1238 6560#define regCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 6561#define regCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1239 6562#define regCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 6563#define regCM3_CM_SHAPER_RAMB_START_CNTL_R 0x123a 6564#define regCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 6565#define regCM3_CM_SHAPER_RAMB_END_CNTL_B 0x123b 6566#define regCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 6567#define regCM3_CM_SHAPER_RAMB_END_CNTL_G 0x123c 6568#define regCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 6569#define regCM3_CM_SHAPER_RAMB_END_CNTL_R 0x123d 6570#define regCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 6571#define regCM3_CM_SHAPER_RAMB_REGION_0_1 0x123e 6572#define regCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 6573#define regCM3_CM_SHAPER_RAMB_REGION_2_3 0x123f 6574#define regCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 6575#define regCM3_CM_SHAPER_RAMB_REGION_4_5 0x1240 6576#define regCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 6577#define regCM3_CM_SHAPER_RAMB_REGION_6_7 0x1241 6578#define regCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 6579#define regCM3_CM_SHAPER_RAMB_REGION_8_9 0x1242 6580#define regCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 6581#define regCM3_CM_SHAPER_RAMB_REGION_10_11 0x1243 6582#define regCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 6583#define regCM3_CM_SHAPER_RAMB_REGION_12_13 0x1244 6584#define regCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 6585#define regCM3_CM_SHAPER_RAMB_REGION_14_15 0x1245 6586#define regCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 6587#define regCM3_CM_SHAPER_RAMB_REGION_16_17 0x1246 6588#define regCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 6589#define regCM3_CM_SHAPER_RAMB_REGION_18_19 0x1247 6590#define regCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 6591#define regCM3_CM_SHAPER_RAMB_REGION_20_21 0x1248 6592#define regCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 6593#define regCM3_CM_SHAPER_RAMB_REGION_22_23 0x1249 6594#define regCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 6595#define regCM3_CM_SHAPER_RAMB_REGION_24_25 0x124a 6596#define regCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 6597#define regCM3_CM_SHAPER_RAMB_REGION_26_27 0x124b 6598#define regCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 6599#define regCM3_CM_SHAPER_RAMB_REGION_28_29 0x124c 6600#define regCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 6601#define regCM3_CM_SHAPER_RAMB_REGION_30_31 0x124d 6602#define regCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 6603#define regCM3_CM_SHAPER_RAMB_REGION_32_33 0x124e 6604#define regCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 6605#define regCM3_CM_MEM_PWR_CTRL2 0x124f 6606#define regCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2 6607#define regCM3_CM_MEM_PWR_STATUS2 0x1250 6608#define regCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2 6609#define regCM3_CM_3DLUT_MODE 0x1251 6610#define regCM3_CM_3DLUT_MODE_BASE_IDX 2 6611#define regCM3_CM_3DLUT_INDEX 0x1252 6612#define regCM3_CM_3DLUT_INDEX_BASE_IDX 2 6613#define regCM3_CM_3DLUT_DATA 0x1253 6614#define regCM3_CM_3DLUT_DATA_BASE_IDX 2 6615#define regCM3_CM_3DLUT_DATA_30BIT 0x1254 6616#define regCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2 6617#define regCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1255 6618#define regCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 6619#define regCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1256 6620#define regCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 6621#define regCM3_CM_3DLUT_OUT_OFFSET_R 0x1257 6622#define regCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 6623#define regCM3_CM_3DLUT_OUT_OFFSET_G 0x1258 6624#define regCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 6625#define regCM3_CM_3DLUT_OUT_OFFSET_B 0x1259 6626#define regCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 6627#define regCM3_CM_TEST_DEBUG_INDEX 0x125a 6628#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 6629#define regCM3_CM_TEST_DEBUG_DATA 0x125b 6630#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 6631 6632 6633// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec 6634// base address: 0x1104 6635#define regDPP_TOP3_DPP_CONTROL 0x1106 6636#define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 6637#define regDPP_TOP3_DPP_SOFT_RESET 0x1107 6638#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 6639#define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 6640#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 6641#define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 6642#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 6643#define regDPP_TOP3_DPP_CRC_CTRL 0x110a 6644#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 6645#define regDPP_TOP3_HOST_READ_CONTROL 0x110b 6646#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 6647 6648 6649// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 6650// base address: 0x4994 6651#define regDC_PERFMON14_PERFCOUNTER_CNTL 0x1265 6652#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 6653#define regDC_PERFMON14_PERFCOUNTER_CNTL2 0x1266 6654#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 6655#define regDC_PERFMON14_PERFCOUNTER_STATE 0x1267 6656#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 6657#define regDC_PERFMON14_PERFMON_CNTL 0x1268 6658#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 6659#define regDC_PERFMON14_PERFMON_CNTL2 0x1269 6660#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 6661#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x126a 6662#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 6663#define regDC_PERFMON14_PERFMON_CVALUE_LOW 0x126b 6664#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 6665#define regDC_PERFMON14_PERFMON_HI 0x126c 6666#define regDC_PERFMON14_PERFMON_HI_BASE_IDX 2 6667#define regDC_PERFMON14_PERFMON_LOW 0x126d 6668#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 6669 6670 6671// addressBlock: dce_dc_mpc_mpcc0_dispdec 6672// base address: 0x0 6673#define regMPCC0_MPCC_TOP_SEL 0x0000 6674#define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 6675#define regMPCC0_MPCC_BOT_SEL 0x0001 6676#define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 6677#define regMPCC0_MPCC_OPP_ID 0x0002 6678#define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 6679#define regMPCC0_MPCC_CONTROL 0x0003 6680#define regMPCC0_MPCC_CONTROL_BASE_IDX 3 6681#define regMPCC0_MPCC_SM_CONTROL 0x0004 6682#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 6683#define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 6684#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6685#define regMPCC0_MPCC_TOP_GAIN 0x0006 6686#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 6687#define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 6688#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6689#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 6690#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6691#define regMPCC0_MPCC_BG_R_CR 0x0009 6692#define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 6693#define regMPCC0_MPCC_BG_G_Y 0x000a 6694#define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 6695#define regMPCC0_MPCC_BG_B_CB 0x000b 6696#define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 6697#define regMPCC0_MPCC_MEM_PWR_CTRL 0x000c 6698#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6699#define regMPCC0_MPCC_STATUS 0x000d 6700#define regMPCC0_MPCC_STATUS_BASE_IDX 3 6701 6702 6703// addressBlock: dce_dc_mpc_mpcc1_dispdec 6704// base address: 0x80 6705#define regMPCC1_MPCC_TOP_SEL 0x0020 6706#define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 6707#define regMPCC1_MPCC_BOT_SEL 0x0021 6708#define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 6709#define regMPCC1_MPCC_OPP_ID 0x0022 6710#define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 6711#define regMPCC1_MPCC_CONTROL 0x0023 6712#define regMPCC1_MPCC_CONTROL_BASE_IDX 3 6713#define regMPCC1_MPCC_SM_CONTROL 0x0024 6714#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 6715#define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025 6716#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6717#define regMPCC1_MPCC_TOP_GAIN 0x0026 6718#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 6719#define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027 6720#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6721#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028 6722#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6723#define regMPCC1_MPCC_BG_R_CR 0x0029 6724#define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 6725#define regMPCC1_MPCC_BG_G_Y 0x002a 6726#define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 6727#define regMPCC1_MPCC_BG_B_CB 0x002b 6728#define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 6729#define regMPCC1_MPCC_MEM_PWR_CTRL 0x002c 6730#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6731#define regMPCC1_MPCC_STATUS 0x002d 6732#define regMPCC1_MPCC_STATUS_BASE_IDX 3 6733 6734 6735// addressBlock: dce_dc_mpc_mpcc2_dispdec 6736// base address: 0x100 6737#define regMPCC2_MPCC_TOP_SEL 0x0040 6738#define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 6739#define regMPCC2_MPCC_BOT_SEL 0x0041 6740#define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 6741#define regMPCC2_MPCC_OPP_ID 0x0042 6742#define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 6743#define regMPCC2_MPCC_CONTROL 0x0043 6744#define regMPCC2_MPCC_CONTROL_BASE_IDX 3 6745#define regMPCC2_MPCC_SM_CONTROL 0x0044 6746#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 6747#define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x0045 6748#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6749#define regMPCC2_MPCC_TOP_GAIN 0x0046 6750#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 6751#define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0047 6752#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6753#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0048 6754#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6755#define regMPCC2_MPCC_BG_R_CR 0x0049 6756#define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 6757#define regMPCC2_MPCC_BG_G_Y 0x004a 6758#define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 6759#define regMPCC2_MPCC_BG_B_CB 0x004b 6760#define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 6761#define regMPCC2_MPCC_MEM_PWR_CTRL 0x004c 6762#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6763#define regMPCC2_MPCC_STATUS 0x004d 6764#define regMPCC2_MPCC_STATUS_BASE_IDX 3 6765 6766 6767// addressBlock: dce_dc_mpc_mpcc3_dispdec 6768// base address: 0x180 6769#define regMPCC3_MPCC_TOP_SEL 0x0060 6770#define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 6771#define regMPCC3_MPCC_BOT_SEL 0x0061 6772#define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 6773#define regMPCC3_MPCC_OPP_ID 0x0062 6774#define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 6775#define regMPCC3_MPCC_CONTROL 0x0063 6776#define regMPCC3_MPCC_CONTROL_BASE_IDX 3 6777#define regMPCC3_MPCC_SM_CONTROL 0x0064 6778#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 6779#define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0065 6780#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6781#define regMPCC3_MPCC_TOP_GAIN 0x0066 6782#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 6783#define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0067 6784#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6785#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0068 6786#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6787#define regMPCC3_MPCC_BG_R_CR 0x0069 6788#define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 6789#define regMPCC3_MPCC_BG_G_Y 0x006a 6790#define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 6791#define regMPCC3_MPCC_BG_B_CB 0x006b 6792#define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 6793#define regMPCC3_MPCC_MEM_PWR_CTRL 0x006c 6794#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6795#define regMPCC3_MPCC_STATUS 0x006d 6796#define regMPCC3_MPCC_STATUS_BASE_IDX 3 6797 6798 6799// addressBlock: dce_dc_mpc_mpc_cfg_dispdec 6800// base address: 0x0 6801#define regMPC_CLOCK_CONTROL 0x0500 6802#define regMPC_CLOCK_CONTROL_BASE_IDX 3 6803#define regMPC_SOFT_RESET 0x0501 6804#define regMPC_SOFT_RESET_BASE_IDX 3 6805#define regMPC_CRC_CTRL 0x0502 6806#define regMPC_CRC_CTRL_BASE_IDX 3 6807#define regMPC_CRC_SEL_CONTROL 0x0503 6808#define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 6809#define regMPC_CRC_RESULT_AR 0x0504 6810#define regMPC_CRC_RESULT_AR_BASE_IDX 3 6811#define regMPC_CRC_RESULT_GB 0x0505 6812#define regMPC_CRC_RESULT_GB_BASE_IDX 3 6813#define regMPC_CRC_RESULT_C 0x0506 6814#define regMPC_CRC_RESULT_C_BASE_IDX 3 6815#define regMPC_PERFMON_EVENT_CTRL 0x0509 6816#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 6817#define regMPC_BYPASS_BG_AR 0x050a 6818#define regMPC_BYPASS_BG_AR_BASE_IDX 3 6819#define regMPC_BYPASS_BG_GB 0x050b 6820#define regMPC_BYPASS_BG_GB_BASE_IDX 3 6821#define regMPC_HOST_READ_CONTROL 0x050c 6822#define regMPC_HOST_READ_CONTROL_BASE_IDX 3 6823#define regMPC_DPP_PENDING_STATUS 0x050d 6824#define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 6825#define regMPC_PENDING_STATUS_MISC 0x050e 6826#define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 6827#define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f 6828#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 6829#define regADR_CFG_VUPDATE_LOCK_SET0 0x0510 6830#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 6831#define regADR_VUPDATE_LOCK_SET0 0x0511 6832#define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 6833#define regCFG_VUPDATE_LOCK_SET0 0x0512 6834#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 6835#define regCUR_VUPDATE_LOCK_SET0 0x0513 6836#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 6837#define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514 6838#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 6839#define regADR_CFG_VUPDATE_LOCK_SET1 0x0515 6840#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 6841#define regADR_VUPDATE_LOCK_SET1 0x0516 6842#define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 6843#define regCFG_VUPDATE_LOCK_SET1 0x0517 6844#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 6845#define regCUR_VUPDATE_LOCK_SET1 0x0518 6846#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 6847#define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x0519 6848#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 6849#define regADR_CFG_VUPDATE_LOCK_SET2 0x051a 6850#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 6851#define regADR_VUPDATE_LOCK_SET2 0x051b 6852#define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 6853#define regCFG_VUPDATE_LOCK_SET2 0x051c 6854#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 6855#define regCUR_VUPDATE_LOCK_SET2 0x051d 6856#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 6857#define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x051e 6858#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 6859#define regADR_CFG_VUPDATE_LOCK_SET3 0x051f 6860#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 6861#define regADR_VUPDATE_LOCK_SET3 0x0520 6862#define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 6863#define regCFG_VUPDATE_LOCK_SET3 0x0521 6864#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 6865#define regCUR_VUPDATE_LOCK_SET3 0x0522 6866#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 6867#define regMPC_DWB0_MUX 0x055c 6868#define regMPC_DWB0_MUX_BASE_IDX 3 6869 6870 6871// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec 6872// base address: 0x1901c 6873#define regDC_PERFMON15_PERFCOUNTER_CNTL 0x08c7 6874#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 3 6875#define regDC_PERFMON15_PERFCOUNTER_CNTL2 0x08c8 6876#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 3 6877#define regDC_PERFMON15_PERFCOUNTER_STATE 0x08c9 6878#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 3 6879#define regDC_PERFMON15_PERFMON_CNTL 0x08ca 6880#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX 3 6881#define regDC_PERFMON15_PERFMON_CNTL2 0x08cb 6882#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 3 6883#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x08cc 6884#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 6885#define regDC_PERFMON15_PERFMON_CVALUE_LOW 0x08cd 6886#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 3 6887#define regDC_PERFMON15_PERFMON_HI 0x08ce 6888#define regDC_PERFMON15_PERFMON_HI_BASE_IDX 3 6889#define regDC_PERFMON15_PERFMON_LOW 0x08cf 6890#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 6891 6892 6893// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec 6894// base address: 0x0 6895#define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100 6896#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 6897#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101 6898#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 6899#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102 6900#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 6901#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103 6902#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 6903#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104 6904#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 6905#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105 6906#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 6907#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106 6908#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 6909#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107 6910#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6911#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108 6912#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6913#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109 6914#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6915#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a 6916#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6917#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b 6918#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6919#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c 6920#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6921#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d 6922#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 6923#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e 6924#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 6925#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f 6926#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 6927#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110 6928#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 6929#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111 6930#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 6931#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112 6932#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 6933#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113 6934#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 6935#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114 6936#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 6937#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115 6938#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 6939#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116 6940#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 6941#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117 6942#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 6943#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118 6944#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 6945#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119 6946#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 6947#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a 6948#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 6949#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b 6950#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 6951#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c 6952#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 6953#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d 6954#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 6955#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e 6956#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 6957#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f 6958#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 6959#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120 6960#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 6961#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121 6962#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 6963#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122 6964#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 6965#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123 6966#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 6967#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124 6968#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 6969#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125 6970#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 6971#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126 6972#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 6973#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127 6974#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 6975#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128 6976#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 6977#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129 6978#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 6979#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a 6980#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6981#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b 6982#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6983#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c 6984#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6985#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d 6986#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6987#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e 6988#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6989#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f 6990#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6991#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130 6992#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 6993#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131 6994#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 6995#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132 6996#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 6997#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133 6998#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 6999#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134 7000#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 7001#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135 7002#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 7003#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136 7004#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 7005#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137 7006#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 7007#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138 7008#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 7009#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139 7010#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 7011#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a 7012#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 7013#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b 7014#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 7015#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c 7016#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 7017#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d 7018#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 7019#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e 7020#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 7021#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f 7022#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 7023#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140 7024#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 7025#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141 7026#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 7027#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142 7028#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 7029#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143 7030#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 7031#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144 7032#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 7033#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145 7034#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 7035#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146 7036#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 7037#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147 7038#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 7039#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148 7040#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 7041#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149 7042#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 7043#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a 7044#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7045#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b 7046#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 7047#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c 7048#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7049#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d 7050#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7051#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e 7052#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7053#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f 7054#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7055#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150 7056#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7057#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151 7058#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7059#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152 7060#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7061#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153 7062#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7063#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154 7064#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7065#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155 7066#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7067#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156 7068#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7069#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157 7070#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7071 7072 7073// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec 7074// base address: 0x200 7075#define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180 7076#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 7077#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181 7078#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 7079#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182 7080#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 7081#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183 7082#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 7083#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184 7084#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 7085#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185 7086#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 7087#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186 7088#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 7089#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187 7090#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 7091#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188 7092#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 7093#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189 7094#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 7095#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a 7096#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 7097#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b 7098#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 7099#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c 7100#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 7101#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d 7102#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 7103#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e 7104#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 7105#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f 7106#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 7107#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190 7108#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 7109#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191 7110#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 7111#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192 7112#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 7113#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193 7114#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 7115#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194 7116#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 7117#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195 7118#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 7119#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196 7120#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 7121#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197 7122#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 7123#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198 7124#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 7125#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199 7126#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 7127#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a 7128#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 7129#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b 7130#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 7131#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c 7132#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 7133#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d 7134#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 7135#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e 7136#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 7137#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f 7138#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 7139#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0 7140#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 7141#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1 7142#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 7143#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2 7144#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 7145#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3 7146#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 7147#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4 7148#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 7149#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5 7150#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 7151#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6 7152#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 7153#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7 7154#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 7155#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8 7156#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 7157#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9 7158#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 7159#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa 7160#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 7161#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab 7162#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 7163#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac 7164#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 7165#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad 7166#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 7167#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae 7168#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 7169#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af 7170#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 7171#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0 7172#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 7173#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1 7174#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 7175#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2 7176#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 7177#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3 7178#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 7179#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4 7180#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 7181#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5 7182#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 7183#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6 7184#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 7185#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7 7186#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 7187#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8 7188#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 7189#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9 7190#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 7191#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba 7192#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 7193#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb 7194#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 7195#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc 7196#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 7197#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd 7198#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 7199#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be 7200#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 7201#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf 7202#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 7203#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0 7204#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 7205#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1 7206#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 7207#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2 7208#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 7209#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3 7210#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 7211#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4 7212#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 7213#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5 7214#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 7215#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6 7216#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 7217#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7 7218#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 7219#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8 7220#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 7221#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9 7222#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 7223#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca 7224#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7225#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb 7226#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 7227#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc 7228#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7229#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd 7230#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7231#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce 7232#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7233#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf 7234#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7235#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0 7236#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7237#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1 7238#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7239#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2 7240#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7241#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3 7242#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7243#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4 7244#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7245#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5 7246#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7247#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6 7248#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7249#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7 7250#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7251 7252 7253// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec 7254// base address: 0x400 7255#define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0200 7256#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 7257#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0201 7258#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 7259#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0202 7260#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 7261#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0203 7262#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 7263#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0204 7264#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 7265#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0205 7266#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 7267#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0206 7268#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 7269#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0207 7270#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 7271#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0208 7272#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 7273#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0209 7274#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 7275#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x020a 7276#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 7277#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x020b 7278#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 7279#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x020c 7280#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 7281#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x020d 7282#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 7283#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x020e 7284#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 7285#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x020f 7286#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 7287#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0210 7288#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 7289#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0211 7290#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 7291#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0212 7292#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 7293#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0213 7294#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 7295#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0214 7296#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 7297#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0215 7298#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 7299#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0216 7300#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 7301#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0217 7302#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 7303#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0218 7304#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 7305#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0219 7306#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 7307#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x021a 7308#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 7309#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x021b 7310#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 7311#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x021c 7312#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 7313#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x021d 7314#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 7315#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x021e 7316#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 7317#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x021f 7318#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 7319#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0220 7320#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 7321#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0221 7322#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 7323#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0222 7324#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 7325#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0223 7326#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 7327#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0224 7328#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 7329#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0225 7330#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 7331#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0226 7332#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 7333#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0227 7334#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 7335#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0228 7336#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 7337#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0229 7338#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 7339#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x022a 7340#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 7341#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x022b 7342#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 7343#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x022c 7344#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 7345#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x022d 7346#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 7347#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x022e 7348#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 7349#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x022f 7350#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 7351#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0230 7352#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 7353#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0231 7354#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 7355#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0232 7356#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 7357#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0233 7358#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 7359#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0234 7360#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 7361#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0235 7362#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 7363#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0236 7364#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 7365#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0237 7366#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 7367#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0238 7368#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 7369#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0239 7370#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 7371#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x023a 7372#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 7373#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x023b 7374#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 7375#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x023c 7376#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 7377#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x023d 7378#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 7379#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x023e 7380#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 7381#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x023f 7382#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 7383#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x0240 7384#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 7385#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x0241 7386#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 7387#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x0242 7388#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 7389#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x0243 7390#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 7391#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x0244 7392#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 7393#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x0245 7394#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 7395#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0246 7396#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 7397#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0247 7398#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 7399#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0248 7400#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 7401#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0249 7402#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 7403#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x024a 7404#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7405#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x024b 7406#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 7407#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x024c 7408#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7409#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x024d 7410#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7411#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x024e 7412#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7413#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x024f 7414#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7415#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x0250 7416#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7417#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x0251 7418#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7419#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x0252 7420#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7421#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x0253 7422#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7423#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x0254 7424#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7425#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x0255 7426#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7427#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0256 7428#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7429#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0257 7430#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7431 7432 7433// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec 7434// base address: 0x600 7435#define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0280 7436#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 7437#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0281 7438#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 7439#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x0282 7440#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 7441#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x0283 7442#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 7443#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x0284 7444#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 7445#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x0285 7446#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 7447#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x0286 7448#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 7449#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0287 7450#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 7451#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0288 7452#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 7453#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0289 7454#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 7455#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x028a 7456#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 7457#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x028b 7458#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 7459#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x028c 7460#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 7461#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x028d 7462#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 7463#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x028e 7464#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 7465#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x028f 7466#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 7467#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x0290 7468#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 7469#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x0291 7470#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 7471#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x0292 7472#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 7473#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x0293 7474#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 7475#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x0294 7476#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 7477#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x0295 7478#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 7479#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x0296 7480#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 7481#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x0297 7482#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 7483#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x0298 7484#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 7485#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x0299 7486#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 7487#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x029a 7488#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 7489#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x029b 7490#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 7491#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x029c 7492#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 7493#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x029d 7494#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 7495#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x029e 7496#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 7497#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x029f 7498#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 7499#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x02a0 7500#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 7501#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x02a1 7502#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 7503#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x02a2 7504#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 7505#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x02a3 7506#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 7507#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x02a4 7508#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 7509#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x02a5 7510#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 7511#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x02a6 7512#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 7513#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x02a7 7514#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 7515#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x02a8 7516#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 7517#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x02a9 7518#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 7519#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x02aa 7520#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 7521#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x02ab 7522#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 7523#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x02ac 7524#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 7525#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x02ad 7526#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 7527#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x02ae 7528#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 7529#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x02af 7530#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 7531#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x02b0 7532#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 7533#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x02b1 7534#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 7535#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x02b2 7536#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 7537#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x02b3 7538#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 7539#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x02b4 7540#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 7541#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x02b5 7542#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 7543#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x02b6 7544#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 7545#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x02b7 7546#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 7547#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x02b8 7548#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 7549#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x02b9 7550#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 7551#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x02ba 7552#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 7553#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x02bb 7554#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 7555#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x02bc 7556#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 7557#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x02bd 7558#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 7559#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x02be 7560#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 7561#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x02bf 7562#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 7563#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x02c0 7564#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 7565#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x02c1 7566#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 7567#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x02c2 7568#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 7569#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x02c3 7570#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 7571#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x02c4 7572#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 7573#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x02c5 7574#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 7575#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x02c6 7576#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 7577#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x02c7 7578#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 7579#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x02c8 7580#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 7581#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x02c9 7582#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 7583#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x02ca 7584#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7585#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x02cb 7586#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 7587#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x02cc 7588#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7589#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x02cd 7590#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7591#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x02ce 7592#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7593#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x02cf 7594#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7595#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x02d0 7596#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7597#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x02d1 7598#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7599#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x02d2 7600#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7601#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x02d3 7602#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7603#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x02d4 7604#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7605#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x02d5 7606#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7607#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x02d6 7608#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7609#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x02d7 7610#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7611 7612 7613// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec 7614// base address: 0x0 7615#define regMPC_OUT0_MUX 0x0580 7616#define regMPC_OUT0_MUX_BASE_IDX 3 7617#define regMPC_OUT0_DENORM_CONTROL 0x0581 7618#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 7619#define regMPC_OUT0_DENORM_CLAMP_G_Y 0x0582 7620#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 7621#define regMPC_OUT0_DENORM_CLAMP_B_CB 0x0583 7622#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 7623#define regMPC_OUT1_MUX 0x0584 7624#define regMPC_OUT1_MUX_BASE_IDX 3 7625#define regMPC_OUT1_DENORM_CONTROL 0x0585 7626#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 7627#define regMPC_OUT1_DENORM_CLAMP_G_Y 0x0586 7628#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 7629#define regMPC_OUT1_DENORM_CLAMP_B_CB 0x0587 7630#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 7631#define regMPC_OUT2_MUX 0x0588 7632#define regMPC_OUT2_MUX_BASE_IDX 3 7633#define regMPC_OUT2_DENORM_CONTROL 0x0589 7634#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 7635#define regMPC_OUT2_DENORM_CLAMP_G_Y 0x058a 7636#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 7637#define regMPC_OUT2_DENORM_CLAMP_B_CB 0x058b 7638#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 7639#define regMPC_OUT3_MUX 0x058c 7640#define regMPC_OUT3_MUX_BASE_IDX 3 7641#define regMPC_OUT3_DENORM_CONTROL 0x058d 7642#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 7643#define regMPC_OUT3_DENORM_CLAMP_G_Y 0x058e 7644#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 7645#define regMPC_OUT3_DENORM_CLAMP_B_CB 0x058f 7646#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 7647#define regMPC_OUT_CSC_COEF_FORMAT 0x05a0 7648#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 7649#define regMPC_OUT0_CSC_MODE 0x05a1 7650#define regMPC_OUT0_CSC_MODE_BASE_IDX 3 7651#define regMPC_OUT0_CSC_C11_C12_A 0x05a2 7652#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 7653#define regMPC_OUT0_CSC_C13_C14_A 0x05a3 7654#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 7655#define regMPC_OUT0_CSC_C21_C22_A 0x05a4 7656#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 7657#define regMPC_OUT0_CSC_C23_C24_A 0x05a5 7658#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 7659#define regMPC_OUT0_CSC_C31_C32_A 0x05a6 7660#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 7661#define regMPC_OUT0_CSC_C33_C34_A 0x05a7 7662#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 7663#define regMPC_OUT0_CSC_C11_C12_B 0x05a8 7664#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 7665#define regMPC_OUT0_CSC_C13_C14_B 0x05a9 7666#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 7667#define regMPC_OUT0_CSC_C21_C22_B 0x05aa 7668#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 7669#define regMPC_OUT0_CSC_C23_C24_B 0x05ab 7670#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 7671#define regMPC_OUT0_CSC_C31_C32_B 0x05ac 7672#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 7673#define regMPC_OUT0_CSC_C33_C34_B 0x05ad 7674#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 7675#define regMPC_OUT1_CSC_MODE 0x05ae 7676#define regMPC_OUT1_CSC_MODE_BASE_IDX 3 7677#define regMPC_OUT1_CSC_C11_C12_A 0x05af 7678#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 7679#define regMPC_OUT1_CSC_C13_C14_A 0x05b0 7680#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 7681#define regMPC_OUT1_CSC_C21_C22_A 0x05b1 7682#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 7683#define regMPC_OUT1_CSC_C23_C24_A 0x05b2 7684#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 7685#define regMPC_OUT1_CSC_C31_C32_A 0x05b3 7686#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 7687#define regMPC_OUT1_CSC_C33_C34_A 0x05b4 7688#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 7689#define regMPC_OUT1_CSC_C11_C12_B 0x05b5 7690#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 7691#define regMPC_OUT1_CSC_C13_C14_B 0x05b6 7692#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 7693#define regMPC_OUT1_CSC_C21_C22_B 0x05b7 7694#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 7695#define regMPC_OUT1_CSC_C23_C24_B 0x05b8 7696#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 7697#define regMPC_OUT1_CSC_C31_C32_B 0x05b9 7698#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 7699#define regMPC_OUT1_CSC_C33_C34_B 0x05ba 7700#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 7701#define regMPC_OUT2_CSC_MODE 0x05bb 7702#define regMPC_OUT2_CSC_MODE_BASE_IDX 3 7703#define regMPC_OUT2_CSC_C11_C12_A 0x05bc 7704#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 7705#define regMPC_OUT2_CSC_C13_C14_A 0x05bd 7706#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 7707#define regMPC_OUT2_CSC_C21_C22_A 0x05be 7708#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 7709#define regMPC_OUT2_CSC_C23_C24_A 0x05bf 7710#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 7711#define regMPC_OUT2_CSC_C31_C32_A 0x05c0 7712#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 7713#define regMPC_OUT2_CSC_C33_C34_A 0x05c1 7714#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 7715#define regMPC_OUT2_CSC_C11_C12_B 0x05c2 7716#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 7717#define regMPC_OUT2_CSC_C13_C14_B 0x05c3 7718#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 7719#define regMPC_OUT2_CSC_C21_C22_B 0x05c4 7720#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 7721#define regMPC_OUT2_CSC_C23_C24_B 0x05c5 7722#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 7723#define regMPC_OUT2_CSC_C31_C32_B 0x05c6 7724#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 7725#define regMPC_OUT2_CSC_C33_C34_B 0x05c7 7726#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 7727#define regMPC_OUT3_CSC_MODE 0x05c8 7728#define regMPC_OUT3_CSC_MODE_BASE_IDX 3 7729#define regMPC_OUT3_CSC_C11_C12_A 0x05c9 7730#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 7731#define regMPC_OUT3_CSC_C13_C14_A 0x05ca 7732#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 7733#define regMPC_OUT3_CSC_C21_C22_A 0x05cb 7734#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 7735#define regMPC_OUT3_CSC_C23_C24_A 0x05cc 7736#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 7737#define regMPC_OUT3_CSC_C31_C32_A 0x05cd 7738#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 7739#define regMPC_OUT3_CSC_C33_C34_A 0x05ce 7740#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 7741#define regMPC_OUT3_CSC_C11_C12_B 0x05cf 7742#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 7743#define regMPC_OUT3_CSC_C13_C14_B 0x05d0 7744#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 7745#define regMPC_OUT3_CSC_C21_C22_B 0x05d1 7746#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 7747#define regMPC_OUT3_CSC_C23_C24_B 0x05d2 7748#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 7749#define regMPC_OUT3_CSC_C31_C32_B 0x05d3 7750#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 7751#define regMPC_OUT3_CSC_C33_C34_B 0x05d4 7752#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 7753#define regMPC_OCSC_TEST_DEBUG_INDEX 0x0605 7754#define regMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX 3 7755#define regMPC_OCSC_TEST_DEBUG_DATA 0x0606 7756#define regMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX 3 7757 7758 7759// addressBlock: dce_dc_mpc_mpc_rmu_dispdec 7760// base address: 0x0 7761#define regMPC_RMU_CONTROL 0x0680 7762#define regMPC_RMU_CONTROL_BASE_IDX 3 7763#define regMPC_RMU_MEM_PWR_CTRL 0x0681 7764#define regMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3 7765#define regMPC_RMU0_SHAPER_CONTROL 0x0682 7766#define regMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3 7767#define regMPC_RMU0_SHAPER_OFFSET_R 0x0683 7768#define regMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3 7769#define regMPC_RMU0_SHAPER_OFFSET_G 0x0684 7770#define regMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3 7771#define regMPC_RMU0_SHAPER_OFFSET_B 0x0685 7772#define regMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3 7773#define regMPC_RMU0_SHAPER_SCALE_R 0x0686 7774#define regMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3 7775#define regMPC_RMU0_SHAPER_SCALE_G_B 0x0687 7776#define regMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3 7777#define regMPC_RMU0_SHAPER_LUT_INDEX 0x0688 7778#define regMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3 7779#define regMPC_RMU0_SHAPER_LUT_DATA 0x0689 7780#define regMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3 7781#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a 7782#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 7783#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b 7784#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 7785#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c 7786#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 7787#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d 7788#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 7789#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e 7790#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 7791#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f 7792#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 7793#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690 7794#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 7795#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691 7796#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 7797#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692 7798#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 7799#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693 7800#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 7801#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694 7802#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 7803#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695 7804#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 7805#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696 7806#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 7807#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697 7808#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 7809#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698 7810#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 7811#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699 7812#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 7813#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a 7814#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 7815#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b 7816#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 7817#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c 7818#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 7819#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d 7820#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 7821#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e 7822#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 7823#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f 7824#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 7825#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0 7826#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 7827#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1 7828#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 7829#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2 7830#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 7831#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3 7832#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 7833#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4 7834#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 7835#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5 7836#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 7837#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6 7838#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 7839#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7 7840#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 7841#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8 7842#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 7843#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9 7844#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 7845#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa 7846#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 7847#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab 7848#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 7849#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac 7850#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 7851#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad 7852#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 7853#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae 7854#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 7855#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af 7856#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 7857#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0 7858#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 7859#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1 7860#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 7861#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2 7862#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 7863#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3 7864#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 7865#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4 7866#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 7867#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5 7868#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 7869#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6 7870#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 7871#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7 7872#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 7873#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8 7874#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 7875#define regMPC_RMU0_3DLUT_MODE 0x06b9 7876#define regMPC_RMU0_3DLUT_MODE_BASE_IDX 3 7877#define regMPC_RMU0_3DLUT_INDEX 0x06ba 7878#define regMPC_RMU0_3DLUT_INDEX_BASE_IDX 3 7879#define regMPC_RMU0_3DLUT_DATA 0x06bb 7880#define regMPC_RMU0_3DLUT_DATA_BASE_IDX 3 7881#define regMPC_RMU0_3DLUT_DATA_30BIT 0x06bc 7882#define regMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3 7883#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd 7884#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 7885#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be 7886#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 7887#define regMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf 7888#define regMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3 7889#define regMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0 7890#define regMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3 7891#define regMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1 7892#define regMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3 7893#define regMPC_RMU1_SHAPER_CONTROL 0x06c2 7894#define regMPC_RMU1_SHAPER_CONTROL_BASE_IDX 3 7895#define regMPC_RMU1_SHAPER_OFFSET_R 0x06c3 7896#define regMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX 3 7897#define regMPC_RMU1_SHAPER_OFFSET_G 0x06c4 7898#define regMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX 3 7899#define regMPC_RMU1_SHAPER_OFFSET_B 0x06c5 7900#define regMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX 3 7901#define regMPC_RMU1_SHAPER_SCALE_R 0x06c6 7902#define regMPC_RMU1_SHAPER_SCALE_R_BASE_IDX 3 7903#define regMPC_RMU1_SHAPER_SCALE_G_B 0x06c7 7904#define regMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX 3 7905#define regMPC_RMU1_SHAPER_LUT_INDEX 0x06c8 7906#define regMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX 3 7907#define regMPC_RMU1_SHAPER_LUT_DATA 0x06c9 7908#define regMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX 3 7909#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK 0x06ca 7910#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 7911#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B 0x06cb 7912#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 7913#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G 0x06cc 7914#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 7915#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R 0x06cd 7916#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 7917#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B 0x06ce 7918#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 7919#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G 0x06cf 7920#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 7921#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R 0x06d0 7922#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 7923#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1 0x06d1 7924#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 7925#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3 0x06d2 7926#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 7927#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5 0x06d3 7928#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 7929#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7 0x06d4 7930#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 7931#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9 0x06d5 7932#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 7933#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11 0x06d6 7934#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 7935#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13 0x06d7 7936#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 7937#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15 0x06d8 7938#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 7939#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17 0x06d9 7940#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 7941#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19 0x06da 7942#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 7943#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21 0x06db 7944#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 7945#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23 0x06dc 7946#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 7947#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25 0x06dd 7948#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 7949#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27 0x06de 7950#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 7951#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29 0x06df 7952#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 7953#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31 0x06e0 7954#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 7955#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33 0x06e1 7956#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 7957#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B 0x06e2 7958#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 7959#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G 0x06e3 7960#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 7961#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R 0x06e4 7962#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 7963#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B 0x06e5 7964#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 7965#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G 0x06e6 7966#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 7967#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R 0x06e7 7968#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 7969#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1 0x06e8 7970#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 7971#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3 0x06e9 7972#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 7973#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5 0x06ea 7974#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 7975#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7 0x06eb 7976#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 7977#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9 0x06ec 7978#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 7979#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11 0x06ed 7980#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 7981#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13 0x06ee 7982#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 7983#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15 0x06ef 7984#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 7985#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17 0x06f0 7986#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 7987#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19 0x06f1 7988#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 7989#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21 0x06f2 7990#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 7991#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23 0x06f3 7992#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 7993#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25 0x06f4 7994#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 7995#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27 0x06f5 7996#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 7997#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29 0x06f6 7998#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 7999#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31 0x06f7 8000#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 8001#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33 0x06f8 8002#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 8003#define regMPC_RMU1_3DLUT_MODE 0x06f9 8004#define regMPC_RMU1_3DLUT_MODE_BASE_IDX 3 8005#define regMPC_RMU1_3DLUT_INDEX 0x06fa 8006#define regMPC_RMU1_3DLUT_INDEX_BASE_IDX 3 8007#define regMPC_RMU1_3DLUT_DATA 0x06fb 8008#define regMPC_RMU1_3DLUT_DATA_BASE_IDX 3 8009#define regMPC_RMU1_3DLUT_DATA_30BIT 0x06fc 8010#define regMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX 3 8011#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL 0x06fd 8012#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 8013#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR 0x06fe 8014#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 8015#define regMPC_RMU1_3DLUT_OUT_OFFSET_R 0x06ff 8016#define regMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX 3 8017#define regMPC_RMU1_3DLUT_OUT_OFFSET_G 0x0700 8018#define regMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX 3 8019#define regMPC_RMU1_3DLUT_OUT_OFFSET_B 0x0701 8020#define regMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX 3 8021 8022 8023// addressBlock: dce_dc_opp_abm0_dispdec 8024// base address: 0x0 8025#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a 8026#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 8027#define regABM0_BL1_PWM_USER_LEVEL 0x0e7b 8028#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 8029#define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c 8030#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 8031#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d 8032#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 8033#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e 8034#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 8035#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f 8036#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 8037#define regABM0_BL1_PWM_ABM_CNTL 0x0e80 8038#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 8039#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 8040#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 8041#define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 8042#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 8043#define regABM0_DC_ABM1_CNTL 0x0e83 8044#define regABM0_DC_ABM1_CNTL_BASE_IDX 3 8045#define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 8046#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 8047#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 8048#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 8049#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 8050#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 8051#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 8052#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 8053#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 8054#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 8055#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 8056#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 8057#define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a 8058#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 8059#define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b 8060#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 8061#define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c 8062#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 8063#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e 8064#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 8065#define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f 8066#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 8067#define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 8068#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 8069#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 8070#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 8071#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 8072#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 8073#define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 8074#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 8075#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 8076#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 8077#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 8078#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 8079#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 8080#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 8081#define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 8082#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 8083#define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 8084#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 8085#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 8086#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 8087#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a 8088#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 8089#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b 8090#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 8091#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c 8092#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 8093#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d 8094#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 8095#define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e 8096#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 8097#define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f 8098#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 8099#define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 8100#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 8101#define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 8102#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 8103#define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 8104#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 8105#define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 8106#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 8107#define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 8108#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 8109#define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 8110#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 8111#define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 8112#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 8113#define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 8114#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 8115#define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 8116#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 8117#define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 8118#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 8119#define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa 8120#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 8121#define regABM0_DC_ABM1_HG_RESULT_14 0x0eab 8122#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 8123#define regABM0_DC_ABM1_HG_RESULT_15 0x0eac 8124#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 8125#define regABM0_DC_ABM1_HG_RESULT_16 0x0ead 8126#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 8127#define regABM0_DC_ABM1_HG_RESULT_17 0x0eae 8128#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 8129#define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf 8130#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 8131#define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 8132#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 8133#define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 8134#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 8135#define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 8136#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 8137#define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 8138#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 8139#define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 8140#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 8141#define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 8142#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 8143#define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 8144#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 8145 8146 8147// addressBlock: dce_dc_opp_abm1_dispdec 8148// base address: 0x104 8149#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb 8150#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 8151#define regABM1_BL1_PWM_USER_LEVEL 0x0ebc 8152#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 8153#define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd 8154#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 8155#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe 8156#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 8157#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf 8158#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 8159#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 8160#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 8161#define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 8162#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 8163#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 8164#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 8165#define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 8166#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 8167#define regABM1_DC_ABM1_CNTL 0x0ec4 8168#define regABM1_DC_ABM1_CNTL_BASE_IDX 3 8169#define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 8170#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 8171#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 8172#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 8173#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 8174#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 8175#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 8176#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 8177#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 8178#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 8179#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca 8180#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 8181#define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb 8182#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 8183#define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc 8184#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 8185#define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd 8186#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 8187#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf 8188#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 8189#define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 8190#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 8191#define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 8192#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 8193#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 8194#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 8195#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 8196#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 8197#define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 8198#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 8199#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 8200#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 8201#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 8202#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 8203#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 8204#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 8205#define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 8206#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 8207#define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 8208#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 8209#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda 8210#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 8211#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb 8212#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 8213#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc 8214#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 8215#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd 8216#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 8217#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede 8218#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 8219#define regABM1_DC_ABM1_HG_RESULT_1 0x0edf 8220#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 8221#define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 8222#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 8223#define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 8224#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 8225#define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 8226#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 8227#define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 8228#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 8229#define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 8230#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 8231#define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 8232#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 8233#define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 8234#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 8235#define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 8236#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 8237#define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 8238#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 8239#define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 8240#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 8241#define regABM1_DC_ABM1_HG_RESULT_12 0x0eea 8242#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 8243#define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb 8244#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 8245#define regABM1_DC_ABM1_HG_RESULT_14 0x0eec 8246#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 8247#define regABM1_DC_ABM1_HG_RESULT_15 0x0eed 8248#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 8249#define regABM1_DC_ABM1_HG_RESULT_16 0x0eee 8250#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 8251#define regABM1_DC_ABM1_HG_RESULT_17 0x0eef 8252#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 8253#define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 8254#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 8255#define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 8256#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 8257#define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 8258#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 8259#define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 8260#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 8261#define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 8262#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 8263#define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 8264#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 8265#define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 8266#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 8267#define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 8268#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 8269 8270 8271// addressBlock: dce_dc_opp_abm2_dispdec 8272// base address: 0x208 8273#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc 8274#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 8275#define regABM2_BL1_PWM_USER_LEVEL 0x0efd 8276#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 8277#define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe 8278#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 8279#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff 8280#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 8281#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 8282#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 8283#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 8284#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 8285#define regABM2_BL1_PWM_ABM_CNTL 0x0f02 8286#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 8287#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 8288#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 8289#define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 8290#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 8291#define regABM2_DC_ABM1_CNTL 0x0f05 8292#define regABM2_DC_ABM1_CNTL_BASE_IDX 3 8293#define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 8294#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 8295#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 8296#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 8297#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 8298#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 8299#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 8300#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 8301#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a 8302#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 8303#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b 8304#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 8305#define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c 8306#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 8307#define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d 8308#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 8309#define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e 8310#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 8311#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 8312#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 8313#define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 8314#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 8315#define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 8316#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 8317#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 8318#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 8319#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 8320#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 8321#define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 8322#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 8323#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 8324#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 8325#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 8326#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 8327#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 8328#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 8329#define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 8330#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 8331#define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a 8332#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 8333#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b 8334#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 8335#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c 8336#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 8337#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d 8338#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 8339#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e 8340#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 8341#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f 8342#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 8343#define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 8344#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 8345#define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 8346#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 8347#define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 8348#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 8349#define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 8350#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 8351#define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 8352#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 8353#define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 8354#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 8355#define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 8356#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 8357#define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 8358#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 8359#define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 8360#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 8361#define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 8362#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 8363#define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a 8364#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 8365#define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b 8366#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 8367#define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c 8368#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 8369#define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d 8370#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 8371#define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e 8372#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 8373#define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f 8374#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 8375#define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 8376#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 8377#define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 8378#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 8379#define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 8380#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 8381#define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 8382#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 8383#define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 8384#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 8385#define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 8386#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 8387#define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 8388#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 8389#define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 8390#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 8391#define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 8392#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 8393 8394 8395// addressBlock: dce_dc_opp_abm3_dispdec 8396// base address: 0x30c 8397#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d 8398#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 8399#define regABM3_BL1_PWM_USER_LEVEL 0x0f3e 8400#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 8401#define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f 8402#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 8403#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 8404#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 8405#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 8406#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 8407#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 8408#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 8409#define regABM3_BL1_PWM_ABM_CNTL 0x0f43 8410#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 8411#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 8412#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 8413#define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 8414#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 8415#define regABM3_DC_ABM1_CNTL 0x0f46 8416#define regABM3_DC_ABM1_CNTL_BASE_IDX 3 8417#define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 8418#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 8419#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 8420#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 8421#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 8422#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 8423#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a 8424#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 8425#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b 8426#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 8427#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c 8428#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 8429#define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d 8430#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 8431#define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e 8432#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 8433#define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f 8434#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 8435#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 8436#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 8437#define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 8438#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 8439#define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 8440#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 8441#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 8442#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 8443#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 8444#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 8445#define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 8446#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 8447#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 8448#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 8449#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 8450#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 8451#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 8452#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 8453#define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a 8454#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 8455#define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b 8456#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 8457#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c 8458#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 8459#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d 8460#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 8461#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e 8462#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 8463#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f 8464#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 8465#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 8466#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 8467#define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 8468#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 8469#define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 8470#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 8471#define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 8472#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 8473#define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 8474#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 8475#define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 8476#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 8477#define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 8478#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 8479#define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 8480#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 8481#define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 8482#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 8483#define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 8484#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 8485#define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a 8486#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 8487#define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b 8488#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 8489#define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c 8490#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 8491#define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d 8492#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 8493#define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e 8494#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 8495#define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f 8496#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 8497#define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 8498#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 8499#define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 8500#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 8501#define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 8502#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 8503#define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 8504#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 8505#define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 8506#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 8507#define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 8508#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 8509#define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 8510#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 8511#define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 8512#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 8513#define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 8514#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 8515#define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 8516#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 8517 8518 8519// addressBlock: dce_dc_opp_dpg0_dispdec 8520// base address: 0x0 8521#define regDPG0_DPG_CONTROL 0x1854 8522#define regDPG0_DPG_CONTROL_BASE_IDX 2 8523#define regDPG0_DPG_RAMP_CONTROL 0x1855 8524#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 8525#define regDPG0_DPG_DIMENSIONS 0x1856 8526#define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 8527#define regDPG0_DPG_COLOUR_R_CR 0x1857 8528#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 8529#define regDPG0_DPG_COLOUR_G_Y 0x1858 8530#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 8531#define regDPG0_DPG_COLOUR_B_CB 0x1859 8532#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 8533#define regDPG0_DPG_OFFSET_SEGMENT 0x185a 8534#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 8535#define regDPG0_DPG_STATUS 0x185b 8536#define regDPG0_DPG_STATUS_BASE_IDX 2 8537 8538 8539// addressBlock: dce_dc_opp_fmt0_dispdec 8540// base address: 0x0 8541#define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c 8542#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8543#define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d 8544#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8545#define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e 8546#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8547#define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 8548#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8549#define regFMT0_FMT_CONTROL 0x1840 8550#define regFMT0_FMT_CONTROL_BASE_IDX 2 8551#define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 8552#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8553#define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 8554#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8555#define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 8556#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8557#define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 8558#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8559#define regFMT0_FMT_CLAMP_CNTL 0x1845 8560#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 8561#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 8562#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8563#define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 8564#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8565#define regFMT0_FMT_422_CONTROL 0x1849 8566#define regFMT0_FMT_422_CONTROL_BASE_IDX 2 8567 8568 8569// addressBlock: dce_dc_opp_oppbuf0_dispdec 8570// base address: 0x0 8571#define regOPPBUF0_OPPBUF_CONTROL 0x1884 8572#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 8573#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 8574#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8575#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 8576#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8577#define regOPPBUF0_OPPBUF_CONTROL1 0x1889 8578#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 8579 8580 8581// addressBlock: dce_dc_opp_opp_pipe0_dispdec 8582// base address: 0x0 8583#define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 8584#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 8585 8586 8587// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec 8588// base address: 0x0 8589#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 8590#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8591#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 8592#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 8593#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 8594#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8595#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 8596#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8597#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 8598#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8599 8600 8601// addressBlock: dce_dc_opp_dpg1_dispdec 8602// base address: 0x168 8603#define regDPG1_DPG_CONTROL 0x18ae 8604#define regDPG1_DPG_CONTROL_BASE_IDX 2 8605#define regDPG1_DPG_RAMP_CONTROL 0x18af 8606#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 8607#define regDPG1_DPG_DIMENSIONS 0x18b0 8608#define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 8609#define regDPG1_DPG_COLOUR_R_CR 0x18b1 8610#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 8611#define regDPG1_DPG_COLOUR_G_Y 0x18b2 8612#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 8613#define regDPG1_DPG_COLOUR_B_CB 0x18b3 8614#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 8615#define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 8616#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 8617#define regDPG1_DPG_STATUS 0x18b5 8618#define regDPG1_DPG_STATUS_BASE_IDX 2 8619 8620 8621// addressBlock: dce_dc_opp_fmt1_dispdec 8622// base address: 0x168 8623#define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 8624#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8625#define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 8626#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8627#define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 8628#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8629#define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 8630#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8631#define regFMT1_FMT_CONTROL 0x189a 8632#define regFMT1_FMT_CONTROL_BASE_IDX 2 8633#define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 8634#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8635#define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c 8636#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8637#define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d 8638#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8639#define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e 8640#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8641#define regFMT1_FMT_CLAMP_CNTL 0x189f 8642#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 8643#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 8644#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8645#define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 8646#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8647#define regFMT1_FMT_422_CONTROL 0x18a3 8648#define regFMT1_FMT_422_CONTROL_BASE_IDX 2 8649 8650 8651// addressBlock: dce_dc_opp_oppbuf1_dispdec 8652// base address: 0x168 8653#define regOPPBUF1_OPPBUF_CONTROL 0x18de 8654#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 8655#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 8656#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8657#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 8658#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8659#define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 8660#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 8661 8662 8663// addressBlock: dce_dc_opp_opp_pipe1_dispdec 8664// base address: 0x168 8665#define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 8666#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 8667 8668 8669// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec 8670// base address: 0x168 8671#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 8672#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8673#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 8674#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 8675#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 8676#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8677#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 8678#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8679#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 8680#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8681 8682 8683// addressBlock: dce_dc_opp_dpg2_dispdec 8684// base address: 0x2d0 8685#define regDPG2_DPG_CONTROL 0x1908 8686#define regDPG2_DPG_CONTROL_BASE_IDX 2 8687#define regDPG2_DPG_RAMP_CONTROL 0x1909 8688#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 8689#define regDPG2_DPG_DIMENSIONS 0x190a 8690#define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 8691#define regDPG2_DPG_COLOUR_R_CR 0x190b 8692#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 8693#define regDPG2_DPG_COLOUR_G_Y 0x190c 8694#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 8695#define regDPG2_DPG_COLOUR_B_CB 0x190d 8696#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 8697#define regDPG2_DPG_OFFSET_SEGMENT 0x190e 8698#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 8699#define regDPG2_DPG_STATUS 0x190f 8700#define regDPG2_DPG_STATUS_BASE_IDX 2 8701 8702 8703// addressBlock: dce_dc_opp_fmt2_dispdec 8704// base address: 0x2d0 8705#define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 8706#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8707#define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 8708#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8709#define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 8710#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8711#define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 8712#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8713#define regFMT2_FMT_CONTROL 0x18f4 8714#define regFMT2_FMT_CONTROL_BASE_IDX 2 8715#define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 8716#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8717#define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 8718#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8719#define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 8720#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8721#define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 8722#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8723#define regFMT2_FMT_CLAMP_CNTL 0x18f9 8724#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 8725#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa 8726#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8727#define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb 8728#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8729#define regFMT2_FMT_422_CONTROL 0x18fd 8730#define regFMT2_FMT_422_CONTROL_BASE_IDX 2 8731 8732 8733// addressBlock: dce_dc_opp_oppbuf2_dispdec 8734// base address: 0x2d0 8735#define regOPPBUF2_OPPBUF_CONTROL 0x1938 8736#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 8737#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 8738#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8739#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a 8740#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8741#define regOPPBUF2_OPPBUF_CONTROL1 0x193d 8742#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 8743 8744 8745// addressBlock: dce_dc_opp_opp_pipe2_dispdec 8746// base address: 0x2d0 8747#define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 8748#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 8749 8750 8751// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec 8752// base address: 0x2d0 8753#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 8754#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8755#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 8756#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 8757#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 8758#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8759#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 8760#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8761#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 8762#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8763 8764 8765// addressBlock: dce_dc_opp_dpg3_dispdec 8766// base address: 0x438 8767#define regDPG3_DPG_CONTROL 0x1962 8768#define regDPG3_DPG_CONTROL_BASE_IDX 2 8769#define regDPG3_DPG_RAMP_CONTROL 0x1963 8770#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 8771#define regDPG3_DPG_DIMENSIONS 0x1964 8772#define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 8773#define regDPG3_DPG_COLOUR_R_CR 0x1965 8774#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 8775#define regDPG3_DPG_COLOUR_G_Y 0x1966 8776#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 8777#define regDPG3_DPG_COLOUR_B_CB 0x1967 8778#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 8779#define regDPG3_DPG_OFFSET_SEGMENT 0x1968 8780#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 8781#define regDPG3_DPG_STATUS 0x1969 8782#define regDPG3_DPG_STATUS_BASE_IDX 2 8783 8784 8785// addressBlock: dce_dc_opp_fmt3_dispdec 8786// base address: 0x438 8787#define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a 8788#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8789#define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b 8790#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8791#define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c 8792#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8793#define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d 8794#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8795#define regFMT3_FMT_CONTROL 0x194e 8796#define regFMT3_FMT_CONTROL_BASE_IDX 2 8797#define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f 8798#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8799#define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 8800#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8801#define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 8802#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8803#define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 8804#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8805#define regFMT3_FMT_CLAMP_CNTL 0x1953 8806#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 8807#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 8808#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8809#define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 8810#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8811#define regFMT3_FMT_422_CONTROL 0x1957 8812#define regFMT3_FMT_422_CONTROL_BASE_IDX 2 8813 8814 8815// addressBlock: dce_dc_opp_oppbuf3_dispdec 8816// base address: 0x438 8817#define regOPPBUF3_OPPBUF_CONTROL 0x1992 8818#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 8819#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 8820#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8821#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 8822#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8823#define regOPPBUF3_OPPBUF_CONTROL1 0x1997 8824#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 8825 8826 8827// addressBlock: dce_dc_opp_opp_pipe3_dispdec 8828// base address: 0x438 8829#define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a 8830#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 8831 8832 8833// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec 8834// base address: 0x438 8835#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f 8836#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8837#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 8838#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 8839#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 8840#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8841#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 8842#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8843#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 8844#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8845 8846 8847// addressBlock: dce_dc_opp_dscrm0_dispdec 8848// base address: 0x0 8849#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 8850#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8851 8852 8853// addressBlock: dce_dc_opp_dscrm1_dispdec 8854// base address: 0x4 8855#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 8856#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8857 8858 8859// addressBlock: dce_dc_opp_dscrm2_dispdec 8860// base address: 0x8 8861#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 8862#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8863 8864 8865// addressBlock: dce_dc_opp_opp_top_dispdec 8866// base address: 0x0 8867#define regOPP_TOP_CLK_CONTROL 0x1a5e 8868#define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 8869#define regOPP_ABM_CONTROL 0x1a60 8870#define regOPP_ABM_CONTROL_BASE_IDX 2 8871 8872 8873// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec 8874// base address: 0x6af8 8875#define regDC_PERFMON16_PERFCOUNTER_CNTL 0x1abe 8876#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 8877#define regDC_PERFMON16_PERFCOUNTER_CNTL2 0x1abf 8878#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 8879#define regDC_PERFMON16_PERFCOUNTER_STATE 0x1ac0 8880#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 8881#define regDC_PERFMON16_PERFMON_CNTL 0x1ac1 8882#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 8883#define regDC_PERFMON16_PERFMON_CNTL2 0x1ac2 8884#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 8885#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1ac3 8886#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 8887#define regDC_PERFMON16_PERFMON_CVALUE_LOW 0x1ac4 8888#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 8889#define regDC_PERFMON16_PERFMON_HI 0x1ac5 8890#define regDC_PERFMON16_PERFMON_HI_BASE_IDX 2 8891#define regDC_PERFMON16_PERFMON_LOW 0x1ac6 8892#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 8893 8894 8895// addressBlock: dce_dc_optc_odm0_dispdec 8896// base address: 0x0 8897#define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 8898#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8899#define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 8900#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8901#define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 8902#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8903#define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd 8904#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8905#define regODM0_OPTC_WIDTH_CONTROL 0x1ace 8906#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 8907#define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf 8908#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8909#define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 8910#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 8911#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 8912#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8913 8914 8915// addressBlock: dce_dc_optc_odm1_dispdec 8916// base address: 0x40 8917#define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 8918#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8919#define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 8920#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8921#define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 8922#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8923#define regODM1_OPTC_BYTES_PER_PIXEL 0x1add 8924#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8925#define regODM1_OPTC_WIDTH_CONTROL 0x1ade 8926#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 8927#define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf 8928#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8929#define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 8930#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 8931#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 8932#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8933 8934 8935// addressBlock: dce_dc_optc_odm2_dispdec 8936// base address: 0x80 8937#define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea 8938#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8939#define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb 8940#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8941#define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec 8942#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8943#define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed 8944#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8945#define regODM2_OPTC_WIDTH_CONTROL 0x1aee 8946#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 8947#define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef 8948#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8949#define regODM2_OPTC_MEMORY_CONFIG 0x1af0 8950#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 8951#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 8952#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8953 8954 8955// addressBlock: dce_dc_optc_odm3_dispdec 8956// base address: 0xc0 8957#define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa 8958#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8959#define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb 8960#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8961#define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc 8962#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8963#define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd 8964#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8965#define regODM3_OPTC_WIDTH_CONTROL 0x1afe 8966#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 8967#define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff 8968#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8969#define regODM3_OPTC_MEMORY_CONFIG 0x1b00 8970#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 8971#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 8972#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8973 8974 8975// addressBlock: dce_dc_optc_otg0_dispdec 8976// base address: 0x0 8977#define regOTG0_OTG_H_TOTAL 0x1b2a 8978#define regOTG0_OTG_H_TOTAL_BASE_IDX 2 8979#define regOTG0_OTG_H_BLANK_START_END 0x1b2b 8980#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 8981#define regOTG0_OTG_H_SYNC_A 0x1b2c 8982#define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 8983#define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 8984#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8985#define regOTG0_OTG_H_TIMING_CNTL 0x1b2e 8986#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 8987#define regOTG0_OTG_V_TOTAL 0x1b2f 8988#define regOTG0_OTG_V_TOTAL_BASE_IDX 2 8989#define regOTG0_OTG_V_TOTAL_MIN 0x1b30 8990#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 8991#define regOTG0_OTG_V_TOTAL_MAX 0x1b31 8992#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 8993#define regOTG0_OTG_V_TOTAL_MID 0x1b32 8994#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 8995#define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 8996#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8997#define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 8998#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8999#define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 9000#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9001#define regOTG0_OTG_V_BLANK_START_END 0x1b36 9002#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 9003#define regOTG0_OTG_V_SYNC_A 0x1b37 9004#define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 9005#define regOTG0_OTG_V_SYNC_A_CNTL 0x1b38 9006#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9007#define regOTG0_OTG_TRIGA_CNTL 0x1b39 9008#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 9009#define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a 9010#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9011#define regOTG0_OTG_TRIGB_CNTL 0x1b3b 9012#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 9013#define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c 9014#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9015#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d 9016#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9017#define regOTG0_OTG_FLOW_CONTROL 0x1b3e 9018#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 9019#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f 9020#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9021#define regOTG0_OTG_CONTROL 0x1b41 9022#define regOTG0_OTG_CONTROL_BASE_IDX 2 9023#define regOTG0_OTG_INTERLACE_CONTROL 0x1b44 9024#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 9025#define regOTG0_OTG_INTERLACE_STATUS 0x1b45 9026#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 9027#define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 9028#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9029#define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 9030#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9031#define regOTG0_OTG_STATUS 0x1b49 9032#define regOTG0_OTG_STATUS_BASE_IDX 2 9033#define regOTG0_OTG_STATUS_POSITION 0x1b4a 9034#define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 9035#define regOTG0_OTG_NOM_VERT_POSITION 0x1b4b 9036#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 9037#define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c 9038#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9039#define regOTG0_OTG_STATUS_VF_COUNT 0x1b4d 9040#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 9041#define regOTG0_OTG_STATUS_HV_COUNT 0x1b4e 9042#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 9043#define regOTG0_OTG_COUNT_CONTROL 0x1b4f 9044#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 9045#define regOTG0_OTG_COUNT_RESET 0x1b50 9046#define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 9047#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 9048#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9049#define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 9050#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9051#define regOTG0_OTG_STEREO_STATUS 0x1b53 9052#define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 9053#define regOTG0_OTG_STEREO_CONTROL 0x1b54 9054#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 9055#define regOTG0_OTG_SNAPSHOT_STATUS 0x1b55 9056#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9057#define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 9058#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9059#define regOTG0_OTG_SNAPSHOT_POSITION 0x1b57 9060#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9061#define regOTG0_OTG_SNAPSHOT_FRAME 0x1b58 9062#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9063#define regOTG0_OTG_INTERRUPT_CONTROL 0x1b59 9064#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9065#define regOTG0_OTG_UPDATE_LOCK 0x1b5a 9066#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 9067#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b 9068#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9069#define regOTG0_OTG_MASTER_EN 0x1b5c 9070#define regOTG0_OTG_MASTER_EN_BASE_IDX 2 9071#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 9072#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9073#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 9074#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9075#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 9076#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9077#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 9078#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9079#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 9080#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9081#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 9082#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9083#define regOTG0_OTG_CRC_CNTL 0x1b68 9084#define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 9085#define regOTG0_OTG_CRC_CNTL2 0x1b69 9086#define regOTG0_OTG_CRC_CNTL2_BASE_IDX 2 9087#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a 9088#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9089#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b 9090#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9091#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c 9092#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9093#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d 9094#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9095#define regOTG0_OTG_CRC0_DATA_RG 0x1b6e 9096#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 9097#define regOTG0_OTG_CRC0_DATA_B 0x1b6f 9098#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 9099#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 9100#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9101#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 9102#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9103#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 9104#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9105#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 9106#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9107#define regOTG0_OTG_CRC1_DATA_RG 0x1b74 9108#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 9109#define regOTG0_OTG_CRC1_DATA_B 0x1b75 9110#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 9111#define regOTG0_OTG_CRC2_DATA_RG 0x1b76 9112#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 9113#define regOTG0_OTG_CRC2_DATA_B 0x1b77 9114#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 9115#define regOTG0_OTG_CRC3_DATA_RG 0x1b78 9116#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 9117#define regOTG0_OTG_CRC3_DATA_B 0x1b79 9118#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 9119#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a 9120#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9121#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b 9122#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9123#define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 9124#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9125#define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 9126#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9127#define regOTG0_OTG_GSL_VSYNC_GAP 0x1b84 9128#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9129#define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 9130#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9131#define regOTG0_OTG_CLOCK_CONTROL 0x1b86 9132#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 9133#define regOTG0_OTG_VSTARTUP_PARAM 0x1b87 9134#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 9135#define regOTG0_OTG_VUPDATE_PARAM 0x1b88 9136#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 9137#define regOTG0_OTG_VREADY_PARAM 0x1b89 9138#define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 9139#define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a 9140#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9141#define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b 9142#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9143#define regOTG0_OTG_GSL_CONTROL 0x1b8c 9144#define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 9145#define regOTG0_OTG_GSL_WINDOW_X 0x1b8d 9146#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 9147#define regOTG0_OTG_GSL_WINDOW_Y 0x1b8e 9148#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 9149#define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f 9150#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9151#define regOTG0_OTG_GLOBAL_CONTROL0 0x1b90 9152#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9153#define regOTG0_OTG_GLOBAL_CONTROL1 0x1b91 9154#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9155#define regOTG0_OTG_GLOBAL_CONTROL2 0x1b92 9156#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9157#define regOTG0_OTG_GLOBAL_CONTROL3 0x1b93 9158#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9159#define regOTG0_OTG_GLOBAL_CONTROL4 0x1b94 9160#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9161#define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b95 9162#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9163#define regOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b96 9164#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9165#define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b97 9166#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9167#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b98 9168#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9169#define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b99 9170#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9171#define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b9a 9172#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9173#define regOTG0_OTG_DRR_CONTROL 0x1b9b 9174#define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 9175#define regOTG0_OTG_M_CONST_DTO0 0x1b9c 9176#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 9177#define regOTG0_OTG_M_CONST_DTO1 0x1b9d 9178#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 9179#define regOTG0_OTG_REQUEST_CONTROL 0x1b9e 9180#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 9181#define regOTG0_OTG_DSC_START_POSITION 0x1b9f 9182#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 9183#define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba0 9184#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9185#define regOTG0_OTG_SPARE_REGISTER 0x1ba2 9186#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 9187 9188 9189// addressBlock: dce_dc_optc_otg1_dispdec 9190// base address: 0x200 9191#define regOTG1_OTG_H_TOTAL 0x1baa 9192#define regOTG1_OTG_H_TOTAL_BASE_IDX 2 9193#define regOTG1_OTG_H_BLANK_START_END 0x1bab 9194#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 9195#define regOTG1_OTG_H_SYNC_A 0x1bac 9196#define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 9197#define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad 9198#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9199#define regOTG1_OTG_H_TIMING_CNTL 0x1bae 9200#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 9201#define regOTG1_OTG_V_TOTAL 0x1baf 9202#define regOTG1_OTG_V_TOTAL_BASE_IDX 2 9203#define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 9204#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 9205#define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 9206#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 9207#define regOTG1_OTG_V_TOTAL_MID 0x1bb2 9208#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 9209#define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 9210#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9211#define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 9212#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9213#define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 9214#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9215#define regOTG1_OTG_V_BLANK_START_END 0x1bb6 9216#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 9217#define regOTG1_OTG_V_SYNC_A 0x1bb7 9218#define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 9219#define regOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 9220#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9221#define regOTG1_OTG_TRIGA_CNTL 0x1bb9 9222#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 9223#define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba 9224#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9225#define regOTG1_OTG_TRIGB_CNTL 0x1bbb 9226#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 9227#define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc 9228#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9229#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd 9230#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9231#define regOTG1_OTG_FLOW_CONTROL 0x1bbe 9232#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 9233#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf 9234#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9235#define regOTG1_OTG_CONTROL 0x1bc1 9236#define regOTG1_OTG_CONTROL_BASE_IDX 2 9237#define regOTG1_OTG_INTERLACE_CONTROL 0x1bc4 9238#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 9239#define regOTG1_OTG_INTERLACE_STATUS 0x1bc5 9240#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 9241#define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 9242#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9243#define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 9244#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9245#define regOTG1_OTG_STATUS 0x1bc9 9246#define regOTG1_OTG_STATUS_BASE_IDX 2 9247#define regOTG1_OTG_STATUS_POSITION 0x1bca 9248#define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 9249#define regOTG1_OTG_NOM_VERT_POSITION 0x1bcb 9250#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 9251#define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc 9252#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9253#define regOTG1_OTG_STATUS_VF_COUNT 0x1bcd 9254#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 9255#define regOTG1_OTG_STATUS_HV_COUNT 0x1bce 9256#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 9257#define regOTG1_OTG_COUNT_CONTROL 0x1bcf 9258#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 9259#define regOTG1_OTG_COUNT_RESET 0x1bd0 9260#define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 9261#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 9262#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9263#define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 9264#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9265#define regOTG1_OTG_STEREO_STATUS 0x1bd3 9266#define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 9267#define regOTG1_OTG_STEREO_CONTROL 0x1bd4 9268#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 9269#define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 9270#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9271#define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 9272#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9273#define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 9274#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9275#define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 9276#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9277#define regOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 9278#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9279#define regOTG1_OTG_UPDATE_LOCK 0x1bda 9280#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 9281#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb 9282#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9283#define regOTG1_OTG_MASTER_EN 0x1bdc 9284#define regOTG1_OTG_MASTER_EN_BASE_IDX 2 9285#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 9286#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9287#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 9288#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9289#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 9290#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9291#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 9292#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9293#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 9294#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9295#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 9296#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9297#define regOTG1_OTG_CRC_CNTL 0x1be8 9298#define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 9299#define regOTG1_OTG_CRC_CNTL2 0x1be9 9300#define regOTG1_OTG_CRC_CNTL2_BASE_IDX 2 9301#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea 9302#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9303#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb 9304#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9305#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec 9306#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9307#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed 9308#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9309#define regOTG1_OTG_CRC0_DATA_RG 0x1bee 9310#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 9311#define regOTG1_OTG_CRC0_DATA_B 0x1bef 9312#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 9313#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 9314#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9315#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 9316#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9317#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 9318#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9319#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 9320#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9321#define regOTG1_OTG_CRC1_DATA_RG 0x1bf4 9322#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 9323#define regOTG1_OTG_CRC1_DATA_B 0x1bf5 9324#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 9325#define regOTG1_OTG_CRC2_DATA_RG 0x1bf6 9326#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 9327#define regOTG1_OTG_CRC2_DATA_B 0x1bf7 9328#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 9329#define regOTG1_OTG_CRC3_DATA_RG 0x1bf8 9330#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 9331#define regOTG1_OTG_CRC3_DATA_B 0x1bf9 9332#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 9333#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa 9334#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9335#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb 9336#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9337#define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 9338#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9339#define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 9340#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9341#define regOTG1_OTG_GSL_VSYNC_GAP 0x1c04 9342#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9343#define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 9344#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9345#define regOTG1_OTG_CLOCK_CONTROL 0x1c06 9346#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 9347#define regOTG1_OTG_VSTARTUP_PARAM 0x1c07 9348#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 9349#define regOTG1_OTG_VUPDATE_PARAM 0x1c08 9350#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 9351#define regOTG1_OTG_VREADY_PARAM 0x1c09 9352#define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 9353#define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a 9354#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9355#define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b 9356#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9357#define regOTG1_OTG_GSL_CONTROL 0x1c0c 9358#define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 9359#define regOTG1_OTG_GSL_WINDOW_X 0x1c0d 9360#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 9361#define regOTG1_OTG_GSL_WINDOW_Y 0x1c0e 9362#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 9363#define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f 9364#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9365#define regOTG1_OTG_GLOBAL_CONTROL0 0x1c10 9366#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9367#define regOTG1_OTG_GLOBAL_CONTROL1 0x1c11 9368#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9369#define regOTG1_OTG_GLOBAL_CONTROL2 0x1c12 9370#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9371#define regOTG1_OTG_GLOBAL_CONTROL3 0x1c13 9372#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9373#define regOTG1_OTG_GLOBAL_CONTROL4 0x1c14 9374#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9375#define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c15 9376#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9377#define regOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c16 9378#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9379#define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c17 9380#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9381#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c18 9382#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9383#define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c19 9384#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9385#define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c1a 9386#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9387#define regOTG1_OTG_DRR_CONTROL 0x1c1b 9388#define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 9389#define regOTG1_OTG_M_CONST_DTO0 0x1c1c 9390#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 9391#define regOTG1_OTG_M_CONST_DTO1 0x1c1d 9392#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 9393#define regOTG1_OTG_REQUEST_CONTROL 0x1c1e 9394#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 9395#define regOTG1_OTG_DSC_START_POSITION 0x1c1f 9396#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 9397#define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c20 9398#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9399#define regOTG1_OTG_SPARE_REGISTER 0x1c22 9400#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 9401 9402 9403// addressBlock: dce_dc_optc_otg2_dispdec 9404// base address: 0x400 9405#define regOTG2_OTG_H_TOTAL 0x1c2a 9406#define regOTG2_OTG_H_TOTAL_BASE_IDX 2 9407#define regOTG2_OTG_H_BLANK_START_END 0x1c2b 9408#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 9409#define regOTG2_OTG_H_SYNC_A 0x1c2c 9410#define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 9411#define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d 9412#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9413#define regOTG2_OTG_H_TIMING_CNTL 0x1c2e 9414#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 9415#define regOTG2_OTG_V_TOTAL 0x1c2f 9416#define regOTG2_OTG_V_TOTAL_BASE_IDX 2 9417#define regOTG2_OTG_V_TOTAL_MIN 0x1c30 9418#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 9419#define regOTG2_OTG_V_TOTAL_MAX 0x1c31 9420#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 9421#define regOTG2_OTG_V_TOTAL_MID 0x1c32 9422#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 9423#define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 9424#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9425#define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 9426#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9427#define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 9428#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9429#define regOTG2_OTG_V_BLANK_START_END 0x1c36 9430#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 9431#define regOTG2_OTG_V_SYNC_A 0x1c37 9432#define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 9433#define regOTG2_OTG_V_SYNC_A_CNTL 0x1c38 9434#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9435#define regOTG2_OTG_TRIGA_CNTL 0x1c39 9436#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 9437#define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a 9438#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9439#define regOTG2_OTG_TRIGB_CNTL 0x1c3b 9440#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 9441#define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c 9442#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9443#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d 9444#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9445#define regOTG2_OTG_FLOW_CONTROL 0x1c3e 9446#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 9447#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f 9448#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9449#define regOTG2_OTG_CONTROL 0x1c41 9450#define regOTG2_OTG_CONTROL_BASE_IDX 2 9451#define regOTG2_OTG_INTERLACE_CONTROL 0x1c44 9452#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 9453#define regOTG2_OTG_INTERLACE_STATUS 0x1c45 9454#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 9455#define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 9456#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9457#define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 9458#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9459#define regOTG2_OTG_STATUS 0x1c49 9460#define regOTG2_OTG_STATUS_BASE_IDX 2 9461#define regOTG2_OTG_STATUS_POSITION 0x1c4a 9462#define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 9463#define regOTG2_OTG_NOM_VERT_POSITION 0x1c4b 9464#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 9465#define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c 9466#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9467#define regOTG2_OTG_STATUS_VF_COUNT 0x1c4d 9468#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 9469#define regOTG2_OTG_STATUS_HV_COUNT 0x1c4e 9470#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 9471#define regOTG2_OTG_COUNT_CONTROL 0x1c4f 9472#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 9473#define regOTG2_OTG_COUNT_RESET 0x1c50 9474#define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 9475#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 9476#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9477#define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 9478#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9479#define regOTG2_OTG_STEREO_STATUS 0x1c53 9480#define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 9481#define regOTG2_OTG_STEREO_CONTROL 0x1c54 9482#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 9483#define regOTG2_OTG_SNAPSHOT_STATUS 0x1c55 9484#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9485#define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 9486#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9487#define regOTG2_OTG_SNAPSHOT_POSITION 0x1c57 9488#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9489#define regOTG2_OTG_SNAPSHOT_FRAME 0x1c58 9490#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9491#define regOTG2_OTG_INTERRUPT_CONTROL 0x1c59 9492#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9493#define regOTG2_OTG_UPDATE_LOCK 0x1c5a 9494#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 9495#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b 9496#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9497#define regOTG2_OTG_MASTER_EN 0x1c5c 9498#define regOTG2_OTG_MASTER_EN_BASE_IDX 2 9499#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 9500#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9501#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 9502#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9503#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 9504#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9505#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 9506#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9507#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 9508#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9509#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 9510#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9511#define regOTG2_OTG_CRC_CNTL 0x1c68 9512#define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 9513#define regOTG2_OTG_CRC_CNTL2 0x1c69 9514#define regOTG2_OTG_CRC_CNTL2_BASE_IDX 2 9515#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a 9516#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9517#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b 9518#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9519#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c 9520#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9521#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d 9522#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9523#define regOTG2_OTG_CRC0_DATA_RG 0x1c6e 9524#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 9525#define regOTG2_OTG_CRC0_DATA_B 0x1c6f 9526#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 9527#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70 9528#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9529#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71 9530#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9531#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72 9532#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9533#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73 9534#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9535#define regOTG2_OTG_CRC1_DATA_RG 0x1c74 9536#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 9537#define regOTG2_OTG_CRC1_DATA_B 0x1c75 9538#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 9539#define regOTG2_OTG_CRC2_DATA_RG 0x1c76 9540#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 9541#define regOTG2_OTG_CRC2_DATA_B 0x1c77 9542#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 9543#define regOTG2_OTG_CRC3_DATA_RG 0x1c78 9544#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 9545#define regOTG2_OTG_CRC3_DATA_B 0x1c79 9546#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 9547#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a 9548#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9549#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b 9550#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9551#define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82 9552#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9553#define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83 9554#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9555#define regOTG2_OTG_GSL_VSYNC_GAP 0x1c84 9556#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9557#define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c85 9558#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9559#define regOTG2_OTG_CLOCK_CONTROL 0x1c86 9560#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 9561#define regOTG2_OTG_VSTARTUP_PARAM 0x1c87 9562#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 9563#define regOTG2_OTG_VUPDATE_PARAM 0x1c88 9564#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 9565#define regOTG2_OTG_VREADY_PARAM 0x1c89 9566#define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 9567#define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a 9568#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9569#define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b 9570#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9571#define regOTG2_OTG_GSL_CONTROL 0x1c8c 9572#define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 9573#define regOTG2_OTG_GSL_WINDOW_X 0x1c8d 9574#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 9575#define regOTG2_OTG_GSL_WINDOW_Y 0x1c8e 9576#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 9577#define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f 9578#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9579#define regOTG2_OTG_GLOBAL_CONTROL0 0x1c90 9580#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9581#define regOTG2_OTG_GLOBAL_CONTROL1 0x1c91 9582#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9583#define regOTG2_OTG_GLOBAL_CONTROL2 0x1c92 9584#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9585#define regOTG2_OTG_GLOBAL_CONTROL3 0x1c93 9586#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9587#define regOTG2_OTG_GLOBAL_CONTROL4 0x1c94 9588#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9589#define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c95 9590#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9591#define regOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c96 9592#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9593#define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c97 9594#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9595#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c98 9596#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9597#define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c99 9598#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9599#define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c9a 9600#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9601#define regOTG2_OTG_DRR_CONTROL 0x1c9b 9602#define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 9603#define regOTG2_OTG_M_CONST_DTO0 0x1c9c 9604#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 9605#define regOTG2_OTG_M_CONST_DTO1 0x1c9d 9606#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 9607#define regOTG2_OTG_REQUEST_CONTROL 0x1c9e 9608#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 9609#define regOTG2_OTG_DSC_START_POSITION 0x1c9f 9610#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 9611#define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1ca0 9612#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9613#define regOTG2_OTG_SPARE_REGISTER 0x1ca2 9614#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 9615 9616 9617// addressBlock: dce_dc_optc_otg3_dispdec 9618// base address: 0x600 9619#define regOTG3_OTG_H_TOTAL 0x1caa 9620#define regOTG3_OTG_H_TOTAL_BASE_IDX 2 9621#define regOTG3_OTG_H_BLANK_START_END 0x1cab 9622#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 9623#define regOTG3_OTG_H_SYNC_A 0x1cac 9624#define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 9625#define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad 9626#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9627#define regOTG3_OTG_H_TIMING_CNTL 0x1cae 9628#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 9629#define regOTG3_OTG_V_TOTAL 0x1caf 9630#define regOTG3_OTG_V_TOTAL_BASE_IDX 2 9631#define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 9632#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 9633#define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 9634#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 9635#define regOTG3_OTG_V_TOTAL_MID 0x1cb2 9636#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 9637#define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 9638#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9639#define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 9640#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9641#define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 9642#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9643#define regOTG3_OTG_V_BLANK_START_END 0x1cb6 9644#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 9645#define regOTG3_OTG_V_SYNC_A 0x1cb7 9646#define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 9647#define regOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 9648#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9649#define regOTG3_OTG_TRIGA_CNTL 0x1cb9 9650#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 9651#define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba 9652#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9653#define regOTG3_OTG_TRIGB_CNTL 0x1cbb 9654#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 9655#define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc 9656#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9657#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd 9658#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9659#define regOTG3_OTG_FLOW_CONTROL 0x1cbe 9660#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 9661#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf 9662#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9663#define regOTG3_OTG_CONTROL 0x1cc1 9664#define regOTG3_OTG_CONTROL_BASE_IDX 2 9665#define regOTG3_OTG_INTERLACE_CONTROL 0x1cc4 9666#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 9667#define regOTG3_OTG_INTERLACE_STATUS 0x1cc5 9668#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 9669#define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 9670#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9671#define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 9672#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9673#define regOTG3_OTG_STATUS 0x1cc9 9674#define regOTG3_OTG_STATUS_BASE_IDX 2 9675#define regOTG3_OTG_STATUS_POSITION 0x1cca 9676#define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 9677#define regOTG3_OTG_NOM_VERT_POSITION 0x1ccb 9678#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 9679#define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc 9680#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9681#define regOTG3_OTG_STATUS_VF_COUNT 0x1ccd 9682#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 9683#define regOTG3_OTG_STATUS_HV_COUNT 0x1cce 9684#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 9685#define regOTG3_OTG_COUNT_CONTROL 0x1ccf 9686#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 9687#define regOTG3_OTG_COUNT_RESET 0x1cd0 9688#define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 9689#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 9690#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9691#define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 9692#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9693#define regOTG3_OTG_STEREO_STATUS 0x1cd3 9694#define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 9695#define regOTG3_OTG_STEREO_CONTROL 0x1cd4 9696#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 9697#define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 9698#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9699#define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 9700#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9701#define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 9702#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9703#define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 9704#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9705#define regOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 9706#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9707#define regOTG3_OTG_UPDATE_LOCK 0x1cda 9708#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 9709#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb 9710#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9711#define regOTG3_OTG_MASTER_EN 0x1cdc 9712#define regOTG3_OTG_MASTER_EN_BASE_IDX 2 9713#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 9714#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9715#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 9716#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9717#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 9718#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9719#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 9720#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9721#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 9722#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9723#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 9724#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9725#define regOTG3_OTG_CRC_CNTL 0x1ce8 9726#define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 9727#define regOTG3_OTG_CRC_CNTL2 0x1ce9 9728#define regOTG3_OTG_CRC_CNTL2_BASE_IDX 2 9729#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea 9730#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9731#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb 9732#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9733#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec 9734#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9735#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced 9736#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9737#define regOTG3_OTG_CRC0_DATA_RG 0x1cee 9738#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 9739#define regOTG3_OTG_CRC0_DATA_B 0x1cef 9740#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 9741#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0 9742#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9743#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1 9744#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9745#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2 9746#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9747#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3 9748#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9749#define regOTG3_OTG_CRC1_DATA_RG 0x1cf4 9750#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 9751#define regOTG3_OTG_CRC1_DATA_B 0x1cf5 9752#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 9753#define regOTG3_OTG_CRC2_DATA_RG 0x1cf6 9754#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 9755#define regOTG3_OTG_CRC2_DATA_B 0x1cf7 9756#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 9757#define regOTG3_OTG_CRC3_DATA_RG 0x1cf8 9758#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 9759#define regOTG3_OTG_CRC3_DATA_B 0x1cf9 9760#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 9761#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa 9762#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9763#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb 9764#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9765#define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02 9766#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9767#define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03 9768#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9769#define regOTG3_OTG_GSL_VSYNC_GAP 0x1d04 9770#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9771#define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d05 9772#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9773#define regOTG3_OTG_CLOCK_CONTROL 0x1d06 9774#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 9775#define regOTG3_OTG_VSTARTUP_PARAM 0x1d07 9776#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 9777#define regOTG3_OTG_VUPDATE_PARAM 0x1d08 9778#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 9779#define regOTG3_OTG_VREADY_PARAM 0x1d09 9780#define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 9781#define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a 9782#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9783#define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b 9784#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9785#define regOTG3_OTG_GSL_CONTROL 0x1d0c 9786#define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 9787#define regOTG3_OTG_GSL_WINDOW_X 0x1d0d 9788#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 9789#define regOTG3_OTG_GSL_WINDOW_Y 0x1d0e 9790#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 9791#define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f 9792#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9793#define regOTG3_OTG_GLOBAL_CONTROL0 0x1d10 9794#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9795#define regOTG3_OTG_GLOBAL_CONTROL1 0x1d11 9796#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9797#define regOTG3_OTG_GLOBAL_CONTROL2 0x1d12 9798#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9799#define regOTG3_OTG_GLOBAL_CONTROL3 0x1d13 9800#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9801#define regOTG3_OTG_GLOBAL_CONTROL4 0x1d14 9802#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9803#define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d15 9804#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9805#define regOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d16 9806#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9807#define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d17 9808#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9809#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d18 9810#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9811#define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d19 9812#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9813#define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d1a 9814#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9815#define regOTG3_OTG_DRR_CONTROL 0x1d1b 9816#define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 9817#define regOTG3_OTG_M_CONST_DTO0 0x1d1c 9818#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 9819#define regOTG3_OTG_M_CONST_DTO1 0x1d1d 9820#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 9821#define regOTG3_OTG_REQUEST_CONTROL 0x1d1e 9822#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 9823#define regOTG3_OTG_DSC_START_POSITION 0x1d1f 9824#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 9825#define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d20 9826#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9827#define regOTG3_OTG_SPARE_REGISTER 0x1d22 9828#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 9829 9830 9831// addressBlock: dce_dc_optc_optc_misc_dispdec 9832// base address: 0x0 9833#define regDWB_SOURCE_SELECT 0x1e2a 9834#define regDWB_SOURCE_SELECT_BASE_IDX 2 9835#define regGSL_SOURCE_SELECT 0x1e2b 9836#define regGSL_SOURCE_SELECT_BASE_IDX 2 9837#define regOPTC_CLOCK_CONTROL 0x1e2c 9838#define regOPTC_CLOCK_CONTROL_BASE_IDX 2 9839#define regODM_MEM_PWR_CTRL 0x1e2d 9840#define regODM_MEM_PWR_CTRL_BASE_IDX 2 9841#define regODM_MEM_PWR_CTRL3 0x1e2f 9842#define regODM_MEM_PWR_CTRL3_BASE_IDX 2 9843#define regODM_MEM_PWR_STATUS 0x1e30 9844#define regODM_MEM_PWR_STATUS_BASE_IDX 2 9845#define regOPTC_MISC_SPARE_REGISTER 0x1e31 9846#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 9847 9848 9849// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec 9850// base address: 0x79a8 9851#define regDC_PERFMON17_PERFCOUNTER_CNTL 0x1e6a 9852#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 9853#define regDC_PERFMON17_PERFCOUNTER_CNTL2 0x1e6b 9854#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 9855#define regDC_PERFMON17_PERFCOUNTER_STATE 0x1e6c 9856#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 9857#define regDC_PERFMON17_PERFMON_CNTL 0x1e6d 9858#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 9859#define regDC_PERFMON17_PERFMON_CNTL2 0x1e6e 9860#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 9861#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1e6f 9862#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 9863#define regDC_PERFMON17_PERFMON_CVALUE_LOW 0x1e70 9864#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 9865#define regDC_PERFMON17_PERFMON_HI 0x1e71 9866#define regDC_PERFMON17_PERFMON_HI_BASE_IDX 2 9867#define regDC_PERFMON17_PERFMON_LOW 0x1e72 9868#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 9869 9870 9871// addressBlock: dce_dc_dio_hpd0_dispdec 9872// base address: 0x0 9873#define regHPD0_DC_HPD_INT_STATUS 0x1f14 9874#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 9875#define regHPD0_DC_HPD_INT_CONTROL 0x1f15 9876#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 9877#define regHPD0_DC_HPD_CONTROL 0x1f16 9878#define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 9879#define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 9880#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9881#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 9882#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9883 9884 9885// addressBlock: dce_dc_dio_hpd1_dispdec 9886// base address: 0x20 9887#define regHPD1_DC_HPD_INT_STATUS 0x1f1c 9888#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 9889#define regHPD1_DC_HPD_INT_CONTROL 0x1f1d 9890#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 9891#define regHPD1_DC_HPD_CONTROL 0x1f1e 9892#define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 9893#define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 9894#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9895#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 9896#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9897 9898 9899// addressBlock: dce_dc_dio_hpd2_dispdec 9900// base address: 0x40 9901#define regHPD2_DC_HPD_INT_STATUS 0x1f24 9902#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 9903#define regHPD2_DC_HPD_INT_CONTROL 0x1f25 9904#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 9905#define regHPD2_DC_HPD_CONTROL 0x1f26 9906#define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 9907#define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 9908#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9909#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 9910#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9911 9912 9913// addressBlock: dce_dc_dio_hpd3_dispdec 9914// base address: 0x60 9915#define regHPD3_DC_HPD_INT_STATUS 0x1f2c 9916#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 9917#define regHPD3_DC_HPD_INT_CONTROL 0x1f2d 9918#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 9919#define regHPD3_DC_HPD_CONTROL 0x1f2e 9920#define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 9921#define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f 9922#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9923#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 9924#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9925 9926 9927// addressBlock: dce_dc_dio_hpd4_dispdec 9928// base address: 0x80 9929#define regHPD4_DC_HPD_INT_STATUS 0x1f34 9930#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 9931#define regHPD4_DC_HPD_INT_CONTROL 0x1f35 9932#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 9933#define regHPD4_DC_HPD_CONTROL 0x1f36 9934#define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 9935#define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 9936#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9937#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 9938#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9939 9940 9941// addressBlock: dce_dc_dio_dp0_dispdec 9942// base address: 0x0 9943#define regDP0_DP_LINK_CNTL 0x2108 9944#define regDP0_DP_LINK_CNTL_BASE_IDX 2 9945#define regDP0_DP_PIXEL_FORMAT 0x2109 9946#define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 9947#define regDP0_DP_MSA_COLORIMETRY 0x210a 9948#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 9949#define regDP0_DP_CONFIG 0x210b 9950#define regDP0_DP_CONFIG_BASE_IDX 2 9951#define regDP0_DP_VID_STREAM_CNTL 0x210c 9952#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 9953#define regDP0_DP_STEER_FIFO 0x210d 9954#define regDP0_DP_STEER_FIFO_BASE_IDX 2 9955#define regDP0_DP_MSA_MISC 0x210e 9956#define regDP0_DP_MSA_MISC_BASE_IDX 2 9957#define regDP0_DP_DPHY_INTERNAL_CTRL 0x210f 9958#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9959#define regDP0_DP_VID_TIMING 0x2110 9960#define regDP0_DP_VID_TIMING_BASE_IDX 2 9961#define regDP0_DP_VID_N 0x2111 9962#define regDP0_DP_VID_N_BASE_IDX 2 9963#define regDP0_DP_VID_M 0x2112 9964#define regDP0_DP_VID_M_BASE_IDX 2 9965#define regDP0_DP_LINK_FRAMING_CNTL 0x2113 9966#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9967#define regDP0_DP_HBR2_EYE_PATTERN 0x2114 9968#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9969#define regDP0_DP_VID_MSA_VBID 0x2115 9970#define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 9971#define regDP0_DP_VID_INTERRUPT_CNTL 0x2116 9972#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9973#define regDP0_DP_DPHY_CNTL 0x2117 9974#define regDP0_DP_DPHY_CNTL_BASE_IDX 2 9975#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 9976#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9977#define regDP0_DP_DPHY_SYM0 0x2119 9978#define regDP0_DP_DPHY_SYM0_BASE_IDX 2 9979#define regDP0_DP_DPHY_SYM1 0x211a 9980#define regDP0_DP_DPHY_SYM1_BASE_IDX 2 9981#define regDP0_DP_DPHY_SYM2 0x211b 9982#define regDP0_DP_DPHY_SYM2_BASE_IDX 2 9983#define regDP0_DP_DPHY_8B10B_CNTL 0x211c 9984#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9985#define regDP0_DP_DPHY_PRBS_CNTL 0x211d 9986#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9987#define regDP0_DP_DPHY_SCRAM_CNTL 0x211e 9988#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9989#define regDP0_DP_DPHY_CRC_EN 0x211f 9990#define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 9991#define regDP0_DP_DPHY_CRC_CNTL 0x2120 9992#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 9993#define regDP0_DP_DPHY_CRC_RESULT 0x2121 9994#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 9995#define regDP0_DP_DPHY_CRC_MST_CNTL 0x2122 9996#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9997#define regDP0_DP_DPHY_CRC_MST_STATUS 0x2123 9998#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9999#define regDP0_DP_DPHY_FAST_TRAINING 0x2124 10000#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10001#define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 10002#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10003#define regDP0_DP_SEC_CNTL 0x212b 10004#define regDP0_DP_SEC_CNTL_BASE_IDX 2 10005#define regDP0_DP_SEC_CNTL1 0x212c 10006#define regDP0_DP_SEC_CNTL1_BASE_IDX 2 10007#define regDP0_DP_SEC_FRAMING1 0x212d 10008#define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 10009#define regDP0_DP_SEC_FRAMING2 0x212e 10010#define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 10011#define regDP0_DP_SEC_FRAMING3 0x212f 10012#define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 10013#define regDP0_DP_SEC_FRAMING4 0x2130 10014#define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 10015#define regDP0_DP_SEC_AUD_N 0x2131 10016#define regDP0_DP_SEC_AUD_N_BASE_IDX 2 10017#define regDP0_DP_SEC_AUD_N_READBACK 0x2132 10018#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10019#define regDP0_DP_SEC_AUD_M 0x2133 10020#define regDP0_DP_SEC_AUD_M_BASE_IDX 2 10021#define regDP0_DP_SEC_AUD_M_READBACK 0x2134 10022#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10023#define regDP0_DP_SEC_TIMESTAMP 0x2135 10024#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 10025#define regDP0_DP_SEC_PACKET_CNTL 0x2136 10026#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 10027#define regDP0_DP_MSE_RATE_CNTL 0x2137 10028#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 10029#define regDP0_DP_MSE_RATE_UPDATE 0x2139 10030#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 10031#define regDP0_DP_MSE_SAT0 0x213a 10032#define regDP0_DP_MSE_SAT0_BASE_IDX 2 10033#define regDP0_DP_MSE_SAT1 0x213b 10034#define regDP0_DP_MSE_SAT1_BASE_IDX 2 10035#define regDP0_DP_MSE_SAT2 0x213c 10036#define regDP0_DP_MSE_SAT2_BASE_IDX 2 10037#define regDP0_DP_MSE_SAT_UPDATE 0x213d 10038#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 10039#define regDP0_DP_MSE_LINK_TIMING 0x213e 10040#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 10041#define regDP0_DP_MSE_MISC_CNTL 0x213f 10042#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 10043#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 10044#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10045#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 10046#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10047#define regDP0_DP_MSE_SAT0_STATUS 0x2147 10048#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 10049#define regDP0_DP_MSE_SAT1_STATUS 0x2148 10050#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 10051#define regDP0_DP_MSE_SAT2_STATUS 0x2149 10052#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 10053#define regDP0_DP_MSA_TIMING_PARAM1 0x214c 10054#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10055#define regDP0_DP_MSA_TIMING_PARAM2 0x214d 10056#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10057#define regDP0_DP_MSA_TIMING_PARAM3 0x214e 10058#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10059#define regDP0_DP_MSA_TIMING_PARAM4 0x214f 10060#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10061#define regDP0_DP_MSO_CNTL 0x2150 10062#define regDP0_DP_MSO_CNTL_BASE_IDX 2 10063#define regDP0_DP_MSO_CNTL1 0x2151 10064#define regDP0_DP_MSO_CNTL1_BASE_IDX 2 10065#define regDP0_DP_DSC_CNTL 0x2152 10066#define regDP0_DP_DSC_CNTL_BASE_IDX 2 10067#define regDP0_DP_SEC_CNTL2 0x2153 10068#define regDP0_DP_SEC_CNTL2_BASE_IDX 2 10069#define regDP0_DP_SEC_CNTL3 0x2154 10070#define regDP0_DP_SEC_CNTL3_BASE_IDX 2 10071#define regDP0_DP_SEC_CNTL4 0x2155 10072#define regDP0_DP_SEC_CNTL4_BASE_IDX 2 10073#define regDP0_DP_SEC_CNTL5 0x2156 10074#define regDP0_DP_SEC_CNTL5_BASE_IDX 2 10075#define regDP0_DP_SEC_CNTL6 0x2157 10076#define regDP0_DP_SEC_CNTL6_BASE_IDX 2 10077#define regDP0_DP_SEC_CNTL7 0x2158 10078#define regDP0_DP_SEC_CNTL7_BASE_IDX 2 10079#define regDP0_DP_DB_CNTL 0x2159 10080#define regDP0_DP_DB_CNTL_BASE_IDX 2 10081#define regDP0_DP_MSA_VBID_MISC 0x215a 10082#define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 10083#define regDP0_DP_SEC_METADATA_TRANSMISSION 0x215b 10084#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10085#define regDP0_DP_DSC_BYTES_PER_PIXEL 0x215c 10086#define regDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10087#define regDP0_DP_ALPM_CNTL 0x215d 10088#define regDP0_DP_ALPM_CNTL_BASE_IDX 2 10089#define regDP0_DP_GSP8_CNTL 0x215e 10090#define regDP0_DP_GSP8_CNTL_BASE_IDX 2 10091#define regDP0_DP_GSP9_CNTL 0x215f 10092#define regDP0_DP_GSP9_CNTL_BASE_IDX 2 10093#define regDP0_DP_GSP10_CNTL 0x2160 10094#define regDP0_DP_GSP10_CNTL_BASE_IDX 2 10095#define regDP0_DP_GSP11_CNTL 0x2161 10096#define regDP0_DP_GSP11_CNTL_BASE_IDX 2 10097#define regDP0_DP_GSP_EN_DB_STATUS 0x2162 10098#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10099 10100 10101// addressBlock: dce_dc_dio_dig0_dispdec 10102// base address: 0x0 10103#define regDIG0_DIG_FE_CNTL 0x208b 10104#define regDIG0_DIG_FE_CNTL_BASE_IDX 2 10105#define regDIG0_DIG_OUTPUT_CRC_CNTL 0x208c 10106#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10107#define regDIG0_DIG_OUTPUT_CRC_RESULT 0x208d 10108#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10109#define regDIG0_DIG_CLOCK_PATTERN 0x208e 10110#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 10111#define regDIG0_DIG_TEST_PATTERN 0x208f 10112#define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 10113#define regDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 10114#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10115#define regDIG0_DIG_FIFO_STATUS 0x2091 10116#define regDIG0_DIG_FIFO_STATUS_BASE_IDX 2 10117#define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x2092 10118#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10119#define regDIG0_HDMI_CONTROL 0x2093 10120#define regDIG0_HDMI_CONTROL_BASE_IDX 2 10121#define regDIG0_HDMI_STATUS 0x2094 10122#define regDIG0_HDMI_STATUS_BASE_IDX 2 10123#define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2095 10124#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10125#define regDIG0_HDMI_ACR_PACKET_CONTROL 0x2096 10126#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10127#define regDIG0_HDMI_VBI_PACKET_CONTROL 0x2097 10128#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10129#define regDIG0_HDMI_INFOFRAME_CONTROL0 0x2098 10130#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10131#define regDIG0_HDMI_INFOFRAME_CONTROL1 0x2099 10132#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10133#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209a 10134#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10135#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209b 10136#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10137#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209c 10138#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10139#define regDIG0_HDMI_GC 0x209d 10140#define regDIG0_HDMI_GC_BASE_IDX 2 10141#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209e 10142#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10143#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x209f 10144#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10145#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a0 10146#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10147#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a1 10148#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10149#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a2 10150#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10151#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a3 10152#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10153#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a4 10154#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10155#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a5 10156#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10157#define regDIG0_HDMI_DB_CONTROL 0x20a6 10158#define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 10159#define regDIG0_HDMI_ACR_32_0 0x20a7 10160#define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 10161#define regDIG0_HDMI_ACR_32_1 0x20a8 10162#define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 10163#define regDIG0_HDMI_ACR_44_0 0x20a9 10164#define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 10165#define regDIG0_HDMI_ACR_44_1 0x20aa 10166#define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 10167#define regDIG0_HDMI_ACR_48_0 0x20ab 10168#define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 10169#define regDIG0_HDMI_ACR_48_1 0x20ac 10170#define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 10171#define regDIG0_HDMI_ACR_STATUS_0 0x20ad 10172#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 10173#define regDIG0_HDMI_ACR_STATUS_1 0x20ae 10174#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 10175#define regDIG0_AFMT_CNTL 0x20af 10176#define regDIG0_AFMT_CNTL_BASE_IDX 2 10177#define regDIG0_DIG_BE_CNTL 0x20b0 10178#define regDIG0_DIG_BE_CNTL_BASE_IDX 2 10179#define regDIG0_DIG_BE_EN_CNTL 0x20b1 10180#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 10181#define regDIG0_TMDS_CNTL 0x20d7 10182#define regDIG0_TMDS_CNTL_BASE_IDX 2 10183#define regDIG0_TMDS_CONTROL_CHAR 0x20d8 10184#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 10185#define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20d9 10186#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10187#define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20da 10188#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10189#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20db 10190#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10191#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dc 10192#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10193#define regDIG0_TMDS_CTL_BITS 0x20de 10194#define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 10195#define regDIG0_TMDS_DCBALANCER_CONTROL 0x20df 10196#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10197#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e0 10198#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10199#define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e1 10200#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10201#define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e2 10202#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10203#define regDIG0_DIG_VERSION 0x20e4 10204#define regDIG0_DIG_VERSION_BASE_IDX 2 10205#define regDIG0_FORCE_DIG_DISABLE 0x20e5 10206#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 10207 10208 10209// addressBlock: dce_dc_dio_dp1_dispdec 10210// base address: 0x400 10211#define regDP1_DP_LINK_CNTL 0x2208 10212#define regDP1_DP_LINK_CNTL_BASE_IDX 2 10213#define regDP1_DP_PIXEL_FORMAT 0x2209 10214#define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 10215#define regDP1_DP_MSA_COLORIMETRY 0x220a 10216#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 10217#define regDP1_DP_CONFIG 0x220b 10218#define regDP1_DP_CONFIG_BASE_IDX 2 10219#define regDP1_DP_VID_STREAM_CNTL 0x220c 10220#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 10221#define regDP1_DP_STEER_FIFO 0x220d 10222#define regDP1_DP_STEER_FIFO_BASE_IDX 2 10223#define regDP1_DP_MSA_MISC 0x220e 10224#define regDP1_DP_MSA_MISC_BASE_IDX 2 10225#define regDP1_DP_DPHY_INTERNAL_CTRL 0x220f 10226#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10227#define regDP1_DP_VID_TIMING 0x2210 10228#define regDP1_DP_VID_TIMING_BASE_IDX 2 10229#define regDP1_DP_VID_N 0x2211 10230#define regDP1_DP_VID_N_BASE_IDX 2 10231#define regDP1_DP_VID_M 0x2212 10232#define regDP1_DP_VID_M_BASE_IDX 2 10233#define regDP1_DP_LINK_FRAMING_CNTL 0x2213 10234#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10235#define regDP1_DP_HBR2_EYE_PATTERN 0x2214 10236#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10237#define regDP1_DP_VID_MSA_VBID 0x2215 10238#define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 10239#define regDP1_DP_VID_INTERRUPT_CNTL 0x2216 10240#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10241#define regDP1_DP_DPHY_CNTL 0x2217 10242#define regDP1_DP_DPHY_CNTL_BASE_IDX 2 10243#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 10244#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10245#define regDP1_DP_DPHY_SYM0 0x2219 10246#define regDP1_DP_DPHY_SYM0_BASE_IDX 2 10247#define regDP1_DP_DPHY_SYM1 0x221a 10248#define regDP1_DP_DPHY_SYM1_BASE_IDX 2 10249#define regDP1_DP_DPHY_SYM2 0x221b 10250#define regDP1_DP_DPHY_SYM2_BASE_IDX 2 10251#define regDP1_DP_DPHY_8B10B_CNTL 0x221c 10252#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10253#define regDP1_DP_DPHY_PRBS_CNTL 0x221d 10254#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10255#define regDP1_DP_DPHY_SCRAM_CNTL 0x221e 10256#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10257#define regDP1_DP_DPHY_CRC_EN 0x221f 10258#define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 10259#define regDP1_DP_DPHY_CRC_CNTL 0x2220 10260#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 10261#define regDP1_DP_DPHY_CRC_RESULT 0x2221 10262#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 10263#define regDP1_DP_DPHY_CRC_MST_CNTL 0x2222 10264#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10265#define regDP1_DP_DPHY_CRC_MST_STATUS 0x2223 10266#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10267#define regDP1_DP_DPHY_FAST_TRAINING 0x2224 10268#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10269#define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 10270#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10271#define regDP1_DP_SEC_CNTL 0x222b 10272#define regDP1_DP_SEC_CNTL_BASE_IDX 2 10273#define regDP1_DP_SEC_CNTL1 0x222c 10274#define regDP1_DP_SEC_CNTL1_BASE_IDX 2 10275#define regDP1_DP_SEC_FRAMING1 0x222d 10276#define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 10277#define regDP1_DP_SEC_FRAMING2 0x222e 10278#define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 10279#define regDP1_DP_SEC_FRAMING3 0x222f 10280#define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 10281#define regDP1_DP_SEC_FRAMING4 0x2230 10282#define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 10283#define regDP1_DP_SEC_AUD_N 0x2231 10284#define regDP1_DP_SEC_AUD_N_BASE_IDX 2 10285#define regDP1_DP_SEC_AUD_N_READBACK 0x2232 10286#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10287#define regDP1_DP_SEC_AUD_M 0x2233 10288#define regDP1_DP_SEC_AUD_M_BASE_IDX 2 10289#define regDP1_DP_SEC_AUD_M_READBACK 0x2234 10290#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10291#define regDP1_DP_SEC_TIMESTAMP 0x2235 10292#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 10293#define regDP1_DP_SEC_PACKET_CNTL 0x2236 10294#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 10295#define regDP1_DP_MSE_RATE_CNTL 0x2237 10296#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 10297#define regDP1_DP_MSE_RATE_UPDATE 0x2239 10298#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 10299#define regDP1_DP_MSE_SAT0 0x223a 10300#define regDP1_DP_MSE_SAT0_BASE_IDX 2 10301#define regDP1_DP_MSE_SAT1 0x223b 10302#define regDP1_DP_MSE_SAT1_BASE_IDX 2 10303#define regDP1_DP_MSE_SAT2 0x223c 10304#define regDP1_DP_MSE_SAT2_BASE_IDX 2 10305#define regDP1_DP_MSE_SAT_UPDATE 0x223d 10306#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 10307#define regDP1_DP_MSE_LINK_TIMING 0x223e 10308#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 10309#define regDP1_DP_MSE_MISC_CNTL 0x223f 10310#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 10311#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 10312#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10313#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 10314#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10315#define regDP1_DP_MSE_SAT0_STATUS 0x2247 10316#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 10317#define regDP1_DP_MSE_SAT1_STATUS 0x2248 10318#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 10319#define regDP1_DP_MSE_SAT2_STATUS 0x2249 10320#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 10321#define regDP1_DP_MSA_TIMING_PARAM1 0x224c 10322#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10323#define regDP1_DP_MSA_TIMING_PARAM2 0x224d 10324#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10325#define regDP1_DP_MSA_TIMING_PARAM3 0x224e 10326#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10327#define regDP1_DP_MSA_TIMING_PARAM4 0x224f 10328#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10329#define regDP1_DP_MSO_CNTL 0x2250 10330#define regDP1_DP_MSO_CNTL_BASE_IDX 2 10331#define regDP1_DP_MSO_CNTL1 0x2251 10332#define regDP1_DP_MSO_CNTL1_BASE_IDX 2 10333#define regDP1_DP_DSC_CNTL 0x2252 10334#define regDP1_DP_DSC_CNTL_BASE_IDX 2 10335#define regDP1_DP_SEC_CNTL2 0x2253 10336#define regDP1_DP_SEC_CNTL2_BASE_IDX 2 10337#define regDP1_DP_SEC_CNTL3 0x2254 10338#define regDP1_DP_SEC_CNTL3_BASE_IDX 2 10339#define regDP1_DP_SEC_CNTL4 0x2255 10340#define regDP1_DP_SEC_CNTL4_BASE_IDX 2 10341#define regDP1_DP_SEC_CNTL5 0x2256 10342#define regDP1_DP_SEC_CNTL5_BASE_IDX 2 10343#define regDP1_DP_SEC_CNTL6 0x2257 10344#define regDP1_DP_SEC_CNTL6_BASE_IDX 2 10345#define regDP1_DP_SEC_CNTL7 0x2258 10346#define regDP1_DP_SEC_CNTL7_BASE_IDX 2 10347#define regDP1_DP_DB_CNTL 0x2259 10348#define regDP1_DP_DB_CNTL_BASE_IDX 2 10349#define regDP1_DP_MSA_VBID_MISC 0x225a 10350#define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 10351#define regDP1_DP_SEC_METADATA_TRANSMISSION 0x225b 10352#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10353#define regDP1_DP_DSC_BYTES_PER_PIXEL 0x225c 10354#define regDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10355#define regDP1_DP_ALPM_CNTL 0x225d 10356#define regDP1_DP_ALPM_CNTL_BASE_IDX 2 10357#define regDP1_DP_GSP8_CNTL 0x225e 10358#define regDP1_DP_GSP8_CNTL_BASE_IDX 2 10359#define regDP1_DP_GSP9_CNTL 0x225f 10360#define regDP1_DP_GSP9_CNTL_BASE_IDX 2 10361#define regDP1_DP_GSP10_CNTL 0x2260 10362#define regDP1_DP_GSP10_CNTL_BASE_IDX 2 10363#define regDP1_DP_GSP11_CNTL 0x2261 10364#define regDP1_DP_GSP11_CNTL_BASE_IDX 2 10365#define regDP1_DP_GSP_EN_DB_STATUS 0x2262 10366#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10367 10368 10369// addressBlock: dce_dc_dio_dig1_dispdec 10370// base address: 0x400 10371#define regDIG1_DIG_FE_CNTL 0x218b 10372#define regDIG1_DIG_FE_CNTL_BASE_IDX 2 10373#define regDIG1_DIG_OUTPUT_CRC_CNTL 0x218c 10374#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10375#define regDIG1_DIG_OUTPUT_CRC_RESULT 0x218d 10376#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10377#define regDIG1_DIG_CLOCK_PATTERN 0x218e 10378#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 10379#define regDIG1_DIG_TEST_PATTERN 0x218f 10380#define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 10381#define regDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 10382#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10383#define regDIG1_DIG_FIFO_STATUS 0x2191 10384#define regDIG1_DIG_FIFO_STATUS_BASE_IDX 2 10385#define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x2192 10386#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10387#define regDIG1_HDMI_CONTROL 0x2193 10388#define regDIG1_HDMI_CONTROL_BASE_IDX 2 10389#define regDIG1_HDMI_STATUS 0x2194 10390#define regDIG1_HDMI_STATUS_BASE_IDX 2 10391#define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2195 10392#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10393#define regDIG1_HDMI_ACR_PACKET_CONTROL 0x2196 10394#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10395#define regDIG1_HDMI_VBI_PACKET_CONTROL 0x2197 10396#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10397#define regDIG1_HDMI_INFOFRAME_CONTROL0 0x2198 10398#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10399#define regDIG1_HDMI_INFOFRAME_CONTROL1 0x2199 10400#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10401#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219a 10402#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10403#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219b 10404#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10405#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219c 10406#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10407#define regDIG1_HDMI_GC 0x219d 10408#define regDIG1_HDMI_GC_BASE_IDX 2 10409#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219e 10410#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10411#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x219f 10412#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10413#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a0 10414#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10415#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a1 10416#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10417#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a2 10418#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10419#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a3 10420#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10421#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a4 10422#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10423#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a5 10424#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10425#define regDIG1_HDMI_DB_CONTROL 0x21a6 10426#define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 10427#define regDIG1_HDMI_ACR_32_0 0x21a7 10428#define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 10429#define regDIG1_HDMI_ACR_32_1 0x21a8 10430#define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 10431#define regDIG1_HDMI_ACR_44_0 0x21a9 10432#define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 10433#define regDIG1_HDMI_ACR_44_1 0x21aa 10434#define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 10435#define regDIG1_HDMI_ACR_48_0 0x21ab 10436#define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 10437#define regDIG1_HDMI_ACR_48_1 0x21ac 10438#define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 10439#define regDIG1_HDMI_ACR_STATUS_0 0x21ad 10440#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 10441#define regDIG1_HDMI_ACR_STATUS_1 0x21ae 10442#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 10443#define regDIG1_AFMT_CNTL 0x21af 10444#define regDIG1_AFMT_CNTL_BASE_IDX 2 10445#define regDIG1_DIG_BE_CNTL 0x21b0 10446#define regDIG1_DIG_BE_CNTL_BASE_IDX 2 10447#define regDIG1_DIG_BE_EN_CNTL 0x21b1 10448#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 10449#define regDIG1_TMDS_CNTL 0x21d7 10450#define regDIG1_TMDS_CNTL_BASE_IDX 2 10451#define regDIG1_TMDS_CONTROL_CHAR 0x21d8 10452#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 10453#define regDIG1_TMDS_CONTROL0_FEEDBACK 0x21d9 10454#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10455#define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21da 10456#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10457#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21db 10458#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10459#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dc 10460#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10461#define regDIG1_TMDS_CTL_BITS 0x21de 10462#define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 10463#define regDIG1_TMDS_DCBALANCER_CONTROL 0x21df 10464#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10465#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e0 10466#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10467#define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e1 10468#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10469#define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e2 10470#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10471#define regDIG1_DIG_VERSION 0x21e4 10472#define regDIG1_DIG_VERSION_BASE_IDX 2 10473#define regDIG1_FORCE_DIG_DISABLE 0x21e5 10474#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 10475 10476 10477// addressBlock: dce_dc_dio_dp2_dispdec 10478// base address: 0x800 10479#define regDP2_DP_LINK_CNTL 0x2308 10480#define regDP2_DP_LINK_CNTL_BASE_IDX 2 10481#define regDP2_DP_PIXEL_FORMAT 0x2309 10482#define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 10483#define regDP2_DP_MSA_COLORIMETRY 0x230a 10484#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 10485#define regDP2_DP_CONFIG 0x230b 10486#define regDP2_DP_CONFIG_BASE_IDX 2 10487#define regDP2_DP_VID_STREAM_CNTL 0x230c 10488#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 10489#define regDP2_DP_STEER_FIFO 0x230d 10490#define regDP2_DP_STEER_FIFO_BASE_IDX 2 10491#define regDP2_DP_MSA_MISC 0x230e 10492#define regDP2_DP_MSA_MISC_BASE_IDX 2 10493#define regDP2_DP_DPHY_INTERNAL_CTRL 0x230f 10494#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10495#define regDP2_DP_VID_TIMING 0x2310 10496#define regDP2_DP_VID_TIMING_BASE_IDX 2 10497#define regDP2_DP_VID_N 0x2311 10498#define regDP2_DP_VID_N_BASE_IDX 2 10499#define regDP2_DP_VID_M 0x2312 10500#define regDP2_DP_VID_M_BASE_IDX 2 10501#define regDP2_DP_LINK_FRAMING_CNTL 0x2313 10502#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10503#define regDP2_DP_HBR2_EYE_PATTERN 0x2314 10504#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10505#define regDP2_DP_VID_MSA_VBID 0x2315 10506#define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 10507#define regDP2_DP_VID_INTERRUPT_CNTL 0x2316 10508#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10509#define regDP2_DP_DPHY_CNTL 0x2317 10510#define regDP2_DP_DPHY_CNTL_BASE_IDX 2 10511#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 10512#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10513#define regDP2_DP_DPHY_SYM0 0x2319 10514#define regDP2_DP_DPHY_SYM0_BASE_IDX 2 10515#define regDP2_DP_DPHY_SYM1 0x231a 10516#define regDP2_DP_DPHY_SYM1_BASE_IDX 2 10517#define regDP2_DP_DPHY_SYM2 0x231b 10518#define regDP2_DP_DPHY_SYM2_BASE_IDX 2 10519#define regDP2_DP_DPHY_8B10B_CNTL 0x231c 10520#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10521#define regDP2_DP_DPHY_PRBS_CNTL 0x231d 10522#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10523#define regDP2_DP_DPHY_SCRAM_CNTL 0x231e 10524#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10525#define regDP2_DP_DPHY_CRC_EN 0x231f 10526#define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 10527#define regDP2_DP_DPHY_CRC_CNTL 0x2320 10528#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 10529#define regDP2_DP_DPHY_CRC_RESULT 0x2321 10530#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 10531#define regDP2_DP_DPHY_CRC_MST_CNTL 0x2322 10532#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10533#define regDP2_DP_DPHY_CRC_MST_STATUS 0x2323 10534#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10535#define regDP2_DP_DPHY_FAST_TRAINING 0x2324 10536#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10537#define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 10538#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10539#define regDP2_DP_SEC_CNTL 0x232b 10540#define regDP2_DP_SEC_CNTL_BASE_IDX 2 10541#define regDP2_DP_SEC_CNTL1 0x232c 10542#define regDP2_DP_SEC_CNTL1_BASE_IDX 2 10543#define regDP2_DP_SEC_FRAMING1 0x232d 10544#define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 10545#define regDP2_DP_SEC_FRAMING2 0x232e 10546#define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 10547#define regDP2_DP_SEC_FRAMING3 0x232f 10548#define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 10549#define regDP2_DP_SEC_FRAMING4 0x2330 10550#define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 10551#define regDP2_DP_SEC_AUD_N 0x2331 10552#define regDP2_DP_SEC_AUD_N_BASE_IDX 2 10553#define regDP2_DP_SEC_AUD_N_READBACK 0x2332 10554#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10555#define regDP2_DP_SEC_AUD_M 0x2333 10556#define regDP2_DP_SEC_AUD_M_BASE_IDX 2 10557#define regDP2_DP_SEC_AUD_M_READBACK 0x2334 10558#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10559#define regDP2_DP_SEC_TIMESTAMP 0x2335 10560#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 10561#define regDP2_DP_SEC_PACKET_CNTL 0x2336 10562#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 10563#define regDP2_DP_MSE_RATE_CNTL 0x2337 10564#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 10565#define regDP2_DP_MSE_RATE_UPDATE 0x2339 10566#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 10567#define regDP2_DP_MSE_SAT0 0x233a 10568#define regDP2_DP_MSE_SAT0_BASE_IDX 2 10569#define regDP2_DP_MSE_SAT1 0x233b 10570#define regDP2_DP_MSE_SAT1_BASE_IDX 2 10571#define regDP2_DP_MSE_SAT2 0x233c 10572#define regDP2_DP_MSE_SAT2_BASE_IDX 2 10573#define regDP2_DP_MSE_SAT_UPDATE 0x233d 10574#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 10575#define regDP2_DP_MSE_LINK_TIMING 0x233e 10576#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 10577#define regDP2_DP_MSE_MISC_CNTL 0x233f 10578#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 10579#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 10580#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10581#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 10582#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10583#define regDP2_DP_MSE_SAT0_STATUS 0x2347 10584#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 10585#define regDP2_DP_MSE_SAT1_STATUS 0x2348 10586#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 10587#define regDP2_DP_MSE_SAT2_STATUS 0x2349 10588#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 10589#define regDP2_DP_MSA_TIMING_PARAM1 0x234c 10590#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10591#define regDP2_DP_MSA_TIMING_PARAM2 0x234d 10592#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10593#define regDP2_DP_MSA_TIMING_PARAM3 0x234e 10594#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10595#define regDP2_DP_MSA_TIMING_PARAM4 0x234f 10596#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10597#define regDP2_DP_MSO_CNTL 0x2350 10598#define regDP2_DP_MSO_CNTL_BASE_IDX 2 10599#define regDP2_DP_MSO_CNTL1 0x2351 10600#define regDP2_DP_MSO_CNTL1_BASE_IDX 2 10601#define regDP2_DP_DSC_CNTL 0x2352 10602#define regDP2_DP_DSC_CNTL_BASE_IDX 2 10603#define regDP2_DP_SEC_CNTL2 0x2353 10604#define regDP2_DP_SEC_CNTL2_BASE_IDX 2 10605#define regDP2_DP_SEC_CNTL3 0x2354 10606#define regDP2_DP_SEC_CNTL3_BASE_IDX 2 10607#define regDP2_DP_SEC_CNTL4 0x2355 10608#define regDP2_DP_SEC_CNTL4_BASE_IDX 2 10609#define regDP2_DP_SEC_CNTL5 0x2356 10610#define regDP2_DP_SEC_CNTL5_BASE_IDX 2 10611#define regDP2_DP_SEC_CNTL6 0x2357 10612#define regDP2_DP_SEC_CNTL6_BASE_IDX 2 10613#define regDP2_DP_SEC_CNTL7 0x2358 10614#define regDP2_DP_SEC_CNTL7_BASE_IDX 2 10615#define regDP2_DP_DB_CNTL 0x2359 10616#define regDP2_DP_DB_CNTL_BASE_IDX 2 10617#define regDP2_DP_MSA_VBID_MISC 0x235a 10618#define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 10619#define regDP2_DP_SEC_METADATA_TRANSMISSION 0x235b 10620#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10621#define regDP2_DP_DSC_BYTES_PER_PIXEL 0x235c 10622#define regDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10623#define regDP2_DP_ALPM_CNTL 0x235d 10624#define regDP2_DP_ALPM_CNTL_BASE_IDX 2 10625#define regDP2_DP_GSP8_CNTL 0x235e 10626#define regDP2_DP_GSP8_CNTL_BASE_IDX 2 10627#define regDP2_DP_GSP9_CNTL 0x235f 10628#define regDP2_DP_GSP9_CNTL_BASE_IDX 2 10629#define regDP2_DP_GSP10_CNTL 0x2360 10630#define regDP2_DP_GSP10_CNTL_BASE_IDX 2 10631#define regDP2_DP_GSP11_CNTL 0x2361 10632#define regDP2_DP_GSP11_CNTL_BASE_IDX 2 10633#define regDP2_DP_GSP_EN_DB_STATUS 0x2362 10634#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10635 10636 10637// addressBlock: dce_dc_dio_dig2_dispdec 10638// base address: 0x800 10639#define regDIG2_DIG_FE_CNTL 0x228b 10640#define regDIG2_DIG_FE_CNTL_BASE_IDX 2 10641#define regDIG2_DIG_OUTPUT_CRC_CNTL 0x228c 10642#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10643#define regDIG2_DIG_OUTPUT_CRC_RESULT 0x228d 10644#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10645#define regDIG2_DIG_CLOCK_PATTERN 0x228e 10646#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 10647#define regDIG2_DIG_TEST_PATTERN 0x228f 10648#define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 10649#define regDIG2_DIG_RANDOM_PATTERN_SEED 0x2290 10650#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10651#define regDIG2_DIG_FIFO_STATUS 0x2291 10652#define regDIG2_DIG_FIFO_STATUS_BASE_IDX 2 10653#define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x2292 10654#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10655#define regDIG2_HDMI_CONTROL 0x2293 10656#define regDIG2_HDMI_CONTROL_BASE_IDX 2 10657#define regDIG2_HDMI_STATUS 0x2294 10658#define regDIG2_HDMI_STATUS_BASE_IDX 2 10659#define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2295 10660#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10661#define regDIG2_HDMI_ACR_PACKET_CONTROL 0x2296 10662#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10663#define regDIG2_HDMI_VBI_PACKET_CONTROL 0x2297 10664#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10665#define regDIG2_HDMI_INFOFRAME_CONTROL0 0x2298 10666#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10667#define regDIG2_HDMI_INFOFRAME_CONTROL1 0x2299 10668#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10669#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229a 10670#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10671#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229b 10672#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10673#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229c 10674#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10675#define regDIG2_HDMI_GC 0x229d 10676#define regDIG2_HDMI_GC_BASE_IDX 2 10677#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229e 10678#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10679#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x229f 10680#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10681#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a0 10682#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10683#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a1 10684#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10685#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a2 10686#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10687#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a3 10688#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10689#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a4 10690#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10691#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a5 10692#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10693#define regDIG2_HDMI_DB_CONTROL 0x22a6 10694#define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 10695#define regDIG2_HDMI_ACR_32_0 0x22a7 10696#define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 10697#define regDIG2_HDMI_ACR_32_1 0x22a8 10698#define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 10699#define regDIG2_HDMI_ACR_44_0 0x22a9 10700#define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 10701#define regDIG2_HDMI_ACR_44_1 0x22aa 10702#define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 10703#define regDIG2_HDMI_ACR_48_0 0x22ab 10704#define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 10705#define regDIG2_HDMI_ACR_48_1 0x22ac 10706#define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 10707#define regDIG2_HDMI_ACR_STATUS_0 0x22ad 10708#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 10709#define regDIG2_HDMI_ACR_STATUS_1 0x22ae 10710#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 10711#define regDIG2_AFMT_CNTL 0x22af 10712#define regDIG2_AFMT_CNTL_BASE_IDX 2 10713#define regDIG2_DIG_BE_CNTL 0x22b0 10714#define regDIG2_DIG_BE_CNTL_BASE_IDX 2 10715#define regDIG2_DIG_BE_EN_CNTL 0x22b1 10716#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 10717#define regDIG2_TMDS_CNTL 0x22d7 10718#define regDIG2_TMDS_CNTL_BASE_IDX 2 10719#define regDIG2_TMDS_CONTROL_CHAR 0x22d8 10720#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 10721#define regDIG2_TMDS_CONTROL0_FEEDBACK 0x22d9 10722#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10723#define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22da 10724#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10725#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22db 10726#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10727#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dc 10728#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10729#define regDIG2_TMDS_CTL_BITS 0x22de 10730#define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 10731#define regDIG2_TMDS_DCBALANCER_CONTROL 0x22df 10732#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10733#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e0 10734#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10735#define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e1 10736#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10737#define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e2 10738#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10739#define regDIG2_DIG_VERSION 0x22e4 10740#define regDIG2_DIG_VERSION_BASE_IDX 2 10741#define regDIG2_FORCE_DIG_DISABLE 0x22e5 10742#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 10743 10744 10745// addressBlock: dce_dc_dio_dp3_dispdec 10746// base address: 0xc00 10747#define regDP3_DP_LINK_CNTL 0x2408 10748#define regDP3_DP_LINK_CNTL_BASE_IDX 2 10749#define regDP3_DP_PIXEL_FORMAT 0x2409 10750#define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 10751#define regDP3_DP_MSA_COLORIMETRY 0x240a 10752#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 10753#define regDP3_DP_CONFIG 0x240b 10754#define regDP3_DP_CONFIG_BASE_IDX 2 10755#define regDP3_DP_VID_STREAM_CNTL 0x240c 10756#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 10757#define regDP3_DP_STEER_FIFO 0x240d 10758#define regDP3_DP_STEER_FIFO_BASE_IDX 2 10759#define regDP3_DP_MSA_MISC 0x240e 10760#define regDP3_DP_MSA_MISC_BASE_IDX 2 10761#define regDP3_DP_DPHY_INTERNAL_CTRL 0x240f 10762#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10763#define regDP3_DP_VID_TIMING 0x2410 10764#define regDP3_DP_VID_TIMING_BASE_IDX 2 10765#define regDP3_DP_VID_N 0x2411 10766#define regDP3_DP_VID_N_BASE_IDX 2 10767#define regDP3_DP_VID_M 0x2412 10768#define regDP3_DP_VID_M_BASE_IDX 2 10769#define regDP3_DP_LINK_FRAMING_CNTL 0x2413 10770#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10771#define regDP3_DP_HBR2_EYE_PATTERN 0x2414 10772#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10773#define regDP3_DP_VID_MSA_VBID 0x2415 10774#define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 10775#define regDP3_DP_VID_INTERRUPT_CNTL 0x2416 10776#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10777#define regDP3_DP_DPHY_CNTL 0x2417 10778#define regDP3_DP_DPHY_CNTL_BASE_IDX 2 10779#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 10780#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10781#define regDP3_DP_DPHY_SYM0 0x2419 10782#define regDP3_DP_DPHY_SYM0_BASE_IDX 2 10783#define regDP3_DP_DPHY_SYM1 0x241a 10784#define regDP3_DP_DPHY_SYM1_BASE_IDX 2 10785#define regDP3_DP_DPHY_SYM2 0x241b 10786#define regDP3_DP_DPHY_SYM2_BASE_IDX 2 10787#define regDP3_DP_DPHY_8B10B_CNTL 0x241c 10788#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10789#define regDP3_DP_DPHY_PRBS_CNTL 0x241d 10790#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10791#define regDP3_DP_DPHY_SCRAM_CNTL 0x241e 10792#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10793#define regDP3_DP_DPHY_CRC_EN 0x241f 10794#define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 10795#define regDP3_DP_DPHY_CRC_CNTL 0x2420 10796#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 10797#define regDP3_DP_DPHY_CRC_RESULT 0x2421 10798#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 10799#define regDP3_DP_DPHY_CRC_MST_CNTL 0x2422 10800#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10801#define regDP3_DP_DPHY_CRC_MST_STATUS 0x2423 10802#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10803#define regDP3_DP_DPHY_FAST_TRAINING 0x2424 10804#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10805#define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 10806#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10807#define regDP3_DP_SEC_CNTL 0x242b 10808#define regDP3_DP_SEC_CNTL_BASE_IDX 2 10809#define regDP3_DP_SEC_CNTL1 0x242c 10810#define regDP3_DP_SEC_CNTL1_BASE_IDX 2 10811#define regDP3_DP_SEC_FRAMING1 0x242d 10812#define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 10813#define regDP3_DP_SEC_FRAMING2 0x242e 10814#define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 10815#define regDP3_DP_SEC_FRAMING3 0x242f 10816#define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 10817#define regDP3_DP_SEC_FRAMING4 0x2430 10818#define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 10819#define regDP3_DP_SEC_AUD_N 0x2431 10820#define regDP3_DP_SEC_AUD_N_BASE_IDX 2 10821#define regDP3_DP_SEC_AUD_N_READBACK 0x2432 10822#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10823#define regDP3_DP_SEC_AUD_M 0x2433 10824#define regDP3_DP_SEC_AUD_M_BASE_IDX 2 10825#define regDP3_DP_SEC_AUD_M_READBACK 0x2434 10826#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10827#define regDP3_DP_SEC_TIMESTAMP 0x2435 10828#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 10829#define regDP3_DP_SEC_PACKET_CNTL 0x2436 10830#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 10831#define regDP3_DP_MSE_RATE_CNTL 0x2437 10832#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 10833#define regDP3_DP_MSE_RATE_UPDATE 0x2439 10834#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 10835#define regDP3_DP_MSE_SAT0 0x243a 10836#define regDP3_DP_MSE_SAT0_BASE_IDX 2 10837#define regDP3_DP_MSE_SAT1 0x243b 10838#define regDP3_DP_MSE_SAT1_BASE_IDX 2 10839#define regDP3_DP_MSE_SAT2 0x243c 10840#define regDP3_DP_MSE_SAT2_BASE_IDX 2 10841#define regDP3_DP_MSE_SAT_UPDATE 0x243d 10842#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 10843#define regDP3_DP_MSE_LINK_TIMING 0x243e 10844#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 10845#define regDP3_DP_MSE_MISC_CNTL 0x243f 10846#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 10847#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 10848#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10849#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 10850#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10851#define regDP3_DP_MSE_SAT0_STATUS 0x2447 10852#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 10853#define regDP3_DP_MSE_SAT1_STATUS 0x2448 10854#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 10855#define regDP3_DP_MSE_SAT2_STATUS 0x2449 10856#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 10857#define regDP3_DP_MSA_TIMING_PARAM1 0x244c 10858#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10859#define regDP3_DP_MSA_TIMING_PARAM2 0x244d 10860#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10861#define regDP3_DP_MSA_TIMING_PARAM3 0x244e 10862#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10863#define regDP3_DP_MSA_TIMING_PARAM4 0x244f 10864#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10865#define regDP3_DP_MSO_CNTL 0x2450 10866#define regDP3_DP_MSO_CNTL_BASE_IDX 2 10867#define regDP3_DP_MSO_CNTL1 0x2451 10868#define regDP3_DP_MSO_CNTL1_BASE_IDX 2 10869#define regDP3_DP_DSC_CNTL 0x2452 10870#define regDP3_DP_DSC_CNTL_BASE_IDX 2 10871#define regDP3_DP_SEC_CNTL2 0x2453 10872#define regDP3_DP_SEC_CNTL2_BASE_IDX 2 10873#define regDP3_DP_SEC_CNTL3 0x2454 10874#define regDP3_DP_SEC_CNTL3_BASE_IDX 2 10875#define regDP3_DP_SEC_CNTL4 0x2455 10876#define regDP3_DP_SEC_CNTL4_BASE_IDX 2 10877#define regDP3_DP_SEC_CNTL5 0x2456 10878#define regDP3_DP_SEC_CNTL5_BASE_IDX 2 10879#define regDP3_DP_SEC_CNTL6 0x2457 10880#define regDP3_DP_SEC_CNTL6_BASE_IDX 2 10881#define regDP3_DP_SEC_CNTL7 0x2458 10882#define regDP3_DP_SEC_CNTL7_BASE_IDX 2 10883#define regDP3_DP_DB_CNTL 0x2459 10884#define regDP3_DP_DB_CNTL_BASE_IDX 2 10885#define regDP3_DP_MSA_VBID_MISC 0x245a 10886#define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 10887#define regDP3_DP_SEC_METADATA_TRANSMISSION 0x245b 10888#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10889#define regDP3_DP_DSC_BYTES_PER_PIXEL 0x245c 10890#define regDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10891#define regDP3_DP_ALPM_CNTL 0x245d 10892#define regDP3_DP_ALPM_CNTL_BASE_IDX 2 10893#define regDP3_DP_GSP8_CNTL 0x245e 10894#define regDP3_DP_GSP8_CNTL_BASE_IDX 2 10895#define regDP3_DP_GSP9_CNTL 0x245f 10896#define regDP3_DP_GSP9_CNTL_BASE_IDX 2 10897#define regDP3_DP_GSP10_CNTL 0x2460 10898#define regDP3_DP_GSP10_CNTL_BASE_IDX 2 10899#define regDP3_DP_GSP11_CNTL 0x2461 10900#define regDP3_DP_GSP11_CNTL_BASE_IDX 2 10901#define regDP3_DP_GSP_EN_DB_STATUS 0x2462 10902#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10903 10904 10905// addressBlock: dce_dc_dio_dig3_dispdec 10906// base address: 0xc00 10907#define regDIG3_DIG_FE_CNTL 0x238b 10908#define regDIG3_DIG_FE_CNTL_BASE_IDX 2 10909#define regDIG3_DIG_OUTPUT_CRC_CNTL 0x238c 10910#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10911#define regDIG3_DIG_OUTPUT_CRC_RESULT 0x238d 10912#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10913#define regDIG3_DIG_CLOCK_PATTERN 0x238e 10914#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 10915#define regDIG3_DIG_TEST_PATTERN 0x238f 10916#define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 10917#define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2390 10918#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10919#define regDIG3_DIG_FIFO_STATUS 0x2391 10920#define regDIG3_DIG_FIFO_STATUS_BASE_IDX 2 10921#define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2392 10922#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10923#define regDIG3_HDMI_CONTROL 0x2393 10924#define regDIG3_HDMI_CONTROL_BASE_IDX 2 10925#define regDIG3_HDMI_STATUS 0x2394 10926#define regDIG3_HDMI_STATUS_BASE_IDX 2 10927#define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2395 10928#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10929#define regDIG3_HDMI_ACR_PACKET_CONTROL 0x2396 10930#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10931#define regDIG3_HDMI_VBI_PACKET_CONTROL 0x2397 10932#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10933#define regDIG3_HDMI_INFOFRAME_CONTROL0 0x2398 10934#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10935#define regDIG3_HDMI_INFOFRAME_CONTROL1 0x2399 10936#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10937#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239a 10938#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10939#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239b 10940#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10941#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239c 10942#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10943#define regDIG3_HDMI_GC 0x239d 10944#define regDIG3_HDMI_GC_BASE_IDX 2 10945#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239e 10946#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10947#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x239f 10948#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10949#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a0 10950#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10951#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a1 10952#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10953#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a2 10954#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10955#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a3 10956#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10957#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a4 10958#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10959#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a5 10960#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10961#define regDIG3_HDMI_DB_CONTROL 0x23a6 10962#define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 10963#define regDIG3_HDMI_ACR_32_0 0x23a7 10964#define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 10965#define regDIG3_HDMI_ACR_32_1 0x23a8 10966#define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 10967#define regDIG3_HDMI_ACR_44_0 0x23a9 10968#define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 10969#define regDIG3_HDMI_ACR_44_1 0x23aa 10970#define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 10971#define regDIG3_HDMI_ACR_48_0 0x23ab 10972#define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 10973#define regDIG3_HDMI_ACR_48_1 0x23ac 10974#define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 10975#define regDIG3_HDMI_ACR_STATUS_0 0x23ad 10976#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 10977#define regDIG3_HDMI_ACR_STATUS_1 0x23ae 10978#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 10979#define regDIG3_AFMT_CNTL 0x23af 10980#define regDIG3_AFMT_CNTL_BASE_IDX 2 10981#define regDIG3_DIG_BE_CNTL 0x23b0 10982#define regDIG3_DIG_BE_CNTL_BASE_IDX 2 10983#define regDIG3_DIG_BE_EN_CNTL 0x23b1 10984#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 10985#define regDIG3_TMDS_CNTL 0x23d7 10986#define regDIG3_TMDS_CNTL_BASE_IDX 2 10987#define regDIG3_TMDS_CONTROL_CHAR 0x23d8 10988#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 10989#define regDIG3_TMDS_CONTROL0_FEEDBACK 0x23d9 10990#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10991#define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23da 10992#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10993#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23db 10994#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10995#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dc 10996#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10997#define regDIG3_TMDS_CTL_BITS 0x23de 10998#define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 10999#define regDIG3_TMDS_DCBALANCER_CONTROL 0x23df 11000#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 11001#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e0 11002#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 11003#define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e1 11004#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 11005#define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e2 11006#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 11007#define regDIG3_DIG_VERSION 0x23e4 11008#define regDIG3_DIG_VERSION_BASE_IDX 2 11009#define regDIG3_FORCE_DIG_DISABLE 0x23e5 11010#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 11011 11012 11013// addressBlock: dce_dc_dio_dp4_dispdec 11014// base address: 0x1000 11015#define regDP4_DP_LINK_CNTL 0x2508 11016#define regDP4_DP_LINK_CNTL_BASE_IDX 2 11017#define regDP4_DP_PIXEL_FORMAT 0x2509 11018#define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 11019#define regDP4_DP_MSA_COLORIMETRY 0x250a 11020#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 11021#define regDP4_DP_CONFIG 0x250b 11022#define regDP4_DP_CONFIG_BASE_IDX 2 11023#define regDP4_DP_VID_STREAM_CNTL 0x250c 11024#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 11025#define regDP4_DP_STEER_FIFO 0x250d 11026#define regDP4_DP_STEER_FIFO_BASE_IDX 2 11027#define regDP4_DP_MSA_MISC 0x250e 11028#define regDP4_DP_MSA_MISC_BASE_IDX 2 11029#define regDP4_DP_DPHY_INTERNAL_CTRL 0x250f 11030#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 11031#define regDP4_DP_VID_TIMING 0x2510 11032#define regDP4_DP_VID_TIMING_BASE_IDX 2 11033#define regDP4_DP_VID_N 0x2511 11034#define regDP4_DP_VID_N_BASE_IDX 2 11035#define regDP4_DP_VID_M 0x2512 11036#define regDP4_DP_VID_M_BASE_IDX 2 11037#define regDP4_DP_LINK_FRAMING_CNTL 0x2513 11038#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 11039#define regDP4_DP_HBR2_EYE_PATTERN 0x2514 11040#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 11041#define regDP4_DP_VID_MSA_VBID 0x2515 11042#define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 11043#define regDP4_DP_VID_INTERRUPT_CNTL 0x2516 11044#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 11045#define regDP4_DP_DPHY_CNTL 0x2517 11046#define regDP4_DP_DPHY_CNTL_BASE_IDX 2 11047#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 11048#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 11049#define regDP4_DP_DPHY_SYM0 0x2519 11050#define regDP4_DP_DPHY_SYM0_BASE_IDX 2 11051#define regDP4_DP_DPHY_SYM1 0x251a 11052#define regDP4_DP_DPHY_SYM1_BASE_IDX 2 11053#define regDP4_DP_DPHY_SYM2 0x251b 11054#define regDP4_DP_DPHY_SYM2_BASE_IDX 2 11055#define regDP4_DP_DPHY_8B10B_CNTL 0x251c 11056#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 11057#define regDP4_DP_DPHY_PRBS_CNTL 0x251d 11058#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 11059#define regDP4_DP_DPHY_SCRAM_CNTL 0x251e 11060#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 11061#define regDP4_DP_DPHY_CRC_EN 0x251f 11062#define regDP4_DP_DPHY_CRC_EN_BASE_IDX 2 11063#define regDP4_DP_DPHY_CRC_CNTL 0x2520 11064#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 11065#define regDP4_DP_DPHY_CRC_RESULT 0x2521 11066#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 11067#define regDP4_DP_DPHY_CRC_MST_CNTL 0x2522 11068#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 11069#define regDP4_DP_DPHY_CRC_MST_STATUS 0x2523 11070#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 11071#define regDP4_DP_DPHY_FAST_TRAINING 0x2524 11072#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 11073#define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 11074#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 11075#define regDP4_DP_SEC_CNTL 0x252b 11076#define regDP4_DP_SEC_CNTL_BASE_IDX 2 11077#define regDP4_DP_SEC_CNTL1 0x252c 11078#define regDP4_DP_SEC_CNTL1_BASE_IDX 2 11079#define regDP4_DP_SEC_FRAMING1 0x252d 11080#define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 11081#define regDP4_DP_SEC_FRAMING2 0x252e 11082#define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 11083#define regDP4_DP_SEC_FRAMING3 0x252f 11084#define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 11085#define regDP4_DP_SEC_FRAMING4 0x2530 11086#define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 11087#define regDP4_DP_SEC_AUD_N 0x2531 11088#define regDP4_DP_SEC_AUD_N_BASE_IDX 2 11089#define regDP4_DP_SEC_AUD_N_READBACK 0x2532 11090#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 11091#define regDP4_DP_SEC_AUD_M 0x2533 11092#define regDP4_DP_SEC_AUD_M_BASE_IDX 2 11093#define regDP4_DP_SEC_AUD_M_READBACK 0x2534 11094#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 11095#define regDP4_DP_SEC_TIMESTAMP 0x2535 11096#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 11097#define regDP4_DP_SEC_PACKET_CNTL 0x2536 11098#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 11099#define regDP4_DP_MSE_RATE_CNTL 0x2537 11100#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 11101#define regDP4_DP_MSE_RATE_UPDATE 0x2539 11102#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 11103#define regDP4_DP_MSE_SAT0 0x253a 11104#define regDP4_DP_MSE_SAT0_BASE_IDX 2 11105#define regDP4_DP_MSE_SAT1 0x253b 11106#define regDP4_DP_MSE_SAT1_BASE_IDX 2 11107#define regDP4_DP_MSE_SAT2 0x253c 11108#define regDP4_DP_MSE_SAT2_BASE_IDX 2 11109#define regDP4_DP_MSE_SAT_UPDATE 0x253d 11110#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 11111#define regDP4_DP_MSE_LINK_TIMING 0x253e 11112#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 11113#define regDP4_DP_MSE_MISC_CNTL 0x253f 11114#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 11115#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 11116#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 11117#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 11118#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 11119#define regDP4_DP_MSE_SAT0_STATUS 0x2547 11120#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 11121#define regDP4_DP_MSE_SAT1_STATUS 0x2548 11122#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 11123#define regDP4_DP_MSE_SAT2_STATUS 0x2549 11124#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 11125#define regDP4_DP_MSA_TIMING_PARAM1 0x254c 11126#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 11127#define regDP4_DP_MSA_TIMING_PARAM2 0x254d 11128#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 11129#define regDP4_DP_MSA_TIMING_PARAM3 0x254e 11130#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 11131#define regDP4_DP_MSA_TIMING_PARAM4 0x254f 11132#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 11133#define regDP4_DP_MSO_CNTL 0x2550 11134#define regDP4_DP_MSO_CNTL_BASE_IDX 2 11135#define regDP4_DP_MSO_CNTL1 0x2551 11136#define regDP4_DP_MSO_CNTL1_BASE_IDX 2 11137#define regDP4_DP_DSC_CNTL 0x2552 11138#define regDP4_DP_DSC_CNTL_BASE_IDX 2 11139#define regDP4_DP_SEC_CNTL2 0x2553 11140#define regDP4_DP_SEC_CNTL2_BASE_IDX 2 11141#define regDP4_DP_SEC_CNTL3 0x2554 11142#define regDP4_DP_SEC_CNTL3_BASE_IDX 2 11143#define regDP4_DP_SEC_CNTL4 0x2555 11144#define regDP4_DP_SEC_CNTL4_BASE_IDX 2 11145#define regDP4_DP_SEC_CNTL5 0x2556 11146#define regDP4_DP_SEC_CNTL5_BASE_IDX 2 11147#define regDP4_DP_SEC_CNTL6 0x2557 11148#define regDP4_DP_SEC_CNTL6_BASE_IDX 2 11149#define regDP4_DP_SEC_CNTL7 0x2558 11150#define regDP4_DP_SEC_CNTL7_BASE_IDX 2 11151#define regDP4_DP_DB_CNTL 0x2559 11152#define regDP4_DP_DB_CNTL_BASE_IDX 2 11153#define regDP4_DP_MSA_VBID_MISC 0x255a 11154#define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 11155#define regDP4_DP_SEC_METADATA_TRANSMISSION 0x255b 11156#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 11157#define regDP4_DP_DSC_BYTES_PER_PIXEL 0x255c 11158#define regDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 11159#define regDP4_DP_ALPM_CNTL 0x255d 11160#define regDP4_DP_ALPM_CNTL_BASE_IDX 2 11161#define regDP4_DP_GSP8_CNTL 0x255e 11162#define regDP4_DP_GSP8_CNTL_BASE_IDX 2 11163#define regDP4_DP_GSP9_CNTL 0x255f 11164#define regDP4_DP_GSP9_CNTL_BASE_IDX 2 11165#define regDP4_DP_GSP10_CNTL 0x2560 11166#define regDP4_DP_GSP10_CNTL_BASE_IDX 2 11167#define regDP4_DP_GSP11_CNTL 0x2561 11168#define regDP4_DP_GSP11_CNTL_BASE_IDX 2 11169#define regDP4_DP_GSP_EN_DB_STATUS 0x2562 11170#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 11171 11172 11173// addressBlock: dce_dc_dio_dig4_dispdec 11174// base address: 0x1000 11175#define regDIG4_DIG_FE_CNTL 0x248b 11176#define regDIG4_DIG_FE_CNTL_BASE_IDX 2 11177#define regDIG4_DIG_OUTPUT_CRC_CNTL 0x248c 11178#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 11179#define regDIG4_DIG_OUTPUT_CRC_RESULT 0x248d 11180#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 11181#define regDIG4_DIG_CLOCK_PATTERN 0x248e 11182#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 11183#define regDIG4_DIG_TEST_PATTERN 0x248f 11184#define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 11185#define regDIG4_DIG_RANDOM_PATTERN_SEED 0x2490 11186#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 11187#define regDIG4_DIG_FIFO_STATUS 0x2491 11188#define regDIG4_DIG_FIFO_STATUS_BASE_IDX 2 11189#define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x2492 11190#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 11191#define regDIG4_HDMI_CONTROL 0x2493 11192#define regDIG4_HDMI_CONTROL_BASE_IDX 2 11193#define regDIG4_HDMI_STATUS 0x2494 11194#define regDIG4_HDMI_STATUS_BASE_IDX 2 11195#define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2495 11196#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 11197#define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2496 11198#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 11199#define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2497 11200#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 11201#define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2498 11202#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 11203#define regDIG4_HDMI_INFOFRAME_CONTROL1 0x2499 11204#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 11205#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249a 11206#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 11207#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249b 11208#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 11209#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249c 11210#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 11211#define regDIG4_HDMI_GC 0x249d 11212#define regDIG4_HDMI_GC_BASE_IDX 2 11213#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249e 11214#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 11215#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x249f 11216#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 11217#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a0 11218#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 11219#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a1 11220#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 11221#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a2 11222#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 11223#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a3 11224#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 11225#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a4 11226#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 11227#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a5 11228#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 11229#define regDIG4_HDMI_DB_CONTROL 0x24a6 11230#define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 11231#define regDIG4_HDMI_ACR_32_0 0x24a7 11232#define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 11233#define regDIG4_HDMI_ACR_32_1 0x24a8 11234#define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 11235#define regDIG4_HDMI_ACR_44_0 0x24a9 11236#define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 11237#define regDIG4_HDMI_ACR_44_1 0x24aa 11238#define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 11239#define regDIG4_HDMI_ACR_48_0 0x24ab 11240#define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 11241#define regDIG4_HDMI_ACR_48_1 0x24ac 11242#define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 11243#define regDIG4_HDMI_ACR_STATUS_0 0x24ad 11244#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 11245#define regDIG4_HDMI_ACR_STATUS_1 0x24ae 11246#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 11247#define regDIG4_AFMT_CNTL 0x24af 11248#define regDIG4_AFMT_CNTL_BASE_IDX 2 11249#define regDIG4_DIG_BE_CNTL 0x24b0 11250#define regDIG4_DIG_BE_CNTL_BASE_IDX 2 11251#define regDIG4_DIG_BE_EN_CNTL 0x24b1 11252#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 11253#define regDIG4_TMDS_CNTL 0x24d7 11254#define regDIG4_TMDS_CNTL_BASE_IDX 2 11255#define regDIG4_TMDS_CONTROL_CHAR 0x24d8 11256#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 11257#define regDIG4_TMDS_CONTROL0_FEEDBACK 0x24d9 11258#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 11259#define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24da 11260#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 11261#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24db 11262#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 11263#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dc 11264#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 11265#define regDIG4_TMDS_CTL_BITS 0x24de 11266#define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 11267#define regDIG4_TMDS_DCBALANCER_CONTROL 0x24df 11268#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 11269#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e0 11270#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 11271#define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e1 11272#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 11273#define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e2 11274#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 11275#define regDIG4_DIG_VERSION 0x24e4 11276#define regDIG4_DIG_VERSION_BASE_IDX 2 11277#define regDIG4_FORCE_DIG_DISABLE 0x24e5 11278#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 11279 11280 11281// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec 11282// base address: 0x154cc 11283#define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 11284#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11285#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 11286#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11287#define regAFMT0_AFMT_AUDIO_INFO0 0x2076 11288#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 11289#define regAFMT0_AFMT_AUDIO_INFO1 0x2077 11290#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 11291#define regAFMT0_AFMT_60958_0 0x2078 11292#define regAFMT0_AFMT_60958_0_BASE_IDX 2 11293#define regAFMT0_AFMT_60958_1 0x2079 11294#define regAFMT0_AFMT_60958_1_BASE_IDX 2 11295#define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a 11296#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11297#define regAFMT0_AFMT_RAMP_CONTROL0 0x207b 11298#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 11299#define regAFMT0_AFMT_RAMP_CONTROL1 0x207c 11300#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 11301#define regAFMT0_AFMT_RAMP_CONTROL2 0x207d 11302#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 11303#define regAFMT0_AFMT_RAMP_CONTROL3 0x207e 11304#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 11305#define regAFMT0_AFMT_60958_2 0x207f 11306#define regAFMT0_AFMT_60958_2_BASE_IDX 2 11307#define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 11308#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11309#define regAFMT0_AFMT_STATUS 0x2081 11310#define regAFMT0_AFMT_STATUS_BASE_IDX 2 11311#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 11312#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11313#define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 11314#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11315#define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 11316#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11317#define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 11318#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11319#define regAFMT0_AFMT_MEM_PWR 0x2087 11320#define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 11321 11322 11323// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec 11324// base address: 0x158cc 11325#define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 11326#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11327#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 11328#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11329#define regAFMT1_AFMT_AUDIO_INFO0 0x2176 11330#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 11331#define regAFMT1_AFMT_AUDIO_INFO1 0x2177 11332#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 11333#define regAFMT1_AFMT_60958_0 0x2178 11334#define regAFMT1_AFMT_60958_0_BASE_IDX 2 11335#define regAFMT1_AFMT_60958_1 0x2179 11336#define regAFMT1_AFMT_60958_1_BASE_IDX 2 11337#define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a 11338#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11339#define regAFMT1_AFMT_RAMP_CONTROL0 0x217b 11340#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 11341#define regAFMT1_AFMT_RAMP_CONTROL1 0x217c 11342#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 11343#define regAFMT1_AFMT_RAMP_CONTROL2 0x217d 11344#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 11345#define regAFMT1_AFMT_RAMP_CONTROL3 0x217e 11346#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 11347#define regAFMT1_AFMT_60958_2 0x217f 11348#define regAFMT1_AFMT_60958_2_BASE_IDX 2 11349#define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 11350#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11351#define regAFMT1_AFMT_STATUS 0x2181 11352#define regAFMT1_AFMT_STATUS_BASE_IDX 2 11353#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 11354#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11355#define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 11356#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11357#define regAFMT1_AFMT_INTERRUPT_STATUS 0x2184 11358#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11359#define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 11360#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11361#define regAFMT1_AFMT_MEM_PWR 0x2187 11362#define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 11363 11364 11365// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec 11366// base address: 0x15ccc 11367#define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274 11368#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11369#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275 11370#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11371#define regAFMT2_AFMT_AUDIO_INFO0 0x2276 11372#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 11373#define regAFMT2_AFMT_AUDIO_INFO1 0x2277 11374#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 11375#define regAFMT2_AFMT_60958_0 0x2278 11376#define regAFMT2_AFMT_60958_0_BASE_IDX 2 11377#define regAFMT2_AFMT_60958_1 0x2279 11378#define regAFMT2_AFMT_60958_1_BASE_IDX 2 11379#define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a 11380#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11381#define regAFMT2_AFMT_RAMP_CONTROL0 0x227b 11382#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 11383#define regAFMT2_AFMT_RAMP_CONTROL1 0x227c 11384#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 11385#define regAFMT2_AFMT_RAMP_CONTROL2 0x227d 11386#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 11387#define regAFMT2_AFMT_RAMP_CONTROL3 0x227e 11388#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 11389#define regAFMT2_AFMT_60958_2 0x227f 11390#define regAFMT2_AFMT_60958_2_BASE_IDX 2 11391#define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280 11392#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11393#define regAFMT2_AFMT_STATUS 0x2281 11394#define regAFMT2_AFMT_STATUS_BASE_IDX 2 11395#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282 11396#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11397#define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283 11398#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11399#define regAFMT2_AFMT_INTERRUPT_STATUS 0x2284 11400#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11401#define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285 11402#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11403#define regAFMT2_AFMT_MEM_PWR 0x2287 11404#define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 11405 11406 11407// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec 11408// base address: 0x160cc 11409#define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374 11410#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11411#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375 11412#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11413#define regAFMT3_AFMT_AUDIO_INFO0 0x2376 11414#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 11415#define regAFMT3_AFMT_AUDIO_INFO1 0x2377 11416#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 11417#define regAFMT3_AFMT_60958_0 0x2378 11418#define regAFMT3_AFMT_60958_0_BASE_IDX 2 11419#define regAFMT3_AFMT_60958_1 0x2379 11420#define regAFMT3_AFMT_60958_1_BASE_IDX 2 11421#define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a 11422#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11423#define regAFMT3_AFMT_RAMP_CONTROL0 0x237b 11424#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 11425#define regAFMT3_AFMT_RAMP_CONTROL1 0x237c 11426#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 11427#define regAFMT3_AFMT_RAMP_CONTROL2 0x237d 11428#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 11429#define regAFMT3_AFMT_RAMP_CONTROL3 0x237e 11430#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 11431#define regAFMT3_AFMT_60958_2 0x237f 11432#define regAFMT3_AFMT_60958_2_BASE_IDX 2 11433#define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380 11434#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11435#define regAFMT3_AFMT_STATUS 0x2381 11436#define regAFMT3_AFMT_STATUS_BASE_IDX 2 11437#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382 11438#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11439#define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383 11440#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11441#define regAFMT3_AFMT_INTERRUPT_STATUS 0x2384 11442#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11443#define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385 11444#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11445#define regAFMT3_AFMT_MEM_PWR 0x2387 11446#define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 11447 11448 11449// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec 11450// base address: 0x164cc 11451#define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474 11452#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11453#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475 11454#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11455#define regAFMT4_AFMT_AUDIO_INFO0 0x2476 11456#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 11457#define regAFMT4_AFMT_AUDIO_INFO1 0x2477 11458#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 11459#define regAFMT4_AFMT_60958_0 0x2478 11460#define regAFMT4_AFMT_60958_0_BASE_IDX 2 11461#define regAFMT4_AFMT_60958_1 0x2479 11462#define regAFMT4_AFMT_60958_1_BASE_IDX 2 11463#define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a 11464#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11465#define regAFMT4_AFMT_RAMP_CONTROL0 0x247b 11466#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 11467#define regAFMT4_AFMT_RAMP_CONTROL1 0x247c 11468#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 11469#define regAFMT4_AFMT_RAMP_CONTROL2 0x247d 11470#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 11471#define regAFMT4_AFMT_RAMP_CONTROL3 0x247e 11472#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 11473#define regAFMT4_AFMT_60958_2 0x247f 11474#define regAFMT4_AFMT_60958_2_BASE_IDX 2 11475#define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480 11476#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11477#define regAFMT4_AFMT_STATUS 0x2481 11478#define regAFMT4_AFMT_STATUS_BASE_IDX 2 11479#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482 11480#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11481#define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483 11482#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11483#define regAFMT4_AFMT_INTERRUPT_STATUS 0x2484 11484#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11485#define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485 11486#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11487#define regAFMT4_AFMT_MEM_PWR 0x2487 11488#define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 11489 11490 11491// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec 11492// base address: 0x15524 11493#define regDME0_DME_CONTROL 0x2089 11494#define regDME0_DME_CONTROL_BASE_IDX 2 11495#define regDME0_DME_MEMORY_CONTROL 0x208a 11496#define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 11497 11498 11499// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec 11500// base address: 0x154a0 11501#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 11502#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11503#define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 11504#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11505#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a 11506#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11507#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b 11508#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11509#define regVPG0_VPG_GENERIC_STATUS 0x206c 11510#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 11511#define regVPG0_VPG_MEM_PWR 0x206d 11512#define regVPG0_VPG_MEM_PWR_BASE_IDX 2 11513#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e 11514#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11515#define regVPG0_VPG_ISRC1_2_DATA 0x206f 11516#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 11517#define regVPG0_VPG_MPEG_INFO0 0x2070 11518#define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 11519#define regVPG0_VPG_MPEG_INFO1 0x2071 11520#define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 11521 11522 11523// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec 11524// base address: 0x15924 11525#define regDME1_DME_CONTROL 0x2189 11526#define regDME1_DME_CONTROL_BASE_IDX 2 11527#define regDME1_DME_MEMORY_CONTROL 0x218a 11528#define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 11529 11530 11531// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec 11532// base address: 0x158a0 11533#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 11534#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11535#define regVPG1_VPG_GENERIC_PACKET_DATA 0x2169 11536#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11537#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a 11538#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11539#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b 11540#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11541#define regVPG1_VPG_GENERIC_STATUS 0x216c 11542#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 11543#define regVPG1_VPG_MEM_PWR 0x216d 11544#define regVPG1_VPG_MEM_PWR_BASE_IDX 2 11545#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e 11546#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11547#define regVPG1_VPG_ISRC1_2_DATA 0x216f 11548#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 11549#define regVPG1_VPG_MPEG_INFO0 0x2170 11550#define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 11551#define regVPG1_VPG_MPEG_INFO1 0x2171 11552#define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 11553 11554 11555// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec 11556// base address: 0x15d24 11557#define regDME2_DME_CONTROL 0x2289 11558#define regDME2_DME_CONTROL_BASE_IDX 2 11559#define regDME2_DME_MEMORY_CONTROL 0x228a 11560#define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 11561 11562 11563// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec 11564// base address: 0x15ca0 11565#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268 11566#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11567#define regVPG2_VPG_GENERIC_PACKET_DATA 0x2269 11568#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11569#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a 11570#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11571#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b 11572#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11573#define regVPG2_VPG_GENERIC_STATUS 0x226c 11574#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 11575#define regVPG2_VPG_MEM_PWR 0x226d 11576#define regVPG2_VPG_MEM_PWR_BASE_IDX 2 11577#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e 11578#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11579#define regVPG2_VPG_ISRC1_2_DATA 0x226f 11580#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 11581#define regVPG2_VPG_MPEG_INFO0 0x2270 11582#define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 11583#define regVPG2_VPG_MPEG_INFO1 0x2271 11584#define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 11585 11586 11587// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec 11588// base address: 0x16124 11589#define regDME3_DME_CONTROL 0x2389 11590#define regDME3_DME_CONTROL_BASE_IDX 2 11591#define regDME3_DME_MEMORY_CONTROL 0x238a 11592#define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 11593 11594 11595// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec 11596// base address: 0x160a0 11597#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368 11598#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11599#define regVPG3_VPG_GENERIC_PACKET_DATA 0x2369 11600#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11601#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a 11602#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11603#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b 11604#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11605#define regVPG3_VPG_GENERIC_STATUS 0x236c 11606#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 11607#define regVPG3_VPG_MEM_PWR 0x236d 11608#define regVPG3_VPG_MEM_PWR_BASE_IDX 2 11609#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e 11610#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11611#define regVPG3_VPG_ISRC1_2_DATA 0x236f 11612#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 11613#define regVPG3_VPG_MPEG_INFO0 0x2370 11614#define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 11615#define regVPG3_VPG_MPEG_INFO1 0x2371 11616#define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 11617 11618 11619// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec 11620// base address: 0x16524 11621#define regDME4_DME_CONTROL 0x2489 11622#define regDME4_DME_CONTROL_BASE_IDX 2 11623#define regDME4_DME_MEMORY_CONTROL 0x248a 11624#define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 11625 11626 11627// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec 11628// base address: 0x164a0 11629#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468 11630#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11631#define regVPG4_VPG_GENERIC_PACKET_DATA 0x2469 11632#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11633#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a 11634#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11635#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b 11636#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11637#define regVPG4_VPG_GENERIC_STATUS 0x246c 11638#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 11639#define regVPG4_VPG_MEM_PWR 0x246d 11640#define regVPG4_VPG_MEM_PWR_BASE_IDX 2 11641#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e 11642#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11643#define regVPG4_VPG_ISRC1_2_DATA 0x246f 11644#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 11645#define regVPG4_VPG_MPEG_INFO0 0x2470 11646#define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 11647#define regVPG4_VPG_MPEG_INFO1 0x2471 11648#define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 11649 11650 11651// addressBlock: dce_dc_dio_dp_aux0_dispdec 11652// base address: 0x0 11653#define regDP_AUX0_AUX_CONTROL 0x1f50 11654#define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 11655#define regDP_AUX0_AUX_SW_CONTROL 0x1f51 11656#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 11657#define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 11658#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 11659#define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 11660#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11661#define regDP_AUX0_AUX_SW_STATUS 0x1f54 11662#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 11663#define regDP_AUX0_AUX_LS_STATUS 0x1f55 11664#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 11665#define regDP_AUX0_AUX_SW_DATA 0x1f56 11666#define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 11667#define regDP_AUX0_AUX_LS_DATA 0x1f57 11668#define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 11669#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 11670#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11671#define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 11672#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11673#define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 11674#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11675#define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 11676#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11677#define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 11678#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 11679#define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 11680#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 11681#define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e 11682#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11683#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f 11684#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11685#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 11686#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11687#define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 11688#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11689#define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 11690#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11691 11692 11693// addressBlock: dce_dc_dio_dp_aux1_dispdec 11694// base address: 0x70 11695#define regDP_AUX1_AUX_CONTROL 0x1f6c 11696#define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 11697#define regDP_AUX1_AUX_SW_CONTROL 0x1f6d 11698#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 11699#define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e 11700#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 11701#define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 11702#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11703#define regDP_AUX1_AUX_SW_STATUS 0x1f70 11704#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 11705#define regDP_AUX1_AUX_LS_STATUS 0x1f71 11706#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 11707#define regDP_AUX1_AUX_SW_DATA 0x1f72 11708#define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 11709#define regDP_AUX1_AUX_LS_DATA 0x1f73 11710#define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 11711#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 11712#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11713#define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 11714#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11715#define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 11716#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11717#define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 11718#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11719#define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 11720#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 11721#define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 11722#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 11723#define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a 11724#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11725#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b 11726#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11727#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c 11728#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11729#define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d 11730#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11731#define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 11732#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11733 11734 11735// addressBlock: dce_dc_dio_dp_aux2_dispdec 11736// base address: 0xe0 11737#define regDP_AUX2_AUX_CONTROL 0x1f88 11738#define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 11739#define regDP_AUX2_AUX_SW_CONTROL 0x1f89 11740#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 11741#define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a 11742#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 11743#define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b 11744#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11745#define regDP_AUX2_AUX_SW_STATUS 0x1f8c 11746#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 11747#define regDP_AUX2_AUX_LS_STATUS 0x1f8d 11748#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 11749#define regDP_AUX2_AUX_SW_DATA 0x1f8e 11750#define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 11751#define regDP_AUX2_AUX_LS_DATA 0x1f8f 11752#define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 11753#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 11754#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11755#define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 11756#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11757#define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 11758#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11759#define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 11760#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11761#define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 11762#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 11763#define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 11764#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 11765#define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 11766#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11767#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 11768#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11769#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 11770#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11771#define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 11772#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11773#define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e 11774#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11775 11776 11777// addressBlock: dce_dc_dio_dp_aux3_dispdec 11778// base address: 0x150 11779#define regDP_AUX3_AUX_CONTROL 0x1fa4 11780#define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 11781#define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 11782#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 11783#define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 11784#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 11785#define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 11786#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11787#define regDP_AUX3_AUX_SW_STATUS 0x1fa8 11788#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 11789#define regDP_AUX3_AUX_LS_STATUS 0x1fa9 11790#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 11791#define regDP_AUX3_AUX_SW_DATA 0x1faa 11792#define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 11793#define regDP_AUX3_AUX_LS_DATA 0x1fab 11794#define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 11795#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac 11796#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11797#define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad 11798#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11799#define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae 11800#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11801#define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf 11802#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11803#define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 11804#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 11805#define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 11806#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 11807#define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 11808#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11809#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 11810#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11811#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 11812#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11813#define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 11814#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11815#define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba 11816#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11817 11818 11819// addressBlock: dce_dc_dio_dp_aux4_dispdec 11820// base address: 0x1c0 11821#define regDP_AUX4_AUX_CONTROL 0x1fc0 11822#define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 11823#define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 11824#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 11825#define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 11826#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 11827#define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 11828#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11829#define regDP_AUX4_AUX_SW_STATUS 0x1fc4 11830#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 11831#define regDP_AUX4_AUX_LS_STATUS 0x1fc5 11832#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 11833#define regDP_AUX4_AUX_SW_DATA 0x1fc6 11834#define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 11835#define regDP_AUX4_AUX_LS_DATA 0x1fc7 11836#define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 11837#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 11838#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11839#define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 11840#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11841#define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca 11842#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11843#define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb 11844#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11845#define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc 11846#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 11847#define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd 11848#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 11849#define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce 11850#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11851#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf 11852#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11853#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 11854#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11855#define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 11856#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11857#define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 11858#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11859 11860 11861// addressBlock: dce_dc_dio_dout_i2c_dispdec 11862// base address: 0x0 11863#define regDC_I2C_CONTROL 0x1e98 11864#define regDC_I2C_CONTROL_BASE_IDX 2 11865#define regDC_I2C_ARBITRATION 0x1e99 11866#define regDC_I2C_ARBITRATION_BASE_IDX 2 11867#define regDC_I2C_INTERRUPT_CONTROL 0x1e9a 11868#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 11869#define regDC_I2C_SW_STATUS 0x1e9b 11870#define regDC_I2C_SW_STATUS_BASE_IDX 2 11871#define regDC_I2C_DDC1_HW_STATUS 0x1e9c 11872#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 11873#define regDC_I2C_DDC2_HW_STATUS 0x1e9d 11874#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 11875#define regDC_I2C_DDC3_HW_STATUS 0x1e9e 11876#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 11877#define regDC_I2C_DDC4_HW_STATUS 0x1e9f 11878#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 11879#define regDC_I2C_DDC5_HW_STATUS 0x1ea0 11880#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 11881#define regDC_I2C_DDC1_SPEED 0x1ea2 11882#define regDC_I2C_DDC1_SPEED_BASE_IDX 2 11883#define regDC_I2C_DDC1_SETUP 0x1ea3 11884#define regDC_I2C_DDC1_SETUP_BASE_IDX 2 11885#define regDC_I2C_DDC2_SPEED 0x1ea4 11886#define regDC_I2C_DDC2_SPEED_BASE_IDX 2 11887#define regDC_I2C_DDC2_SETUP 0x1ea5 11888#define regDC_I2C_DDC2_SETUP_BASE_IDX 2 11889#define regDC_I2C_DDC3_SPEED 0x1ea6 11890#define regDC_I2C_DDC3_SPEED_BASE_IDX 2 11891#define regDC_I2C_DDC3_SETUP 0x1ea7 11892#define regDC_I2C_DDC3_SETUP_BASE_IDX 2 11893#define regDC_I2C_DDC4_SPEED 0x1ea8 11894#define regDC_I2C_DDC4_SPEED_BASE_IDX 2 11895#define regDC_I2C_DDC4_SETUP 0x1ea9 11896#define regDC_I2C_DDC4_SETUP_BASE_IDX 2 11897#define regDC_I2C_DDC5_SPEED 0x1eaa 11898#define regDC_I2C_DDC5_SPEED_BASE_IDX 2 11899#define regDC_I2C_DDC5_SETUP 0x1eab 11900#define regDC_I2C_DDC5_SETUP_BASE_IDX 2 11901#define regDC_I2C_TRANSACTION0 0x1eae 11902#define regDC_I2C_TRANSACTION0_BASE_IDX 2 11903#define regDC_I2C_TRANSACTION1 0x1eaf 11904#define regDC_I2C_TRANSACTION1_BASE_IDX 2 11905#define regDC_I2C_TRANSACTION2 0x1eb0 11906#define regDC_I2C_TRANSACTION2_BASE_IDX 2 11907#define regDC_I2C_TRANSACTION3 0x1eb1 11908#define regDC_I2C_TRANSACTION3_BASE_IDX 2 11909#define regDC_I2C_DATA 0x1eb2 11910#define regDC_I2C_DATA_BASE_IDX 2 11911#define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 11912#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 11913#define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 11914#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 11915 11916 11917// addressBlock: dce_dc_dio_dio_misc_dispdec 11918// base address: 0x0 11919#define regDIO_SCRATCH0 0x1eca 11920#define regDIO_SCRATCH0_BASE_IDX 2 11921#define regDIO_SCRATCH1 0x1ecb 11922#define regDIO_SCRATCH1_BASE_IDX 2 11923#define regDIO_SCRATCH2 0x1ecc 11924#define regDIO_SCRATCH2_BASE_IDX 2 11925#define regDIO_SCRATCH3 0x1ecd 11926#define regDIO_SCRATCH3_BASE_IDX 2 11927#define regDIO_SCRATCH4 0x1ece 11928#define regDIO_SCRATCH4_BASE_IDX 2 11929#define regDIO_SCRATCH5 0x1ecf 11930#define regDIO_SCRATCH5_BASE_IDX 2 11931#define regDIO_SCRATCH6 0x1ed0 11932#define regDIO_SCRATCH6_BASE_IDX 2 11933#define regDIO_SCRATCH7 0x1ed1 11934#define regDIO_SCRATCH7_BASE_IDX 2 11935#define regDIO_MEM_PWR_STATUS 0x1edd 11936#define regDIO_MEM_PWR_STATUS_BASE_IDX 2 11937#define regDIO_MEM_PWR_CTRL 0x1ede 11938#define regDIO_MEM_PWR_CTRL_BASE_IDX 2 11939#define regDIO_MEM_PWR_CTRL2 0x1edf 11940#define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 11941#define regDIO_CLK_CNTL 0x1ee0 11942#define regDIO_CLK_CNTL_BASE_IDX 2 11943#define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 11944#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 11945#define regDIG_SOFT_RESET 0x1eee 11946#define regDIG_SOFT_RESET_BASE_IDX 2 11947#define regDIO_CLK_CNTL2 0x1ef2 11948#define regDIO_CLK_CNTL2_BASE_IDX 2 11949#define regDIO_CLK_CNTL3 0x1ef3 11950#define regDIO_CLK_CNTL3_BASE_IDX 2 11951#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 11952#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 11953#define regDIO_PSP_INTERRUPT_STATUS 0x1f00 11954#define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2 11955#define regDIO_PSP_INTERRUPT_CLEAR 0x1f01 11956#define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 11957#define regDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 11958#define regDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 11959#define regDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 11960#define regDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 11961#define regDIO_LINKA_CNTL 0x1f04 11962#define regDIO_LINKA_CNTL_BASE_IDX 2 11963#define regDIO_LINKB_CNTL 0x1f05 11964#define regDIO_LINKB_CNTL_BASE_IDX 2 11965#define regDIO_LINKC_CNTL 0x1f06 11966#define regDIO_LINKC_CNTL_BASE_IDX 2 11967#define regDIO_LINKD_CNTL 0x1f07 11968#define regDIO_LINKD_CNTL_BASE_IDX 2 11969#define regDIO_LINKE_CNTL 0x1f08 11970#define regDIO_LINKE_CNTL_BASE_IDX 2 11971#define regDIO_LINKF_CNTL 0x1f09 11972#define regDIO_LINKF_CNTL_BASE_IDX 2 11973 11974 11975// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec 11976// base address: 0x7d10 11977#define regDC_PERFMON18_PERFCOUNTER_CNTL 0x1f44 11978#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 11979#define regDC_PERFMON18_PERFCOUNTER_CNTL2 0x1f45 11980#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 11981#define regDC_PERFMON18_PERFCOUNTER_STATE 0x1f46 11982#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 11983#define regDC_PERFMON18_PERFMON_CNTL 0x1f47 11984#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 11985#define regDC_PERFMON18_PERFMON_CNTL2 0x1f48 11986#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 11987#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1f49 11988#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 11989#define regDC_PERFMON18_PERFMON_CVALUE_LOW 0x1f4a 11990#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 11991#define regDC_PERFMON18_PERFMON_HI 0x1f4b 11992#define regDC_PERFMON18_PERFMON_HI_BASE_IDX 2 11993#define regDC_PERFMON18_PERFMON_LOW 0x1f4c 11994#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 11995 11996 11997// addressBlock: dce_dc_dcio_dcio_dispdec 11998// base address: 0x0 11999#define regDC_GENERICA 0x2868 12000#define regDC_GENERICA_BASE_IDX 2 12001#define regDC_GENERICB 0x2869 12002#define regDC_GENERICB_BASE_IDX 2 12003#define regDCIO_CLOCK_CNTL 0x286a 12004#define regDCIO_CLOCK_CNTL_BASE_IDX 2 12005#define regDC_REF_CLK_CNTL 0x286b 12006#define regDC_REF_CLK_CNTL_BASE_IDX 2 12007#define regUNIPHYA_LINK_CNTL 0x286d 12008#define regUNIPHYA_LINK_CNTL_BASE_IDX 2 12009#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 12010#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 12011#define regUNIPHYB_LINK_CNTL 0x286f 12012#define regUNIPHYB_LINK_CNTL_BASE_IDX 2 12013#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 12014#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 12015#define regUNIPHYC_LINK_CNTL 0x2871 12016#define regUNIPHYC_LINK_CNTL_BASE_IDX 2 12017#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 12018#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 12019#define regUNIPHYD_LINK_CNTL 0x2873 12020#define regUNIPHYD_LINK_CNTL_BASE_IDX 2 12021#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 12022#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 12023#define regUNIPHYE_LINK_CNTL 0x2875 12024#define regUNIPHYE_LINK_CNTL_BASE_IDX 2 12025#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 12026#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 12027#define regUNIPHYF_LINK_CNTL 0x2877 12028#define regUNIPHYF_LINK_CNTL_BASE_IDX 2 12029#define regUNIPHYF_CHANNEL_XBAR_CNTL 0x2878 12030#define regUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2 12031#define regUNIPHYG_LINK_CNTL 0x2879 12032#define regUNIPHYG_LINK_CNTL_BASE_IDX 2 12033#define regUNIPHYG_CHANNEL_XBAR_CNTL 0x287a 12034#define regUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2 12035#define regDCIO_WRCMD_DELAY 0x287e 12036#define regDCIO_WRCMD_DELAY_BASE_IDX 2 12037#define regDC_PINSTRAPS 0x2880 12038#define regDC_PINSTRAPS_BASE_IDX 2 12039#define regINTERCEPT_STATE 0x2884 12040#define regINTERCEPT_STATE_BASE_IDX 2 12041#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b 12042#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 12043#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c 12044#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 12045#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 12046#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 12047#define regDCIO_SOFT_RESET 0x289e 12048#define regDCIO_SOFT_RESET_BASE_IDX 2 12049 12050 12051// addressBlock: dce_dc_dcio_dcio_chip_dispdec 12052// base address: 0x0 12053#define regDC_GPIO_GENERIC_MASK 0x28c8 12054#define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 12055#define regDC_GPIO_GENERIC_A 0x28c9 12056#define regDC_GPIO_GENERIC_A_BASE_IDX 2 12057#define regDC_GPIO_GENERIC_EN 0x28ca 12058#define regDC_GPIO_GENERIC_EN_BASE_IDX 2 12059#define regDC_GPIO_GENERIC_Y 0x28cb 12060#define regDC_GPIO_GENERIC_Y_BASE_IDX 2 12061#define regDC_GPIO_DDC1_MASK 0x28d0 12062#define regDC_GPIO_DDC1_MASK_BASE_IDX 2 12063#define regDC_GPIO_DDC1_A 0x28d1 12064#define regDC_GPIO_DDC1_A_BASE_IDX 2 12065#define regDC_GPIO_DDC1_EN 0x28d2 12066#define regDC_GPIO_DDC1_EN_BASE_IDX 2 12067#define regDC_GPIO_DDC1_Y 0x28d3 12068#define regDC_GPIO_DDC1_Y_BASE_IDX 2 12069#define regDC_GPIO_DDC2_MASK 0x28d4 12070#define regDC_GPIO_DDC2_MASK_BASE_IDX 2 12071#define regDC_GPIO_DDC2_A 0x28d5 12072#define regDC_GPIO_DDC2_A_BASE_IDX 2 12073#define regDC_GPIO_DDC2_EN 0x28d6 12074#define regDC_GPIO_DDC2_EN_BASE_IDX 2 12075#define regDC_GPIO_DDC2_Y 0x28d7 12076#define regDC_GPIO_DDC2_Y_BASE_IDX 2 12077#define regDC_GPIO_DDC3_MASK 0x28d8 12078#define regDC_GPIO_DDC3_MASK_BASE_IDX 2 12079#define regDC_GPIO_DDC3_A 0x28d9 12080#define regDC_GPIO_DDC3_A_BASE_IDX 2 12081#define regDC_GPIO_DDC3_EN 0x28da 12082#define regDC_GPIO_DDC3_EN_BASE_IDX 2 12083#define regDC_GPIO_DDC3_Y 0x28db 12084#define regDC_GPIO_DDC3_Y_BASE_IDX 2 12085#define regDC_GPIO_DDC4_MASK 0x28dc 12086#define regDC_GPIO_DDC4_MASK_BASE_IDX 2 12087#define regDC_GPIO_DDC4_A 0x28dd 12088#define regDC_GPIO_DDC4_A_BASE_IDX 2 12089#define regDC_GPIO_DDC4_EN 0x28de 12090#define regDC_GPIO_DDC4_EN_BASE_IDX 2 12091#define regDC_GPIO_DDC4_Y 0x28df 12092#define regDC_GPIO_DDC4_Y_BASE_IDX 2 12093#define regDC_GPIO_DDC5_MASK 0x28e0 12094#define regDC_GPIO_DDC5_MASK_BASE_IDX 2 12095#define regDC_GPIO_DDC5_A 0x28e1 12096#define regDC_GPIO_DDC5_A_BASE_IDX 2 12097#define regDC_GPIO_DDC5_EN 0x28e2 12098#define regDC_GPIO_DDC5_EN_BASE_IDX 2 12099#define regDC_GPIO_DDC5_Y 0x28e3 12100#define regDC_GPIO_DDC5_Y_BASE_IDX 2 12101#define regDC_GPIO_DDCVGA_MASK 0x28e8 12102#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 12103#define regDC_GPIO_DDCVGA_A 0x28e9 12104#define regDC_GPIO_DDCVGA_A_BASE_IDX 2 12105#define regDC_GPIO_DDCVGA_EN 0x28ea 12106#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 12107#define regDC_GPIO_DDCVGA_Y 0x28eb 12108#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 12109#define regDC_GPIO_GENLK_MASK 0x28f0 12110#define regDC_GPIO_GENLK_MASK_BASE_IDX 2 12111#define regDC_GPIO_GENLK_A 0x28f1 12112#define regDC_GPIO_GENLK_A_BASE_IDX 2 12113#define regDC_GPIO_GENLK_EN 0x28f2 12114#define regDC_GPIO_GENLK_EN_BASE_IDX 2 12115#define regDC_GPIO_GENLK_Y 0x28f3 12116#define regDC_GPIO_GENLK_Y_BASE_IDX 2 12117#define regDC_GPIO_HPD_MASK 0x28f4 12118#define regDC_GPIO_HPD_MASK_BASE_IDX 2 12119#define regDC_GPIO_HPD_A 0x28f5 12120#define regDC_GPIO_HPD_A_BASE_IDX 2 12121#define regDC_GPIO_HPD_EN 0x28f6 12122#define regDC_GPIO_HPD_EN_BASE_IDX 2 12123#define regDC_GPIO_HPD_Y 0x28f7 12124#define regDC_GPIO_HPD_Y_BASE_IDX 2 12125#define regDC_GPIO_PWRSEQ0_EN 0x28fa 12126#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 12127#define regDC_GPIO_PAD_STRENGTH_1 0x28fc 12128#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 12129#define regDC_GPIO_PAD_STRENGTH_2 0x28fd 12130#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 12131#define regPHY_AUX_CNTL 0x28ff 12132#define regPHY_AUX_CNTL_BASE_IDX 2 12133#define regDC_GPIO_PWRSEQ1_EN 0x2902 12134#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 12135#define regDC_GPIO_TX12_EN 0x2915 12136#define regDC_GPIO_TX12_EN_BASE_IDX 2 12137#define regDC_GPIO_AUX_CTRL_0 0x2916 12138#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 12139#define regDC_GPIO_AUX_CTRL_1 0x2917 12140#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 12141#define regDC_GPIO_AUX_CTRL_2 0x2918 12142#define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 12143#define regDC_GPIO_RXEN 0x2919 12144#define regDC_GPIO_RXEN_BASE_IDX 2 12145#define regDC_GPIO_PULLUPEN 0x291a 12146#define regDC_GPIO_PULLUPEN_BASE_IDX 2 12147#define regDC_GPIO_AUX_CTRL_3 0x291b 12148#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 12149#define regDC_GPIO_AUX_CTRL_4 0x291c 12150#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 12151#define regDC_GPIO_AUX_CTRL_5 0x291d 12152#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 12153#define regAUXI2C_PAD_ALL_PWR_OK 0x291e 12154#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 12155 12156 12157// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec 12158// base address: 0x0 12159#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928 12160#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12161#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929 12162#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12163#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a 12164#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12165#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b 12166#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12167#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c 12168#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12169#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d 12170#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12171#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e 12172#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12173#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f 12174#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12175#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930 12176#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12177#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931 12178#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12179#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932 12180#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12181#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933 12182#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12183#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934 12184#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12185#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935 12186#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12187#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936 12188#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12189#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937 12190#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12191#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938 12192#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12193#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939 12194#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12195#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a 12196#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12197#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b 12198#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12199#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c 12200#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12201#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d 12202#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12203#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e 12204#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12205#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f 12206#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12207#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940 12208#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12209#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941 12210#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12211#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942 12212#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12213#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943 12214#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12215#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944 12216#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12217#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945 12218#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12219#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946 12220#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12221#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947 12222#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12223#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948 12224#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12225#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949 12226#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12227#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a 12228#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12229#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b 12230#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12231#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c 12232#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12233#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d 12234#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12235#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e 12236#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12237#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f 12238#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12239#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950 12240#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12241#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951 12242#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12243#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952 12244#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12245#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953 12246#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12247#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954 12248#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12249#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955 12250#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12251#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956 12252#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12253#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957 12254#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12255#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x2958 12256#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12257#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x2959 12258#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12259#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x295a 12260#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12261#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x295b 12262#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12263#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x295c 12264#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12265#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x295d 12266#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12267#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x295e 12268#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12269#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x295f 12270#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12271#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2960 12272#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12273#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2961 12274#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12275 12276 12277// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec 12278// base address: 0x360 12279#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 12280#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12281#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 12282#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12283#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 12284#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12285#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 12286#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12287#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 12288#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12289#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 12290#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12291#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 12292#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12293#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 12294#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12295#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 12296#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12297#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 12298#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12299#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a 12300#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12301#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b 12302#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12303#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c 12304#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12305#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d 12306#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12307#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e 12308#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12309#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f 12310#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12311#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 12312#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12313#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 12314#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12315#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 12316#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12317#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 12318#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12319#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 12320#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12321#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 12322#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12323#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 12324#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12325#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 12326#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12327#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 12328#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12329#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 12330#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12331#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a 12332#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12333#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b 12334#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12335#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c 12336#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12337#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d 12338#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12339#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e 12340#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12341#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f 12342#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12343#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 12344#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12345#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 12346#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12347#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 12348#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12349#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 12350#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12351#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 12352#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12353#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 12354#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12355#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 12356#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12357#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 12358#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12359#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 12360#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12361#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 12362#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12363#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a 12364#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12365#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b 12366#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12367#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c 12368#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12369#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d 12370#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12371#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e 12372#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12373#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f 12374#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12375#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 12376#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12377#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 12378#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12379#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 12380#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12381#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 12382#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12383#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 12384#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12385#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 12386#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12387#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 12388#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12389#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 12390#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12391#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 12392#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12393#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 12394#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12395 12396 12397// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec 12398// base address: 0x6c0 12399#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 12400#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12401#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 12402#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12403#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada 12404#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12405#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb 12406#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12407#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc 12408#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12409#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add 12410#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12411#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade 12412#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12413#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf 12414#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12415#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 12416#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12417#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 12418#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12419#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 12420#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12421#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 12422#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12423#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 12424#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12425#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 12426#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12427#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 12428#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12429#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 12430#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12431#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 12432#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12433#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 12434#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12435#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea 12436#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12437#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb 12438#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12439#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec 12440#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12441#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed 12442#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12443#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee 12444#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12445#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef 12446#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12447#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 12448#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12449#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 12450#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12451#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 12452#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12453#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 12454#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12455#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 12456#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12457#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 12458#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12459#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 12460#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12461#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 12462#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12463#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 12464#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12465#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 12466#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12467#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa 12468#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12469#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb 12470#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12471#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc 12472#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12473#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd 12474#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12475#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe 12476#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12477#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff 12478#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12479#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 12480#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12481#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 12482#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12483#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 12484#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12485#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 12486#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12487#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 12488#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12489#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 12490#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12491#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 12492#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12493#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 12494#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12495#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 12496#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12497#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 12498#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12499#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a 12500#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12501#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b 12502#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12503#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c 12504#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12505#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d 12506#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12507#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e 12508#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12509#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f 12510#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12511#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 12512#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12513#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 12514#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12515 12516 12517// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec 12518// base address: 0xa20 12519#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 12520#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12521#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 12522#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12523#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 12524#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12525#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 12526#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12527#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 12528#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12529#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 12530#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12531#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 12532#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12533#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 12534#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12535#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 12536#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12537#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 12538#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12539#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba 12540#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12541#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb 12542#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12543#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc 12544#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12545#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd 12546#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12547#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe 12548#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12549#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf 12550#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12551#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 12552#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12553#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 12554#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12555#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 12556#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12557#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 12558#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12559#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 12560#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12561#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 12562#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12563#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 12564#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12565#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 12566#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12567#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 12568#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12569#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 12570#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12571#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca 12572#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12573#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb 12574#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12575#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc 12576#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12577#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd 12578#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12579#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce 12580#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12581#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf 12582#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12583#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 12584#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12585#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 12586#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12587#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 12588#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12589#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 12590#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12591#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 12592#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12593#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 12594#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12595#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 12596#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12597#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 12598#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12599#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 12600#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12601#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 12602#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12603#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda 12604#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12605#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb 12606#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12607#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc 12608#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12609#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd 12610#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12611#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde 12612#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12613#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf 12614#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12615#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 12616#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12617#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 12618#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12619#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 12620#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12621#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 12622#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12623#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 12624#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12625#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 12626#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12627#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 12628#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12629#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 12630#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12631#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 12632#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12633#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 12634#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12635 12636 12637// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec 12638// base address: 0xd80 12639#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 12640#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12641#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 12642#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12643#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a 12644#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12645#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b 12646#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12647#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c 12648#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12649#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d 12650#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12651#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e 12652#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12653#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f 12654#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12655#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 12656#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12657#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 12658#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12659#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 12660#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12661#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 12662#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12663#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 12664#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12665#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 12666#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12667#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 12668#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12669#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 12670#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12671#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 12672#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12673#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 12674#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12675#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a 12676#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12677#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b 12678#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12679#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c 12680#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12681#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d 12682#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12683#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e 12684#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12685#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f 12686#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12687#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 12688#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12689#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 12690#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12691#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 12692#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12693#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 12694#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12695#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 12696#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12697#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 12698#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12699#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 12700#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12701#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 12702#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12703#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 12704#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12705#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 12706#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12707#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa 12708#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12709#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab 12710#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12711#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac 12712#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12713#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad 12714#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12715#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae 12716#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12717#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf 12718#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12719#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 12720#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12721#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 12722#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12723#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 12724#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12725#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 12726#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12727#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 12728#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12729#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 12730#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12731#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 12732#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12733#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 12734#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12735#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 12736#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12737#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 12738#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12739#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba 12740#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12741#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb 12742#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12743#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc 12744#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12745#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd 12746#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12747#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe 12748#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12749#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf 12750#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12751#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 12752#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12753#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 12754#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12755 12756 12757// addressBlock: dce_dc_dcio_dcio_uniphy5_dispdec 12758// base address: 0x10e0 12759#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x2d60 12760#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12761#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x2d61 12762#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12763#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x2d62 12764#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12765#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x2d63 12766#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12767#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x2d64 12768#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12769#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x2d65 12770#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12771#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x2d66 12772#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12773#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x2d67 12774#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12775#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x2d68 12776#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12777#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x2d69 12778#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12779#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x2d6a 12780#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12781#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x2d6b 12782#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12783#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x2d6c 12784#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12785#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x2d6d 12786#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12787#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x2d6e 12788#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12789#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x2d6f 12790#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12791#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x2d70 12792#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12793#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x2d71 12794#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12795#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x2d72 12796#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12797#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x2d73 12798#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12799#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x2d74 12800#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12801#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x2d75 12802#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12803#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x2d76 12804#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12805#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x2d77 12806#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12807#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x2d78 12808#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12809#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x2d79 12810#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12811#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x2d7a 12812#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12813#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x2d7b 12814#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12815#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x2d7c 12816#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12817#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x2d7d 12818#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12819#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x2d7e 12820#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12821#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x2d7f 12822#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12823#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x2d80 12824#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12825#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x2d81 12826#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12827#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x2d82 12828#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12829#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x2d83 12830#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12831#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x2d84 12832#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12833#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x2d85 12834#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12835#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x2d86 12836#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12837#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x2d87 12838#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12839#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x2d88 12840#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12841#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x2d89 12842#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12843#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x2d8a 12844#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12845#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x2d8b 12846#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12847#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x2d8c 12848#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12849#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x2d8d 12850#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12851#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x2d8e 12852#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12853#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x2d8f 12854#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12855#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48 0x2d90 12856#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12857#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49 0x2d91 12858#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12859#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50 0x2d92 12860#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12861#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51 0x2d93 12862#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12863#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52 0x2d94 12864#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12865#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53 0x2d95 12866#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12867#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54 0x2d96 12868#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12869#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55 0x2d97 12870#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12871#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56 0x2d98 12872#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12873#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57 0x2d99 12874#define regDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12875 12876 12877// addressBlock: dce_dc_dcio_dcio_uniphy6_dispdec 12878// base address: 0x1440 12879#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x2e38 12880#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12881#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x2e39 12882#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12883#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x2e3a 12884#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12885#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x2e3b 12886#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12887#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x2e3c 12888#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12889#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x2e3d 12890#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12891#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x2e3e 12892#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12893#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x2e3f 12894#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12895#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x2e40 12896#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12897#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x2e41 12898#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12899#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x2e42 12900#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12901#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x2e43 12902#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12903#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x2e44 12904#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12905#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x2e45 12906#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12907#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x2e46 12908#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12909#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x2e47 12910#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12911#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x2e48 12912#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12913#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x2e49 12914#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12915#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x2e4a 12916#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12917#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x2e4b 12918#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12919#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x2e4c 12920#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12921#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x2e4d 12922#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12923#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x2e4e 12924#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12925#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x2e4f 12926#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12927#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x2e50 12928#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12929#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x2e51 12930#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12931#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x2e52 12932#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12933#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x2e53 12934#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12935#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x2e54 12936#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12937#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x2e55 12938#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12939#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x2e56 12940#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12941#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x2e57 12942#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12943#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0x2e58 12944#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12945#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0x2e59 12946#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12947#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0x2e5a 12948#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12949#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0x2e5b 12950#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12951#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0x2e5c 12952#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12953#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0x2e5d 12954#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12955#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0x2e5e 12956#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12957#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0x2e5f 12958#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12959#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0x2e60 12960#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12961#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0x2e61 12962#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12963#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0x2e62 12964#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12965#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0x2e63 12966#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12967#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0x2e64 12968#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12969#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0x2e65 12970#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12971#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0x2e66 12972#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12973#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0x2e67 12974#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12975#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48 0x2e68 12976#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12977#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49 0x2e69 12978#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12979#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50 0x2e6a 12980#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12981#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51 0x2e6b 12982#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12983#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52 0x2e6c 12984#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12985#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53 0x2e6d 12986#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12987#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54 0x2e6e 12988#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12989#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55 0x2e6f 12990#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12991#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56 0x2e70 12992#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12993#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57 0x2e71 12994#define regDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12995 12996 12997// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec 12998// base address: 0x0 12999#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 13000#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 13001#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 13002#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 13003#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 13004#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 13005#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 13006#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 13007#define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 13008#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 13009#define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 13010#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 13011#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 13012#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 13013#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 13014#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 13015#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 13016#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 13017#define regPWRSEQ0_BL_PWM_CNTL 0x2f19 13018#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 13019#define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a 13020#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 13021#define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b 13022#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 13023#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c 13024#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 13025#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d 13026#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 13027#define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 13028#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 13029 13030 13031// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec 13032// base address: 0x1b0 13033#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c 13034#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 13035#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d 13036#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 13037#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e 13038#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 13039#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f 13040#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 13041#define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 13042#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 13043#define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 13044#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 13045#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 13046#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 13047#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 13048#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 13049#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 13050#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 13051#define regPWRSEQ1_BL_PWM_CNTL 0x2f85 13052#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 13053#define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 13054#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 13055#define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 13056#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 13057#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 13058#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 13059#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 13060#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 13061#define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d 13062#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 13063 13064 13065// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec 13066// base address: 0x0 13067#define regDSCC0_DSCC_CONFIG0 0x300a 13068#define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 13069#define regDSCC0_DSCC_CONFIG1 0x300b 13070#define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 13071#define regDSCC0_DSCC_STATUS 0x300c 13072#define regDSCC0_DSCC_STATUS_BASE_IDX 2 13073#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d 13074#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 13075#define regDSCC0_DSCC_PPS_CONFIG0 0x300e 13076#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 13077#define regDSCC0_DSCC_PPS_CONFIG1 0x300f 13078#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 13079#define regDSCC0_DSCC_PPS_CONFIG2 0x3010 13080#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 13081#define regDSCC0_DSCC_PPS_CONFIG3 0x3011 13082#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 13083#define regDSCC0_DSCC_PPS_CONFIG4 0x3012 13084#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 13085#define regDSCC0_DSCC_PPS_CONFIG5 0x3013 13086#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 13087#define regDSCC0_DSCC_PPS_CONFIG6 0x3014 13088#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 13089#define regDSCC0_DSCC_PPS_CONFIG7 0x3015 13090#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 13091#define regDSCC0_DSCC_PPS_CONFIG8 0x3016 13092#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 13093#define regDSCC0_DSCC_PPS_CONFIG9 0x3017 13094#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 13095#define regDSCC0_DSCC_PPS_CONFIG10 0x3018 13096#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 13097#define regDSCC0_DSCC_PPS_CONFIG11 0x3019 13098#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 13099#define regDSCC0_DSCC_PPS_CONFIG12 0x301a 13100#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 13101#define regDSCC0_DSCC_PPS_CONFIG13 0x301b 13102#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 13103#define regDSCC0_DSCC_PPS_CONFIG14 0x301c 13104#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 13105#define regDSCC0_DSCC_PPS_CONFIG15 0x301d 13106#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 13107#define regDSCC0_DSCC_PPS_CONFIG16 0x301e 13108#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 13109#define regDSCC0_DSCC_PPS_CONFIG17 0x301f 13110#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 13111#define regDSCC0_DSCC_PPS_CONFIG18 0x3020 13112#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 13113#define regDSCC0_DSCC_PPS_CONFIG19 0x3021 13114#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 13115#define regDSCC0_DSCC_PPS_CONFIG20 0x3022 13116#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 13117#define regDSCC0_DSCC_PPS_CONFIG21 0x3023 13118#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 13119#define regDSCC0_DSCC_PPS_CONFIG22 0x3024 13120#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 13121#define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 13122#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 13123#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 13124#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 13125#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 13126#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 13127#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 13128#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 13129#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 13130#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 13131#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a 13132#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 13133#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b 13134#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 13135#define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c 13136#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 13137#define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d 13138#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 13139#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e 13140#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13141#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f 13142#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13143#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 13144#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13145#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 13146#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13147#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 13148#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13149#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 13150#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13151#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 13152#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13153#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 13154#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13155#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a 13156#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 13157 13158 13159// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec 13160// base address: 0x0 13161#define regDSCCIF0_DSCCIF_CONFIG0 0x3005 13162#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 13163#define regDSCCIF0_DSCCIF_CONFIG1 0x3006 13164#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 13165 13166 13167// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec 13168// base address: 0x0 13169#define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 13170#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 13171#define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 13172#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 13173 13174 13175// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 13176// base address: 0xc140 13177#define regDC_PERFMON19_PERFCOUNTER_CNTL 0x3050 13178#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 13179#define regDC_PERFMON19_PERFCOUNTER_CNTL2 0x3051 13180#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 13181#define regDC_PERFMON19_PERFCOUNTER_STATE 0x3052 13182#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 13183#define regDC_PERFMON19_PERFMON_CNTL 0x3053 13184#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 13185#define regDC_PERFMON19_PERFMON_CNTL2 0x3054 13186#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 13187#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x3055 13188#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13189#define regDC_PERFMON19_PERFMON_CVALUE_LOW 0x3056 13190#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 13191#define regDC_PERFMON19_PERFMON_HI 0x3057 13192#define regDC_PERFMON19_PERFMON_HI_BASE_IDX 2 13193#define regDC_PERFMON19_PERFMON_LOW 0x3058 13194#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 13195 13196 13197// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec 13198// base address: 0x170 13199#define regDSCC1_DSCC_CONFIG0 0x3066 13200#define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 13201#define regDSCC1_DSCC_CONFIG1 0x3067 13202#define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 13203#define regDSCC1_DSCC_STATUS 0x3068 13204#define regDSCC1_DSCC_STATUS_BASE_IDX 2 13205#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 13206#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 13207#define regDSCC1_DSCC_PPS_CONFIG0 0x306a 13208#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 13209#define regDSCC1_DSCC_PPS_CONFIG1 0x306b 13210#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 13211#define regDSCC1_DSCC_PPS_CONFIG2 0x306c 13212#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 13213#define regDSCC1_DSCC_PPS_CONFIG3 0x306d 13214#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 13215#define regDSCC1_DSCC_PPS_CONFIG4 0x306e 13216#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 13217#define regDSCC1_DSCC_PPS_CONFIG5 0x306f 13218#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 13219#define regDSCC1_DSCC_PPS_CONFIG6 0x3070 13220#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 13221#define regDSCC1_DSCC_PPS_CONFIG7 0x3071 13222#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 13223#define regDSCC1_DSCC_PPS_CONFIG8 0x3072 13224#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 13225#define regDSCC1_DSCC_PPS_CONFIG9 0x3073 13226#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 13227#define regDSCC1_DSCC_PPS_CONFIG10 0x3074 13228#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 13229#define regDSCC1_DSCC_PPS_CONFIG11 0x3075 13230#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 13231#define regDSCC1_DSCC_PPS_CONFIG12 0x3076 13232#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 13233#define regDSCC1_DSCC_PPS_CONFIG13 0x3077 13234#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 13235#define regDSCC1_DSCC_PPS_CONFIG14 0x3078 13236#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 13237#define regDSCC1_DSCC_PPS_CONFIG15 0x3079 13238#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 13239#define regDSCC1_DSCC_PPS_CONFIG16 0x307a 13240#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 13241#define regDSCC1_DSCC_PPS_CONFIG17 0x307b 13242#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 13243#define regDSCC1_DSCC_PPS_CONFIG18 0x307c 13244#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 13245#define regDSCC1_DSCC_PPS_CONFIG19 0x307d 13246#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 13247#define regDSCC1_DSCC_PPS_CONFIG20 0x307e 13248#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 13249#define regDSCC1_DSCC_PPS_CONFIG21 0x307f 13250#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 13251#define regDSCC1_DSCC_PPS_CONFIG22 0x3080 13252#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 13253#define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 13254#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 13255#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 13256#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 13257#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 13258#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 13259#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 13260#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 13261#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 13262#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 13263#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 13264#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 13265#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 13266#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 13267#define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 13268#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 13269#define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 13270#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 13271#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a 13272#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13273#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b 13274#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13275#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c 13276#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13277#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d 13278#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13279#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e 13280#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13281#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f 13282#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13283#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 13284#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13285#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 13286#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13287#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 13288#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 13289 13290 13291// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec 13292// base address: 0x170 13293#define regDSCCIF1_DSCCIF_CONFIG0 0x3061 13294#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 13295#define regDSCCIF1_DSCCIF_CONFIG1 0x3062 13296#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 13297 13298 13299// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec 13300// base address: 0x170 13301#define regDSC_TOP1_DSC_TOP_CONTROL 0x305c 13302#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 13303#define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d 13304#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 13305 13306 13307// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 13308// base address: 0xc2b0 13309#define regDC_PERFMON20_PERFCOUNTER_CNTL 0x30ac 13310#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 13311#define regDC_PERFMON20_PERFCOUNTER_CNTL2 0x30ad 13312#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 13313#define regDC_PERFMON20_PERFCOUNTER_STATE 0x30ae 13314#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 13315#define regDC_PERFMON20_PERFMON_CNTL 0x30af 13316#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 13317#define regDC_PERFMON20_PERFMON_CNTL2 0x30b0 13318#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 13319#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x30b1 13320#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13321#define regDC_PERFMON20_PERFMON_CVALUE_LOW 0x30b2 13322#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 13323#define regDC_PERFMON20_PERFMON_HI 0x30b3 13324#define regDC_PERFMON20_PERFMON_HI_BASE_IDX 2 13325#define regDC_PERFMON20_PERFMON_LOW 0x30b4 13326#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 13327 13328 13329// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec 13330// base address: 0x2e0 13331#define regDSCC2_DSCC_CONFIG0 0x30c2 13332#define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 13333#define regDSCC2_DSCC_CONFIG1 0x30c3 13334#define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 13335#define regDSCC2_DSCC_STATUS 0x30c4 13336#define regDSCC2_DSCC_STATUS_BASE_IDX 2 13337#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 13338#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 13339#define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 13340#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 13341#define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 13342#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 13343#define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 13344#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 13345#define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 13346#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 13347#define regDSCC2_DSCC_PPS_CONFIG4 0x30ca 13348#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 13349#define regDSCC2_DSCC_PPS_CONFIG5 0x30cb 13350#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 13351#define regDSCC2_DSCC_PPS_CONFIG6 0x30cc 13352#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 13353#define regDSCC2_DSCC_PPS_CONFIG7 0x30cd 13354#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 13355#define regDSCC2_DSCC_PPS_CONFIG8 0x30ce 13356#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 13357#define regDSCC2_DSCC_PPS_CONFIG9 0x30cf 13358#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 13359#define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 13360#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 13361#define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 13362#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 13363#define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 13364#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 13365#define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 13366#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 13367#define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 13368#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 13369#define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 13370#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 13371#define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 13372#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 13373#define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 13374#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 13375#define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 13376#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 13377#define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 13378#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 13379#define regDSCC2_DSCC_PPS_CONFIG20 0x30da 13380#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 13381#define regDSCC2_DSCC_PPS_CONFIG21 0x30db 13382#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 13383#define regDSCC2_DSCC_PPS_CONFIG22 0x30dc 13384#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 13385#define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd 13386#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 13387#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de 13388#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 13389#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df 13390#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 13391#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 13392#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 13393#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 13394#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 13395#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 13396#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 13397#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 13398#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 13399#define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 13400#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 13401#define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 13402#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 13403#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 13404#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13405#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 13406#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13407#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 13408#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13409#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 13410#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13411#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea 13412#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13413#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb 13414#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13415#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec 13416#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13417#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed 13418#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13419#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 13420#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 13421 13422 13423// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec 13424// base address: 0x2e0 13425#define regDSCCIF2_DSCCIF_CONFIG0 0x30bd 13426#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 13427#define regDSCCIF2_DSCCIF_CONFIG1 0x30be 13428#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 13429 13430 13431// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec 13432// base address: 0x2e0 13433#define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 13434#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 13435#define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 13436#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 13437 13438 13439// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 13440// base address: 0xc420 13441#define regDC_PERFMON21_PERFCOUNTER_CNTL 0x3108 13442#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 13443#define regDC_PERFMON21_PERFCOUNTER_CNTL2 0x3109 13444#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 13445#define regDC_PERFMON21_PERFCOUNTER_STATE 0x310a 13446#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 13447#define regDC_PERFMON21_PERFMON_CNTL 0x310b 13448#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 13449#define regDC_PERFMON21_PERFMON_CNTL2 0x310c 13450#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 13451#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x310d 13452#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13453#define regDC_PERFMON21_PERFMON_CVALUE_LOW 0x310e 13454#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 13455#define regDC_PERFMON21_PERFMON_HI 0x310f 13456#define regDC_PERFMON21_PERFMON_HI_BASE_IDX 2 13457#define regDC_PERFMON21_PERFMON_LOW 0x3110 13458#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 13459 13460 13461// addressBlock: dce_dc_hpo_hpo_top_dispdec 13462// base address: 0x2790c 13463#define regHPO_TOP_CLOCK_CONTROL 0x0e43 13464#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 13465#define regHPO_TOP_HW_CONTROL 0x0e4a 13466#define regHPO_TOP_HW_CONTROL_BASE_IDX 3 13467 13468 13469// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec 13470// base address: 0x27958 13471#define regDP_STREAM_MAPPER_CONTROL0 0x0e56 13472#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 13473#define regDP_STREAM_MAPPER_CONTROL1 0x0e57 13474#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 13475#define regDP_STREAM_MAPPER_CONTROL2 0x0e58 13476#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 13477#define regDP_STREAM_MAPPER_CONTROL3 0x0e59 13478#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 13479 13480 13481// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec 13482// base address: 0x1a698 13483#define regDC_PERFMON22_PERFCOUNTER_CNTL 0x0e66 13484#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 3 13485#define regDC_PERFMON22_PERFCOUNTER_CNTL2 0x0e67 13486#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 3 13487#define regDC_PERFMON22_PERFCOUNTER_STATE 0x0e68 13488#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 3 13489#define regDC_PERFMON22_PERFMON_CNTL 0x0e69 13490#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX 3 13491#define regDC_PERFMON22_PERFMON_CNTL2 0x0e6a 13492#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 3 13493#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x0e6b 13494#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 13495#define regDC_PERFMON22_PERFMON_CVALUE_LOW 0x0e6c 13496#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 3 13497#define regDC_PERFMON22_PERFMON_HI 0x0e6d 13498#define regDC_PERFMON22_PERFMON_HI_BASE_IDX 3 13499#define regDC_PERFMON22_PERFMON_LOW 0x0e6e 13500#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 13501 13502 13503// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec 13504// base address: 0x2646c 13505#define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c 13506#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 13507#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d 13508#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 13509#define regAFMT5_AFMT_AUDIO_INFO0 0x091e 13510#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 13511#define regAFMT5_AFMT_AUDIO_INFO1 0x091f 13512#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 13513#define regAFMT5_AFMT_60958_0 0x0920 13514#define regAFMT5_AFMT_60958_0_BASE_IDX 3 13515#define regAFMT5_AFMT_60958_1 0x0921 13516#define regAFMT5_AFMT_60958_1_BASE_IDX 3 13517#define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 13518#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 13519#define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 13520#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 13521#define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 13522#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 13523#define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 13524#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 13525#define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 13526#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 13527#define regAFMT5_AFMT_60958_2 0x0927 13528#define regAFMT5_AFMT_60958_2_BASE_IDX 3 13529#define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 13530#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 13531#define regAFMT5_AFMT_STATUS 0x0929 13532#define regAFMT5_AFMT_STATUS_BASE_IDX 3 13533#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a 13534#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 13535#define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b 13536#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 13537#define regAFMT5_AFMT_INTERRUPT_STATUS 0x092c 13538#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 3 13539#define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d 13540#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 13541#define regAFMT5_AFMT_MEM_PWR 0x092f 13542#define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 13543 13544 13545// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec 13546// base address: 0x264f0 13547#define regDME5_DME_CONTROL 0x093c 13548#define regDME5_DME_CONTROL_BASE_IDX 3 13549#define regDME5_DME_MEMORY_CONTROL 0x093d 13550#define regDME5_DME_MEMORY_CONTROL_BASE_IDX 3 13551 13552 13553// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec 13554// base address: 0x264c4 13555#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 13556#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 13557#define regVPG5_VPG_GENERIC_PACKET_DATA 0x0932 13558#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 13559#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 13560#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 13561#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 13562#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 13563#define regVPG5_VPG_GENERIC_STATUS 0x0935 13564#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 3 13565#define regVPG5_VPG_MEM_PWR 0x0936 13566#define regVPG5_VPG_MEM_PWR_BASE_IDX 3 13567#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x0937 13568#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 13569#define regVPG5_VPG_ISRC1_2_DATA 0x0938 13570#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 3 13571#define regVPG5_VPG_MPEG_INFO0 0x0939 13572#define regVPG5_VPG_MPEG_INFO0_BASE_IDX 3 13573#define regVPG5_VPG_MPEG_INFO1 0x093a 13574#define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 13575 13576 13577// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec 13578// base address: 0x1ab8c 13579#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 13580#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13581#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 13582#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13583#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 13584#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13585#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 13586#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13587#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 13588#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13589#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 13590#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 13591 13592 13593// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec 13594// base address: 0x1abc0 13595#define regAPG0_APG_CONTROL 0x3630 13596#define regAPG0_APG_CONTROL_BASE_IDX 2 13597#define regAPG0_APG_CONTROL2 0x3631 13598#define regAPG0_APG_CONTROL2_BASE_IDX 2 13599#define regAPG0_APG_DBG_GEN_CONTROL 0x3632 13600#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 13601#define regAPG0_APG_PACKET_CONTROL 0x3633 13602#define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 13603#define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a 13604#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13605#define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b 13606#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13607#define regAPG0_APG_AUDIO_CRC_RESULT 0x363c 13608#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13609#define regAPG0_APG_STATUS 0x3641 13610#define regAPG0_APG_STATUS_BASE_IDX 2 13611#define regAPG0_APG_STATUS2 0x3642 13612#define regAPG0_APG_STATUS2_BASE_IDX 2 13613#define regAPG0_APG_MEM_PWR 0x3644 13614#define regAPG0_APG_MEM_PWR_BASE_IDX 2 13615#define regAPG0_APG_SPARE 0x3646 13616#define regAPG0_APG_SPARE_BASE_IDX 2 13617 13618 13619// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec 13620// base address: 0x1ac38 13621#define regDME6_DME_CONTROL 0x364e 13622#define regDME6_DME_CONTROL_BASE_IDX 2 13623#define regDME6_DME_MEMORY_CONTROL 0x364f 13624#define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 13625 13626 13627// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec 13628// base address: 0x1ac44 13629#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 13630#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13631#define regVPG6_VPG_GENERIC_PACKET_DATA 0x3652 13632#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13633#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 13634#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13635#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 13636#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13637#define regVPG6_VPG_GENERIC_STATUS 0x3655 13638#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 13639#define regVPG6_VPG_MEM_PWR 0x3656 13640#define regVPG6_VPG_MEM_PWR_BASE_IDX 2 13641#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x3657 13642#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13643#define regVPG6_VPG_ISRC1_2_DATA 0x3658 13644#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 13645#define regVPG6_VPG_MPEG_INFO0 0x3659 13646#define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 13647#define regVPG6_VPG_MPEG_INFO1 0x365a 13648#define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 13649 13650 13651// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec 13652// base address: 0x1ac74 13653#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d 13654#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13655#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e 13656#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13657#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f 13658#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13659#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 13660#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13661#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 13662#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13663#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 13664#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13665#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 13666#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13667#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 13668#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13669#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 13670#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13671#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 13672#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13673#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 13674#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13675#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 13676#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13677#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 13678#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13679#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a 13680#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13681#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b 13682#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13683#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c 13684#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13685#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d 13686#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13687#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e 13688#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13689#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f 13690#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13691#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 13692#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13693#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 13694#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13695#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 13696#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13697#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 13698#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13699#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 13700#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13701#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 13702#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13703#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 13704#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13705#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 13706#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13707#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 13708#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13709#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 13710#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13711#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a 13712#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13713#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b 13714#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13715#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c 13716#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13717#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d 13718#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13719#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e 13720#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13721#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 13722#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13723#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 13724#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13725#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 13726#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13727#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 13728#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13729#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 13730#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13731#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 13732#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13733#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 13734#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13735#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a 13736#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13737#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368b 13738#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13739#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368c 13740#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 13741 13742 13743// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec 13744// base address: 0x1aedc 13745#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 13746#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13747#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 13748#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13749#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 13750#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13751#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa 13752#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13753#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb 13754#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13755#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc 13756#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 13757 13758 13759// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec 13760// base address: 0x1af10 13761#define regAPG1_APG_CONTROL 0x3704 13762#define regAPG1_APG_CONTROL_BASE_IDX 2 13763#define regAPG1_APG_CONTROL2 0x3705 13764#define regAPG1_APG_CONTROL2_BASE_IDX 2 13765#define regAPG1_APG_DBG_GEN_CONTROL 0x3706 13766#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 13767#define regAPG1_APG_PACKET_CONTROL 0x3707 13768#define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 13769#define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e 13770#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13771#define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f 13772#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13773#define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 13774#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13775#define regAPG1_APG_STATUS 0x3715 13776#define regAPG1_APG_STATUS_BASE_IDX 2 13777#define regAPG1_APG_STATUS2 0x3716 13778#define regAPG1_APG_STATUS2_BASE_IDX 2 13779#define regAPG1_APG_MEM_PWR 0x3718 13780#define regAPG1_APG_MEM_PWR_BASE_IDX 2 13781#define regAPG1_APG_SPARE 0x371a 13782#define regAPG1_APG_SPARE_BASE_IDX 2 13783 13784 13785// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec 13786// base address: 0x1af88 13787#define regDME7_DME_CONTROL 0x3722 13788#define regDME7_DME_CONTROL_BASE_IDX 2 13789#define regDME7_DME_MEMORY_CONTROL 0x3723 13790#define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 13791 13792 13793// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec 13794// base address: 0x1af94 13795#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 13796#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13797#define regVPG7_VPG_GENERIC_PACKET_DATA 0x3726 13798#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13799#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 13800#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13801#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 13802#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13803#define regVPG7_VPG_GENERIC_STATUS 0x3729 13804#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 13805#define regVPG7_VPG_MEM_PWR 0x372a 13806#define regVPG7_VPG_MEM_PWR_BASE_IDX 2 13807#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x372b 13808#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13809#define regVPG7_VPG_ISRC1_2_DATA 0x372c 13810#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 13811#define regVPG7_VPG_MPEG_INFO0 0x372d 13812#define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 13813#define regVPG7_VPG_MPEG_INFO1 0x372e 13814#define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 13815 13816 13817// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec 13818// base address: 0x1afc4 13819#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 13820#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13821#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 13822#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13823#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 13824#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13825#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 13826#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13827#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 13828#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13829#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 13830#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13831#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 13832#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13833#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 13834#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13835#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 13836#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13837#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a 13838#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13839#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b 13840#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13841#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c 13842#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13843#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d 13844#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13845#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e 13846#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13847#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f 13848#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13849#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 13850#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13851#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 13852#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13853#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 13854#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13855#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 13856#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13857#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 13858#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13859#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 13860#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13861#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 13862#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13863#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 13864#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13865#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 13866#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13867#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 13868#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13869#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a 13870#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13871#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b 13872#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13873#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c 13874#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13875#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d 13876#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13877#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e 13878#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13879#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f 13880#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13881#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 13882#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13883#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 13884#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13885#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 13886#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13887#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 13888#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13889#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 13890#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13891#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 13892#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13893#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a 13894#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13895#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b 13896#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13897#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c 13898#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13899#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d 13900#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13901#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e 13902#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13903#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x375f 13904#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13905#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3760 13906#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 13907 13908 13909// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec 13910// base address: 0x1b22c 13911#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb 13912#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13913#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc 13914#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13915#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd 13916#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13917#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce 13918#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13919#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf 13920#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13921#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 13922#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 13923 13924 13925// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec 13926// base address: 0x1b260 13927#define regAPG2_APG_CONTROL 0x37d8 13928#define regAPG2_APG_CONTROL_BASE_IDX 2 13929#define regAPG2_APG_CONTROL2 0x37d9 13930#define regAPG2_APG_CONTROL2_BASE_IDX 2 13931#define regAPG2_APG_DBG_GEN_CONTROL 0x37da 13932#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 13933#define regAPG2_APG_PACKET_CONTROL 0x37db 13934#define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 13935#define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 13936#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13937#define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 13938#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13939#define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 13940#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13941#define regAPG2_APG_STATUS 0x37e9 13942#define regAPG2_APG_STATUS_BASE_IDX 2 13943#define regAPG2_APG_STATUS2 0x37ea 13944#define regAPG2_APG_STATUS2_BASE_IDX 2 13945#define regAPG2_APG_MEM_PWR 0x37ec 13946#define regAPG2_APG_MEM_PWR_BASE_IDX 2 13947#define regAPG2_APG_SPARE 0x37ee 13948#define regAPG2_APG_SPARE_BASE_IDX 2 13949 13950 13951// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec 13952// base address: 0x1b2d8 13953#define regDME8_DME_CONTROL 0x37f6 13954#define regDME8_DME_CONTROL_BASE_IDX 2 13955#define regDME8_DME_MEMORY_CONTROL 0x37f7 13956#define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 13957 13958 13959// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec 13960// base address: 0x1b2e4 13961#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 13962#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13963#define regVPG8_VPG_GENERIC_PACKET_DATA 0x37fa 13964#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13965#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb 13966#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13967#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc 13968#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13969#define regVPG8_VPG_GENERIC_STATUS 0x37fd 13970#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 13971#define regVPG8_VPG_MEM_PWR 0x37fe 13972#define regVPG8_VPG_MEM_PWR_BASE_IDX 2 13973#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x37ff 13974#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13975#define regVPG8_VPG_ISRC1_2_DATA 0x3800 13976#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 13977#define regVPG8_VPG_MPEG_INFO0 0x3801 13978#define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 13979#define regVPG8_VPG_MPEG_INFO1 0x3802 13980#define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 13981 13982 13983// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec 13984// base address: 0x1b314 13985#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 13986#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13987#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 13988#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13989#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 13990#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13991#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 13992#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13993#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 13994#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13995#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a 13996#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13997#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b 13998#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13999#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c 14000#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 14001#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d 14002#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 14003#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e 14004#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 14005#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f 14006#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 14007#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 14008#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 14009#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 14010#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 14011#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 14012#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 14013#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 14014#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 14015#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 14016#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 14017#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 14018#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 14019#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 14020#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 14021#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 14022#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 14023#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 14024#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 14025#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 14026#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 14027#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a 14028#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 14029#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b 14030#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 14031#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c 14032#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 14033#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d 14034#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 14035#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e 14036#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 14037#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f 14038#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 14039#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 14040#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 14041#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 14042#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 14043#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 14044#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 14045#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 14046#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 14047#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 14048#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 14049#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 14050#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 14051#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 14052#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 14053#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b 14054#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 14055#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c 14056#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 14057#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d 14058#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 14059#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e 14060#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 14061#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f 14062#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 14063#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 14064#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 14065#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 14066#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 14067#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 14068#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 14069#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3833 14070#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 14071#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3834 14072#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 14073 14074 14075// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec 14076// base address: 0x1b57c 14077#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f 14078#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 14079#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 14080#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 14081#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 14082#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 14083#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 14084#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 14085#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 14086#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 14087#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 14088#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 14089 14090 14091// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec 14092// base address: 0x1b5b0 14093#define regAPG3_APG_CONTROL 0x38ac 14094#define regAPG3_APG_CONTROL_BASE_IDX 2 14095#define regAPG3_APG_CONTROL2 0x38ad 14096#define regAPG3_APG_CONTROL2_BASE_IDX 2 14097#define regAPG3_APG_DBG_GEN_CONTROL 0x38ae 14098#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 14099#define regAPG3_APG_PACKET_CONTROL 0x38af 14100#define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 14101#define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 14102#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 14103#define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 14104#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 14105#define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 14106#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 14107#define regAPG3_APG_STATUS 0x38bd 14108#define regAPG3_APG_STATUS_BASE_IDX 2 14109#define regAPG3_APG_STATUS2 0x38be 14110#define regAPG3_APG_STATUS2_BASE_IDX 2 14111#define regAPG3_APG_MEM_PWR 0x38c0 14112#define regAPG3_APG_MEM_PWR_BASE_IDX 2 14113#define regAPG3_APG_SPARE 0x38c2 14114#define regAPG3_APG_SPARE_BASE_IDX 2 14115 14116 14117// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec 14118// base address: 0x1b628 14119#define regDME9_DME_CONTROL 0x38ca 14120#define regDME9_DME_CONTROL_BASE_IDX 2 14121#define regDME9_DME_MEMORY_CONTROL 0x38cb 14122#define regDME9_DME_MEMORY_CONTROL_BASE_IDX 2 14123 14124 14125// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec 14126// base address: 0x1b634 14127#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd 14128#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 14129#define regVPG9_VPG_GENERIC_PACKET_DATA 0x38ce 14130#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 14131#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf 14132#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 14133#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 14134#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 14135#define regVPG9_VPG_GENERIC_STATUS 0x38d1 14136#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 2 14137#define regVPG9_VPG_MEM_PWR 0x38d2 14138#define regVPG9_VPG_MEM_PWR_BASE_IDX 2 14139#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 14140#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 14141#define regVPG9_VPG_ISRC1_2_DATA 0x38d4 14142#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 2 14143#define regVPG9_VPG_MPEG_INFO0 0x38d5 14144#define regVPG9_VPG_MPEG_INFO0_BASE_IDX 2 14145#define regVPG9_VPG_MPEG_INFO1 0x38d6 14146#define regVPG9_VPG_MPEG_INFO1_BASE_IDX 2 14147 14148 14149// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec 14150// base address: 0x1b664 14151#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 14152#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 14153#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da 14154#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 14155#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db 14156#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 14157#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc 14158#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 14159#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd 14160#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 14161#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de 14162#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 14163#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df 14164#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 14165#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 14166#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 14167#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 14168#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 14169#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 14170#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 14171#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 14172#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 14173#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 14174#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 14175#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 14176#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 14177#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 14178#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 14179#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 14180#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 14181#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 14182#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 14183#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 14184#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 14185#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea 14186#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 14187#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb 14188#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 14189#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec 14190#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 14191#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed 14192#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 14193#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee 14194#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 14195#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef 14196#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 14197#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 14198#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 14199#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 14200#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 14201#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 14202#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 14203#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 14204#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 14205#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 14206#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 14207#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 14208#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 14209#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 14210#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 14211#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 14212#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 14213#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 14214#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 14215#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 14216#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 14217#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa 14218#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 14219#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff 14220#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 14221#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 14222#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 14223#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 14224#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 14225#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 14226#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 14227#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 14228#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 14229#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 14230#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 14231#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 14232#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 14233#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 14234#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 14235#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3907 14236#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 14237#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3908 14238#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 14239 14240 14241// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec 14242// base address: 0x1ad5c 14243#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 14244#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 14245#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 14246#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 14247 14248 14249// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec 14250// base address: 0x1ae00 14251#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 14252#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 14253#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 14254#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 14255#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 14256#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 14257#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 14258#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 14259#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 14260#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 14261#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 14262#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 14263#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 14264#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 14265#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb 14266#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 14267#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc 14268#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 14269#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd 14270#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 14271#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce 14272#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 14273#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 14274#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 14275#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 14276#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 14277#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 14278#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 14279#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 14280#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 14281#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 14282#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 14283#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 14284#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 14285#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 14286#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 14287#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da 14288#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 14289#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db 14290#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 14291#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc 14292#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 14293#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd 14294#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 14295#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de 14296#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 14297#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df 14298#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 14299#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 14300#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 14301#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 14302#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 14303#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 14304#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 14305#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 14306#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 14307#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 14308#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 14309#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 14310#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 14311#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 14312#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 14313#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 14314#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 14315#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 14316#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 14317#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea 14318#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 14319#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36eb 14320#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 14321#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ec 14322#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 14323#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36ed 14324#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 14325#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36ee 14326#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 14327 14328 14329// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec 14330// base address: 0x1b0ac 14331#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b 14332#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 14333#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c 14334#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 14335 14336 14337// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec 14338// base address: 0x1b150 14339#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 14340#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 14341#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 14342#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 14343#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 14344#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 14345#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 14346#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 14347#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a 14348#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 14349#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b 14350#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 14351#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c 14352#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 14353#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f 14354#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 14355#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 14356#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 14357#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 14358#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 14359#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 14360#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 14361#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 14362#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 14363#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 14364#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 14365#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 14366#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 14367#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 14368#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 14369#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab 14370#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 14371#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac 14372#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 14373#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad 14374#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 14375#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae 14376#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 14377#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af 14378#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 14379#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 14380#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 14381#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 14382#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 14383#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 14384#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 14385#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 14386#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 14387#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 14388#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 14389#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 14390#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 14391#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 14392#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 14393#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 14394#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 14395#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 14396#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 14397#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 14398#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 14399#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba 14400#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 14401#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb 14402#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 14403#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc 14404#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 14405#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be 14406#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 14407#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37bf 14408#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 14409#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c0 14410#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 14411#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c1 14412#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 14413#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c2 14414#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 14415 14416 14417// addressBlock: dce_dc_dchvm_hvm_dispdec 14418// base address: 0x0 14419#define regDCHVM_CTRL0 0x3603 14420#define regDCHVM_CTRL0_BASE_IDX 2 14421#define regDCHVM_CTRL1 0x3604 14422#define regDCHVM_CTRL1_BASE_IDX 2 14423#define regDCHVM_CLK_CTRL 0x3605 14424#define regDCHVM_CLK_CTRL_BASE_IDX 2 14425#define regDCHVM_MEM_CTRL 0x3606 14426#define regDCHVM_MEM_CTRL_BASE_IDX 2 14427#define regDCHVM_RIOMMU_CTRL0 0x3607 14428#define regDCHVM_RIOMMU_CTRL0_BASE_IDX 2 14429#define regDCHVM_RIOMMU_STAT0 0x3608 14430#define regDCHVM_RIOMMU_STAT0_BASE_IDX 2 14431 14432 14433// addressBlock: vga_vgaseqind 14434// base address: 0x0 14435#define ixSEQ00 0x0000 14436#define ixSEQ01 0x0001 14437#define ixSEQ02 0x0002 14438#define ixSEQ03 0x0003 14439#define ixSEQ04 0x0004 14440 14441 14442// addressBlock: vga_vgacrtind 14443// base address: 0x0 14444#define ixCRT00 0x0000 14445#define ixCRT01 0x0001 14446#define ixCRT02 0x0002 14447#define ixCRT03 0x0003 14448#define ixCRT04 0x0004 14449#define ixCRT05 0x0005 14450#define ixCRT06 0x0006 14451#define ixCRT07 0x0007 14452#define ixCRT08 0x0008 14453#define ixCRT09 0x0009 14454#define ixCRT0A 0x000a 14455#define ixCRT0B 0x000b 14456#define ixCRT0C 0x000c 14457#define ixCRT0D 0x000d 14458#define ixCRT0E 0x000e 14459#define ixCRT0F 0x000f 14460#define ixCRT10 0x0010 14461#define ixCRT11 0x0011 14462#define ixCRT12 0x0012 14463#define ixCRT13 0x0013 14464#define ixCRT14 0x0014 14465#define ixCRT15 0x0015 14466#define ixCRT16 0x0016 14467#define ixCRT17 0x0017 14468#define ixCRT18 0x0018 14469#define ixCRT1E 0x001e 14470#define ixCRT1F 0x001f 14471#define ixCRT22 0x0022 14472 14473 14474// addressBlock: vga_vgagrphind 14475// base address: 0x0 14476#define ixGRA00 0x0000 14477#define ixGRA01 0x0001 14478#define ixGRA02 0x0002 14479#define ixGRA03 0x0003 14480#define ixGRA04 0x0004 14481#define ixGRA05 0x0005 14482#define ixGRA06 0x0006 14483#define ixGRA07 0x0007 14484#define ixGRA08 0x0008 14485 14486 14487// addressBlock: vga_vgaattrind 14488// base address: 0x0 14489#define ixATTR00 0x0000 14490#define ixATTR01 0x0001 14491#define ixATTR02 0x0002 14492#define ixATTR03 0x0003 14493#define ixATTR04 0x0004 14494#define ixATTR05 0x0005 14495#define ixATTR06 0x0006 14496#define ixATTR07 0x0007 14497#define ixATTR08 0x0008 14498#define ixATTR09 0x0009 14499#define ixATTR0A 0x000a 14500#define ixATTR0B 0x000b 14501#define ixATTR0C 0x000c 14502#define ixATTR0D 0x000d 14503#define ixATTR0E 0x000e 14504#define ixATTR0F 0x000f 14505#define ixATTR10 0x0010 14506#define ixATTR11 0x0011 14507#define ixATTR12 0x0012 14508#define ixATTR13 0x0013 14509#define ixATTR14 0x0014 14510 14511 14512// addressBlock: azendpoint_f2codecind 14513// base address: 0x0 14514#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 14515#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 14516#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 14517#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 14518#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 14519#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 14520#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 14521#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 14522#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 14523#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 14524#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 14525#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 14526#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 14527#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 14528#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 14529#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 14530#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 14531#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 14532#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 14533#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 14534#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 14535#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 14536#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 14537#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 14538#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 14539#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 14540#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 14541#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 14542#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 14543#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 14544#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 14545#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 14546#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 14547#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 14548#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 14549#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 14550#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 14551#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 14552#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 14553#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 14554#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 14555#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 14556#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 14557#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 14558#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 14559#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 14560#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 14561#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 14562#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 14563#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 14564#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 14565#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 14566#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 14567#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 14568#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 14569#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 14570#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 14571#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 14572 14573 14574// addressBlock: azendpoint_descriptorind 14575// base address: 0x0 14576#define ixAUDIO_DESCRIPTOR0 0x0001 14577#define ixAUDIO_DESCRIPTOR1 0x0002 14578#define ixAUDIO_DESCRIPTOR2 0x0003 14579#define ixAUDIO_DESCRIPTOR3 0x0004 14580#define ixAUDIO_DESCRIPTOR4 0x0005 14581#define ixAUDIO_DESCRIPTOR5 0x0006 14582#define ixAUDIO_DESCRIPTOR6 0x0007 14583#define ixAUDIO_DESCRIPTOR7 0x0008 14584#define ixAUDIO_DESCRIPTOR8 0x0009 14585#define ixAUDIO_DESCRIPTOR9 0x000a 14586#define ixAUDIO_DESCRIPTOR10 0x000b 14587#define ixAUDIO_DESCRIPTOR11 0x000c 14588#define ixAUDIO_DESCRIPTOR12 0x000d 14589#define ixAUDIO_DESCRIPTOR13 0x000e 14590 14591 14592// addressBlock: azendpoint_sinkinfoind 14593// base address: 0x0 14594#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 14595#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 14596#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 14597#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 14598#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 14599#define ixSINK_DESCRIPTION0 0x0005 14600#define ixSINK_DESCRIPTION1 0x0006 14601#define ixSINK_DESCRIPTION2 0x0007 14602#define ixSINK_DESCRIPTION3 0x0008 14603#define ixSINK_DESCRIPTION4 0x0009 14604#define ixSINK_DESCRIPTION5 0x000a 14605#define ixSINK_DESCRIPTION6 0x000b 14606#define ixSINK_DESCRIPTION7 0x000c 14607#define ixSINK_DESCRIPTION8 0x000d 14608#define ixSINK_DESCRIPTION9 0x000e 14609#define ixSINK_DESCRIPTION10 0x000f 14610#define ixSINK_DESCRIPTION11 0x0010 14611#define ixSINK_DESCRIPTION12 0x0011 14612#define ixSINK_DESCRIPTION13 0x0012 14613#define ixSINK_DESCRIPTION14 0x0013 14614#define ixSINK_DESCRIPTION15 0x0014 14615#define ixSINK_DESCRIPTION16 0x0015 14616#define ixSINK_DESCRIPTION17 0x0016 14617 14618 14619// addressBlock: azf0controller_azinputcrc0resultind 14620// base address: 0x0 14621#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 14622#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 14623#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 14624#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 14625#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 14626#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 14627#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 14628#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 14629 14630 14631// addressBlock: azf0controller_azinputcrc1resultind 14632// base address: 0x0 14633#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 14634#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 14635#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 14636#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 14637#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 14638#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 14639#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 14640#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 14641 14642 14643// addressBlock: azf0controller_azcrc0resultind 14644// base address: 0x0 14645#define ixAZALIA_CRC0_CHANNEL0 0x0000 14646#define ixAZALIA_CRC0_CHANNEL1 0x0001 14647#define ixAZALIA_CRC0_CHANNEL2 0x0002 14648#define ixAZALIA_CRC0_CHANNEL3 0x0003 14649#define ixAZALIA_CRC0_CHANNEL4 0x0004 14650#define ixAZALIA_CRC0_CHANNEL5 0x0005 14651#define ixAZALIA_CRC0_CHANNEL6 0x0006 14652#define ixAZALIA_CRC0_CHANNEL7 0x0007 14653 14654 14655// addressBlock: azf0controller_azcrc1resultind 14656// base address: 0x0 14657#define ixAZALIA_CRC1_CHANNEL0 0x0000 14658#define ixAZALIA_CRC1_CHANNEL1 0x0001 14659#define ixAZALIA_CRC1_CHANNEL2 0x0002 14660#define ixAZALIA_CRC1_CHANNEL3 0x0003 14661#define ixAZALIA_CRC1_CHANNEL4 0x0004 14662#define ixAZALIA_CRC1_CHANNEL5 0x0005 14663#define ixAZALIA_CRC1_CHANNEL6 0x0006 14664#define ixAZALIA_CRC1_CHANNEL7 0x0007 14665 14666 14667// addressBlock: azinputendpoint_f2codecind 14668// base address: 0x0 14669#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 14670#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 14671#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 14672#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 14673#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 14674#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 14675#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 14676#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 14677#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 14678#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 14679#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 14680#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 14681#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 14682#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 14683#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 14684#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 14685#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 14686#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 14687#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 14688#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 14689#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 14690#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 14691#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 14692#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 14693#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 14694#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 14695#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 14696#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 14697#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 14698#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 14699#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 14700#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 14701 14702 14703// addressBlock: azroot_f2codecind 14704// base address: 0x0 14705#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 14706#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 14707#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 14708#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 14709#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 14710#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 14711#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 14712#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 14713#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 14714#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 14715#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 14716#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 14717#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 14718#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 14719#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 14720 14721 14722// addressBlock: azf0stream0_streamind 14723// base address: 0x0 14724#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 14725#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14726#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14727#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14728#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14729 14730 14731// addressBlock: azf0stream1_streamind 14732// base address: 0x0 14733#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 14734#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14735#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14736#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14737#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14738 14739 14740// addressBlock: azf0stream2_streamind 14741// base address: 0x0 14742#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 14743#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14744#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14745#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14746#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14747 14748 14749// addressBlock: azf0stream3_streamind 14750// base address: 0x0 14751#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 14752#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14753#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14754#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14755#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14756 14757 14758// addressBlock: azf0stream4_streamind 14759// base address: 0x0 14760#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 14761#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14762#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14763#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14764#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14765 14766 14767// addressBlock: azf0stream5_streamind 14768// base address: 0x0 14769#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 14770#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14771#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14772#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14773#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14774 14775 14776// addressBlock: azf0stream6_streamind 14777// base address: 0x0 14778#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 14779#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14780#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14781#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14782#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14783 14784 14785// addressBlock: azf0stream7_streamind 14786// base address: 0x0 14787#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 14788#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14789#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14790#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14791#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14792 14793 14794// addressBlock: azf0stream8_streamind 14795// base address: 0x0 14796#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 14797#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14798#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14799#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14800#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14801 14802 14803// addressBlock: azf0stream9_streamind 14804// base address: 0x0 14805#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 14806#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14807#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14808#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14809#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14810 14811 14812// addressBlock: azf0stream10_streamind 14813// base address: 0x0 14814#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 14815#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14816#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14817#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14818#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14819 14820 14821// addressBlock: azf0stream11_streamind 14822// base address: 0x0 14823#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 14824#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14825#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14826#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14827#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14828 14829 14830// addressBlock: azf0stream12_streamind 14831// base address: 0x0 14832#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 14833#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14834#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14835#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14836#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14837 14838 14839// addressBlock: azf0stream13_streamind 14840// base address: 0x0 14841#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 14842#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14843#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14844#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14845#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14846 14847 14848// addressBlock: azf0stream14_streamind 14849// base address: 0x0 14850#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 14851#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14852#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14853#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14854#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14855 14856 14857// addressBlock: azf0stream15_streamind 14858// base address: 0x0 14859#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 14860#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14861#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14862#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14863#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14864 14865 14866// addressBlock: azf0endpoint0_endpointind 14867// base address: 0x0 14868#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14869#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14870#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14871#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14872#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14873#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14874#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14875#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14876#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14877#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14878#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14879#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14880#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14881#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14882#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14883#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14884#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14885#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14886#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14887#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14888#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14889#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14890#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14891#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14892#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14893#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14894#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14895#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14896#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14897#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14898#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14899#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14900#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14901#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14902#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14903#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14904#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14905#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14906#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14907#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14908#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14909#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14910#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14911#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14912#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14913#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14914#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14915#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14916#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14917#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14918#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14919#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14920#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14921#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14922#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14923#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14924#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14925#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14926#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14927#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14928#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14929#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14930#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14931#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14932#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14933#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14934#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14935#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14936#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14937#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14938#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14939 14940 14941// addressBlock: azf0endpoint1_endpointind 14942// base address: 0x0 14943#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14944#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14945#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14946#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14947#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14948#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14949#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14950#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14951#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14952#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14953#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14954#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14955#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14956#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14957#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14958#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14959#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14960#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14961#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14962#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14963#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14964#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14965#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14966#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14967#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14968#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14969#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14970#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14971#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14972#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14973#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14974#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14975#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14976#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14977#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14978#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14979#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14980#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14981#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14982#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14983#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14984#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14985#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14986#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14987#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14988#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14989#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14990#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14991#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14992#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14993#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14994#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14995#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14996#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14997#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14998#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14999#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15000#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15001#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15002#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15003#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15004#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15005#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15006#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15007#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15008#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15009#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15010#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15011#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15012#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15013#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15014 15015 15016// addressBlock: azf0endpoint2_endpointind 15017// base address: 0x0 15018#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15019#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15020#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15021#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15022#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15023#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15024#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 15025#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 15026#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 15027#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 15028#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 15029#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 15030#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15031#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 15032#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15033#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 15034#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 15035#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 15036#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 15037#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 15038#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 15039#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 15040#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 15041#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 15042#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 15043#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 15044#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 15045#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 15046#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 15047#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 15048#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 15049#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 15050#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15051#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 15052#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 15053#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 15054#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 15055#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 15056#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 15057#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 15058#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 15059#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 15060#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 15061#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 15062#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15063#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15064#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15065#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 15066#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 15067#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 15068#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 15069#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 15070#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 15071#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 15072#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 15073#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 15074#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15075#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15076#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15077#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15078#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15079#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15080#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15081#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15082#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15083#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15084#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15085#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15086#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15087#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15088#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15089 15090 15091// addressBlock: azf0endpoint3_endpointind 15092// base address: 0x0 15093#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15094#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15095#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15096#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15097#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15098#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15099#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 15100#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 15101#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 15102#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 15103#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 15104#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 15105#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15106#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 15107#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15108#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 15109#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 15110#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 15111#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 15112#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 15113#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 15114#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 15115#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 15116#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 15117#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 15118#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 15119#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 15120#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 15121#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 15122#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 15123#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 15124#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 15125#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15126#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 15127#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 15128#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 15129#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 15130#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 15131#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 15132#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 15133#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 15134#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 15135#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 15136#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 15137#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15138#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15139#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15140#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 15141#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 15142#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 15143#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 15144#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 15145#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 15146#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 15147#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 15148#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 15149#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15150#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15151#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15152#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15153#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15154#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15155#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15156#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15157#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15158#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15159#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15160#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15161#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15162#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15163#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15164 15165 15166// addressBlock: azf0endpoint4_endpointind 15167// base address: 0x0 15168#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15169#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15170#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15171#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15172#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15173#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15174#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 15175#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 15176#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 15177#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 15178#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 15179#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 15180#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15181#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 15182#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15183#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 15184#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 15185#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 15186#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 15187#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 15188#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 15189#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 15190#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 15191#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 15192#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 15193#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 15194#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 15195#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 15196#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 15197#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 15198#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 15199#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 15200#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15201#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 15202#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 15203#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 15204#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 15205#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 15206#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 15207#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 15208#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 15209#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 15210#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 15211#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 15212#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15213#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15214#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15215#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 15216#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 15217#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 15218#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 15219#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 15220#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 15221#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 15222#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 15223#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 15224#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15225#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15226#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15227#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15228#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15229#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15230#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15231#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15232#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15233#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15234#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15235#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15236#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15237#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15238#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15239 15240 15241// addressBlock: azf0endpoint5_endpointind 15242// base address: 0x0 15243#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15244#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15245#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15246#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15247#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15248#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15249#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 15250#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 15251#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 15252#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 15253#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 15254#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 15255#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15256#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 15257#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15258#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 15259#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 15260#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 15261#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 15262#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 15263#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 15264#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 15265#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 15266#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 15267#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 15268#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 15269#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 15270#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 15271#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 15272#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 15273#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 15274#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 15275#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15276#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 15277#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 15278#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 15279#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 15280#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 15281#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 15282#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 15283#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 15284#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 15285#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 15286#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 15287#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15288#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15289#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15290#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 15291#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 15292#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 15293#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 15294#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 15295#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 15296#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 15297#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 15298#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 15299#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15300#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15301#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15302#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15303#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15304#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15305#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15306#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15307#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15308#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15309#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15310#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15311#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15312#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15313#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15314 15315 15316// addressBlock: azf0endpoint6_endpointind 15317// base address: 0x0 15318#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15319#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15320#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15321#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15322#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15323#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15324#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 15325#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 15326#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 15327#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 15328#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 15329#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 15330#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15331#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 15332#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15333#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 15334#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 15335#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 15336#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 15337#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 15338#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 15339#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 15340#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 15341#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 15342#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 15343#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 15344#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 15345#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 15346#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 15347#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 15348#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 15349#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 15350#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15351#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 15352#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 15353#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 15354#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 15355#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 15356#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 15357#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 15358#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 15359#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 15360#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 15361#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 15362#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15363#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15364#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15365#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 15366#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 15367#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 15368#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 15369#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 15370#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 15371#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 15372#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 15373#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 15374#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15375#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15376#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15377#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15378#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15379#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15380#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15381#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15382#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15383#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15384#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15385#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15386#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15387#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15388#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15389 15390 15391// addressBlock: azf0endpoint7_endpointind 15392// base address: 0x0 15393#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15394#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15395#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15396#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15397#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15398#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15399#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 15400#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 15401#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 15402#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 15403#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 15404#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 15405#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15406#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 15407#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15408#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 15409#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 15410#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 15411#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 15412#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 15413#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 15414#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 15415#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 15416#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 15417#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 15418#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 15419#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 15420#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 15421#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 15422#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 15423#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 15424#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 15425#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15426#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 15427#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 15428#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 15429#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 15430#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 15431#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 15432#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 15433#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 15434#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 15435#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 15436#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 15437#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15438#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15439#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15440#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 15441#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 15442#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 15443#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 15444#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 15445#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 15446#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 15447#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 15448#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 15449#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15450#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15451#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15452#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15453#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15454#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15455#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15456#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15457#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15458#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15459#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15460#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15461#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15462#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15463#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15464 15465 15466// addressBlock: azf0inputendpoint0_inputendpointind 15467// base address: 0x0 15468#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15469#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15470#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15471#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15472#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15473#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15474#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15475#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15476#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15477#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15478#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15479#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15480#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15481#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15482#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15483#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15484#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15485#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15486#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15487#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15488#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15489#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15490#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15491 15492 15493// addressBlock: azf0inputendpoint1_inputendpointind 15494// base address: 0x0 15495#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15496#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15497#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15498#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15499#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15500#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15501#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15502#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15503#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15504#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15505#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15506#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15507#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15508#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15509#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15510#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15511#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15512#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15513#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15514#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15515#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15516#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15517#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15518 15519 15520// addressBlock: azf0inputendpoint2_inputendpointind 15521// base address: 0x0 15522#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15523#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15524#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15525#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15526#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15527#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15528#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15529#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15530#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15531#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15532#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15533#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15534#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15535#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15536#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15537#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15538#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15539#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15540#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15541#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15542#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15543#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15544#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15545 15546 15547// addressBlock: azf0inputendpoint3_inputendpointind 15548// base address: 0x0 15549#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15550#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15551#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15552#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15553#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15554#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15555#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15556#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15557#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15558#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15559#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15560#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15561#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15562#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15563#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15564#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15565#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15566#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15567#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15568#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15569#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15570#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15571#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15572 15573 15574// addressBlock: azf0inputendpoint4_inputendpointind 15575// base address: 0x0 15576#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15577#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15578#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15579#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15580#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15581#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15582#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15583#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15584#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15585#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15586#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15587#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15588#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15589#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15590#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15591#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15592#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15593#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15594#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15595#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15596#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15597#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15598#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15599 15600 15601// addressBlock: azf0inputendpoint5_inputendpointind 15602// base address: 0x0 15603#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15604#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15605#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15606#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15607#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15608#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15609#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15610#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15611#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15612#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15613#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15614#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15615#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15616#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15617#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15618#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15619#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15620#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15621#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15622#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15623#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15624#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15625#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15626 15627 15628// addressBlock: azf0inputendpoint6_inputendpointind 15629// base address: 0x0 15630#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15631#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15632#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15633#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15634#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15635#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15636#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15637#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15638#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15639#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15640#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15641#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15642#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15643#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15644#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15645#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15646#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15647#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15648#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15649#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15650#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15651#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15652#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15653 15654 15655// addressBlock: azf0inputendpoint7_inputendpointind 15656// base address: 0x0 15657#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15658#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15659#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15660#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15661#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15662#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15663#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15664#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15665#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15666#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15667#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15668#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15669#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15670#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15671#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15672#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15673#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15674#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15675#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15676#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15677#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15678#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15679#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15680 15681 15682#endif 15683