dcn_3_1_5_offset.h revision 1.1
1/* 2 * Copyright (C) 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _dcn_3_1_5_OFFSET_HEADER 22#define _dcn_3_1_5_OFFSET_HEADER 23 24 25 26// addressBlock: dce_dc_dccg_dccg_dfs_dispdec 27// base address: 0x0 28#define regDENTIST_DISPCLK_CNTL 0x0064 29#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 30 31 32// addressBlock: dce_dc_dccg_dccg_dispdec 33// base address: 0x0 34#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 35#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 36#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 37#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 38#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 39#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 40#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 41#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 42#define regDP_DTO_DBUF_EN 0x0044 43#define regDP_DTO_DBUF_EN_BASE_IDX 1 44#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 45#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 46#define regDCCG_GATE_DISABLE_CNTL4 0x0049 47#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 48#define regDPSTREAMCLK_CNTL 0x004a 49#define regDPSTREAMCLK_CNTL_BASE_IDX 1 50#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b 51#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 52#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c 53#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 54#define regDCCG_PERFMON_CNTL2 0x004e 55#define regDCCG_PERFMON_CNTL2_BASE_IDX 1 56#define regDCCG_DS_DTO_INCR 0x0053 57#define regDCCG_DS_DTO_INCR_BASE_IDX 1 58#define regDCCG_DS_DTO_MODULO 0x0054 59#define regDCCG_DS_DTO_MODULO_BASE_IDX 1 60#define regDCCG_DS_CNTL 0x0055 61#define regDCCG_DS_CNTL_BASE_IDX 1 62#define regDCCG_DS_HW_CAL_INTERVAL 0x0056 63#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 64#define regDPREFCLK_CNTL 0x0058 65#define regDPREFCLK_CNTL_BASE_IDX 1 66#define regDCE_VERSION 0x005e 67#define regDCE_VERSION_BASE_IDX 1 68#define regDCCG_GTC_CNTL 0x0060 69#define regDCCG_GTC_CNTL_BASE_IDX 1 70#define regDCCG_GTC_DTO_INCR 0x0061 71#define regDCCG_GTC_DTO_INCR_BASE_IDX 1 72#define regDCCG_GTC_DTO_MODULO 0x0062 73#define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 74#define regDCCG_GTC_CURRENT 0x0063 75#define regDCCG_GTC_CURRENT_BASE_IDX 1 76#define regSYMCLK32_SE_CNTL 0x0065 77#define regSYMCLK32_SE_CNTL_BASE_IDX 1 78#define regSYMCLK32_LE_CNTL 0x0066 79#define regSYMCLK32_LE_CNTL_BASE_IDX 1 80#define regDSCCLK0_DTO_PARAM 0x006c 81#define regDSCCLK0_DTO_PARAM_BASE_IDX 1 82#define regDSCCLK1_DTO_PARAM 0x006d 83#define regDSCCLK1_DTO_PARAM_BASE_IDX 1 84#define regDSCCLK2_DTO_PARAM 0x006e 85#define regDSCCLK2_DTO_PARAM_BASE_IDX 1 86#define regMILLISECOND_TIME_BASE_DIV 0x0070 87#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 88#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 89#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 90#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 91#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 92#define regDCCG_PERFMON_CNTL 0x0073 93#define regDCCG_PERFMON_CNTL_BASE_IDX 1 94#define regDCCG_GATE_DISABLE_CNTL 0x0074 95#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 96#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 97#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 98#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 99#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 100#define regDCCG_CAC_STATUS 0x0077 101#define regDCCG_CAC_STATUS_BASE_IDX 1 102#define regMICROSECOND_TIME_BASE_DIV 0x007b 103#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 104#define regDCCG_GATE_DISABLE_CNTL2 0x007c 105#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 106#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d 107#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 108#define regDCCG_DISP_CNTL_REG 0x007f 109#define regDCCG_DISP_CNTL_REG_BASE_IDX 1 110#define regOTG0_PIXEL_RATE_CNTL 0x0080 111#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 112#define regDP_DTO0_PHASE 0x0081 113#define regDP_DTO0_PHASE_BASE_IDX 1 114#define regDP_DTO0_MODULO 0x0082 115#define regDP_DTO0_MODULO_BASE_IDX 1 116#define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 117#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 118#define regOTG1_PIXEL_RATE_CNTL 0x0084 119#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 120#define regDP_DTO1_PHASE 0x0085 121#define regDP_DTO1_PHASE_BASE_IDX 1 122#define regDP_DTO1_MODULO 0x0086 123#define regDP_DTO1_MODULO_BASE_IDX 1 124#define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 125#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 126#define regOTG2_PIXEL_RATE_CNTL 0x0088 127#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 128#define regDP_DTO2_PHASE 0x0089 129#define regDP_DTO2_PHASE_BASE_IDX 1 130#define regDP_DTO2_MODULO 0x008a 131#define regDP_DTO2_MODULO_BASE_IDX 1 132#define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b 133#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 134#define regOTG3_PIXEL_RATE_CNTL 0x008c 135#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 136#define regDP_DTO3_PHASE 0x008d 137#define regDP_DTO3_PHASE_BASE_IDX 1 138#define regDP_DTO3_MODULO 0x008e 139#define regDP_DTO3_MODULO_BASE_IDX 1 140#define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f 141#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 142#define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 143#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 144#define regDPPCLK0_DTO_PARAM 0x0099 145#define regDPPCLK0_DTO_PARAM_BASE_IDX 1 146#define regDPPCLK1_DTO_PARAM 0x009a 147#define regDPPCLK1_DTO_PARAM_BASE_IDX 1 148#define regDPPCLK2_DTO_PARAM 0x009b 149#define regDPPCLK2_DTO_PARAM_BASE_IDX 1 150#define regDPPCLK3_DTO_PARAM 0x009c 151#define regDPPCLK3_DTO_PARAM_BASE_IDX 1 152#define regDCCG_CAC_STATUS2 0x009f 153#define regDCCG_CAC_STATUS2_BASE_IDX 1 154#define regSYMCLKA_CLOCK_ENABLE 0x00a0 155#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 156#define regSYMCLKB_CLOCK_ENABLE 0x00a1 157#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 158#define regSYMCLKC_CLOCK_ENABLE 0x00a2 159#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 160#define regSYMCLKD_CLOCK_ENABLE 0x00a3 161#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 162#define regSYMCLKE_CLOCK_ENABLE 0x00a4 163#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 164#define regDCCG_SOFT_RESET 0x00a6 165#define regDCCG_SOFT_RESET_BASE_IDX 1 166#define regDSCCLK_DTO_CTRL 0x00a7 167#define regDSCCLK_DTO_CTRL_BASE_IDX 1 168#define regDCCG_AUDIO_DTO_SOURCE 0x00ab 169#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 170#define regDCCG_AUDIO_DTO0_PHASE 0x00ac 171#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 172#define regDCCG_AUDIO_DTO0_MODULE 0x00ad 173#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 174#define regDCCG_AUDIO_DTO1_PHASE 0x00ae 175#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 176#define regDCCG_AUDIO_DTO1_MODULE 0x00af 177#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 178#define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 179#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 180#define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 181#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 182#define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 183#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 184#define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 185#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 186#define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 187#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 188#define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 189#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 190#define regDPPCLK_DTO_CTRL 0x00b6 191#define regDPPCLK_DTO_CTRL_BASE_IDX 1 192#define regDCCG_VSYNC_CNT_CTRL 0x00b8 193#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 194#define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 195#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 196#define regFORCE_SYMCLK_DISABLE 0x00ba 197#define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 198#define regDCCG_TEST_CLK_SEL 0x00be 199#define regDCCG_TEST_CLK_SEL_BASE_IDX 1 200#define regDTBCLK_DTO0_PHASE 0x0018 201#define regDTBCLK_DTO0_PHASE_BASE_IDX 2 202#define regDTBCLK_DTO1_PHASE 0x0019 203#define regDTBCLK_DTO1_PHASE_BASE_IDX 2 204#define regDTBCLK_DTO2_PHASE 0x001a 205#define regDTBCLK_DTO2_PHASE_BASE_IDX 2 206#define regDTBCLK_DTO3_PHASE 0x001b 207#define regDTBCLK_DTO3_PHASE_BASE_IDX 2 208#define regDTBCLK_DTO0_MODULO 0x001f 209#define regDTBCLK_DTO0_MODULO_BASE_IDX 2 210#define regDTBCLK_DTO1_MODULO 0x0020 211#define regDTBCLK_DTO1_MODULO_BASE_IDX 2 212#define regDTBCLK_DTO2_MODULO 0x0021 213#define regDTBCLK_DTO2_MODULO_BASE_IDX 2 214#define regDTBCLK_DTO3_MODULO 0x0022 215#define regDTBCLK_DTO3_MODULO_BASE_IDX 2 216#define regPHYASYMCLK_CLOCK_CNTL 0x0052 217#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 218#define regPHYBSYMCLK_CLOCK_CNTL 0x0053 219#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 220#define regPHYCSYMCLK_CLOCK_CNTL 0x0054 221#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 222#define regPHYDSYMCLK_CLOCK_CNTL 0x0055 223#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 224#define regPHYESYMCLK_CLOCK_CNTL 0x0056 225#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 226#define regDCCG_GATE_DISABLE_CNTL3 0x005a 227#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 228#define regHDMISTREAMCLK0_DTO_PARAM 0x005b 229#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 230#define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 231#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 232#define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 233#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 234#define regDTBCLK_DTO_DBUF_EN 0x0063 235#define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 236 237 238// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec 239// base address: 0x0 240#define regDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 241#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 242#define regDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 243#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 244#define regDC_PERFMON0_PERFCOUNTER_STATE 0x0002 245#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 246#define regDC_PERFMON0_PERFMON_CNTL 0x0003 247#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 248#define regDC_PERFMON0_PERFMON_CNTL2 0x0004 249#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 250#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 251#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 252#define regDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 253#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 254#define regDC_PERFMON0_PERFMON_HI 0x0007 255#define regDC_PERFMON0_PERFMON_HI_BASE_IDX 2 256#define regDC_PERFMON0_PERFMON_LOW 0x0008 257#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 258 259 260// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec 261// base address: 0x30 262#define regDC_PERFMON1_PERFCOUNTER_CNTL 0x000c 263#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 264#define regDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d 265#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 266#define regDC_PERFMON1_PERFCOUNTER_STATE 0x000e 267#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 268#define regDC_PERFMON1_PERFMON_CNTL 0x000f 269#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 270#define regDC_PERFMON1_PERFMON_CNTL2 0x0010 271#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 272#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 273#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 274#define regDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 275#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 276#define regDC_PERFMON1_PERFMON_HI 0x0013 277#define regDC_PERFMON1_PERFMON_HI_BASE_IDX 2 278#define regDC_PERFMON1_PERFMON_LOW 0x0014 279#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 280 281 282// addressBlock: dce_dc_dmu_dmcu_dispdec 283// base address: 0x0 284#define regDMCU_CTRL 0x00da 285#define regDMCU_CTRL_BASE_IDX 2 286#define regDMCU_STATUS 0x00db 287#define regDMCU_STATUS_BASE_IDX 2 288#define regDMCU_PC_START_ADDR 0x00dc 289#define regDMCU_PC_START_ADDR_BASE_IDX 2 290#define regDMCU_FW_START_ADDR 0x00dd 291#define regDMCU_FW_START_ADDR_BASE_IDX 2 292#define regDMCU_FW_END_ADDR 0x00de 293#define regDMCU_FW_END_ADDR_BASE_IDX 2 294#define regDMCU_FW_ISR_START_ADDR 0x00df 295#define regDMCU_FW_ISR_START_ADDR_BASE_IDX 2 296#define regDMCU_FW_CS_HI 0x00e0 297#define regDMCU_FW_CS_HI_BASE_IDX 2 298#define regDMCU_FW_CS_LO 0x00e1 299#define regDMCU_FW_CS_LO_BASE_IDX 2 300#define regDMCU_RAM_ACCESS_CTRL 0x00e2 301#define regDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 302#define regDMCU_ERAM_WR_CTRL 0x00e3 303#define regDMCU_ERAM_WR_CTRL_BASE_IDX 2 304#define regDMCU_ERAM_WR_DATA 0x00e4 305#define regDMCU_ERAM_WR_DATA_BASE_IDX 2 306#define regDMCU_ERAM_RD_CTRL 0x00e5 307#define regDMCU_ERAM_RD_CTRL_BASE_IDX 2 308#define regDMCU_ERAM_RD_DATA 0x00e6 309#define regDMCU_ERAM_RD_DATA_BASE_IDX 2 310#define regDMCU_IRAM_WR_CTRL 0x00e7 311#define regDMCU_IRAM_WR_CTRL_BASE_IDX 2 312#define regDMCU_IRAM_WR_DATA 0x00e8 313#define regDMCU_IRAM_WR_DATA_BASE_IDX 2 314#define regDMCU_IRAM_RD_CTRL 0x00e9 315#define regDMCU_IRAM_RD_CTRL_BASE_IDX 2 316#define regDMCU_IRAM_RD_DATA 0x00ea 317#define regDMCU_IRAM_RD_DATA_BASE_IDX 2 318#define regDMCU_EVENT_TRIGGER 0x00eb 319#define regDMCU_EVENT_TRIGGER_BASE_IDX 2 320#define regDMCU_UC_INTERNAL_INT_STATUS 0x00ec 321#define regDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 322#define regDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed 323#define regDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 324#define regDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 325#define regDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 326#define regDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 327#define regDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 328#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 329#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 330#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 331#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 332#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 333#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 334#define regDC_DMCU_SCRATCH 0x00f5 335#define regDC_DMCU_SCRATCH_BASE_IDX 2 336#define regDMCU_INT_CNT 0x00f6 337#define regDMCU_INT_CNT_BASE_IDX 2 338#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 339#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 340#define regDMCU_UC_CLK_GATING_CNTL 0x00f8 341#define regDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 342#define regMASTER_COMM_DATA_REG1 0x00f9 343#define regMASTER_COMM_DATA_REG1_BASE_IDX 2 344#define regMASTER_COMM_DATA_REG2 0x00fa 345#define regMASTER_COMM_DATA_REG2_BASE_IDX 2 346#define regMASTER_COMM_DATA_REG3 0x00fb 347#define regMASTER_COMM_DATA_REG3_BASE_IDX 2 348#define regMASTER_COMM_CMD_REG 0x00fc 349#define regMASTER_COMM_CMD_REG_BASE_IDX 2 350#define regMASTER_COMM_CNTL_REG 0x00fd 351#define regMASTER_COMM_CNTL_REG_BASE_IDX 2 352#define regSLAVE_COMM_DATA_REG1 0x00fe 353#define regSLAVE_COMM_DATA_REG1_BASE_IDX 2 354#define regSLAVE_COMM_DATA_REG2 0x00ff 355#define regSLAVE_COMM_DATA_REG2_BASE_IDX 2 356#define regSLAVE_COMM_DATA_REG3 0x0100 357#define regSLAVE_COMM_DATA_REG3_BASE_IDX 2 358#define regSLAVE_COMM_CMD_REG 0x0101 359#define regSLAVE_COMM_CMD_REG_BASE_IDX 2 360#define regSLAVE_COMM_CNTL_REG 0x0102 361#define regSLAVE_COMM_CNTL_REG_BASE_IDX 2 362#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a 363#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 364#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b 365#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 366#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c 367#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 368#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d 369#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 370#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e 371#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 372#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f 373#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 374#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 375#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 376#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 377#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 378#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 379#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 380#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 381#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 382#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 383#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 384#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 385#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 386#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a 387#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 388#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b 389#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 390#define regDMCU_INT_CNT_CONTINUE 0x011c 391#define regDMCU_INT_CNT_CONTINUE_BASE_IDX 2 392#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d 393#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 394#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f 395#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 396#define regDMCU_INT_CNT_CONT2 0x0120 397#define regDMCU_INT_CNT_CONT2_BASE_IDX 2 398#define regDMCU_INT_CNT_CONT3 0x0121 399#define regDMCU_INT_CNT_CONT3_BASE_IDX 2 400 401 402// addressBlock: dce_dc_dmu_fgsec_dispdec 403// base address: 0x0 404#define regDMCUB_RBBMIF_SEC_CNTL 0x017a 405#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 406 407 408// addressBlock: dce_dc_dmu_rbbmif_dispdec 409// base address: 0x0 410#define regRBBMIF_TIMEOUT 0x017f 411#define regRBBMIF_TIMEOUT_BASE_IDX 2 412#define regRBBMIF_STATUS 0x0180 413#define regRBBMIF_STATUS_BASE_IDX 2 414#define regRBBMIF_STATUS_2 0x0181 415#define regRBBMIF_STATUS_2_BASE_IDX 2 416#define regRBBMIF_INT_STATUS 0x0182 417#define regRBBMIF_INT_STATUS_BASE_IDX 2 418#define regRBBMIF_TIMEOUT_DIS 0x0183 419#define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 420#define regRBBMIF_TIMEOUT_DIS_2 0x0184 421#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 422#define regRBBMIF_STATUS_FLAG 0x0185 423#define regRBBMIF_STATUS_FLAG_BASE_IDX 2 424 425 426// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec 427// base address: 0x2f8 428#define regDC_PERFMON2_PERFCOUNTER_CNTL 0x00be 429#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 430#define regDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf 431#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 432#define regDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 433#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 434#define regDC_PERFMON2_PERFMON_CNTL 0x00c1 435#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 436#define regDC_PERFMON2_PERFMON_CNTL2 0x00c2 437#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 438#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 439#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 440#define regDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 441#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 442#define regDC_PERFMON2_PERFMON_HI 0x00c5 443#define regDC_PERFMON2_PERFMON_HI_BASE_IDX 2 444#define regDC_PERFMON2_PERFMON_LOW 0x00c6 445#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 446 447 448// addressBlock: dce_dc_dmu_ihc_dispdec 449// base address: 0x0 450#define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 451#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 452#define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 453#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 454#define regDC_GPU_TIMER_READ 0x0128 455#define regDC_GPU_TIMER_READ_BASE_IDX 2 456#define regDC_GPU_TIMER_READ_CNTL 0x0129 457#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 458#define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 459#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 460#define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 461#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 462#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 463#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 464#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 465#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 466#define regDCCG_INTERRUPT_DEST 0x0148 467#define regDCCG_INTERRUPT_DEST_BASE_IDX 2 468#define regDMU_INTERRUPT_DEST 0x0149 469#define regDMU_INTERRUPT_DEST_BASE_IDX 2 470#define regDMU_INTERRUPT_DEST2 0x014a 471#define regDMU_INTERRUPT_DEST2_BASE_IDX 2 472#define regDCPG_INTERRUPT_DEST 0x014b 473#define regDCPG_INTERRUPT_DEST_BASE_IDX 2 474#define regDCPG_INTERRUPT_DEST2 0x014c 475#define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 476#define regMMHUBBUB_INTERRUPT_DEST 0x014d 477#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 478#define regWB_INTERRUPT_DEST 0x014e 479#define regWB_INTERRUPT_DEST_BASE_IDX 2 480#define regDCHUB_INTERRUPT_DEST 0x014f 481#define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 482#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 483#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 484#define regDCHUB_INTERRUPT_DEST2 0x0151 485#define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 486#define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 487#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 488#define regMPC_INTERRUPT_DEST 0x0153 489#define regMPC_INTERRUPT_DEST_BASE_IDX 2 490#define regOPP_INTERRUPT_DEST 0x0154 491#define regOPP_INTERRUPT_DEST_BASE_IDX 2 492#define regOPTC_INTERRUPT_DEST 0x0155 493#define regOPTC_INTERRUPT_DEST_BASE_IDX 2 494#define regOTG0_INTERRUPT_DEST 0x0156 495#define regOTG0_INTERRUPT_DEST_BASE_IDX 2 496#define regOTG1_INTERRUPT_DEST 0x0157 497#define regOTG1_INTERRUPT_DEST_BASE_IDX 2 498#define regOTG2_INTERRUPT_DEST 0x0158 499#define regOTG2_INTERRUPT_DEST_BASE_IDX 2 500#define regOTG3_INTERRUPT_DEST 0x0159 501#define regOTG3_INTERRUPT_DEST_BASE_IDX 2 502#define regOTG4_INTERRUPT_DEST 0x015a 503#define regOTG4_INTERRUPT_DEST_BASE_IDX 2 504#define regOTG5_INTERRUPT_DEST 0x015b 505#define regOTG5_INTERRUPT_DEST_BASE_IDX 2 506#define regDIG_INTERRUPT_DEST 0x015c 507#define regDIG_INTERRUPT_DEST_BASE_IDX 2 508#define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d 509#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 510#define regDIO_INTERRUPT_DEST 0x015f 511#define regDIO_INTERRUPT_DEST_BASE_IDX 2 512#define regDCIO_INTERRUPT_DEST 0x0160 513#define regDCIO_INTERRUPT_DEST_BASE_IDX 2 514#define regHPD_INTERRUPT_DEST 0x0161 515#define regHPD_INTERRUPT_DEST_BASE_IDX 2 516#define regAZ_INTERRUPT_DEST 0x0162 517#define regAZ_INTERRUPT_DEST_BASE_IDX 2 518#define regAUX_INTERRUPT_DEST 0x0163 519#define regAUX_INTERRUPT_DEST_BASE_IDX 2 520#define regDSC_INTERRUPT_DEST 0x0164 521#define regDSC_INTERRUPT_DEST_BASE_IDX 2 522#define regHPO_INTERRUPT_DEST 0x0165 523#define regHPO_INTERRUPT_DEST_BASE_IDX 2 524 525 526// addressBlock: dce_dc_dmu_dmu_misc_dispdec 527// base address: 0x0 528#define regCC_DC_PIPE_DIS 0x00ca 529#define regCC_DC_PIPE_DIS_BASE_IDX 2 530#define regDMU_CLK_CNTL 0x00cb 531#define regDMU_CLK_CNTL_BASE_IDX 2 532#define regDMU_MEM_PWR_CNTL 0x00cc 533#define regDMU_MEM_PWR_CNTL_BASE_IDX 2 534#define regDMCU_SMU_INTERRUPT_CNTL 0x00cd 535#define regDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 536#define regZSC_CNTL 0x00cf 537#define regZSC_CNTL_BASE_IDX 2 538#define regZSC_CNTL2 0x00d0 539#define regZSC_CNTL2_BASE_IDX 2 540#define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 541#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 542#define regZSC_STATUS 0x00d7 543#define regZSC_STATUS_BASE_IDX 2 544 545 546// addressBlock: dce_dc_dmu_dc_pg_dispdec 547// base address: 0x0 548#define regDOMAIN0_PG_CONFIG 0x0080 549#define regDOMAIN0_PG_CONFIG_BASE_IDX 2 550#define regDOMAIN0_PG_STATUS 0x0081 551#define regDOMAIN0_PG_STATUS_BASE_IDX 2 552#define regDOMAIN1_PG_CONFIG 0x0082 553#define regDOMAIN1_PG_CONFIG_BASE_IDX 2 554#define regDOMAIN1_PG_STATUS 0x0083 555#define regDOMAIN1_PG_STATUS_BASE_IDX 2 556#define regDOMAIN2_PG_CONFIG 0x0084 557#define regDOMAIN2_PG_CONFIG_BASE_IDX 2 558#define regDOMAIN2_PG_STATUS 0x0085 559#define regDOMAIN2_PG_STATUS_BASE_IDX 2 560#define regDOMAIN3_PG_CONFIG 0x0086 561#define regDOMAIN3_PG_CONFIG_BASE_IDX 2 562#define regDOMAIN3_PG_STATUS 0x0087 563#define regDOMAIN3_PG_STATUS_BASE_IDX 2 564#define regDOMAIN16_PG_CONFIG 0x0089 565#define regDOMAIN16_PG_CONFIG_BASE_IDX 2 566#define regDOMAIN16_PG_STATUS 0x008a 567#define regDOMAIN16_PG_STATUS_BASE_IDX 2 568#define regDOMAIN17_PG_CONFIG 0x008b 569#define regDOMAIN17_PG_CONFIG_BASE_IDX 2 570#define regDOMAIN17_PG_STATUS 0x008c 571#define regDOMAIN17_PG_STATUS_BASE_IDX 2 572#define regDOMAIN18_PG_CONFIG 0x008d 573#define regDOMAIN18_PG_CONFIG_BASE_IDX 2 574#define regDOMAIN18_PG_STATUS 0x008e 575#define regDOMAIN18_PG_STATUS_BASE_IDX 2 576#define regDC_IP_REQUEST_CNTL 0x0093 577#define regDC_IP_REQUEST_CNTL_BASE_IDX 2 578 579 580// addressBlock: dce_dc_dmu_dmcub_dispdec 581// base address: 0x0 582#define regDMCUB_REGION0_OFFSET 0x018e 583#define regDMCUB_REGION0_OFFSET_BASE_IDX 2 584#define regDMCUB_REGION0_OFFSET_HIGH 0x018f 585#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 586#define regDMCUB_REGION1_OFFSET 0x0190 587#define regDMCUB_REGION1_OFFSET_BASE_IDX 2 588#define regDMCUB_REGION1_OFFSET_HIGH 0x0191 589#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 590#define regDMCUB_REGION2_OFFSET 0x0192 591#define regDMCUB_REGION2_OFFSET_BASE_IDX 2 592#define regDMCUB_REGION2_OFFSET_HIGH 0x0193 593#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 594#define regDMCUB_REGION4_OFFSET 0x0196 595#define regDMCUB_REGION4_OFFSET_BASE_IDX 2 596#define regDMCUB_REGION4_OFFSET_HIGH 0x0197 597#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 598#define regDMCUB_REGION5_OFFSET 0x0198 599#define regDMCUB_REGION5_OFFSET_BASE_IDX 2 600#define regDMCUB_REGION5_OFFSET_HIGH 0x0199 601#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 602#define regDMCUB_REGION6_OFFSET 0x019a 603#define regDMCUB_REGION6_OFFSET_BASE_IDX 2 604#define regDMCUB_REGION6_OFFSET_HIGH 0x019b 605#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 606#define regDMCUB_REGION7_OFFSET 0x019c 607#define regDMCUB_REGION7_OFFSET_BASE_IDX 2 608#define regDMCUB_REGION7_OFFSET_HIGH 0x019d 609#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 610#define regDMCUB_REGION0_TOP_ADDRESS 0x019e 611#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 612#define regDMCUB_REGION1_TOP_ADDRESS 0x019f 613#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 614#define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 615#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 616#define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 617#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 618#define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 619#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 620#define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 621#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 622#define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 623#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 624#define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 625#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 626#define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 627#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 628#define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 629#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 630#define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 631#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 632#define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 633#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 634#define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa 635#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 636#define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab 637#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 638#define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac 639#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 640#define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad 641#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 642#define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae 643#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 644#define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af 645#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 646#define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 647#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 648#define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 649#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 650#define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 651#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 652#define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 653#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 654#define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 655#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 656#define regDMCUB_REGION3_CW0_OFFSET 0x01b5 657#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 658#define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 659#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 660#define regDMCUB_REGION3_CW1_OFFSET 0x01b7 661#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 662#define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 663#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 664#define regDMCUB_REGION3_CW2_OFFSET 0x01b9 665#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 666#define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba 667#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 668#define regDMCUB_REGION3_CW3_OFFSET 0x01bb 669#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 670#define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc 671#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 672#define regDMCUB_REGION3_CW4_OFFSET 0x01bd 673#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 674#define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be 675#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 676#define regDMCUB_REGION3_CW5_OFFSET 0x01bf 677#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 678#define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 679#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 680#define regDMCUB_REGION3_CW6_OFFSET 0x01c1 681#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 682#define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 683#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 684#define regDMCUB_REGION3_CW7_OFFSET 0x01c3 685#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 686#define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 687#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 688#define regDMCUB_INTERRUPT_ENABLE 0x01c5 689#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 690#define regDMCUB_INTERRUPT_ACK 0x01c6 691#define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 692#define regDMCUB_INTERRUPT_TYPE 0x01c8 693#define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 694#define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca 695#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 696#define regDMCUB_EXT_INTERRUPT_ACK 0x01cb 697#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 698#define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc 699#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 700#define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd 701#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 702#define regDMCUB_SEC_CNTL 0x01ce 703#define regDMCUB_SEC_CNTL_BASE_IDX 2 704#define regDMCUB_MEM_CNTL 0x01cf 705#define regDMCUB_MEM_CNTL_BASE_IDX 2 706#define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 707#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 708#define regDMCUB_INBOX0_SIZE 0x01d1 709#define regDMCUB_INBOX0_SIZE_BASE_IDX 2 710#define regDMCUB_INBOX0_WPTR 0x01d2 711#define regDMCUB_INBOX0_WPTR_BASE_IDX 2 712#define regDMCUB_INBOX0_RPTR 0x01d3 713#define regDMCUB_INBOX0_RPTR_BASE_IDX 2 714#define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 715#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 716#define regDMCUB_INBOX1_SIZE 0x01d5 717#define regDMCUB_INBOX1_SIZE_BASE_IDX 2 718#define regDMCUB_INBOX1_WPTR 0x01d6 719#define regDMCUB_INBOX1_WPTR_BASE_IDX 2 720#define regDMCUB_INBOX1_RPTR 0x01d7 721#define regDMCUB_INBOX1_RPTR_BASE_IDX 2 722#define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 723#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 724#define regDMCUB_OUTBOX0_SIZE 0x01d9 725#define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 726#define regDMCUB_OUTBOX0_WPTR 0x01da 727#define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 728#define regDMCUB_OUTBOX0_RPTR 0x01db 729#define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 730#define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc 731#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 732#define regDMCUB_OUTBOX1_SIZE 0x01dd 733#define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 734#define regDMCUB_OUTBOX1_WPTR 0x01de 735#define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 736#define regDMCUB_OUTBOX1_RPTR 0x01df 737#define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 738#define regDMCUB_TIMER_TRIGGER0 0x01e0 739#define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 740#define regDMCUB_TIMER_TRIGGER1 0x01e1 741#define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 742#define regDMCUB_TIMER_WINDOW 0x01e2 743#define regDMCUB_TIMER_WINDOW_BASE_IDX 2 744#define regDMCUB_SCRATCH0 0x01e3 745#define regDMCUB_SCRATCH0_BASE_IDX 2 746#define regDMCUB_SCRATCH1 0x01e4 747#define regDMCUB_SCRATCH1_BASE_IDX 2 748#define regDMCUB_SCRATCH2 0x01e5 749#define regDMCUB_SCRATCH2_BASE_IDX 2 750#define regDMCUB_SCRATCH3 0x01e6 751#define regDMCUB_SCRATCH3_BASE_IDX 2 752#define regDMCUB_SCRATCH4 0x01e7 753#define regDMCUB_SCRATCH4_BASE_IDX 2 754#define regDMCUB_SCRATCH5 0x01e8 755#define regDMCUB_SCRATCH5_BASE_IDX 2 756#define regDMCUB_SCRATCH6 0x01e9 757#define regDMCUB_SCRATCH6_BASE_IDX 2 758#define regDMCUB_SCRATCH7 0x01ea 759#define regDMCUB_SCRATCH7_BASE_IDX 2 760#define regDMCUB_SCRATCH8 0x01eb 761#define regDMCUB_SCRATCH8_BASE_IDX 2 762#define regDMCUB_SCRATCH9 0x01ec 763#define regDMCUB_SCRATCH9_BASE_IDX 2 764#define regDMCUB_SCRATCH10 0x01ed 765#define regDMCUB_SCRATCH10_BASE_IDX 2 766#define regDMCUB_SCRATCH11 0x01ee 767#define regDMCUB_SCRATCH11_BASE_IDX 2 768#define regDMCUB_SCRATCH12 0x01ef 769#define regDMCUB_SCRATCH12_BASE_IDX 2 770#define regDMCUB_SCRATCH13 0x01f0 771#define regDMCUB_SCRATCH13_BASE_IDX 2 772#define regDMCUB_SCRATCH14 0x01f1 773#define regDMCUB_SCRATCH14_BASE_IDX 2 774#define regDMCUB_SCRATCH15 0x01f2 775#define regDMCUB_SCRATCH15_BASE_IDX 2 776#define regDMCUB_CNTL 0x01f6 777#define regDMCUB_CNTL_BASE_IDX 2 778#define regDMCUB_GPINT_DATAIN0 0x01f7 779#define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 780#define regDMCUB_GPINT_DATAIN1 0x01f8 781#define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 782#define regDMCUB_GPINT_DATAOUT 0x01f9 783#define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 784#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa 785#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 786#define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb 787#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 788#define regDMCUB_MEM_PWR_CNTL 0x01fc 789#define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 790#define regDMCUB_TIMER_CURRENT 0x01fd 791#define regDMCUB_TIMER_CURRENT_BASE_IDX 2 792#define regDMCUB_PROC_ID 0x01ff 793#define regDMCUB_PROC_ID_BASE_IDX 2 794#define regDMCUB_CNTL2 0x0200 795#define regDMCUB_CNTL2_BASE_IDX 2 796 797 798// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec 799// base address: 0x0 800#define regDWB_ENABLE_CLK_CTRL 0x3228 801#define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 802#define regDWB_MEM_PWR_CTRL 0x3229 803#define regDWB_MEM_PWR_CTRL_BASE_IDX 2 804#define regFC_MODE_CTRL 0x322a 805#define regFC_MODE_CTRL_BASE_IDX 2 806#define regFC_FLOW_CTRL 0x322b 807#define regFC_FLOW_CTRL_BASE_IDX 2 808#define regFC_WINDOW_START 0x322c 809#define regFC_WINDOW_START_BASE_IDX 2 810#define regFC_WINDOW_SIZE 0x322d 811#define regFC_WINDOW_SIZE_BASE_IDX 2 812#define regFC_SOURCE_SIZE 0x322e 813#define regFC_SOURCE_SIZE_BASE_IDX 2 814#define regDWB_UPDATE_CTRL 0x322f 815#define regDWB_UPDATE_CTRL_BASE_IDX 2 816#define regDWB_CRC_CTRL 0x3230 817#define regDWB_CRC_CTRL_BASE_IDX 2 818#define regDWB_CRC_MASK_R_G 0x3231 819#define regDWB_CRC_MASK_R_G_BASE_IDX 2 820#define regDWB_CRC_MASK_B_A 0x3232 821#define regDWB_CRC_MASK_B_A_BASE_IDX 2 822#define regDWB_CRC_VAL_R_G 0x3233 823#define regDWB_CRC_VAL_R_G_BASE_IDX 2 824#define regDWB_CRC_VAL_B_A 0x3234 825#define regDWB_CRC_VAL_B_A_BASE_IDX 2 826#define regDWB_OUT_CTRL 0x3235 827#define regDWB_OUT_CTRL_BASE_IDX 2 828#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 829#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 830#define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 831#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 832#define regDWB_HOST_READ_CONTROL 0x3238 833#define regDWB_HOST_READ_CONTROL_BASE_IDX 2 834#define regDWB_OVERFLOW_STATUS 0x3239 835#define regDWB_OVERFLOW_STATUS_BASE_IDX 2 836#define regDWB_OVERFLOW_COUNTER 0x323a 837#define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 838#define regDWB_SOFT_RESET 0x323b 839#define regDWB_SOFT_RESET_BASE_IDX 2 840#define regDWB_DEBUG_CTRL 0x323c 841#define regDWB_DEBUG_CTRL_BASE_IDX 2 842 843 844// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec 845// base address: 0x0 846#define regDWB_HDR_MULT_COEF 0x3294 847#define regDWB_HDR_MULT_COEF_BASE_IDX 2 848#define regDWB_GAMUT_REMAP_MODE 0x3295 849#define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 850#define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 851#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 852#define regDWB_GAMUT_REMAPA_C11_C12 0x3297 853#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 854#define regDWB_GAMUT_REMAPA_C13_C14 0x3298 855#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 856#define regDWB_GAMUT_REMAPA_C21_C22 0x3299 857#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 858#define regDWB_GAMUT_REMAPA_C23_C24 0x329a 859#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 860#define regDWB_GAMUT_REMAPA_C31_C32 0x329b 861#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 862#define regDWB_GAMUT_REMAPA_C33_C34 0x329c 863#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 864#define regDWB_GAMUT_REMAPB_C11_C12 0x329d 865#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 866#define regDWB_GAMUT_REMAPB_C13_C14 0x329e 867#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 868#define regDWB_GAMUT_REMAPB_C21_C22 0x329f 869#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 870#define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 871#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 872#define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 873#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 874#define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 875#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 876#define regDWB_OGAM_CONTROL 0x32a3 877#define regDWB_OGAM_CONTROL_BASE_IDX 2 878#define regDWB_OGAM_LUT_INDEX 0x32a4 879#define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 880#define regDWB_OGAM_LUT_DATA 0x32a5 881#define regDWB_OGAM_LUT_DATA_BASE_IDX 2 882#define regDWB_OGAM_LUT_CONTROL 0x32a6 883#define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 884#define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 885#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 886#define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 887#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 888#define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 889#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 890#define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa 891#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 892#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab 893#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 894#define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac 895#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 896#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad 897#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 898#define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae 899#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 900#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af 901#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 902#define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 903#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 904#define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 905#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 906#define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 907#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 908#define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 909#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 910#define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 911#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 912#define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 913#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 914#define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 915#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 916#define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 917#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 918#define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 919#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 920#define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 921#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 922#define regDWB_OGAM_RAMA_REGION_2_3 0x32ba 923#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 924#define regDWB_OGAM_RAMA_REGION_4_5 0x32bb 925#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 926#define regDWB_OGAM_RAMA_REGION_6_7 0x32bc 927#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 928#define regDWB_OGAM_RAMA_REGION_8_9 0x32bd 929#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 930#define regDWB_OGAM_RAMA_REGION_10_11 0x32be 931#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 932#define regDWB_OGAM_RAMA_REGION_12_13 0x32bf 933#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 934#define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 935#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 936#define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 937#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 938#define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 939#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 940#define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 941#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 942#define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 943#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 944#define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 945#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 946#define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 947#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 948#define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 949#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 950#define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 951#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 952#define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 953#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 954#define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca 955#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 956#define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb 957#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 958#define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc 959#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 960#define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd 961#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 962#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce 963#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 964#define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf 965#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 966#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 967#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 968#define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 969#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 970#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 971#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 972#define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 973#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 974#define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 975#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 976#define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 977#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 978#define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 979#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 980#define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 981#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 982#define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 983#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 984#define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 985#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 986#define regDWB_OGAM_RAMB_OFFSET_G 0x32da 987#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 988#define regDWB_OGAM_RAMB_OFFSET_R 0x32db 989#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 990#define regDWB_OGAM_RAMB_REGION_0_1 0x32dc 991#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 992#define regDWB_OGAM_RAMB_REGION_2_3 0x32dd 993#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 994#define regDWB_OGAM_RAMB_REGION_4_5 0x32de 995#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 996#define regDWB_OGAM_RAMB_REGION_6_7 0x32df 997#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 998#define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 999#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 1000#define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 1001#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 1002#define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 1003#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 1004#define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 1005#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 1006#define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 1007#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 1008#define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 1009#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 1010#define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 1011#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 1012#define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 1013#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 1014#define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 1015#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 1016#define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 1017#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 1018#define regDWB_OGAM_RAMB_REGION_28_29 0x32ea 1019#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 1020#define regDWB_OGAM_RAMB_REGION_30_31 0x32eb 1021#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 1022#define regDWB_OGAM_RAMB_REGION_32_33 0x32ec 1023#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 1024 1025 1026// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec 1027// base address: 0xca20 1028#define regDC_PERFMON3_PERFCOUNTER_CNTL 0x3288 1029#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 1030#define regDC_PERFMON3_PERFCOUNTER_CNTL2 0x3289 1031#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 1032#define regDC_PERFMON3_PERFCOUNTER_STATE 0x328a 1033#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 1034#define regDC_PERFMON3_PERFMON_CNTL 0x328b 1035#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 1036#define regDC_PERFMON3_PERFMON_CNTL2 0x328c 1037#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 1038#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x328d 1039#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1040#define regDC_PERFMON3_PERFMON_CVALUE_LOW 0x328e 1041#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 1042#define regDC_PERFMON3_PERFMON_HI 0x328f 1043#define regDC_PERFMON3_PERFMON_HI_BASE_IDX 2 1044#define regDC_PERFMON3_PERFMON_LOW 0x3290 1045#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 1046 1047 1048// addressBlock: dce_dc_mmhubbub_vga_dispdec 1049// base address: 0x0 1050#define regVGA_MEM_WRITE_PAGE_ADDR 0x0000 1051#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 1052#define regVGA_MEM_READ_PAGE_ADDR 0x0001 1053#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 1054#define regVGA_RENDER_CONTROL 0x0000 1055#define regVGA_RENDER_CONTROL_BASE_IDX 1 1056#define regVGA_SEQUENCER_RESET_CONTROL 0x0001 1057#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 1058#define regVGA_MODE_CONTROL 0x0002 1059#define regVGA_MODE_CONTROL_BASE_IDX 1 1060#define regVGA_SURFACE_PITCH_SELECT 0x0003 1061#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 1062#define regVGA_MEMORY_BASE_ADDRESS 0x0004 1063#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 1064#define regVGA_TEST_DEBUG_INDEX 0x0005 1065#define regVGA_TEST_DEBUG_INDEX_BASE_IDX 1 1066#define regVGA_DISPBUF1_SURFACE_ADDR 0x0006 1067#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 1068#define regVGA_TEST_DEBUG_DATA 0x0007 1069#define regVGA_TEST_DEBUG_DATA_BASE_IDX 1 1070#define regVGA_DISPBUF2_SURFACE_ADDR 0x0008 1071#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 1072#define regVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 1073#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 1074#define regVGA_HDP_CONTROL 0x000a 1075#define regVGA_HDP_CONTROL_BASE_IDX 1 1076#define regVGA_CACHE_CONTROL 0x000b 1077#define regVGA_CACHE_CONTROL_BASE_IDX 1 1078#define regD1VGA_CONTROL 0x000c 1079#define regD1VGA_CONTROL_BASE_IDX 1 1080#define regVGA_SECURITY_LEVEL 0x000d 1081#define regVGA_SECURITY_LEVEL_BASE_IDX 1 1082#define regD2VGA_CONTROL 0x000e 1083#define regD2VGA_CONTROL_BASE_IDX 1 1084#define regVGA_HW_DEBUG 0x000f 1085#define regVGA_HW_DEBUG_BASE_IDX 1 1086#define regVGA_STATUS 0x0010 1087#define regVGA_STATUS_BASE_IDX 1 1088#define regVGA_STATUS_CLEAR 0x0012 1089#define regVGA_STATUS_CLEAR_BASE_IDX 1 1090#define regVGA_MAIN_CONTROL 0x0014 1091#define regVGA_MAIN_CONTROL_BASE_IDX 1 1092#define regVGA_TEST_CONTROL 0x0015 1093#define regVGA_TEST_CONTROL_BASE_IDX 1 1094#define regVGA_DEBUG_READBACK_INDEX 0x0016 1095#define regVGA_DEBUG_READBACK_INDEX_BASE_IDX 1 1096#define regVGA_DEBUG_READBACK_DATA 0x0017 1097#define regVGA_DEBUG_READBACK_DATA_BASE_IDX 1 1098#define regVGA_QOS_CTRL 0x0018 1099#define regVGA_QOS_CTRL_BASE_IDX 1 1100#define regCRTC8_IDX 0x002d 1101#define regCRTC8_IDX_BASE_IDX 1 1102#define regCRTC8_DATA 0x002d 1103#define regCRTC8_DATA_BASE_IDX 1 1104#define regGENFC_WT 0x002e 1105#define regGENFC_WT_BASE_IDX 1 1106#define regGENS1 0x002e 1107#define regGENS1_BASE_IDX 1 1108#define regATTRDW 0x0030 1109#define regATTRDW_BASE_IDX 1 1110#define regATTRX 0x0030 1111#define regATTRX_BASE_IDX 1 1112#define regATTRDR 0x0030 1113#define regATTRDR_BASE_IDX 1 1114#define regGENMO_WT 0x0030 1115#define regGENMO_WT_BASE_IDX 1 1116#define regGENS0 0x0030 1117#define regGENS0_BASE_IDX 1 1118#define regGENENB 0x0030 1119#define regGENENB_BASE_IDX 1 1120#define regSEQ8_IDX 0x0031 1121#define regSEQ8_IDX_BASE_IDX 1 1122#define regSEQ8_DATA 0x0031 1123#define regSEQ8_DATA_BASE_IDX 1 1124#define regDAC_MASK 0x0031 1125#define regDAC_MASK_BASE_IDX 1 1126#define regDAC_R_INDEX 0x0031 1127#define regDAC_R_INDEX_BASE_IDX 1 1128#define regDAC_W_INDEX 0x0032 1129#define regDAC_W_INDEX_BASE_IDX 1 1130#define regDAC_DATA 0x0032 1131#define regDAC_DATA_BASE_IDX 1 1132#define regGENFC_RD 0x0032 1133#define regGENFC_RD_BASE_IDX 1 1134#define regGENMO_RD 0x0033 1135#define regGENMO_RD_BASE_IDX 1 1136#define regGRPH8_IDX 0x0033 1137#define regGRPH8_IDX_BASE_IDX 1 1138#define regGRPH8_DATA 0x0033 1139#define regGRPH8_DATA_BASE_IDX 1 1140#define regCRTC8_IDX_1 0x0035 1141#define regCRTC8_IDX_1_BASE_IDX 1 1142#define regCRTC8_DATA_1 0x0035 1143#define regCRTC8_DATA_1_BASE_IDX 1 1144#define regGENFC_WT_1 0x0036 1145#define regGENFC_WT_1_BASE_IDX 1 1146#define regGENS1_1 0x0036 1147#define regGENS1_1_BASE_IDX 1 1148#define regD3VGA_CONTROL 0x0038 1149#define regD3VGA_CONTROL_BASE_IDX 1 1150#define regD4VGA_CONTROL 0x0039 1151#define regD4VGA_CONTROL_BASE_IDX 1 1152#define regD5VGA_CONTROL 0x003a 1153#define regD5VGA_CONTROL_BASE_IDX 1 1154#define regD6VGA_CONTROL 0x003b 1155#define regD6VGA_CONTROL_BASE_IDX 1 1156#define regVGA_SOURCE_SELECT 0x003c 1157#define regVGA_SOURCE_SELECT_BASE_IDX 1 1158 1159 1160// addressBlock: dce_dc_mmhubbub_vgaif_dispdec 1161// base address: 0x0 1162#define regMCIF_CONTROL 0x034a 1163#define regMCIF_CONTROL_BASE_IDX 2 1164#define regMCIF_WRITE_COMBINE_CONTROL 0x034b 1165#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 1166#define regMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e 1167#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1168#define regMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f 1169#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1170#define regMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 1171#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 1172 1173 1174// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec 1175// base address: 0x0 1176#define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 1177#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 1178#define regMCIF_WB_BUFMGR_STATUS 0x0274 1179#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 1180#define regMCIF_WB_BUF_PITCH 0x0275 1181#define regMCIF_WB_BUF_PITCH_BASE_IDX 2 1182#define regMCIF_WB_BUF_1_STATUS 0x0276 1183#define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 1184#define regMCIF_WB_BUF_1_STATUS2 0x0277 1185#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 1186#define regMCIF_WB_BUF_2_STATUS 0x0278 1187#define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 1188#define regMCIF_WB_BUF_2_STATUS2 0x0279 1189#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 1190#define regMCIF_WB_BUF_3_STATUS 0x027a 1191#define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 1192#define regMCIF_WB_BUF_3_STATUS2 0x027b 1193#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 1194#define regMCIF_WB_BUF_4_STATUS 0x027c 1195#define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 1196#define regMCIF_WB_BUF_4_STATUS2 0x027d 1197#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 1198#define regMCIF_WB_ARBITRATION_CONTROL 0x027e 1199#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 1200#define regMCIF_WB_SCLK_CHANGE 0x027f 1201#define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 1202#define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 1203#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 1204#define regMCIF_WB_TEST_DEBUG_DATA 0x0281 1205#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 1206#define regMCIF_WB_BUF_1_ADDR_Y 0x0282 1207#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 1208#define regMCIF_WB_BUF_1_ADDR_C 0x0284 1209#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 1210#define regMCIF_WB_BUF_2_ADDR_Y 0x0286 1211#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 1212#define regMCIF_WB_BUF_2_ADDR_C 0x0288 1213#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 1214#define regMCIF_WB_BUF_3_ADDR_Y 0x028a 1215#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 1216#define regMCIF_WB_BUF_3_ADDR_C 0x028c 1217#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 1218#define regMCIF_WB_BUF_4_ADDR_Y 0x028e 1219#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 1220#define regMCIF_WB_BUF_4_ADDR_C 0x0290 1221#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 1222#define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 1223#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 1224#define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 1225#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 1226#define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 1227#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 1228#define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 1229#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 1230#define regMULTI_LEVEL_QOS_CTRL 0x0297 1231#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 1232#define regMCIF_WB_BUF_LUMA_SIZE 0x0299 1233#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 1234#define regMCIF_WB_BUF_CHROMA_SIZE 0x029a 1235#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 1236#define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b 1237#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 1238#define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c 1239#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 1240#define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d 1241#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 1242#define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e 1243#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 1244#define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f 1245#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 1246#define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 1247#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 1248#define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 1249#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 1250#define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 1251#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 1252#define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 1253#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 1254#define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 1255#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 1256#define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 1257#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 1258#define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 1259#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 1260#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7 1261#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2 1262#define regMCIF_WB_VMID_CONTROL 0x02a8 1263#define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 1264#define regMCIF_WB_MIN_TTO 0x02a9 1265#define regMCIF_WB_MIN_TTO_BASE_IDX 2 1266 1267 1268// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec 1269// base address: 0xd48 1270#define regDC_PERFMON4_PERFCOUNTER_CNTL 0x0352 1271#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 1272#define regDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353 1273#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 1274#define regDC_PERFMON4_PERFCOUNTER_STATE 0x0354 1275#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 1276#define regDC_PERFMON4_PERFMON_CNTL 0x0355 1277#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 1278#define regDC_PERFMON4_PERFMON_CNTL2 0x0356 1279#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 1280#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357 1281#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1282#define regDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358 1283#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 1284#define regDC_PERFMON4_PERFMON_HI 0x0359 1285#define regDC_PERFMON4_PERFMON_HI_BASE_IDX 2 1286#define regDC_PERFMON4_PERFMON_LOW 0x035a 1287#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 1288 1289 1290// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec 1291// base address: 0x0 1292#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa 1293#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 1294#define regMCIF_WB_WATERMARK 0x02ab 1295#define regMCIF_WB_WATERMARK_BASE_IDX 2 1296#define regMMHUBBUB_WARMUP_CONFIG 0x02ac 1297#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 1298#define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad 1299#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 1300#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae 1301#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 1302#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af 1303#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 1304#define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 1305#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 1306#define regMMHUBBUB_MIN_TTO 0x02b1 1307#define regMMHUBBUB_MIN_TTO_BASE_IDX 2 1308#define regMMHUBBUB_CTRL 0x0333 1309#define regMMHUBBUB_CTRL_BASE_IDX 2 1310#define regWBIF_SMU_WM_CONTROL 0x0334 1311#define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 1312#define regWBIF0_MISC_CTRL 0x0335 1313#define regWBIF0_MISC_CTRL_BASE_IDX 2 1314#define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 1315#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1316#define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 1317#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1318#define regVGA_SRC_SPLIT_CNTL 0x033e 1319#define regVGA_SRC_SPLIT_CNTL_BASE_IDX 2 1320#define regMMHUBBUB_MEM_PWR_STATUS 0x033f 1321#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 1322#define regMMHUBBUB_MEM_PWR_CNTL 0x0340 1323#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 1324#define regMMHUBBUB_CLOCK_CNTL 0x0341 1325#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 1326#define regMMHUBBUB_SOFT_RESET 0x0342 1327#define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 1328#define regDMU_IF_ERR_STATUS 0x0346 1329#define regDMU_IF_ERR_STATUS_BASE_IDX 2 1330#define regMMHUBBUB_CLIENT_UNIT_ID 0x0347 1331#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 1332#define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0349 1333#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 1334 1335 1336// addressBlock: dce_dc_hda_azf0controller_dispdec 1337// base address: 0x0 1338#define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 1339#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 1340#define regAZALIA_AUDIO_DTO 0x03c3 1341#define regAZALIA_AUDIO_DTO_BASE_IDX 2 1342#define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 1343#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 1344#define regAZALIA_SOCCLK_CONTROL 0x03c5 1345#define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 1346#define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 1347#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 1348#define regAZALIA_DATA_DMA_CONTROL 0x03c7 1349#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 1350#define regAZALIA_BDL_DMA_CONTROL 0x03c8 1351#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 1352#define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 1353#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 1354#define regAZALIA_CORB_DMA_CONTROL 0x03ca 1355#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 1356#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 1357#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 1358#define regAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 1359#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 1360#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 1361#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 1362#define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 1363#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 1364#define regAZALIA_INPUT_CRC0_CONTROL1 0x03da 1365#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 1366#define regAZALIA_INPUT_CRC0_CONTROL2 0x03db 1367#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 1368#define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc 1369#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 1370#define regAZALIA_INPUT_CRC0_RESULT 0x03dd 1371#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 1372#define regAZALIA_INPUT_CRC1_CONTROL0 0x03de 1373#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 1374#define regAZALIA_INPUT_CRC1_CONTROL1 0x03df 1375#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 1376#define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 1377#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 1378#define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 1379#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 1380#define regAZALIA_INPUT_CRC1_RESULT 0x03e2 1381#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 1382#define regAZALIA_CRC0_CONTROL0 0x03e3 1383#define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 1384#define regAZALIA_CRC0_CONTROL1 0x03e4 1385#define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 1386#define regAZALIA_CRC0_CONTROL2 0x03e5 1387#define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 1388#define regAZALIA_CRC0_CONTROL3 0x03e6 1389#define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 1390#define regAZALIA_CRC0_RESULT 0x03e7 1391#define regAZALIA_CRC0_RESULT_BASE_IDX 2 1392#define regAZALIA_CRC1_CONTROL0 0x03e8 1393#define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 1394#define regAZALIA_CRC1_CONTROL1 0x03e9 1395#define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 1396#define regAZALIA_CRC1_CONTROL2 0x03ea 1397#define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 1398#define regAZALIA_CRC1_CONTROL3 0x03eb 1399#define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 1400#define regAZALIA_CRC1_RESULT 0x03ec 1401#define regAZALIA_CRC1_RESULT_BASE_IDX 2 1402#define regAZALIA_MEM_PWR_CTRL 0x03ee 1403#define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 1404#define regAZALIA_MEM_PWR_STATUS 0x03ef 1405#define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 1406 1407 1408// addressBlock: dce_dc_hda_azf0root_dispdec 1409// base address: 0x0 1410#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 1411#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 1412#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 1413#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 1414#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 1415#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 1416#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 1417#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 1418#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 1419#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 1420#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 1421#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 1422#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 1423#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 1424#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 1425#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 1426#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 1427#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 1428#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 1429#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 1430#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 1431#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 1432#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 1433#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 1434#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 1435#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1436#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 1437#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1438#define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 1439#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 1440#define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 1441#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 1442#define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 1443#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 1444#define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 1445#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 1446#define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 1447#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 1448#define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a 1449#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 1450#define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b 1451#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 1452#define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 1453#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1454#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 1455#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1456 1457 1458// addressBlock: dce_dc_hda_az_misc_dispdec 1459// base address: 0x0 1460#define regAZ_CLOCK_CNTL 0x0372 1461#define regAZ_CLOCK_CNTL_BASE_IDX 2 1462 1463 1464// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec 1465// base address: 0xde8 1466#define regDC_PERFMON5_PERFCOUNTER_CNTL 0x037a 1467#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 1468#define regDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b 1469#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 1470#define regDC_PERFMON5_PERFCOUNTER_STATE 0x037c 1471#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 1472#define regDC_PERFMON5_PERFMON_CNTL 0x037d 1473#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 1474#define regDC_PERFMON5_PERFMON_CNTL2 0x037e 1475#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 1476#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f 1477#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1478#define regDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380 1479#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 1480#define regDC_PERFMON5_PERFMON_HI 0x0381 1481#define regDC_PERFMON5_PERFMON_HI_BASE_IDX 2 1482#define regDC_PERFMON5_PERFMON_LOW 0x0382 1483#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 1484 1485 1486// addressBlock: dce_dc_hda_azf0stream0_dispdec 1487// base address: 0x0 1488#define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 1489#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 1490#define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 1491#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 1492 1493 1494// addressBlock: dce_dc_hda_azf0stream1_dispdec 1495// base address: 0x8 1496#define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 1497#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 1498#define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 1499#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 1500 1501 1502// addressBlock: dce_dc_hda_azf0stream2_dispdec 1503// base address: 0x10 1504#define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 1505#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 1506#define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 1507#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 1508 1509 1510// addressBlock: dce_dc_hda_azf0stream3_dispdec 1511// base address: 0x18 1512#define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 1513#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 1514#define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 1515#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 1516 1517 1518// addressBlock: dce_dc_hda_azf0stream4_dispdec 1519// base address: 0x20 1520#define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 1521#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 1522#define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 1523#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 1524 1525 1526// addressBlock: dce_dc_hda_azf0stream5_dispdec 1527// base address: 0x28 1528#define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 1529#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 1530#define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 1531#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 1532 1533 1534// addressBlock: dce_dc_hda_azf0stream6_dispdec 1535// base address: 0x30 1536#define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 1537#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 1538#define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 1539#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 1540 1541 1542// addressBlock: dce_dc_hda_azf0stream7_dispdec 1543// base address: 0x38 1544#define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 1545#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 1546#define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 1547#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 1548 1549 1550// addressBlock: dce_dc_hda_azf0stream8_dispdec 1551// base address: 0x320 1552#define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 1553#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 1554#define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 1555#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 1556 1557 1558// addressBlock: dce_dc_hda_azf0stream9_dispdec 1559// base address: 0x328 1560#define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 1561#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 1562#define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 1563#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 1564 1565 1566// addressBlock: dce_dc_hda_azf0stream10_dispdec 1567// base address: 0x330 1568#define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 1569#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 1570#define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 1571#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 1572 1573 1574// addressBlock: dce_dc_hda_azf0stream11_dispdec 1575// base address: 0x338 1576#define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 1577#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 1578#define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 1579#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 1580 1581 1582// addressBlock: dce_dc_hda_azf0stream12_dispdec 1583// base address: 0x340 1584#define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 1585#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 1586#define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 1587#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 1588 1589 1590// addressBlock: dce_dc_hda_azf0stream13_dispdec 1591// base address: 0x348 1592#define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 1593#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 1594#define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 1595#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 1596 1597 1598// addressBlock: dce_dc_hda_azf0stream14_dispdec 1599// base address: 0x350 1600#define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 1601#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 1602#define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 1603#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 1604 1605 1606// addressBlock: dce_dc_hda_azf0stream15_dispdec 1607// base address: 0x358 1608#define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 1609#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 1610#define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 1611#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 1612 1613 1614// addressBlock: dce_dc_hda_azf0endpoint0_dispdec 1615// base address: 0x0 1616#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 1617#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1618#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 1619#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1620 1621 1622// addressBlock: dce_dc_hda_azf0endpoint1_dispdec 1623// base address: 0x18 1624#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 1625#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1626#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 1627#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1628 1629 1630// addressBlock: dce_dc_hda_azf0endpoint2_dispdec 1631// base address: 0x30 1632#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 1633#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1634#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 1635#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1636 1637 1638// addressBlock: dce_dc_hda_azf0endpoint3_dispdec 1639// base address: 0x48 1640#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 1641#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1642#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 1643#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1644 1645 1646// addressBlock: dce_dc_hda_azf0endpoint4_dispdec 1647// base address: 0x60 1648#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 1649#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1650#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 1651#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1652 1653 1654// addressBlock: dce_dc_hda_azf0endpoint5_dispdec 1655// base address: 0x78 1656#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 1657#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1658#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 1659#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1660 1661 1662// addressBlock: dce_dc_hda_azf0endpoint6_dispdec 1663// base address: 0x90 1664#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 1665#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1666#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 1667#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1668 1669 1670// addressBlock: dce_dc_hda_azf0endpoint7_dispdec 1671// base address: 0xa8 1672#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 1673#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1674#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 1675#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1676 1677 1678// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec 1679// base address: 0x0 1680#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 1681#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1682#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 1683#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1684 1685 1686// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec 1687// base address: 0x10 1688#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 1689#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1690#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 1691#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1692 1693 1694// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec 1695// base address: 0x20 1696#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 1697#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1698#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 1699#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1700 1701 1702// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec 1703// base address: 0x30 1704#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 1705#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1706#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 1707#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1708 1709 1710// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec 1711// base address: 0x40 1712#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 1713#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1714#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 1715#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1716 1717 1718// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec 1719// base address: 0x50 1720#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 1721#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1722#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 1723#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1724 1725 1726// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec 1727// base address: 0x60 1728#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 1729#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1730#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 1731#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1732 1733 1734// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec 1735// base address: 0x70 1736#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 1737#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1738#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 1739#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1740 1741 1742// addressBlock: dce_dc_dchubbubl_hubbub_dispdec 1743// base address: 0x0 1744#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 1745#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 1746#define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa 1747#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 1748#define regDCHUBBUB_ARB_QOS_FORCE 0x04fb 1749#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 1750#define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc 1751#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 1752#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fd 1753#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 1754#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x04fe 1755#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 1756#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x04ff 1757#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 1758#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0x0500 1759#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX 2 1760#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0501 1761#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 1762#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0x0502 1763#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX 2 1764#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x0503 1765#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 1766#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0504 1767#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 1768#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0505 1769#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 1770#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0506 1771#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 1772#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0507 1773#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 1774#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0508 1775#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 1776#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0x0509 1777#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX 2 1778#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050a 1779#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 1780#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0x050b 1781#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX 2 1782#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x050c 1783#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 1784#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x050d 1785#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 1786#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x050e 1787#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 1788#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x050f 1789#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 1790#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0510 1791#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 1792#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0511 1793#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 1794#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0x0512 1795#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX 2 1796#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0513 1797#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 1798#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0x0514 1799#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX 2 1800#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0515 1801#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 1802#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0516 1803#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 1804#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0517 1805#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 1806#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 1807#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 1808#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 1809#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 1810#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a 1811#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 1812#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0x051b 1813#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX 2 1814#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051c 1815#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 1816#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0x051d 1817#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX 2 1818#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051e 1819#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 1820#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x051f 1821#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 1822#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0520 1823#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 1824#define regDCHUBBUB_ARB_HOSTVM_CNTL 0x0521 1825#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 1826#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0522 1827#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 1828#define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0523 1829#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 1830#define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0524 1831#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 1832#define regSURFACE_CHECK0_ADDRESS_LSB 0x0525 1833#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 1834#define regSURFACE_CHECK0_ADDRESS_MSB 0x0526 1835#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 1836#define regSURFACE_CHECK1_ADDRESS_LSB 0x0527 1837#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 1838#define regSURFACE_CHECK1_ADDRESS_MSB 0x0528 1839#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 1840#define regSURFACE_CHECK2_ADDRESS_LSB 0x0529 1841#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 1842#define regSURFACE_CHECK2_ADDRESS_MSB 0x052a 1843#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 1844#define regSURFACE_CHECK3_ADDRESS_LSB 0x052b 1845#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 1846#define regSURFACE_CHECK3_ADDRESS_MSB 0x052c 1847#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 1848#define regVTG0_CONTROL 0x052d 1849#define regVTG0_CONTROL_BASE_IDX 2 1850#define regVTG1_CONTROL 0x052e 1851#define regVTG1_CONTROL_BASE_IDX 2 1852#define regVTG2_CONTROL 0x052f 1853#define regVTG2_CONTROL_BASE_IDX 2 1854#define regVTG3_CONTROL 0x0530 1855#define regVTG3_CONTROL_BASE_IDX 2 1856#define regDCHUBBUB_SOFT_RESET 0x0531 1857#define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 1858#define regDCHUBBUB_CLOCK_CNTL 0x0532 1859#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 1860#define regDCFCLK_CNTL 0x0533 1861#define regDCFCLK_CNTL_BASE_IDX 2 1862#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0534 1863#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 1864#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0535 1865#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 1866#define regDCHUBBUB_VLINE_SNAPSHOT 0x0536 1867#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 1868#define regDCHUBBUB_CTRL_STATUS 0x0537 1869#define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 1870#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053d 1871#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 1872#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053e 1873#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 1874#define regFMON_CTRL 0x0540 1875#define regFMON_CTRL_BASE_IDX 2 1876#define regDCHUBBUB_TEST_DEBUG_INDEX 0x0541 1877#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 1878#define regDCHUBBUB_TEST_DEBUG_DATA 0x0542 1879#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 1880 1881 1882// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec 1883// base address: 0x0 1884#define regDCHUBBUB_SDPIF_CFG0 0x046f 1885#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 1886#define regDCHUBBUB_SDPIF_CFG1 0x0470 1887#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 1888#define regDCHUBBUB_SDPIF_CFG2 0x0471 1889#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 1890#define regVM_REQUEST_PHYSICAL 0x0472 1891#define regVM_REQUEST_PHYSICAL_BASE_IDX 2 1892#define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 1893#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 1894#define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 1895#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 1896#define regDCN_VM_FB_LOCATION_BASE 0x0475 1897#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 1898#define regDCN_VM_FB_LOCATION_TOP 0x0476 1899#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 1900#define regDCN_VM_FB_OFFSET 0x0477 1901#define regDCN_VM_FB_OFFSET_BASE_IDX 2 1902#define regDCN_VM_AGP_BOT 0x0478 1903#define regDCN_VM_AGP_BOT_BASE_IDX 2 1904#define regDCN_VM_AGP_TOP 0x0479 1905#define regDCN_VM_AGP_TOP_BASE_IDX 2 1906#define regDCN_VM_AGP_BASE 0x047a 1907#define regDCN_VM_AGP_BASE_BASE_IDX 2 1908#define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b 1909#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 1910#define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c 1911#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 1912#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d 1913#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 1914#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x047e 1915#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 1916#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x047f 1917#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 1918#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0483 1919#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 1920#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0484 1921#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 1922 1923 1924// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec 1925// base address: 0x0 1926#define regDCHUBBUB_RET_PATH_DCC_CFG 0x04af 1927#define regDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 1928#define regDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04b0 1929#define regDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 1930#define regDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04b1 1931#define regDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 1932#define regDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04b2 1933#define regDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 1934#define regDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04b3 1935#define regDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 1936#define regDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04b4 1937#define regDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 1938#define regDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04b5 1939#define regDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 1940#define regDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04b6 1941#define regDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 1942#define regDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04b7 1943#define regDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 1944#define regDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04b8 1945#define regDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 1946#define regDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04b9 1947#define regDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 1948#define regDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04ba 1949#define regDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 1950#define regDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04bb 1951#define regDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 1952#define regDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04bc 1953#define regDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 1954#define regDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04bd 1955#define regDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 1956#define regDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04be 1957#define regDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 1958#define regDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04bf 1959#define regDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 1960#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04c0 1961#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 1962#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04c1 1963#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 1964#define regDCHUBBUB_CRC_CTRL 0x04c2 1965#define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 1966#define regDCHUBBUB_CRC0_VAL_R_G 0x04c3 1967#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 1968#define regDCHUBBUB_CRC0_VAL_B_A 0x04c4 1969#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 1970#define regDCHUBBUB_CRC1_VAL_R_G 0x04c5 1971#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 1972#define regDCHUBBUB_CRC1_VAL_B_A 0x04c6 1973#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 1974#define regDCHUBBUB_DCC_STAT_CNTL 0x04c7 1975#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 1976#define regDCHUBBUB_DCC_STAT0 0x04c8 1977#define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 1978#define regDCHUBBUB_DCC_STAT1 0x04c9 1979#define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 1980#define regDCHUBBUB_DCC_STAT2 0x04ca 1981#define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 1982#define regDCHUBBUB_COMPBUF_CTRL 0x04cb 1983#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 1984#define regDCHUBBUB_DET0_CTRL 0x04cc 1985#define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 1986#define regDCHUBBUB_DET1_CTRL 0x04cd 1987#define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 1988#define regDCHUBBUB_DET2_CTRL 0x04ce 1989#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 1990#define regDCHUBBUB_DET3_CTRL 0x04cf 1991#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 1992#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04d1 1993#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 1994#define regCOMPBUF_MEM_PWR_CTRL_1 0x04d2 1995#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 1996#define regCOMPBUF_MEM_PWR_CTRL_2 0x04d3 1997#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 1998#define regDCHUBBUB_MEM_PWR_STATUS 0x04d4 1999#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 2000#define regCOMPBUF_RESERVED_SPACE 0x04d5 2001#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 2002 2003 2004// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec 2005// base address: 0x0 2006#define regDCN_VM_CONTEXT0_CNTL 0x0559 2007#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 2008#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a 2009#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2010#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b 2011#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2012#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c 2013#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2014#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d 2015#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2016#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e 2017#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2018#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f 2019#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2020#define regDCN_VM_CONTEXT1_CNTL 0x0560 2021#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 2022#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 2023#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2024#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 2025#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2026#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 2027#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2028#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 2029#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2030#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 2031#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2032#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 2033#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2034#define regDCN_VM_CONTEXT2_CNTL 0x0567 2035#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 2036#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 2037#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2038#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 2039#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2040#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a 2041#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2042#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b 2043#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2044#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c 2045#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2046#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d 2047#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2048#define regDCN_VM_CONTEXT3_CNTL 0x056e 2049#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 2050#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f 2051#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2052#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 2053#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2054#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 2055#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2056#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 2057#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2058#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 2059#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2060#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 2061#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2062#define regDCN_VM_CONTEXT4_CNTL 0x0575 2063#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 2064#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 2065#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2066#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 2067#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2068#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 2069#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2070#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 2071#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2072#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a 2073#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2074#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b 2075#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2076#define regDCN_VM_CONTEXT5_CNTL 0x057c 2077#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 2078#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d 2079#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2080#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e 2081#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2082#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f 2083#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2084#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 2085#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2086#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 2087#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2088#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 2089#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2090#define regDCN_VM_CONTEXT6_CNTL 0x0583 2091#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 2092#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 2093#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2094#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 2095#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2096#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 2097#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2098#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 2099#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2100#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 2101#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2102#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 2103#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2104#define regDCN_VM_CONTEXT7_CNTL 0x058a 2105#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 2106#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b 2107#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2108#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c 2109#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2110#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d 2111#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2112#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e 2113#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2114#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f 2115#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2116#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 2117#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2118#define regDCN_VM_CONTEXT8_CNTL 0x0591 2119#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 2120#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 2121#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2122#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 2123#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2124#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 2125#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2126#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 2127#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2128#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 2129#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2130#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 2131#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2132#define regDCN_VM_CONTEXT9_CNTL 0x0598 2133#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 2134#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 2135#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2136#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a 2137#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2138#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b 2139#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2140#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c 2141#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2142#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d 2143#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2144#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e 2145#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2146#define regDCN_VM_CONTEXT10_CNTL 0x059f 2147#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 2148#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 2149#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2150#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 2151#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2152#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 2153#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2154#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 2155#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2156#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 2157#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2158#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 2159#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2160#define regDCN_VM_CONTEXT11_CNTL 0x05a6 2161#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 2162#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 2163#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2164#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 2165#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2166#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 2167#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2168#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa 2169#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2170#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab 2171#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2172#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac 2173#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2174#define regDCN_VM_CONTEXT12_CNTL 0x05ad 2175#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 2176#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae 2177#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2178#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af 2179#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2180#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 2181#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2182#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 2183#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2184#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 2185#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2186#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 2187#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2188#define regDCN_VM_CONTEXT13_CNTL 0x05b4 2189#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 2190#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 2191#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2192#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 2193#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2194#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 2195#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2196#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 2197#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2198#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 2199#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2200#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba 2201#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2202#define regDCN_VM_CONTEXT14_CNTL 0x05bb 2203#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 2204#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc 2205#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2206#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd 2207#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2208#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be 2209#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2210#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf 2211#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2212#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 2213#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2214#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 2215#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2216#define regDCN_VM_CONTEXT15_CNTL 0x05c2 2217#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 2218#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 2219#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2220#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 2221#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2222#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 2223#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2224#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 2225#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2226#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 2227#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2228#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 2229#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2230#define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 2231#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 2232#define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca 2233#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 2234#define regDCN_VM_FAULT_CNTL 0x05cb 2235#define regDCN_VM_FAULT_CNTL_BASE_IDX 2 2236#define regDCN_VM_FAULT_STATUS 0x05cc 2237#define regDCN_VM_FAULT_STATUS_BASE_IDX 2 2238#define regDCN_VM_FAULT_ADDR_MSB 0x05cd 2239#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 2240#define regDCN_VM_FAULT_ADDR_LSB 0x05ce 2241#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 2242 2243 2244// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec 2245// base address: 0x1534 2246#define regDC_PERFMON6_PERFCOUNTER_CNTL 0x054d 2247#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 2248#define regDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e 2249#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 2250#define regDC_PERFMON6_PERFCOUNTER_STATE 0x054f 2251#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 2252#define regDC_PERFMON6_PERFMON_CNTL 0x0550 2253#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 2254#define regDC_PERFMON6_PERFMON_CNTL2 0x0551 2255#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 2256#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552 2257#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2258#define regDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553 2259#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 2260#define regDC_PERFMON6_PERFMON_HI 0x0554 2261#define regDC_PERFMON6_PERFMON_HI_BASE_IDX 2 2262#define regDC_PERFMON6_PERFMON_LOW 0x0555 2263#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 2264 2265 2266// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec 2267// base address: 0x0 2268#define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 2269#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2270#define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 2271#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 2272#define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 2273#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 2274#define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 2275#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2276#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea 2277#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2278#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb 2279#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2280#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec 2281#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2282#define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed 2283#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2284#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee 2285#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2286#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef 2287#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2288#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 2289#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2290#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 2291#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2292#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 2293#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2294#define regHUBP0_DCHUBP_CNTL 0x05f3 2295#define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 2296#define regHUBP0_HUBP_CLK_CNTL 0x05f4 2297#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 2298#define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 2299#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2300#define regHUBP0_HUBPREQ_DEBUG_DB 0x05f6 2301#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 2302#define regHUBP0_HUBPREQ_DEBUG 0x05f7 2303#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 2304#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb 2305#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2306#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc 2307#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2308 2309 2310// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 2311// base address: 0x0 2312#define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 2313#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 2314#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 2315#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2316#define regHUBPREQ0_VMID_SETTINGS_0 0x0609 2317#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 2318#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 2319#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2320#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 2321#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2322#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 2323#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2324#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 2325#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2326#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 2327#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2328#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 2329#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2330#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 2331#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2332#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 2333#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2334#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 2335#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2336#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 2337#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2338#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 2339#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2340#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 2341#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2342#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 2343#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2344#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 2345#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2346#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 2347#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2348#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 2349#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2350#define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a 2351#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2352#define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b 2353#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 2354#define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c 2355#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2356#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 2357#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2358#define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 2359#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 2360#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 2361#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2362#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 2363#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2364#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 2365#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2366#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 2367#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2368#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 2369#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2370#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 2371#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2372#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 2373#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2374#define regHUBPREQ0_DCN_EXPANSION_MODE 0x0629 2375#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 2376#define regHUBPREQ0_DCN_TTU_QOS_WM 0x062a 2377#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 2378#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b 2379#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2380#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c 2381#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2382#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d 2383#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2384#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e 2385#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2386#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f 2387#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2388#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630 2389#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2390#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631 2391#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2392#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632 2393#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2394#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633 2395#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2396#define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634 2397#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2398#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635 2399#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2400#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636 2401#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2402#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643 2403#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2404#define regHUBPREQ0_BLANK_OFFSET_0 0x0644 2405#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 2406#define regHUBPREQ0_BLANK_OFFSET_1 0x0645 2407#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 2408#define regHUBPREQ0_DST_DIMENSIONS 0x0646 2409#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 2410#define regHUBPREQ0_DST_AFTER_SCALER 0x0647 2411#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 2412#define regHUBPREQ0_PREFETCH_SETTINGS 0x0648 2413#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 2414#define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0649 2415#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 2416#define regHUBPREQ0_VBLANK_PARAMETERS_0 0x064a 2417#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 2418#define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064b 2419#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 2420#define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064c 2421#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 2422#define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064d 2423#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 2424#define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064e 2425#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 2426#define regHUBPREQ0_FLIP_PARAMETERS_0 0x064f 2427#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 2428#define regHUBPREQ0_FLIP_PARAMETERS_1 0x0650 2429#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 2430#define regHUBPREQ0_FLIP_PARAMETERS_2 0x0651 2431#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 2432#define regHUBPREQ0_NOM_PARAMETERS_0 0x0652 2433#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 2434#define regHUBPREQ0_NOM_PARAMETERS_1 0x0653 2435#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 2436#define regHUBPREQ0_NOM_PARAMETERS_2 0x0654 2437#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 2438#define regHUBPREQ0_NOM_PARAMETERS_3 0x0655 2439#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 2440#define regHUBPREQ0_NOM_PARAMETERS_4 0x0656 2441#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 2442#define regHUBPREQ0_NOM_PARAMETERS_5 0x0657 2443#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 2444#define regHUBPREQ0_NOM_PARAMETERS_6 0x0658 2445#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 2446#define regHUBPREQ0_NOM_PARAMETERS_7 0x0659 2447#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 2448#define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a 2449#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2450#define regHUBPREQ0_PER_LINE_DELIVERY 0x065b 2451#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 2452#define regHUBPREQ0_CURSOR_SETTINGS 0x065c 2453#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 2454#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d 2455#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2456#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e 2457#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2458#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f 2459#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2460#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660 2461#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2462#define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0663 2463#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 2464#define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0664 2465#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 2466#define regHUBPREQ0_FLIP_PARAMETERS_3 0x0665 2467#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 2468#define regHUBPREQ0_FLIP_PARAMETERS_4 0x0666 2469#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 2470#define regHUBPREQ0_FLIP_PARAMETERS_5 0x0667 2471#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 2472#define regHUBPREQ0_FLIP_PARAMETERS_6 0x0668 2473#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 2474 2475 2476// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec 2477// base address: 0x0 2478#define regHUBPRET0_HUBPRET_CONTROL 0x066c 2479#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 2480#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d 2481#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2482#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e 2483#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2484#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f 2485#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2486#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 2487#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2488#define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 2489#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 2490#define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 2491#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 2492#define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 2493#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 2494#define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 2495#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2496#define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 2497#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2498 2499 2500// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec 2501// base address: 0x0 2502#define regCURSOR0_0_CURSOR_CONTROL 0x0678 2503#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 2504#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 2505#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2506#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a 2507#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2508#define regCURSOR0_0_CURSOR_SIZE 0x067b 2509#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 2510#define regCURSOR0_0_CURSOR_POSITION 0x067c 2511#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 2512#define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d 2513#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 2514#define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e 2515#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 2516#define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f 2517#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 2518#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 2519#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2520#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 2521#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2522#define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 2523#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2524#define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 2525#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 2526#define regCURSOR0_0_DMDATA_CNTL 0x0684 2527#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 2528#define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 2529#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 2530#define regCURSOR0_0_DMDATA_STATUS 0x0686 2531#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 2532#define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 2533#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 2534#define regCURSOR0_0_DMDATA_SW_DATA 0x0688 2535#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 2536 2537 2538// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2539// base address: 0x1a74 2540#define regDC_PERFMON7_PERFCOUNTER_CNTL 0x069d 2541#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 2542#define regDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e 2543#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 2544#define regDC_PERFMON7_PERFCOUNTER_STATE 0x069f 2545#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 2546#define regDC_PERFMON7_PERFMON_CNTL 0x06a0 2547#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 2548#define regDC_PERFMON7_PERFMON_CNTL2 0x06a1 2549#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 2550#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2 2551#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2552#define regDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3 2553#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 2554#define regDC_PERFMON7_PERFMON_HI 0x06a4 2555#define regDC_PERFMON7_PERFMON_HI_BASE_IDX 2 2556#define regDC_PERFMON7_PERFMON_LOW 0x06a5 2557#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 2558 2559 2560// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec 2561// base address: 0x370 2562#define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 2563#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2564#define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 2565#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 2566#define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 2567#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 2568#define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 2569#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2570#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 2571#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2572#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 2573#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2574#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 2575#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2576#define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 2577#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2578#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca 2579#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2580#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb 2581#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2582#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc 2583#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2584#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd 2585#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2586#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce 2587#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2588#define regHUBP1_DCHUBP_CNTL 0x06cf 2589#define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 2590#define regHUBP1_HUBP_CLK_CNTL 0x06d0 2591#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 2592#define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 2593#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2594#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d2 2595#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 2596#define regHUBP1_HUBPREQ_DEBUG 0x06d3 2597#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 2598#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 2599#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2600#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 2601#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2602 2603 2604// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec 2605// base address: 0x370 2606#define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 2607#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 2608#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 2609#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2610#define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 2611#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 2612#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 2613#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2614#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 2615#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2616#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 2617#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2618#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 2619#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2620#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 2621#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2622#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 2623#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2624#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 2625#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2626#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 2627#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2628#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee 2629#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2630#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef 2631#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2632#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 2633#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2634#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 2635#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2636#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 2637#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2638#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 2639#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2640#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 2641#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2642#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 2643#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2644#define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 2645#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2646#define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 2647#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 2648#define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 2649#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2650#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc 2651#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2652#define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd 2653#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 2654#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe 2655#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2656#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff 2657#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2658#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 2659#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2660#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 2661#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2662#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 2663#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2664#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 2665#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2666#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 2667#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2668#define regHUBPREQ1_DCN_EXPANSION_MODE 0x0705 2669#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 2670#define regHUBPREQ1_DCN_TTU_QOS_WM 0x0706 2671#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 2672#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707 2673#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2674#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708 2675#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2676#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709 2677#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2678#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a 2679#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2680#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b 2681#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2682#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c 2683#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2684#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d 2685#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2686#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e 2687#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2688#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f 2689#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2690#define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710 2691#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2692#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711 2693#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2694#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712 2695#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2696#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f 2697#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2698#define regHUBPREQ1_BLANK_OFFSET_0 0x0720 2699#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 2700#define regHUBPREQ1_BLANK_OFFSET_1 0x0721 2701#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 2702#define regHUBPREQ1_DST_DIMENSIONS 0x0722 2703#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 2704#define regHUBPREQ1_DST_AFTER_SCALER 0x0723 2705#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 2706#define regHUBPREQ1_PREFETCH_SETTINGS 0x0724 2707#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 2708#define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0725 2709#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 2710#define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0726 2711#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 2712#define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0727 2713#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 2714#define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0728 2715#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 2716#define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0729 2717#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 2718#define regHUBPREQ1_VBLANK_PARAMETERS_4 0x072a 2719#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 2720#define regHUBPREQ1_FLIP_PARAMETERS_0 0x072b 2721#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 2722#define regHUBPREQ1_FLIP_PARAMETERS_1 0x072c 2723#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 2724#define regHUBPREQ1_FLIP_PARAMETERS_2 0x072d 2725#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 2726#define regHUBPREQ1_NOM_PARAMETERS_0 0x072e 2727#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 2728#define regHUBPREQ1_NOM_PARAMETERS_1 0x072f 2729#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 2730#define regHUBPREQ1_NOM_PARAMETERS_2 0x0730 2731#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 2732#define regHUBPREQ1_NOM_PARAMETERS_3 0x0731 2733#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 2734#define regHUBPREQ1_NOM_PARAMETERS_4 0x0732 2735#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 2736#define regHUBPREQ1_NOM_PARAMETERS_5 0x0733 2737#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 2738#define regHUBPREQ1_NOM_PARAMETERS_6 0x0734 2739#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 2740#define regHUBPREQ1_NOM_PARAMETERS_7 0x0735 2741#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 2742#define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736 2743#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2744#define regHUBPREQ1_PER_LINE_DELIVERY 0x0737 2745#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 2746#define regHUBPREQ1_CURSOR_SETTINGS 0x0738 2747#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 2748#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739 2749#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2750#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a 2751#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2752#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b 2753#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2754#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c 2755#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2756#define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073f 2757#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 2758#define regHUBPREQ1_VBLANK_PARAMETERS_6 0x0740 2759#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 2760#define regHUBPREQ1_FLIP_PARAMETERS_3 0x0741 2761#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 2762#define regHUBPREQ1_FLIP_PARAMETERS_4 0x0742 2763#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 2764#define regHUBPREQ1_FLIP_PARAMETERS_5 0x0743 2765#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 2766#define regHUBPREQ1_FLIP_PARAMETERS_6 0x0744 2767#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 2768 2769 2770// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec 2771// base address: 0x370 2772#define regHUBPRET1_HUBPRET_CONTROL 0x0748 2773#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 2774#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 2775#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2776#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a 2777#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2778#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b 2779#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2780#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c 2781#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2782#define regHUBPRET1_HUBPRET_READ_LINE0 0x074d 2783#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 2784#define regHUBPRET1_HUBPRET_READ_LINE1 0x074e 2785#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 2786#define regHUBPRET1_HUBPRET_INTERRUPT 0x074f 2787#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 2788#define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 2789#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2790#define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 2791#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2792 2793 2794// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec 2795// base address: 0x370 2796#define regCURSOR0_1_CURSOR_CONTROL 0x0754 2797#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 2798#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 2799#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2800#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 2801#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2802#define regCURSOR0_1_CURSOR_SIZE 0x0757 2803#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 2804#define regCURSOR0_1_CURSOR_POSITION 0x0758 2805#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 2806#define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 2807#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 2808#define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a 2809#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 2810#define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b 2811#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 2812#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c 2813#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2814#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d 2815#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2816#define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e 2817#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2818#define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f 2819#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 2820#define regCURSOR0_1_DMDATA_CNTL 0x0760 2821#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 2822#define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 2823#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 2824#define regCURSOR0_1_DMDATA_STATUS 0x0762 2825#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 2826#define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 2827#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 2828#define regCURSOR0_1_DMDATA_SW_DATA 0x0764 2829#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 2830 2831 2832// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2833// base address: 0x1de4 2834#define regDC_PERFMON8_PERFCOUNTER_CNTL 0x0779 2835#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 2836#define regDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a 2837#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 2838#define regDC_PERFMON8_PERFCOUNTER_STATE 0x077b 2839#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 2840#define regDC_PERFMON8_PERFMON_CNTL 0x077c 2841#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 2842#define regDC_PERFMON8_PERFMON_CNTL2 0x077d 2843#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 2844#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e 2845#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2846#define regDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f 2847#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 2848#define regDC_PERFMON8_PERFMON_HI 0x0780 2849#define regDC_PERFMON8_PERFMON_HI_BASE_IDX 2 2850#define regDC_PERFMON8_PERFMON_LOW 0x0781 2851#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 2852 2853 2854// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec 2855// base address: 0x6e0 2856#define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d 2857#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2858#define regHUBP2_DCSURF_ADDR_CONFIG 0x079e 2859#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 2860#define regHUBP2_DCSURF_TILING_CONFIG 0x079f 2861#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 2862#define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 2863#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2864#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 2865#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2866#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 2867#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2868#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 2869#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2870#define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 2871#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2872#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 2873#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2874#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 2875#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2876#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 2877#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2878#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 2879#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2880#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa 2881#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2882#define regHUBP2_DCHUBP_CNTL 0x07ab 2883#define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 2884#define regHUBP2_HUBP_CLK_CNTL 0x07ac 2885#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 2886#define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad 2887#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2888#define regHUBP2_HUBPREQ_DEBUG_DB 0x07ae 2889#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 2890#define regHUBP2_HUBPREQ_DEBUG 0x07af 2891#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 2892#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3 2893#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2894#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4 2895#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2896 2897 2898// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec 2899// base address: 0x6e0 2900#define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf 2901#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 2902#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 2903#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2904#define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 2905#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 2906#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 2907#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2908#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 2909#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2910#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 2911#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2912#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 2913#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2914#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 2915#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2916#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 2917#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2918#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 2919#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2920#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 2921#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2922#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca 2923#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2924#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb 2925#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2926#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc 2927#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2928#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd 2929#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2930#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce 2931#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2932#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf 2933#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2934#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 2935#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2936#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 2937#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2938#define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 2939#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2940#define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 2941#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 2942#define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 2943#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2944#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8 2945#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2946#define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9 2947#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 2948#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da 2949#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2950#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db 2951#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2952#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc 2953#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2954#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd 2955#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2956#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de 2957#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2958#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df 2959#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2960#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0 2961#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2962#define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e1 2963#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 2964#define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e2 2965#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 2966#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e3 2967#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2968#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e4 2969#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2970#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e5 2971#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2972#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e6 2973#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2974#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e7 2975#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2976#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e8 2977#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2978#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e9 2979#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2980#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ea 2981#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2982#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07eb 2983#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2984#define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07ec 2985#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2986#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ed 2987#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2988#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ee 2989#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2990#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fb 2991#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2992#define regHUBPREQ2_BLANK_OFFSET_0 0x07fc 2993#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 2994#define regHUBPREQ2_BLANK_OFFSET_1 0x07fd 2995#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 2996#define regHUBPREQ2_DST_DIMENSIONS 0x07fe 2997#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 2998#define regHUBPREQ2_DST_AFTER_SCALER 0x07ff 2999#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 3000#define regHUBPREQ2_PREFETCH_SETTINGS 0x0800 3001#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 3002#define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0801 3003#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 3004#define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0802 3005#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 3006#define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0803 3007#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 3008#define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0804 3009#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 3010#define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0805 3011#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 3012#define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0806 3013#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 3014#define regHUBPREQ2_FLIP_PARAMETERS_0 0x0807 3015#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 3016#define regHUBPREQ2_FLIP_PARAMETERS_1 0x0808 3017#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 3018#define regHUBPREQ2_FLIP_PARAMETERS_2 0x0809 3019#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 3020#define regHUBPREQ2_NOM_PARAMETERS_0 0x080a 3021#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 3022#define regHUBPREQ2_NOM_PARAMETERS_1 0x080b 3023#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 3024#define regHUBPREQ2_NOM_PARAMETERS_2 0x080c 3025#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 3026#define regHUBPREQ2_NOM_PARAMETERS_3 0x080d 3027#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 3028#define regHUBPREQ2_NOM_PARAMETERS_4 0x080e 3029#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 3030#define regHUBPREQ2_NOM_PARAMETERS_5 0x080f 3031#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 3032#define regHUBPREQ2_NOM_PARAMETERS_6 0x0810 3033#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 3034#define regHUBPREQ2_NOM_PARAMETERS_7 0x0811 3035#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 3036#define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0812 3037#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3038#define regHUBPREQ2_PER_LINE_DELIVERY 0x0813 3039#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 3040#define regHUBPREQ2_CURSOR_SETTINGS 0x0814 3041#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 3042#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0815 3043#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3044#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0816 3045#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3046#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0817 3047#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3048#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0818 3049#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3050#define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081b 3051#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 3052#define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081c 3053#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 3054#define regHUBPREQ2_FLIP_PARAMETERS_3 0x081d 3055#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 3056#define regHUBPREQ2_FLIP_PARAMETERS_4 0x081e 3057#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 3058#define regHUBPREQ2_FLIP_PARAMETERS_5 0x081f 3059#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 3060#define regHUBPREQ2_FLIP_PARAMETERS_6 0x0820 3061#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 3062 3063 3064// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec 3065// base address: 0x6e0 3066#define regHUBPRET2_HUBPRET_CONTROL 0x0824 3067#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 3068#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 3069#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3070#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 3071#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3072#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 3073#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3074#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 3075#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3076#define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 3077#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 3078#define regHUBPRET2_HUBPRET_READ_LINE1 0x082a 3079#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 3080#define regHUBPRET2_HUBPRET_INTERRUPT 0x082b 3081#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 3082#define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c 3083#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3084#define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d 3085#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3086 3087 3088// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec 3089// base address: 0x6e0 3090#define regCURSOR0_2_CURSOR_CONTROL 0x0830 3091#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 3092#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 3093#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3094#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 3095#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3096#define regCURSOR0_2_CURSOR_SIZE 0x0833 3097#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 3098#define regCURSOR0_2_CURSOR_POSITION 0x0834 3099#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 3100#define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 3101#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 3102#define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 3103#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 3104#define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 3105#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 3106#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 3107#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3108#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 3109#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3110#define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a 3111#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3112#define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b 3113#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 3114#define regCURSOR0_2_DMDATA_CNTL 0x083c 3115#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 3116#define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d 3117#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 3118#define regCURSOR0_2_DMDATA_STATUS 0x083e 3119#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 3120#define regCURSOR0_2_DMDATA_SW_CNTL 0x083f 3121#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 3122#define regCURSOR0_2_DMDATA_SW_DATA 0x0840 3123#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 3124 3125 3126// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3127// base address: 0x2154 3128#define regDC_PERFMON9_PERFCOUNTER_CNTL 0x0855 3129#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 3130#define regDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856 3131#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 3132#define regDC_PERFMON9_PERFCOUNTER_STATE 0x0857 3133#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 3134#define regDC_PERFMON9_PERFMON_CNTL 0x0858 3135#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 3136#define regDC_PERFMON9_PERFMON_CNTL2 0x0859 3137#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 3138#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a 3139#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3140#define regDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b 3141#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 3142#define regDC_PERFMON9_PERFMON_HI 0x085c 3143#define regDC_PERFMON9_PERFMON_HI_BASE_IDX 2 3144#define regDC_PERFMON9_PERFMON_LOW 0x085d 3145#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 3146 3147 3148// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec 3149// base address: 0xa50 3150#define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 3151#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3152#define regHUBP3_DCSURF_ADDR_CONFIG 0x087a 3153#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 3154#define regHUBP3_DCSURF_TILING_CONFIG 0x087b 3155#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 3156#define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d 3157#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3158#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e 3159#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3160#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f 3161#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3162#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 3163#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3164#define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 3165#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3166#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 3167#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3168#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 3169#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3170#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 3171#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3172#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 3173#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3174#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 3175#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3176#define regHUBP3_DCHUBP_CNTL 0x0887 3177#define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 3178#define regHUBP3_HUBP_CLK_CNTL 0x0888 3179#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 3180#define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 3181#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3182#define regHUBP3_HUBPREQ_DEBUG_DB 0x088a 3183#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 3184#define regHUBP3_HUBPREQ_DEBUG 0x088b 3185#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 3186#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f 3187#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3188#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890 3189#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3190 3191 3192// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec 3193// base address: 0xa50 3194#define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b 3195#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 3196#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c 3197#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3198#define regHUBPREQ3_VMID_SETTINGS_0 0x089d 3199#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 3200#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e 3201#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3202#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f 3203#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3204#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 3205#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3206#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 3207#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3208#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 3209#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3210#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 3211#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3212#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 3213#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3214#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 3215#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3216#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 3217#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3218#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 3219#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3220#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 3221#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3222#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 3223#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3224#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa 3225#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3226#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab 3227#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3228#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac 3229#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3230#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad 3231#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3232#define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae 3233#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3234#define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af 3235#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 3236#define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 3237#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3238#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4 3239#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3240#define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5 3241#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 3242#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6 3243#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3244#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7 3245#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3246#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8 3247#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3248#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9 3249#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3250#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba 3251#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3252#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb 3253#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3254#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc 3255#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3256#define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bd 3257#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 3258#define regHUBPREQ3_DCN_TTU_QOS_WM 0x08be 3259#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 3260#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08bf 3261#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3262#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c0 3263#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3264#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c1 3265#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3266#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c2 3267#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3268#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c3 3269#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3270#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c4 3271#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3272#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c5 3273#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3274#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c6 3275#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3276#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c7 3277#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3278#define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c8 3279#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3280#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c9 3281#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3282#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08ca 3283#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3284#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d7 3285#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3286#define regHUBPREQ3_BLANK_OFFSET_0 0x08d8 3287#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 3288#define regHUBPREQ3_BLANK_OFFSET_1 0x08d9 3289#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 3290#define regHUBPREQ3_DST_DIMENSIONS 0x08da 3291#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 3292#define regHUBPREQ3_DST_AFTER_SCALER 0x08db 3293#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 3294#define regHUBPREQ3_PREFETCH_SETTINGS 0x08dc 3295#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 3296#define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dd 3297#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 3298#define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08de 3299#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 3300#define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08df 3301#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 3302#define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08e0 3303#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 3304#define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e1 3305#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 3306#define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e2 3307#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 3308#define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e3 3309#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 3310#define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e4 3311#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 3312#define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e5 3313#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 3314#define regHUBPREQ3_NOM_PARAMETERS_0 0x08e6 3315#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 3316#define regHUBPREQ3_NOM_PARAMETERS_1 0x08e7 3317#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 3318#define regHUBPREQ3_NOM_PARAMETERS_2 0x08e8 3319#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 3320#define regHUBPREQ3_NOM_PARAMETERS_3 0x08e9 3321#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 3322#define regHUBPREQ3_NOM_PARAMETERS_4 0x08ea 3323#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 3324#define regHUBPREQ3_NOM_PARAMETERS_5 0x08eb 3325#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 3326#define regHUBPREQ3_NOM_PARAMETERS_6 0x08ec 3327#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 3328#define regHUBPREQ3_NOM_PARAMETERS_7 0x08ed 3329#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 3330#define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ee 3331#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3332#define regHUBPREQ3_PER_LINE_DELIVERY 0x08ef 3333#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 3334#define regHUBPREQ3_CURSOR_SETTINGS 0x08f0 3335#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 3336#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f1 3337#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3338#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f2 3339#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3340#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f3 3341#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3342#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f4 3343#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3344#define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f7 3345#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 3346#define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f8 3347#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 3348#define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f9 3349#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 3350#define regHUBPREQ3_FLIP_PARAMETERS_4 0x08fa 3351#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 3352#define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fb 3353#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 3354#define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fc 3355#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 3356 3357 3358// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec 3359// base address: 0xa50 3360#define regHUBPRET3_HUBPRET_CONTROL 0x0900 3361#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 3362#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 3363#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3364#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 3365#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3366#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 3367#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3368#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 3369#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3370#define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 3371#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 3372#define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 3373#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 3374#define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 3375#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 3376#define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 3377#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3378#define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 3379#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3380 3381 3382// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec 3383// base address: 0xa50 3384#define regCURSOR0_3_CURSOR_CONTROL 0x090c 3385#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 3386#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d 3387#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3388#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e 3389#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3390#define regCURSOR0_3_CURSOR_SIZE 0x090f 3391#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 3392#define regCURSOR0_3_CURSOR_POSITION 0x0910 3393#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 3394#define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 3395#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 3396#define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 3397#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 3398#define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 3399#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 3400#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 3401#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3402#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 3403#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3404#define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 3405#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3406#define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 3407#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 3408#define regCURSOR0_3_DMDATA_CNTL 0x0918 3409#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 3410#define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 3411#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 3412#define regCURSOR0_3_DMDATA_STATUS 0x091a 3413#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 3414#define regCURSOR0_3_DMDATA_SW_CNTL 0x091b 3415#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 3416#define regCURSOR0_3_DMDATA_SW_DATA 0x091c 3417#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 3418 3419 3420// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3421// base address: 0x24c4 3422#define regDC_PERFMON10_PERFCOUNTER_CNTL 0x0931 3423#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 3424#define regDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932 3425#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 3426#define regDC_PERFMON10_PERFCOUNTER_STATE 0x0933 3427#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 3428#define regDC_PERFMON10_PERFMON_CNTL 0x0934 3429#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 3430#define regDC_PERFMON10_PERFMON_CNTL2 0x0935 3431#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 3432#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936 3433#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3434#define regDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937 3435#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 3436#define regDC_PERFMON10_PERFMON_HI 0x0938 3437#define regDC_PERFMON10_PERFMON_HI_BASE_IDX 2 3438#define regDC_PERFMON10_PERFMON_LOW 0x0939 3439#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 3440 3441 3442// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec 3443// base address: 0x0 3444#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 3445#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3446#define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 3447#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 3448#define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 3449#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 3450#define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 3451#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 3452#define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 3453#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 3454#define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 3455#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 3456#define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 3457#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 3458#define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 3459#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 3460#define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 3461#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 3462#define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 3463#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 3464#define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 3465#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 3466#define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 3467#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 3468#define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 3469#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 3470#define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 3471#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 3472#define regCNVC_CFG0_PRE_DEALPHA 0x0cde 3473#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 3474#define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf 3475#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 3476#define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 3477#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 3478#define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 3479#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 3480#define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 3481#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 3482#define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 3483#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 3484#define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 3485#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 3486#define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 3487#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 3488#define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 3489#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 3490#define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 3491#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 3492#define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 3493#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 3494#define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 3495#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 3496#define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea 3497#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 3498#define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb 3499#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 3500#define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec 3501#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 3502#define regCNVC_CFG0_PRE_DEGAM 0x0ced 3503#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 3504#define regCNVC_CFG0_PRE_REALPHA 0x0cee 3505#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 3506 3507 3508// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec 3509// base address: 0x0 3510#define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 3511#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 3512#define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 3513#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 3514#define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 3515#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 3516#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 3517#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3518 3519 3520// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec 3521// base address: 0x0 3522#define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 3523#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3524#define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa 3525#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3526#define regDSCL0_SCL_MODE 0x0cfb 3527#define regDSCL0_SCL_MODE_BASE_IDX 2 3528#define regDSCL0_SCL_TAP_CONTROL 0x0cfc 3529#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 3530#define regDSCL0_DSCL_CONTROL 0x0cfd 3531#define regDSCL0_DSCL_CONTROL_BASE_IDX 2 3532#define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe 3533#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 3534#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff 3535#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3536#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 3537#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3538#define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 3539#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3540#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 3541#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3542#define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 3543#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3544#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 3545#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3546#define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 3547#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 3548#define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 3549#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3550#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 3551#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3552#define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 3553#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3554#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 3555#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3556#define regDSCL0_SCL_BLACK_COLOR 0x0d0a 3557#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 3558#define regDSCL0_DSCL_UPDATE 0x0d0b 3559#define regDSCL0_DSCL_UPDATE_BASE_IDX 2 3560#define regDSCL0_DSCL_AUTOCAL 0x0d0c 3561#define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 3562#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d 3563#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3564#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e 3565#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3566#define regDSCL0_OTG_H_BLANK 0x0d0f 3567#define regDSCL0_OTG_H_BLANK_BASE_IDX 2 3568#define regDSCL0_OTG_V_BLANK 0x0d10 3569#define regDSCL0_OTG_V_BLANK_BASE_IDX 2 3570#define regDSCL0_RECOUT_START 0x0d11 3571#define regDSCL0_RECOUT_START_BASE_IDX 2 3572#define regDSCL0_RECOUT_SIZE 0x0d12 3573#define regDSCL0_RECOUT_SIZE_BASE_IDX 2 3574#define regDSCL0_MPC_SIZE 0x0d13 3575#define regDSCL0_MPC_SIZE_BASE_IDX 2 3576#define regDSCL0_LB_DATA_FORMAT 0x0d14 3577#define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 3578#define regDSCL0_LB_MEMORY_CTRL 0x0d15 3579#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 3580#define regDSCL0_LB_V_COUNTER 0x0d16 3581#define regDSCL0_LB_V_COUNTER_BASE_IDX 2 3582#define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 3583#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 3584#define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 3585#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 3586#define regDSCL0_OBUF_CONTROL 0x0d19 3587#define regDSCL0_OBUF_CONTROL_BASE_IDX 2 3588#define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a 3589#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 3590 3591 3592// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec 3593// base address: 0x0 3594#define regCM0_CM_CONTROL 0x0d20 3595#define regCM0_CM_CONTROL_BASE_IDX 2 3596#define regCM0_CM_POST_CSC_CONTROL 0x0d21 3597#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 3598#define regCM0_CM_POST_CSC_C11_C12 0x0d22 3599#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 3600#define regCM0_CM_POST_CSC_C13_C14 0x0d23 3601#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 3602#define regCM0_CM_POST_CSC_C21_C22 0x0d24 3603#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 3604#define regCM0_CM_POST_CSC_C23_C24 0x0d25 3605#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 3606#define regCM0_CM_POST_CSC_C31_C32 0x0d26 3607#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 3608#define regCM0_CM_POST_CSC_C33_C34 0x0d27 3609#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 3610#define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 3611#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 3612#define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 3613#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 3614#define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a 3615#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 3616#define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b 3617#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 3618#define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c 3619#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 3620#define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d 3621#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 3622#define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e 3623#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 3624#define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f 3625#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 3626#define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 3627#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 3628#define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 3629#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 3630#define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 3631#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 3632#define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 3633#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 3634#define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 3635#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 3636#define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 3637#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 3638#define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 3639#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 3640#define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 3641#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 3642#define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 3643#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 3644#define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 3645#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 3646#define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a 3647#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 3648#define regCM0_CM_BIAS_CR_R 0x0d3b 3649#define regCM0_CM_BIAS_CR_R_BASE_IDX 2 3650#define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c 3651#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 3652#define regCM0_CM_GAMCOR_CONTROL 0x0d3d 3653#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 3654#define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e 3655#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 3656#define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f 3657#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 3658#define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 3659#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 3660#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 3661#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 3662#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 3663#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 3664#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 3665#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 3666#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 3667#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 3668#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 3669#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 3670#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 3671#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 3672#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 3673#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 3674#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 3675#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 3676#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 3677#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 3678#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a 3679#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 3680#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b 3681#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 3682#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c 3683#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 3684#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d 3685#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 3686#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e 3687#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 3688#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f 3689#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 3690#define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 3691#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 3692#define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 3693#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 3694#define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 3695#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 3696#define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 3697#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 3698#define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 3699#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 3700#define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 3701#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 3702#define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 3703#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 3704#define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 3705#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 3706#define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 3707#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 3708#define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 3709#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 3710#define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a 3711#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 3712#define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b 3713#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 3714#define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c 3715#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 3716#define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d 3717#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 3718#define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e 3719#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 3720#define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f 3721#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 3722#define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 3723#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 3724#define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 3725#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 3726#define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 3727#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 3728#define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 3729#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 3730#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 3731#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 3732#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 3733#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 3734#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 3735#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 3736#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 3737#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 3738#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 3739#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 3740#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 3741#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 3742#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a 3743#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 3744#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b 3745#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 3746#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c 3747#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 3748#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d 3749#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 3750#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e 3751#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 3752#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f 3753#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 3754#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 3755#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 3756#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 3757#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 3758#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 3759#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 3760#define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 3761#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 3762#define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 3763#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 3764#define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 3765#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 3766#define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 3767#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 3768#define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 3769#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 3770#define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 3771#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 3772#define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 3773#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 3774#define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a 3775#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 3776#define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b 3777#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 3778#define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c 3779#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 3780#define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d 3781#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 3782#define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e 3783#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 3784#define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f 3785#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 3786#define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 3787#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 3788#define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 3789#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 3790#define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 3791#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 3792#define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 3793#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 3794#define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 3795#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 3796#define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 3797#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 3798#define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 3799#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 3800#define regCM0_CM_BLNDGAM_CONTROL 0x0d87 3801#define regCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 3802#define regCM0_CM_BLNDGAM_LUT_INDEX 0x0d88 3803#define regCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 3804#define regCM0_CM_BLNDGAM_LUT_DATA 0x0d89 3805#define regCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 3806#define regCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a 3807#define regCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 3808#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b 3809#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 3810#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c 3811#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 3812#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d 3813#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 3814#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e 3815#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 3816#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f 3817#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 3818#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90 3819#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 3820#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91 3821#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 3822#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92 3823#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 3824#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93 3825#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 3826#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94 3827#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 3828#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95 3829#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 3830#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96 3831#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 3832#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97 3833#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 3834#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98 3835#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 3836#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99 3837#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 3838#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a 3839#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 3840#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b 3841#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 3842#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c 3843#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 3844#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d 3845#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 3846#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e 3847#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 3848#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f 3849#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 3850#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0 3851#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 3852#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1 3853#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 3854#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2 3855#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 3856#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3 3857#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 3858#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4 3859#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 3860#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5 3861#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 3862#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6 3863#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 3864#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7 3865#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 3866#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8 3867#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 3868#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9 3869#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 3870#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa 3871#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 3872#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab 3873#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 3874#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac 3875#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 3876#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad 3877#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 3878#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae 3879#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 3880#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf 3881#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 3882#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0 3883#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 3884#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1 3885#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 3886#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2 3887#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 3888#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3 3889#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 3890#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4 3891#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 3892#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5 3893#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 3894#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6 3895#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 3896#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7 3897#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 3898#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8 3899#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 3900#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9 3901#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 3902#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba 3903#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 3904#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb 3905#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 3906#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc 3907#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 3908#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd 3909#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 3910#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe 3911#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 3912#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf 3913#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 3914#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0 3915#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 3916#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1 3917#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 3918#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2 3919#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 3920#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3 3921#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 3922#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4 3923#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 3924#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5 3925#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 3926#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6 3927#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 3928#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7 3929#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 3930#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8 3931#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 3932#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9 3933#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 3934#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca 3935#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 3936#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb 3937#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 3938#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc 3939#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 3940#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd 3941#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 3942#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce 3943#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 3944#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf 3945#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 3946#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0 3947#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 3948#define regCM0_CM_HDR_MULT_COEF 0x0dd1 3949#define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 3950#define regCM0_CM_MEM_PWR_CTRL 0x0dd2 3951#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 3952#define regCM0_CM_MEM_PWR_STATUS 0x0dd3 3953#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 3954#define regCM0_CM_DEALPHA 0x0dd5 3955#define regCM0_CM_DEALPHA_BASE_IDX 2 3956#define regCM0_CM_COEF_FORMAT 0x0dd6 3957#define regCM0_CM_COEF_FORMAT_BASE_IDX 2 3958#define regCM0_CM_SHAPER_CONTROL 0x0dd7 3959#define regCM0_CM_SHAPER_CONTROL_BASE_IDX 2 3960#define regCM0_CM_SHAPER_OFFSET_R 0x0dd8 3961#define regCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 3962#define regCM0_CM_SHAPER_OFFSET_G 0x0dd9 3963#define regCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 3964#define regCM0_CM_SHAPER_OFFSET_B 0x0dda 3965#define regCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 3966#define regCM0_CM_SHAPER_SCALE_R 0x0ddb 3967#define regCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 3968#define regCM0_CM_SHAPER_SCALE_G_B 0x0ddc 3969#define regCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 3970#define regCM0_CM_SHAPER_LUT_INDEX 0x0ddd 3971#define regCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 3972#define regCM0_CM_SHAPER_LUT_DATA 0x0dde 3973#define regCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 3974#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf 3975#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 3976#define regCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0 3977#define regCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 3978#define regCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1 3979#define regCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 3980#define regCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2 3981#define regCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 3982#define regCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3 3983#define regCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 3984#define regCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4 3985#define regCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 3986#define regCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5 3987#define regCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 3988#define regCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6 3989#define regCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 3990#define regCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7 3991#define regCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 3992#define regCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8 3993#define regCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 3994#define regCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9 3995#define regCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 3996#define regCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea 3997#define regCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 3998#define regCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb 3999#define regCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 4000#define regCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec 4001#define regCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 4002#define regCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded 4003#define regCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 4004#define regCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee 4005#define regCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 4006#define regCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def 4007#define regCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 4008#define regCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0 4009#define regCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 4010#define regCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1 4011#define regCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 4012#define regCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2 4013#define regCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 4014#define regCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3 4015#define regCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 4016#define regCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4 4017#define regCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 4018#define regCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5 4019#define regCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 4020#define regCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6 4021#define regCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 4022#define regCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7 4023#define regCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 4024#define regCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8 4025#define regCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 4026#define regCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9 4027#define regCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 4028#define regCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa 4029#define regCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 4030#define regCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb 4031#define regCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 4032#define regCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc 4033#define regCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 4034#define regCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd 4035#define regCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 4036#define regCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe 4037#define regCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 4038#define regCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff 4039#define regCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 4040#define regCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00 4041#define regCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 4042#define regCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01 4043#define regCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 4044#define regCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02 4045#define regCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 4046#define regCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03 4047#define regCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 4048#define regCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04 4049#define regCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 4050#define regCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05 4051#define regCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 4052#define regCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06 4053#define regCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 4054#define regCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07 4055#define regCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 4056#define regCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08 4057#define regCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 4058#define regCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09 4059#define regCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 4060#define regCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a 4061#define regCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 4062#define regCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b 4063#define regCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 4064#define regCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c 4065#define regCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 4066#define regCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d 4067#define regCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 4068#define regCM0_CM_MEM_PWR_CTRL2 0x0e0e 4069#define regCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 4070#define regCM0_CM_MEM_PWR_STATUS2 0x0e0f 4071#define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 4072#define regCM0_CM_3DLUT_MODE 0x0e10 4073#define regCM0_CM_3DLUT_MODE_BASE_IDX 2 4074#define regCM0_CM_3DLUT_INDEX 0x0e11 4075#define regCM0_CM_3DLUT_INDEX_BASE_IDX 2 4076#define regCM0_CM_3DLUT_DATA 0x0e12 4077#define regCM0_CM_3DLUT_DATA_BASE_IDX 2 4078#define regCM0_CM_3DLUT_DATA_30BIT 0x0e13 4079#define regCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 4080#define regCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14 4081#define regCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 4082#define regCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15 4083#define regCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 4084#define regCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16 4085#define regCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 4086#define regCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17 4087#define regCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 4088#define regCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18 4089#define regCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 4090#define regCM0_CM_TEST_DEBUG_INDEX 0x0e19 4091#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4092#define regCM0_CM_TEST_DEBUG_DATA 0x0e1a 4093#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 4094 4095 4096// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec 4097// base address: 0x0 4098#define regDPP_TOP0_DPP_CONTROL 0x0cc5 4099#define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 4100#define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 4101#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 4102#define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 4103#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 4104#define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 4105#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 4106#define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 4107#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 4108#define regDPP_TOP0_HOST_READ_CONTROL 0x0cca 4109#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 4110 4111 4112// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 4113// base address: 0x3890 4114#define regDC_PERFMON11_PERFCOUNTER_CNTL 0x0e24 4115#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 4116#define regDC_PERFMON11_PERFCOUNTER_CNTL2 0x0e25 4117#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 4118#define regDC_PERFMON11_PERFCOUNTER_STATE 0x0e26 4119#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 4120#define regDC_PERFMON11_PERFMON_CNTL 0x0e27 4121#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 4122#define regDC_PERFMON11_PERFMON_CNTL2 0x0e28 4123#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 4124#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0e29 4125#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4126#define regDC_PERFMON11_PERFMON_CVALUE_LOW 0x0e2a 4127#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 4128#define regDC_PERFMON11_PERFMON_HI 0x0e2b 4129#define regDC_PERFMON11_PERFMON_HI_BASE_IDX 2 4130#define regDC_PERFMON11_PERFMON_LOW 0x0e2c 4131#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 4132 4133 4134// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec 4135// base address: 0x5ac 4136#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 4137#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4138#define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b 4139#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 4140#define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 4141#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 4142#define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 4143#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 4144#define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 4145#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 4146#define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 4147#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 4148#define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 4149#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 4150#define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 4151#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 4152#define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 4153#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 4154#define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 4155#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 4156#define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 4157#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 4158#define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 4159#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 4160#define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 4161#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 4162#define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 4163#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 4164#define regCNVC_CFG1_PRE_DEALPHA 0x0e49 4165#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 4166#define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a 4167#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 4168#define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b 4169#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 4170#define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c 4171#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 4172#define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d 4173#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 4174#define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e 4175#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 4176#define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f 4177#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 4178#define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 4179#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 4180#define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 4181#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 4182#define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 4183#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 4184#define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 4185#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 4186#define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 4187#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 4188#define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 4189#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 4190#define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 4191#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 4192#define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 4193#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 4194#define regCNVC_CFG1_PRE_DEGAM 0x0e58 4195#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 4196#define regCNVC_CFG1_PRE_REALPHA 0x0e59 4197#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 4198 4199 4200// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec 4201// base address: 0x5ac 4202#define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c 4203#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 4204#define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d 4205#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 4206#define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e 4207#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 4208#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f 4209#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4210 4211 4212// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec 4213// base address: 0x5ac 4214#define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 4215#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4216#define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 4217#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4218#define regDSCL1_SCL_MODE 0x0e66 4219#define regDSCL1_SCL_MODE_BASE_IDX 2 4220#define regDSCL1_SCL_TAP_CONTROL 0x0e67 4221#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 4222#define regDSCL1_DSCL_CONTROL 0x0e68 4223#define regDSCL1_DSCL_CONTROL_BASE_IDX 2 4224#define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 4225#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 4226#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a 4227#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4228#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b 4229#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4230#define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c 4231#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4232#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d 4233#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4234#define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e 4235#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4236#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f 4237#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4238#define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 4239#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 4240#define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 4241#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4242#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 4243#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4244#define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 4245#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4246#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 4247#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4248#define regDSCL1_SCL_BLACK_COLOR 0x0e75 4249#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 4250#define regDSCL1_DSCL_UPDATE 0x0e76 4251#define regDSCL1_DSCL_UPDATE_BASE_IDX 2 4252#define regDSCL1_DSCL_AUTOCAL 0x0e77 4253#define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 4254#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 4255#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4256#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 4257#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4258#define regDSCL1_OTG_H_BLANK 0x0e7a 4259#define regDSCL1_OTG_H_BLANK_BASE_IDX 2 4260#define regDSCL1_OTG_V_BLANK 0x0e7b 4261#define regDSCL1_OTG_V_BLANK_BASE_IDX 2 4262#define regDSCL1_RECOUT_START 0x0e7c 4263#define regDSCL1_RECOUT_START_BASE_IDX 2 4264#define regDSCL1_RECOUT_SIZE 0x0e7d 4265#define regDSCL1_RECOUT_SIZE_BASE_IDX 2 4266#define regDSCL1_MPC_SIZE 0x0e7e 4267#define regDSCL1_MPC_SIZE_BASE_IDX 2 4268#define regDSCL1_LB_DATA_FORMAT 0x0e7f 4269#define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 4270#define regDSCL1_LB_MEMORY_CTRL 0x0e80 4271#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 4272#define regDSCL1_LB_V_COUNTER 0x0e81 4273#define regDSCL1_LB_V_COUNTER_BASE_IDX 2 4274#define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 4275#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4276#define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 4277#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4278#define regDSCL1_OBUF_CONTROL 0x0e84 4279#define regDSCL1_OBUF_CONTROL_BASE_IDX 2 4280#define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 4281#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4282 4283 4284// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec 4285// base address: 0x5ac 4286#define regCM1_CM_CONTROL 0x0e8b 4287#define regCM1_CM_CONTROL_BASE_IDX 2 4288#define regCM1_CM_POST_CSC_CONTROL 0x0e8c 4289#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 4290#define regCM1_CM_POST_CSC_C11_C12 0x0e8d 4291#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 4292#define regCM1_CM_POST_CSC_C13_C14 0x0e8e 4293#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 4294#define regCM1_CM_POST_CSC_C21_C22 0x0e8f 4295#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 4296#define regCM1_CM_POST_CSC_C23_C24 0x0e90 4297#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 4298#define regCM1_CM_POST_CSC_C31_C32 0x0e91 4299#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 4300#define regCM1_CM_POST_CSC_C33_C34 0x0e92 4301#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 4302#define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 4303#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4304#define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 4305#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4306#define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 4307#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4308#define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 4309#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4310#define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 4311#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4312#define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 4313#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4314#define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 4315#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4316#define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a 4317#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4318#define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b 4319#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4320#define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c 4321#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4322#define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d 4323#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4324#define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e 4325#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4326#define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f 4327#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4328#define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 4329#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4330#define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 4331#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4332#define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 4333#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4334#define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 4335#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4336#define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 4337#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4338#define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 4339#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4340#define regCM1_CM_BIAS_CR_R 0x0ea6 4341#define regCM1_CM_BIAS_CR_R_BASE_IDX 2 4342#define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 4343#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4344#define regCM1_CM_GAMCOR_CONTROL 0x0ea8 4345#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 4346#define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 4347#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4348#define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa 4349#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4350#define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab 4351#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4352#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac 4353#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4354#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead 4355#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4356#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae 4357#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4358#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf 4359#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4360#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 4361#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4362#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 4363#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4364#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 4365#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4366#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 4367#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4368#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 4369#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4370#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 4371#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4372#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 4373#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4374#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 4375#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4376#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 4377#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4378#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 4379#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4380#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba 4381#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4382#define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb 4383#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4384#define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc 4385#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4386#define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd 4387#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4388#define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe 4389#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4390#define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf 4391#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4392#define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 4393#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4394#define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 4395#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4396#define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 4397#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4398#define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 4399#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4400#define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 4401#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4402#define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 4403#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4404#define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 4405#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4406#define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 4407#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4408#define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 4409#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4410#define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 4411#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4412#define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca 4413#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4414#define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb 4415#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4416#define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc 4417#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4418#define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd 4419#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4420#define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece 4421#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4422#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf 4423#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4424#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 4425#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4426#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 4427#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4428#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 4429#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4430#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 4431#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4432#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 4433#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4434#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 4435#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4436#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 4437#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4438#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 4439#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4440#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 4441#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4442#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 4443#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4444#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda 4445#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4446#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb 4447#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4448#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc 4449#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4450#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd 4451#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4452#define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede 4453#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4454#define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf 4455#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4456#define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 4457#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4458#define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 4459#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4460#define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 4461#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4462#define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 4463#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4464#define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 4465#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4466#define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 4467#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4468#define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 4469#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4470#define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 4471#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4472#define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 4473#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4474#define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 4475#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4476#define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea 4477#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4478#define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb 4479#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4480#define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec 4481#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4482#define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed 4483#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4484#define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee 4485#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4486#define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef 4487#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4488#define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 4489#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4490#define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 4491#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4492#define regCM1_CM_BLNDGAM_CONTROL 0x0ef2 4493#define regCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 4494#define regCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3 4495#define regCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 4496#define regCM1_CM_BLNDGAM_LUT_DATA 0x0ef4 4497#define regCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 4498#define regCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5 4499#define regCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 4500#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6 4501#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 4502#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7 4503#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 4504#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8 4505#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 4506#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9 4507#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4508#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa 4509#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4510#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb 4511#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4512#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc 4513#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4514#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd 4515#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4516#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe 4517#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4518#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff 4519#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4520#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00 4521#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4522#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01 4523#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4524#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02 4525#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4526#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03 4527#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4528#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04 4529#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4530#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05 4531#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 4532#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06 4533#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 4534#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07 4535#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 4536#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08 4537#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 4538#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09 4539#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 4540#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a 4541#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 4542#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b 4543#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 4544#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c 4545#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 4546#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d 4547#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 4548#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e 4549#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 4550#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f 4551#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 4552#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10 4553#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 4554#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11 4555#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 4556#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12 4557#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 4558#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13 4559#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 4560#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14 4561#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 4562#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15 4563#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 4564#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16 4565#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 4566#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17 4567#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 4568#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18 4569#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 4570#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19 4571#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 4572#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a 4573#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 4574#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b 4575#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 4576#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c 4577#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4578#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d 4579#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4580#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e 4581#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4582#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f 4583#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4584#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20 4585#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4586#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21 4587#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4588#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22 4589#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4590#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23 4591#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4592#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24 4593#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4594#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25 4595#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4596#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26 4597#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4598#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27 4599#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4600#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28 4601#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 4602#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29 4603#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 4604#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a 4605#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 4606#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b 4607#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 4608#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c 4609#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 4610#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d 4611#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 4612#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e 4613#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 4614#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f 4615#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 4616#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30 4617#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 4618#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31 4619#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 4620#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32 4621#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 4622#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33 4623#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 4624#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34 4625#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 4626#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35 4627#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 4628#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36 4629#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 4630#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37 4631#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 4632#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38 4633#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 4634#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39 4635#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 4636#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a 4637#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 4638#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b 4639#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 4640#define regCM1_CM_HDR_MULT_COEF 0x0f3c 4641#define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 4642#define regCM1_CM_MEM_PWR_CTRL 0x0f3d 4643#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 4644#define regCM1_CM_MEM_PWR_STATUS 0x0f3e 4645#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 4646#define regCM1_CM_DEALPHA 0x0f40 4647#define regCM1_CM_DEALPHA_BASE_IDX 2 4648#define regCM1_CM_COEF_FORMAT 0x0f41 4649#define regCM1_CM_COEF_FORMAT_BASE_IDX 2 4650#define regCM1_CM_SHAPER_CONTROL 0x0f42 4651#define regCM1_CM_SHAPER_CONTROL_BASE_IDX 2 4652#define regCM1_CM_SHAPER_OFFSET_R 0x0f43 4653#define regCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 4654#define regCM1_CM_SHAPER_OFFSET_G 0x0f44 4655#define regCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 4656#define regCM1_CM_SHAPER_OFFSET_B 0x0f45 4657#define regCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 4658#define regCM1_CM_SHAPER_SCALE_R 0x0f46 4659#define regCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 4660#define regCM1_CM_SHAPER_SCALE_G_B 0x0f47 4661#define regCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 4662#define regCM1_CM_SHAPER_LUT_INDEX 0x0f48 4663#define regCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 4664#define regCM1_CM_SHAPER_LUT_DATA 0x0f49 4665#define regCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 4666#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a 4667#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 4668#define regCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b 4669#define regCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 4670#define regCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c 4671#define regCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 4672#define regCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d 4673#define regCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 4674#define regCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e 4675#define regCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 4676#define regCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f 4677#define regCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 4678#define regCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50 4679#define regCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 4680#define regCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51 4681#define regCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 4682#define regCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52 4683#define regCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 4684#define regCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53 4685#define regCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 4686#define regCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54 4687#define regCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 4688#define regCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55 4689#define regCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 4690#define regCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56 4691#define regCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 4692#define regCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57 4693#define regCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 4694#define regCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58 4695#define regCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 4696#define regCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59 4697#define regCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 4698#define regCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a 4699#define regCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 4700#define regCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b 4701#define regCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 4702#define regCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c 4703#define regCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 4704#define regCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d 4705#define regCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 4706#define regCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e 4707#define regCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 4708#define regCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f 4709#define regCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 4710#define regCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60 4711#define regCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 4712#define regCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61 4713#define regCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 4714#define regCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62 4715#define regCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 4716#define regCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63 4717#define regCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 4718#define regCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64 4719#define regCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 4720#define regCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65 4721#define regCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 4722#define regCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66 4723#define regCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 4724#define regCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67 4725#define regCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 4726#define regCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68 4727#define regCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 4728#define regCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69 4729#define regCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 4730#define regCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a 4731#define regCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 4732#define regCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b 4733#define regCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 4734#define regCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c 4735#define regCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 4736#define regCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d 4737#define regCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 4738#define regCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e 4739#define regCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 4740#define regCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f 4741#define regCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 4742#define regCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70 4743#define regCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 4744#define regCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71 4745#define regCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 4746#define regCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72 4747#define regCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 4748#define regCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73 4749#define regCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 4750#define regCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74 4751#define regCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 4752#define regCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75 4753#define regCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 4754#define regCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76 4755#define regCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 4756#define regCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77 4757#define regCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 4758#define regCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78 4759#define regCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 4760#define regCM1_CM_MEM_PWR_CTRL2 0x0f79 4761#define regCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 4762#define regCM1_CM_MEM_PWR_STATUS2 0x0f7a 4763#define regCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 4764#define regCM1_CM_3DLUT_MODE 0x0f7b 4765#define regCM1_CM_3DLUT_MODE_BASE_IDX 2 4766#define regCM1_CM_3DLUT_INDEX 0x0f7c 4767#define regCM1_CM_3DLUT_INDEX_BASE_IDX 2 4768#define regCM1_CM_3DLUT_DATA 0x0f7d 4769#define regCM1_CM_3DLUT_DATA_BASE_IDX 2 4770#define regCM1_CM_3DLUT_DATA_30BIT 0x0f7e 4771#define regCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 4772#define regCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f 4773#define regCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 4774#define regCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80 4775#define regCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 4776#define regCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81 4777#define regCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 4778#define regCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82 4779#define regCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 4780#define regCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83 4781#define regCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 4782#define regCM1_CM_TEST_DEBUG_INDEX 0x0f84 4783#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4784#define regCM1_CM_TEST_DEBUG_DATA 0x0f85 4785#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 4786 4787 4788// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec 4789// base address: 0x5ac 4790#define regDPP_TOP1_DPP_CONTROL 0x0e30 4791#define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 4792#define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 4793#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 4794#define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 4795#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 4796#define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 4797#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 4798#define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 4799#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 4800#define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 4801#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 4802 4803 4804// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 4805// base address: 0x3e3c 4806#define regDC_PERFMON12_PERFCOUNTER_CNTL 0x0f8f 4807#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 4808#define regDC_PERFMON12_PERFCOUNTER_CNTL2 0x0f90 4809#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 4810#define regDC_PERFMON12_PERFCOUNTER_STATE 0x0f91 4811#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 4812#define regDC_PERFMON12_PERFMON_CNTL 0x0f92 4813#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 4814#define regDC_PERFMON12_PERFMON_CNTL2 0x0f93 4815#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 4816#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0f94 4817#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4818#define regDC_PERFMON12_PERFMON_CVALUE_LOW 0x0f95 4819#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 4820#define regDC_PERFMON12_PERFMON_HI 0x0f96 4821#define regDC_PERFMON12_PERFMON_HI_BASE_IDX 2 4822#define regDC_PERFMON12_PERFMON_LOW 0x0f97 4823#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 4824 4825 4826// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec 4827// base address: 0xb58 4828#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 4829#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4830#define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 4831#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 4832#define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 4833#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 4834#define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 4835#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 4836#define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 4837#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 4838#define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa 4839#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 4840#define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab 4841#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 4842#define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac 4843#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 4844#define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad 4845#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 4846#define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae 4847#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 4848#define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf 4849#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 4850#define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 4851#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 4852#define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 4853#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 4854#define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 4855#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 4856#define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 4857#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 4858#define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 4859#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 4860#define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 4861#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 4862#define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 4863#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 4864#define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 4865#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 4866#define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 4867#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 4868#define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba 4869#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 4870#define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb 4871#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 4872#define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc 4873#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 4874#define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd 4875#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 4876#define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe 4877#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 4878#define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf 4879#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 4880#define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 4881#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 4882#define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 4883#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 4884#define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 4885#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 4886#define regCNVC_CFG2_PRE_DEGAM 0x0fc3 4887#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 4888#define regCNVC_CFG2_PRE_REALPHA 0x0fc4 4889#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 4890 4891 4892// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec 4893// base address: 0xb58 4894#define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 4895#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 4896#define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 4897#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 4898#define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 4899#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 4900#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca 4901#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4902 4903 4904// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec 4905// base address: 0xb58 4906#define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf 4907#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4908#define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 4909#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4910#define regDSCL2_SCL_MODE 0x0fd1 4911#define regDSCL2_SCL_MODE_BASE_IDX 2 4912#define regDSCL2_SCL_TAP_CONTROL 0x0fd2 4913#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 4914#define regDSCL2_DSCL_CONTROL 0x0fd3 4915#define regDSCL2_DSCL_CONTROL_BASE_IDX 2 4916#define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 4917#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 4918#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 4919#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4920#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 4921#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4922#define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 4923#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4924#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 4925#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4926#define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 4927#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4928#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda 4929#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4930#define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb 4931#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 4932#define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc 4933#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4934#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd 4935#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4936#define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde 4937#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4938#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf 4939#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4940#define regDSCL2_SCL_BLACK_COLOR 0x0fe0 4941#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 4942#define regDSCL2_DSCL_UPDATE 0x0fe1 4943#define regDSCL2_DSCL_UPDATE_BASE_IDX 2 4944#define regDSCL2_DSCL_AUTOCAL 0x0fe2 4945#define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 4946#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 4947#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4948#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 4949#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4950#define regDSCL2_OTG_H_BLANK 0x0fe5 4951#define regDSCL2_OTG_H_BLANK_BASE_IDX 2 4952#define regDSCL2_OTG_V_BLANK 0x0fe6 4953#define regDSCL2_OTG_V_BLANK_BASE_IDX 2 4954#define regDSCL2_RECOUT_START 0x0fe7 4955#define regDSCL2_RECOUT_START_BASE_IDX 2 4956#define regDSCL2_RECOUT_SIZE 0x0fe8 4957#define regDSCL2_RECOUT_SIZE_BASE_IDX 2 4958#define regDSCL2_MPC_SIZE 0x0fe9 4959#define regDSCL2_MPC_SIZE_BASE_IDX 2 4960#define regDSCL2_LB_DATA_FORMAT 0x0fea 4961#define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 4962#define regDSCL2_LB_MEMORY_CTRL 0x0feb 4963#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 4964#define regDSCL2_LB_V_COUNTER 0x0fec 4965#define regDSCL2_LB_V_COUNTER_BASE_IDX 2 4966#define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed 4967#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4968#define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee 4969#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4970#define regDSCL2_OBUF_CONTROL 0x0fef 4971#define regDSCL2_OBUF_CONTROL_BASE_IDX 2 4972#define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 4973#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4974 4975 4976// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec 4977// base address: 0xb58 4978#define regCM2_CM_CONTROL 0x0ff6 4979#define regCM2_CM_CONTROL_BASE_IDX 2 4980#define regCM2_CM_POST_CSC_CONTROL 0x0ff7 4981#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 4982#define regCM2_CM_POST_CSC_C11_C12 0x0ff8 4983#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 4984#define regCM2_CM_POST_CSC_C13_C14 0x0ff9 4985#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 4986#define regCM2_CM_POST_CSC_C21_C22 0x0ffa 4987#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 4988#define regCM2_CM_POST_CSC_C23_C24 0x0ffb 4989#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 4990#define regCM2_CM_POST_CSC_C31_C32 0x0ffc 4991#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 4992#define regCM2_CM_POST_CSC_C33_C34 0x0ffd 4993#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 4994#define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe 4995#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4996#define regCM2_CM_POST_CSC_B_C13_C14 0x0fff 4997#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4998#define regCM2_CM_POST_CSC_B_C21_C22 0x1000 4999#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5000#define regCM2_CM_POST_CSC_B_C23_C24 0x1001 5001#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5002#define regCM2_CM_POST_CSC_B_C31_C32 0x1002 5003#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5004#define regCM2_CM_POST_CSC_B_C33_C34 0x1003 5005#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5006#define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 5007#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5008#define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 5009#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5010#define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 5011#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5012#define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 5013#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5014#define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 5015#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5016#define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 5017#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5018#define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a 5019#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5020#define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b 5021#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5022#define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c 5023#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5024#define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d 5025#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5026#define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e 5027#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5028#define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f 5029#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5030#define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 5031#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5032#define regCM2_CM_BIAS_CR_R 0x1011 5033#define regCM2_CM_BIAS_CR_R_BASE_IDX 2 5034#define regCM2_CM_BIAS_Y_G_CB_B 0x1012 5035#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5036#define regCM2_CM_GAMCOR_CONTROL 0x1013 5037#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 5038#define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 5039#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5040#define regCM2_CM_GAMCOR_LUT_DATA 0x1015 5041#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5042#define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 5043#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5044#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 5045#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5046#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 5047#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5048#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 5049#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5050#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a 5051#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5052#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b 5053#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5054#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c 5055#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5056#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d 5057#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5058#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e 5059#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5060#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f 5061#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5062#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 5063#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5064#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 5065#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5066#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 5067#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5068#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 5069#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5070#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 5071#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5072#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 5073#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5074#define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 5075#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5076#define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 5077#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5078#define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 5079#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5080#define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 5081#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5082#define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a 5083#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5084#define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b 5085#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5086#define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c 5087#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5088#define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d 5089#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5090#define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e 5091#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5092#define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f 5093#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5094#define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 5095#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5096#define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 5097#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5098#define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 5099#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5100#define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 5101#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5102#define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 5103#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5104#define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 5105#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5106#define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 5107#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5108#define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 5109#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5110#define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 5111#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5112#define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 5113#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5114#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a 5115#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5116#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b 5117#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5118#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c 5119#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5120#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d 5121#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5122#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e 5123#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5124#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f 5125#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5126#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 5127#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5128#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 5129#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5130#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 5131#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5132#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 5133#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5134#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 5135#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5136#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 5137#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5138#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 5139#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5140#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 5141#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5142#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 5143#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5144#define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 5145#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5146#define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a 5147#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5148#define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b 5149#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5150#define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c 5151#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5152#define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d 5153#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5154#define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e 5155#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5156#define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f 5157#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5158#define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 5159#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5160#define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 5161#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5162#define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 5163#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5164#define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 5165#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5166#define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 5167#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5168#define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 5169#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5170#define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 5171#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5172#define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 5173#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 5174#define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 5175#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 5176#define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 5177#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 5178#define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a 5179#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 5180#define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b 5181#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 5182#define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c 5183#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 5184#define regCM2_CM_BLNDGAM_CONTROL 0x105d 5185#define regCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2 5186#define regCM2_CM_BLNDGAM_LUT_INDEX 0x105e 5187#define regCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 5188#define regCM2_CM_BLNDGAM_LUT_DATA 0x105f 5189#define regCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 5190#define regCM2_CM_BLNDGAM_LUT_CONTROL 0x1060 5191#define regCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 5192#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x1061 5193#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 5194#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x1062 5195#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 5196#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x1063 5197#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 5198#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x1064 5199#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5200#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x1065 5201#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5202#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x1066 5203#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5204#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x1067 5205#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5206#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x1068 5207#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5208#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x1069 5209#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5210#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x106a 5211#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 5212#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x106b 5213#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 5214#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x106c 5215#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 5216#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x106d 5217#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 5218#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x106e 5219#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 5220#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x106f 5221#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 5222#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B 0x1070 5223#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 5224#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G 0x1071 5225#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 5226#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R 0x1072 5227#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 5228#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1073 5229#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 5230#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x1074 5231#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 5232#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x1075 5233#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 5234#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x1076 5235#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 5236#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x1077 5237#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 5238#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x1078 5239#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 5240#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x1079 5241#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 5242#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x107a 5243#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 5244#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x107b 5245#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 5246#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x107c 5247#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 5248#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x107d 5249#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 5250#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x107e 5251#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 5252#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x107f 5253#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 5254#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1080 5255#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 5256#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1081 5257#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 5258#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1082 5259#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 5260#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1083 5261#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 5262#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x1084 5263#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 5264#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x1085 5265#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 5266#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x1086 5267#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 5268#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x1087 5269#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5270#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x1088 5271#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5272#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x1089 5273#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5274#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x108a 5275#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5276#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x108b 5277#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5278#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x108c 5279#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5280#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x108d 5281#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5282#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x108e 5283#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5284#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x108f 5285#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5286#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1090 5287#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5288#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1091 5289#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5290#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1092 5291#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5292#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B 0x1093 5293#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 5294#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G 0x1094 5295#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 5296#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R 0x1095 5297#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 5298#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1096 5299#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 5300#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1097 5301#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 5302#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1098 5303#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 5304#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1099 5305#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 5306#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x109a 5307#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 5308#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x109b 5309#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 5310#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x109c 5311#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 5312#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x109d 5313#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 5314#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x109e 5315#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 5316#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x109f 5317#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 5318#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x10a0 5319#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 5320#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x10a1 5321#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 5322#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x10a2 5323#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 5324#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x10a3 5325#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 5326#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x10a4 5327#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 5328#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x10a5 5329#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 5330#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x10a6 5331#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 5332#define regCM2_CM_HDR_MULT_COEF 0x10a7 5333#define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 5334#define regCM2_CM_MEM_PWR_CTRL 0x10a8 5335#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 5336#define regCM2_CM_MEM_PWR_STATUS 0x10a9 5337#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 5338#define regCM2_CM_DEALPHA 0x10ab 5339#define regCM2_CM_DEALPHA_BASE_IDX 2 5340#define regCM2_CM_COEF_FORMAT 0x10ac 5341#define regCM2_CM_COEF_FORMAT_BASE_IDX 2 5342#define regCM2_CM_SHAPER_CONTROL 0x10ad 5343#define regCM2_CM_SHAPER_CONTROL_BASE_IDX 2 5344#define regCM2_CM_SHAPER_OFFSET_R 0x10ae 5345#define regCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2 5346#define regCM2_CM_SHAPER_OFFSET_G 0x10af 5347#define regCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2 5348#define regCM2_CM_SHAPER_OFFSET_B 0x10b0 5349#define regCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2 5350#define regCM2_CM_SHAPER_SCALE_R 0x10b1 5351#define regCM2_CM_SHAPER_SCALE_R_BASE_IDX 2 5352#define regCM2_CM_SHAPER_SCALE_G_B 0x10b2 5353#define regCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2 5354#define regCM2_CM_SHAPER_LUT_INDEX 0x10b3 5355#define regCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2 5356#define regCM2_CM_SHAPER_LUT_DATA 0x10b4 5357#define regCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2 5358#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x10b5 5359#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 5360#define regCM2_CM_SHAPER_RAMA_START_CNTL_B 0x10b6 5361#define regCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 5362#define regCM2_CM_SHAPER_RAMA_START_CNTL_G 0x10b7 5363#define regCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 5364#define regCM2_CM_SHAPER_RAMA_START_CNTL_R 0x10b8 5365#define regCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 5366#define regCM2_CM_SHAPER_RAMA_END_CNTL_B 0x10b9 5367#define regCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 5368#define regCM2_CM_SHAPER_RAMA_END_CNTL_G 0x10ba 5369#define regCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 5370#define regCM2_CM_SHAPER_RAMA_END_CNTL_R 0x10bb 5371#define regCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 5372#define regCM2_CM_SHAPER_RAMA_REGION_0_1 0x10bc 5373#define regCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 5374#define regCM2_CM_SHAPER_RAMA_REGION_2_3 0x10bd 5375#define regCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 5376#define regCM2_CM_SHAPER_RAMA_REGION_4_5 0x10be 5377#define regCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 5378#define regCM2_CM_SHAPER_RAMA_REGION_6_7 0x10bf 5379#define regCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 5380#define regCM2_CM_SHAPER_RAMA_REGION_8_9 0x10c0 5381#define regCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 5382#define regCM2_CM_SHAPER_RAMA_REGION_10_11 0x10c1 5383#define regCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 5384#define regCM2_CM_SHAPER_RAMA_REGION_12_13 0x10c2 5385#define regCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 5386#define regCM2_CM_SHAPER_RAMA_REGION_14_15 0x10c3 5387#define regCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 5388#define regCM2_CM_SHAPER_RAMA_REGION_16_17 0x10c4 5389#define regCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 5390#define regCM2_CM_SHAPER_RAMA_REGION_18_19 0x10c5 5391#define regCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 5392#define regCM2_CM_SHAPER_RAMA_REGION_20_21 0x10c6 5393#define regCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 5394#define regCM2_CM_SHAPER_RAMA_REGION_22_23 0x10c7 5395#define regCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 5396#define regCM2_CM_SHAPER_RAMA_REGION_24_25 0x10c8 5397#define regCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 5398#define regCM2_CM_SHAPER_RAMA_REGION_26_27 0x10c9 5399#define regCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 5400#define regCM2_CM_SHAPER_RAMA_REGION_28_29 0x10ca 5401#define regCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 5402#define regCM2_CM_SHAPER_RAMA_REGION_30_31 0x10cb 5403#define regCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 5404#define regCM2_CM_SHAPER_RAMA_REGION_32_33 0x10cc 5405#define regCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 5406#define regCM2_CM_SHAPER_RAMB_START_CNTL_B 0x10cd 5407#define regCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 5408#define regCM2_CM_SHAPER_RAMB_START_CNTL_G 0x10ce 5409#define regCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 5410#define regCM2_CM_SHAPER_RAMB_START_CNTL_R 0x10cf 5411#define regCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 5412#define regCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10d0 5413#define regCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 5414#define regCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10d1 5415#define regCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 5416#define regCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10d2 5417#define regCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 5418#define regCM2_CM_SHAPER_RAMB_REGION_0_1 0x10d3 5419#define regCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 5420#define regCM2_CM_SHAPER_RAMB_REGION_2_3 0x10d4 5421#define regCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 5422#define regCM2_CM_SHAPER_RAMB_REGION_4_5 0x10d5 5423#define regCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 5424#define regCM2_CM_SHAPER_RAMB_REGION_6_7 0x10d6 5425#define regCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 5426#define regCM2_CM_SHAPER_RAMB_REGION_8_9 0x10d7 5427#define regCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 5428#define regCM2_CM_SHAPER_RAMB_REGION_10_11 0x10d8 5429#define regCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 5430#define regCM2_CM_SHAPER_RAMB_REGION_12_13 0x10d9 5431#define regCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 5432#define regCM2_CM_SHAPER_RAMB_REGION_14_15 0x10da 5433#define regCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 5434#define regCM2_CM_SHAPER_RAMB_REGION_16_17 0x10db 5435#define regCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 5436#define regCM2_CM_SHAPER_RAMB_REGION_18_19 0x10dc 5437#define regCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 5438#define regCM2_CM_SHAPER_RAMB_REGION_20_21 0x10dd 5439#define regCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 5440#define regCM2_CM_SHAPER_RAMB_REGION_22_23 0x10de 5441#define regCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 5442#define regCM2_CM_SHAPER_RAMB_REGION_24_25 0x10df 5443#define regCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 5444#define regCM2_CM_SHAPER_RAMB_REGION_26_27 0x10e0 5445#define regCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 5446#define regCM2_CM_SHAPER_RAMB_REGION_28_29 0x10e1 5447#define regCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 5448#define regCM2_CM_SHAPER_RAMB_REGION_30_31 0x10e2 5449#define regCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 5450#define regCM2_CM_SHAPER_RAMB_REGION_32_33 0x10e3 5451#define regCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 5452#define regCM2_CM_MEM_PWR_CTRL2 0x10e4 5453#define regCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2 5454#define regCM2_CM_MEM_PWR_STATUS2 0x10e5 5455#define regCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2 5456#define regCM2_CM_3DLUT_MODE 0x10e6 5457#define regCM2_CM_3DLUT_MODE_BASE_IDX 2 5458#define regCM2_CM_3DLUT_INDEX 0x10e7 5459#define regCM2_CM_3DLUT_INDEX_BASE_IDX 2 5460#define regCM2_CM_3DLUT_DATA 0x10e8 5461#define regCM2_CM_3DLUT_DATA_BASE_IDX 2 5462#define regCM2_CM_3DLUT_DATA_30BIT 0x10e9 5463#define regCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5464#define regCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ea 5465#define regCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5466#define regCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10eb 5467#define regCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5468#define regCM2_CM_3DLUT_OUT_OFFSET_R 0x10ec 5469#define regCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5470#define regCM2_CM_3DLUT_OUT_OFFSET_G 0x10ed 5471#define regCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5472#define regCM2_CM_3DLUT_OUT_OFFSET_B 0x10ee 5473#define regCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5474#define regCM2_CM_TEST_DEBUG_INDEX 0x10ef 5475#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5476#define regCM2_CM_TEST_DEBUG_DATA 0x10f0 5477#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 5478 5479 5480// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec 5481// base address: 0xb58 5482#define regDPP_TOP2_DPP_CONTROL 0x0f9b 5483#define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 5484#define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c 5485#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 5486#define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d 5487#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 5488#define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e 5489#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 5490#define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f 5491#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 5492#define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 5493#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 5494 5495 5496// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5497// base address: 0x43e8 5498#define regDC_PERFMON13_PERFCOUNTER_CNTL 0x10fa 5499#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 5500#define regDC_PERFMON13_PERFCOUNTER_CNTL2 0x10fb 5501#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 5502#define regDC_PERFMON13_PERFCOUNTER_STATE 0x10fc 5503#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 5504#define regDC_PERFMON13_PERFMON_CNTL 0x10fd 5505#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 5506#define regDC_PERFMON13_PERFMON_CNTL2 0x10fe 5507#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 5508#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x10ff 5509#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5510#define regDC_PERFMON13_PERFMON_CVALUE_LOW 0x1100 5511#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 5512#define regDC_PERFMON13_PERFMON_HI 0x1101 5513#define regDC_PERFMON13_PERFMON_HI_BASE_IDX 2 5514#define regDC_PERFMON13_PERFMON_LOW 0x1102 5515#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 5516 5517 5518// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec 5519// base address: 0x1104 5520#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 5521#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5522#define regCNVC_CFG3_FORMAT_CONTROL 0x1111 5523#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 5524#define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 5525#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 5526#define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 5527#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 5528#define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 5529#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 5530#define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 5531#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 5532#define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 5533#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 5534#define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 5535#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 5536#define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 5537#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 5538#define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 5539#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 5540#define regCNVC_CFG3_COLOR_KEYER_RED 0x111a 5541#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 5542#define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b 5543#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 5544#define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c 5545#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 5546#define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e 5547#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 5548#define regCNVC_CFG3_PRE_DEALPHA 0x111f 5549#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 5550#define regCNVC_CFG3_PRE_CSC_MODE 0x1120 5551#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 5552#define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 5553#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 5554#define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 5555#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 5556#define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 5557#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 5558#define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 5559#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 5560#define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 5561#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 5562#define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 5563#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 5564#define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 5565#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 5566#define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 5567#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 5568#define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 5569#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 5570#define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a 5571#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 5572#define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b 5573#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 5574#define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c 5575#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 5576#define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d 5577#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 5578#define regCNVC_CFG3_PRE_DEGAM 0x112e 5579#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 5580#define regCNVC_CFG3_PRE_REALPHA 0x112f 5581#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 5582 5583 5584// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec 5585// base address: 0x1104 5586#define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 5587#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 5588#define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 5589#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 5590#define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 5591#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 5592#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 5593#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 5594 5595 5596// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec 5597// base address: 0x1104 5598#define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a 5599#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 5600#define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b 5601#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 5602#define regDSCL3_SCL_MODE 0x113c 5603#define regDSCL3_SCL_MODE_BASE_IDX 2 5604#define regDSCL3_SCL_TAP_CONTROL 0x113d 5605#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 5606#define regDSCL3_DSCL_CONTROL 0x113e 5607#define regDSCL3_DSCL_CONTROL_BASE_IDX 2 5608#define regDSCL3_DSCL_2TAP_CONTROL 0x113f 5609#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 5610#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 5611#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 5612#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 5613#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 5614#define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 5615#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 5616#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 5617#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 5618#define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 5619#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 5620#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 5621#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 5622#define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 5623#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 5624#define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 5625#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 5626#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 5627#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 5628#define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 5629#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 5630#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a 5631#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 5632#define regDSCL3_SCL_BLACK_COLOR 0x114b 5633#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 5634#define regDSCL3_DSCL_UPDATE 0x114c 5635#define regDSCL3_DSCL_UPDATE_BASE_IDX 2 5636#define regDSCL3_DSCL_AUTOCAL 0x114d 5637#define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 5638#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e 5639#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 5640#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f 5641#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 5642#define regDSCL3_OTG_H_BLANK 0x1150 5643#define regDSCL3_OTG_H_BLANK_BASE_IDX 2 5644#define regDSCL3_OTG_V_BLANK 0x1151 5645#define regDSCL3_OTG_V_BLANK_BASE_IDX 2 5646#define regDSCL3_RECOUT_START 0x1152 5647#define regDSCL3_RECOUT_START_BASE_IDX 2 5648#define regDSCL3_RECOUT_SIZE 0x1153 5649#define regDSCL3_RECOUT_SIZE_BASE_IDX 2 5650#define regDSCL3_MPC_SIZE 0x1154 5651#define regDSCL3_MPC_SIZE_BASE_IDX 2 5652#define regDSCL3_LB_DATA_FORMAT 0x1155 5653#define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 5654#define regDSCL3_LB_MEMORY_CTRL 0x1156 5655#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 5656#define regDSCL3_LB_V_COUNTER 0x1157 5657#define regDSCL3_LB_V_COUNTER_BASE_IDX 2 5658#define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 5659#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 5660#define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 5661#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 5662#define regDSCL3_OBUF_CONTROL 0x115a 5663#define regDSCL3_OBUF_CONTROL_BASE_IDX 2 5664#define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b 5665#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 5666 5667 5668// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec 5669// base address: 0x1104 5670#define regCM3_CM_CONTROL 0x1161 5671#define regCM3_CM_CONTROL_BASE_IDX 2 5672#define regCM3_CM_POST_CSC_CONTROL 0x1162 5673#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 5674#define regCM3_CM_POST_CSC_C11_C12 0x1163 5675#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 5676#define regCM3_CM_POST_CSC_C13_C14 0x1164 5677#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 5678#define regCM3_CM_POST_CSC_C21_C22 0x1165 5679#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 5680#define regCM3_CM_POST_CSC_C23_C24 0x1166 5681#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 5682#define regCM3_CM_POST_CSC_C31_C32 0x1167 5683#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 5684#define regCM3_CM_POST_CSC_C33_C34 0x1168 5685#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 5686#define regCM3_CM_POST_CSC_B_C11_C12 0x1169 5687#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 5688#define regCM3_CM_POST_CSC_B_C13_C14 0x116a 5689#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5690#define regCM3_CM_POST_CSC_B_C21_C22 0x116b 5691#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5692#define regCM3_CM_POST_CSC_B_C23_C24 0x116c 5693#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5694#define regCM3_CM_POST_CSC_B_C31_C32 0x116d 5695#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5696#define regCM3_CM_POST_CSC_B_C33_C34 0x116e 5697#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5698#define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f 5699#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5700#define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 5701#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5702#define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 5703#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5704#define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 5705#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5706#define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 5707#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5708#define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 5709#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5710#define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 5711#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5712#define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 5713#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5714#define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 5715#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5716#define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 5717#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5718#define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 5719#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5720#define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a 5721#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5722#define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b 5723#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5724#define regCM3_CM_BIAS_CR_R 0x117c 5725#define regCM3_CM_BIAS_CR_R_BASE_IDX 2 5726#define regCM3_CM_BIAS_Y_G_CB_B 0x117d 5727#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5728#define regCM3_CM_GAMCOR_CONTROL 0x117e 5729#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 5730#define regCM3_CM_GAMCOR_LUT_INDEX 0x117f 5731#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5732#define regCM3_CM_GAMCOR_LUT_DATA 0x1180 5733#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5734#define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 5735#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5736#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 5737#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5738#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 5739#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5740#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 5741#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5742#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 5743#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5744#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 5745#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5746#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 5747#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5748#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 5749#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5750#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 5751#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5752#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a 5753#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5754#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b 5755#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5756#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c 5757#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5758#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d 5759#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5760#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e 5761#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5762#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f 5763#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5764#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 5765#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5766#define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 5767#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5768#define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 5769#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5770#define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 5771#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5772#define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 5773#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5774#define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 5775#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5776#define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 5777#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5778#define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 5779#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5780#define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 5781#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5782#define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 5783#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5784#define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a 5785#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5786#define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b 5787#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5788#define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c 5789#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5790#define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d 5791#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5792#define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e 5793#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5794#define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f 5795#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5796#define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 5797#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5798#define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 5799#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5800#define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 5801#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5802#define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 5803#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5804#define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 5805#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5806#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 5807#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5808#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 5809#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5810#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 5811#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5812#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 5813#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5814#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 5815#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5816#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa 5817#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5818#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab 5819#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5820#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac 5821#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5822#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad 5823#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5824#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae 5825#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5826#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af 5827#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5828#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 5829#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5830#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 5831#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5832#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 5833#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5834#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 5835#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5836#define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 5837#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5838#define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 5839#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5840#define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 5841#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5842#define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 5843#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5844#define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 5845#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5846#define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 5847#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5848#define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba 5849#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5850#define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb 5851#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5852#define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc 5853#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5854#define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd 5855#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5856#define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be 5857#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5858#define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf 5859#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5860#define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 5861#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5862#define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 5863#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5864#define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 5865#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 5866#define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 5867#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 5868#define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 5869#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 5870#define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 5871#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 5872#define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 5873#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 5874#define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 5875#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 5876#define regCM3_CM_BLNDGAM_CONTROL 0x11c8 5877#define regCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2 5878#define regCM3_CM_BLNDGAM_LUT_INDEX 0x11c9 5879#define regCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 5880#define regCM3_CM_BLNDGAM_LUT_DATA 0x11ca 5881#define regCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 5882#define regCM3_CM_BLNDGAM_LUT_CONTROL 0x11cb 5883#define regCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 5884#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11cc 5885#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 5886#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11cd 5887#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 5888#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11ce 5889#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 5890#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x11cf 5891#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5892#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x11d0 5893#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5894#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x11d1 5895#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5896#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x11d2 5897#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5898#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x11d3 5899#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5900#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x11d4 5901#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5902#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11d5 5903#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 5904#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11d6 5905#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 5906#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11d7 5907#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 5908#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11d8 5909#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 5910#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11d9 5911#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 5912#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11da 5913#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 5914#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B 0x11db 5915#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 5916#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G 0x11dc 5917#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 5918#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R 0x11dd 5919#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 5920#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11de 5921#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 5922#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11df 5923#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 5924#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11e0 5925#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 5926#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11e1 5927#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 5928#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11e2 5929#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 5930#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11e3 5931#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 5932#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11e4 5933#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 5934#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11e5 5935#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 5936#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11e6 5937#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 5938#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11e7 5939#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 5940#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11e8 5941#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 5942#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11e9 5943#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 5944#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11ea 5945#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 5946#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11eb 5947#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 5948#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11ec 5949#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 5950#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11ed 5951#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 5952#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11ee 5953#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 5954#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11ef 5955#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 5956#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11f0 5957#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 5958#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11f1 5959#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 5960#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x11f2 5961#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5962#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x11f3 5963#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5964#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x11f4 5965#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5966#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x11f5 5967#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5968#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x11f6 5969#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5970#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x11f7 5971#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5972#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11f8 5973#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5974#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11f9 5975#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5976#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11fa 5977#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5978#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11fb 5979#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5980#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11fc 5981#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5982#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11fd 5983#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5984#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B 0x11fe 5985#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 5986#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G 0x11ff 5987#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 5988#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R 0x1200 5989#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 5990#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x1201 5991#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 5992#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x1202 5993#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 5994#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x1203 5995#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 5996#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x1204 5997#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 5998#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x1205 5999#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 6000#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x1206 6001#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 6002#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x1207 6003#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 6004#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x1208 6005#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 6006#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x1209 6007#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 6008#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x120a 6009#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 6010#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x120b 6011#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 6012#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x120c 6013#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 6014#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x120d 6015#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 6016#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x120e 6017#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 6018#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x120f 6019#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 6020#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x1210 6021#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 6022#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x1211 6023#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 6024#define regCM3_CM_HDR_MULT_COEF 0x1212 6025#define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 6026#define regCM3_CM_MEM_PWR_CTRL 0x1213 6027#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 6028#define regCM3_CM_MEM_PWR_STATUS 0x1214 6029#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 6030#define regCM3_CM_DEALPHA 0x1216 6031#define regCM3_CM_DEALPHA_BASE_IDX 2 6032#define regCM3_CM_COEF_FORMAT 0x1217 6033#define regCM3_CM_COEF_FORMAT_BASE_IDX 2 6034#define regCM3_CM_SHAPER_CONTROL 0x1218 6035#define regCM3_CM_SHAPER_CONTROL_BASE_IDX 2 6036#define regCM3_CM_SHAPER_OFFSET_R 0x1219 6037#define regCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2 6038#define regCM3_CM_SHAPER_OFFSET_G 0x121a 6039#define regCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2 6040#define regCM3_CM_SHAPER_OFFSET_B 0x121b 6041#define regCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2 6042#define regCM3_CM_SHAPER_SCALE_R 0x121c 6043#define regCM3_CM_SHAPER_SCALE_R_BASE_IDX 2 6044#define regCM3_CM_SHAPER_SCALE_G_B 0x121d 6045#define regCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2 6046#define regCM3_CM_SHAPER_LUT_INDEX 0x121e 6047#define regCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2 6048#define regCM3_CM_SHAPER_LUT_DATA 0x121f 6049#define regCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2 6050#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x1220 6051#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 6052#define regCM3_CM_SHAPER_RAMA_START_CNTL_B 0x1221 6053#define regCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 6054#define regCM3_CM_SHAPER_RAMA_START_CNTL_G 0x1222 6055#define regCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 6056#define regCM3_CM_SHAPER_RAMA_START_CNTL_R 0x1223 6057#define regCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 6058#define regCM3_CM_SHAPER_RAMA_END_CNTL_B 0x1224 6059#define regCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 6060#define regCM3_CM_SHAPER_RAMA_END_CNTL_G 0x1225 6061#define regCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 6062#define regCM3_CM_SHAPER_RAMA_END_CNTL_R 0x1226 6063#define regCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 6064#define regCM3_CM_SHAPER_RAMA_REGION_0_1 0x1227 6065#define regCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 6066#define regCM3_CM_SHAPER_RAMA_REGION_2_3 0x1228 6067#define regCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 6068#define regCM3_CM_SHAPER_RAMA_REGION_4_5 0x1229 6069#define regCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 6070#define regCM3_CM_SHAPER_RAMA_REGION_6_7 0x122a 6071#define regCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 6072#define regCM3_CM_SHAPER_RAMA_REGION_8_9 0x122b 6073#define regCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 6074#define regCM3_CM_SHAPER_RAMA_REGION_10_11 0x122c 6075#define regCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 6076#define regCM3_CM_SHAPER_RAMA_REGION_12_13 0x122d 6077#define regCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 6078#define regCM3_CM_SHAPER_RAMA_REGION_14_15 0x122e 6079#define regCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 6080#define regCM3_CM_SHAPER_RAMA_REGION_16_17 0x122f 6081#define regCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 6082#define regCM3_CM_SHAPER_RAMA_REGION_18_19 0x1230 6083#define regCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 6084#define regCM3_CM_SHAPER_RAMA_REGION_20_21 0x1231 6085#define regCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 6086#define regCM3_CM_SHAPER_RAMA_REGION_22_23 0x1232 6087#define regCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 6088#define regCM3_CM_SHAPER_RAMA_REGION_24_25 0x1233 6089#define regCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 6090#define regCM3_CM_SHAPER_RAMA_REGION_26_27 0x1234 6091#define regCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 6092#define regCM3_CM_SHAPER_RAMA_REGION_28_29 0x1235 6093#define regCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 6094#define regCM3_CM_SHAPER_RAMA_REGION_30_31 0x1236 6095#define regCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 6096#define regCM3_CM_SHAPER_RAMA_REGION_32_33 0x1237 6097#define regCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 6098#define regCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1238 6099#define regCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 6100#define regCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1239 6101#define regCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 6102#define regCM3_CM_SHAPER_RAMB_START_CNTL_R 0x123a 6103#define regCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 6104#define regCM3_CM_SHAPER_RAMB_END_CNTL_B 0x123b 6105#define regCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 6106#define regCM3_CM_SHAPER_RAMB_END_CNTL_G 0x123c 6107#define regCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 6108#define regCM3_CM_SHAPER_RAMB_END_CNTL_R 0x123d 6109#define regCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 6110#define regCM3_CM_SHAPER_RAMB_REGION_0_1 0x123e 6111#define regCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 6112#define regCM3_CM_SHAPER_RAMB_REGION_2_3 0x123f 6113#define regCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 6114#define regCM3_CM_SHAPER_RAMB_REGION_4_5 0x1240 6115#define regCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 6116#define regCM3_CM_SHAPER_RAMB_REGION_6_7 0x1241 6117#define regCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 6118#define regCM3_CM_SHAPER_RAMB_REGION_8_9 0x1242 6119#define regCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 6120#define regCM3_CM_SHAPER_RAMB_REGION_10_11 0x1243 6121#define regCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 6122#define regCM3_CM_SHAPER_RAMB_REGION_12_13 0x1244 6123#define regCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 6124#define regCM3_CM_SHAPER_RAMB_REGION_14_15 0x1245 6125#define regCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 6126#define regCM3_CM_SHAPER_RAMB_REGION_16_17 0x1246 6127#define regCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 6128#define regCM3_CM_SHAPER_RAMB_REGION_18_19 0x1247 6129#define regCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 6130#define regCM3_CM_SHAPER_RAMB_REGION_20_21 0x1248 6131#define regCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 6132#define regCM3_CM_SHAPER_RAMB_REGION_22_23 0x1249 6133#define regCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 6134#define regCM3_CM_SHAPER_RAMB_REGION_24_25 0x124a 6135#define regCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 6136#define regCM3_CM_SHAPER_RAMB_REGION_26_27 0x124b 6137#define regCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 6138#define regCM3_CM_SHAPER_RAMB_REGION_28_29 0x124c 6139#define regCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 6140#define regCM3_CM_SHAPER_RAMB_REGION_30_31 0x124d 6141#define regCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 6142#define regCM3_CM_SHAPER_RAMB_REGION_32_33 0x124e 6143#define regCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 6144#define regCM3_CM_MEM_PWR_CTRL2 0x124f 6145#define regCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2 6146#define regCM3_CM_MEM_PWR_STATUS2 0x1250 6147#define regCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2 6148#define regCM3_CM_3DLUT_MODE 0x1251 6149#define regCM3_CM_3DLUT_MODE_BASE_IDX 2 6150#define regCM3_CM_3DLUT_INDEX 0x1252 6151#define regCM3_CM_3DLUT_INDEX_BASE_IDX 2 6152#define regCM3_CM_3DLUT_DATA 0x1253 6153#define regCM3_CM_3DLUT_DATA_BASE_IDX 2 6154#define regCM3_CM_3DLUT_DATA_30BIT 0x1254 6155#define regCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2 6156#define regCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1255 6157#define regCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 6158#define regCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1256 6159#define regCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 6160#define regCM3_CM_3DLUT_OUT_OFFSET_R 0x1257 6161#define regCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 6162#define regCM3_CM_3DLUT_OUT_OFFSET_G 0x1258 6163#define regCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 6164#define regCM3_CM_3DLUT_OUT_OFFSET_B 0x1259 6165#define regCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 6166#define regCM3_CM_TEST_DEBUG_INDEX 0x125a 6167#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 6168#define regCM3_CM_TEST_DEBUG_DATA 0x125b 6169#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 6170 6171 6172// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec 6173// base address: 0x1104 6174#define regDPP_TOP3_DPP_CONTROL 0x1106 6175#define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 6176#define regDPP_TOP3_DPP_SOFT_RESET 0x1107 6177#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 6178#define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 6179#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 6180#define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 6181#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 6182#define regDPP_TOP3_DPP_CRC_CTRL 0x110a 6183#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 6184#define regDPP_TOP3_HOST_READ_CONTROL 0x110b 6185#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 6186 6187 6188// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 6189// base address: 0x4994 6190#define regDC_PERFMON14_PERFCOUNTER_CNTL 0x1265 6191#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 6192#define regDC_PERFMON14_PERFCOUNTER_CNTL2 0x1266 6193#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 6194#define regDC_PERFMON14_PERFCOUNTER_STATE 0x1267 6195#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 6196#define regDC_PERFMON14_PERFMON_CNTL 0x1268 6197#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 6198#define regDC_PERFMON14_PERFMON_CNTL2 0x1269 6199#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 6200#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x126a 6201#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 6202#define regDC_PERFMON14_PERFMON_CVALUE_LOW 0x126b 6203#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 6204#define regDC_PERFMON14_PERFMON_HI 0x126c 6205#define regDC_PERFMON14_PERFMON_HI_BASE_IDX 2 6206#define regDC_PERFMON14_PERFMON_LOW 0x126d 6207#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 6208 6209 6210// addressBlock: dce_dc_mpc_mpcc0_dispdec 6211// base address: 0x0 6212#define regMPCC0_MPCC_TOP_SEL 0x0000 6213#define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 6214#define regMPCC0_MPCC_BOT_SEL 0x0001 6215#define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 6216#define regMPCC0_MPCC_OPP_ID 0x0002 6217#define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 6218#define regMPCC0_MPCC_CONTROL 0x0003 6219#define regMPCC0_MPCC_CONTROL_BASE_IDX 3 6220#define regMPCC0_MPCC_SM_CONTROL 0x0004 6221#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 6222#define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 6223#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6224#define regMPCC0_MPCC_TOP_GAIN 0x0006 6225#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 6226#define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 6227#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6228#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 6229#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6230#define regMPCC0_MPCC_BG_R_CR 0x0009 6231#define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 6232#define regMPCC0_MPCC_BG_G_Y 0x000a 6233#define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 6234#define regMPCC0_MPCC_BG_B_CB 0x000b 6235#define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 6236#define regMPCC0_MPCC_MEM_PWR_CTRL 0x000c 6237#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6238#define regMPCC0_MPCC_STATUS 0x000d 6239#define regMPCC0_MPCC_STATUS_BASE_IDX 3 6240 6241 6242// addressBlock: dce_dc_mpc_mpcc1_dispdec 6243// base address: 0x80 6244#define regMPCC1_MPCC_TOP_SEL 0x0020 6245#define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 6246#define regMPCC1_MPCC_BOT_SEL 0x0021 6247#define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 6248#define regMPCC1_MPCC_OPP_ID 0x0022 6249#define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 6250#define regMPCC1_MPCC_CONTROL 0x0023 6251#define regMPCC1_MPCC_CONTROL_BASE_IDX 3 6252#define regMPCC1_MPCC_SM_CONTROL 0x0024 6253#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 6254#define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025 6255#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6256#define regMPCC1_MPCC_TOP_GAIN 0x0026 6257#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 6258#define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027 6259#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6260#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028 6261#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6262#define regMPCC1_MPCC_BG_R_CR 0x0029 6263#define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 6264#define regMPCC1_MPCC_BG_G_Y 0x002a 6265#define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 6266#define regMPCC1_MPCC_BG_B_CB 0x002b 6267#define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 6268#define regMPCC1_MPCC_MEM_PWR_CTRL 0x002c 6269#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6270#define regMPCC1_MPCC_STATUS 0x002d 6271#define regMPCC1_MPCC_STATUS_BASE_IDX 3 6272 6273 6274// addressBlock: dce_dc_mpc_mpcc2_dispdec 6275// base address: 0x100 6276#define regMPCC2_MPCC_TOP_SEL 0x0040 6277#define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 6278#define regMPCC2_MPCC_BOT_SEL 0x0041 6279#define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 6280#define regMPCC2_MPCC_OPP_ID 0x0042 6281#define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 6282#define regMPCC2_MPCC_CONTROL 0x0043 6283#define regMPCC2_MPCC_CONTROL_BASE_IDX 3 6284#define regMPCC2_MPCC_SM_CONTROL 0x0044 6285#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 6286#define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x0045 6287#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6288#define regMPCC2_MPCC_TOP_GAIN 0x0046 6289#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 6290#define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0047 6291#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6292#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0048 6293#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6294#define regMPCC2_MPCC_BG_R_CR 0x0049 6295#define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 6296#define regMPCC2_MPCC_BG_G_Y 0x004a 6297#define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 6298#define regMPCC2_MPCC_BG_B_CB 0x004b 6299#define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 6300#define regMPCC2_MPCC_MEM_PWR_CTRL 0x004c 6301#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6302#define regMPCC2_MPCC_STATUS 0x004d 6303#define regMPCC2_MPCC_STATUS_BASE_IDX 3 6304 6305 6306// addressBlock: dce_dc_mpc_mpcc3_dispdec 6307// base address: 0x180 6308#define regMPCC3_MPCC_TOP_SEL 0x0060 6309#define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 6310#define regMPCC3_MPCC_BOT_SEL 0x0061 6311#define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 6312#define regMPCC3_MPCC_OPP_ID 0x0062 6313#define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 6314#define regMPCC3_MPCC_CONTROL 0x0063 6315#define regMPCC3_MPCC_CONTROL_BASE_IDX 3 6316#define regMPCC3_MPCC_SM_CONTROL 0x0064 6317#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 6318#define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0065 6319#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6320#define regMPCC3_MPCC_TOP_GAIN 0x0066 6321#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 6322#define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0067 6323#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6324#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0068 6325#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6326#define regMPCC3_MPCC_BG_R_CR 0x0069 6327#define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 6328#define regMPCC3_MPCC_BG_G_Y 0x006a 6329#define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 6330#define regMPCC3_MPCC_BG_B_CB 0x006b 6331#define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 6332#define regMPCC3_MPCC_MEM_PWR_CTRL 0x006c 6333#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6334#define regMPCC3_MPCC_STATUS 0x006d 6335#define regMPCC3_MPCC_STATUS_BASE_IDX 3 6336 6337 6338// addressBlock: dce_dc_mpc_mpc_cfg_dispdec 6339// base address: 0x0 6340#define regMPC_CLOCK_CONTROL 0x0500 6341#define regMPC_CLOCK_CONTROL_BASE_IDX 3 6342#define regMPC_SOFT_RESET 0x0501 6343#define regMPC_SOFT_RESET_BASE_IDX 3 6344#define regMPC_CRC_CTRL 0x0502 6345#define regMPC_CRC_CTRL_BASE_IDX 3 6346#define regMPC_CRC_SEL_CONTROL 0x0503 6347#define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 6348#define regMPC_CRC_RESULT_AR 0x0504 6349#define regMPC_CRC_RESULT_AR_BASE_IDX 3 6350#define regMPC_CRC_RESULT_GB 0x0505 6351#define regMPC_CRC_RESULT_GB_BASE_IDX 3 6352#define regMPC_CRC_RESULT_C 0x0506 6353#define regMPC_CRC_RESULT_C_BASE_IDX 3 6354#define regMPC_PERFMON_EVENT_CTRL 0x0509 6355#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 6356#define regMPC_BYPASS_BG_AR 0x050a 6357#define regMPC_BYPASS_BG_AR_BASE_IDX 3 6358#define regMPC_BYPASS_BG_GB 0x050b 6359#define regMPC_BYPASS_BG_GB_BASE_IDX 3 6360#define regMPC_HOST_READ_CONTROL 0x050c 6361#define regMPC_HOST_READ_CONTROL_BASE_IDX 3 6362#define regMPC_DPP_PENDING_STATUS 0x050d 6363#define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 6364#define regMPC_PENDING_STATUS_MISC 0x050e 6365#define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 6366#define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f 6367#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 6368#define regADR_CFG_VUPDATE_LOCK_SET0 0x0510 6369#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 6370#define regADR_VUPDATE_LOCK_SET0 0x0511 6371#define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 6372#define regCFG_VUPDATE_LOCK_SET0 0x0512 6373#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 6374#define regCUR_VUPDATE_LOCK_SET0 0x0513 6375#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 6376#define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514 6377#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 6378#define regADR_CFG_VUPDATE_LOCK_SET1 0x0515 6379#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 6380#define regADR_VUPDATE_LOCK_SET1 0x0516 6381#define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 6382#define regCFG_VUPDATE_LOCK_SET1 0x0517 6383#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 6384#define regCUR_VUPDATE_LOCK_SET1 0x0518 6385#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 6386#define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x0519 6387#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 6388#define regADR_CFG_VUPDATE_LOCK_SET2 0x051a 6389#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 6390#define regADR_VUPDATE_LOCK_SET2 0x051b 6391#define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 6392#define regCFG_VUPDATE_LOCK_SET2 0x051c 6393#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 6394#define regCUR_VUPDATE_LOCK_SET2 0x051d 6395#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 6396#define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x051e 6397#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 6398#define regADR_CFG_VUPDATE_LOCK_SET3 0x051f 6399#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 6400#define regADR_VUPDATE_LOCK_SET3 0x0520 6401#define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 6402#define regCFG_VUPDATE_LOCK_SET3 0x0521 6403#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 6404#define regCUR_VUPDATE_LOCK_SET3 0x0522 6405#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 6406#define regMPC_DWB0_MUX 0x055c 6407#define regMPC_DWB0_MUX_BASE_IDX 3 6408 6409 6410// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec 6411// base address: 0x1901c 6412#define regDC_PERFMON15_PERFCOUNTER_CNTL 0x08c7 6413#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 3 6414#define regDC_PERFMON15_PERFCOUNTER_CNTL2 0x08c8 6415#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 3 6416#define regDC_PERFMON15_PERFCOUNTER_STATE 0x08c9 6417#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 3 6418#define regDC_PERFMON15_PERFMON_CNTL 0x08ca 6419#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX 3 6420#define regDC_PERFMON15_PERFMON_CNTL2 0x08cb 6421#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 3 6422#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x08cc 6423#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 6424#define regDC_PERFMON15_PERFMON_CVALUE_LOW 0x08cd 6425#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 3 6426#define regDC_PERFMON15_PERFMON_HI 0x08ce 6427#define regDC_PERFMON15_PERFMON_HI_BASE_IDX 3 6428#define regDC_PERFMON15_PERFMON_LOW 0x08cf 6429#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 6430 6431 6432// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec 6433// base address: 0x0 6434#define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100 6435#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 6436#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101 6437#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 6438#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102 6439#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 6440#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103 6441#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 6442#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104 6443#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 6444#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105 6445#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 6446#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106 6447#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 6448#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107 6449#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6450#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108 6451#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6452#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109 6453#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6454#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a 6455#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6456#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b 6457#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6458#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c 6459#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6460#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d 6461#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 6462#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e 6463#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 6464#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f 6465#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 6466#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110 6467#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 6468#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111 6469#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 6470#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112 6471#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 6472#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113 6473#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 6474#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114 6475#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 6476#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115 6477#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 6478#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116 6479#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 6480#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117 6481#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 6482#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118 6483#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 6484#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119 6485#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 6486#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a 6487#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 6488#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b 6489#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 6490#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c 6491#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 6492#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d 6493#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 6494#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e 6495#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 6496#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f 6497#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 6498#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120 6499#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 6500#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121 6501#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 6502#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122 6503#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 6504#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123 6505#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 6506#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124 6507#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 6508#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125 6509#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 6510#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126 6511#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 6512#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127 6513#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 6514#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128 6515#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 6516#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129 6517#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 6518#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a 6519#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6520#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b 6521#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6522#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c 6523#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6524#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d 6525#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6526#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e 6527#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6528#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f 6529#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6530#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130 6531#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 6532#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131 6533#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 6534#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132 6535#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 6536#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133 6537#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 6538#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134 6539#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 6540#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135 6541#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 6542#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136 6543#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 6544#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137 6545#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 6546#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138 6547#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 6548#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139 6549#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 6550#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a 6551#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 6552#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b 6553#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 6554#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c 6555#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 6556#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d 6557#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 6558#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e 6559#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 6560#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f 6561#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 6562#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140 6563#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 6564#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141 6565#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 6566#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142 6567#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 6568#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143 6569#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 6570#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144 6571#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 6572#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145 6573#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 6574#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146 6575#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 6576#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147 6577#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 6578#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148 6579#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 6580#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149 6581#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 6582#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a 6583#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6584#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b 6585#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 6586#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c 6587#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6588#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d 6589#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6590#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e 6591#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6592#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f 6593#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6594#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150 6595#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6596#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151 6597#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6598#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152 6599#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6600#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153 6601#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6602#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154 6603#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6604#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155 6605#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6606#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156 6607#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6608#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157 6609#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6610 6611 6612// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec 6613// base address: 0x200 6614#define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180 6615#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 6616#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181 6617#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 6618#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182 6619#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 6620#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183 6621#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 6622#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184 6623#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 6624#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185 6625#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 6626#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186 6627#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 6628#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187 6629#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6630#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188 6631#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6632#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189 6633#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6634#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a 6635#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6636#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b 6637#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6638#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c 6639#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6640#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d 6641#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 6642#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e 6643#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 6644#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f 6645#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 6646#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190 6647#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 6648#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191 6649#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 6650#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192 6651#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 6652#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193 6653#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 6654#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194 6655#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 6656#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195 6657#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 6658#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196 6659#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 6660#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197 6661#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 6662#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198 6663#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 6664#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199 6665#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 6666#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a 6667#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 6668#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b 6669#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 6670#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c 6671#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 6672#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d 6673#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 6674#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e 6675#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 6676#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f 6677#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 6678#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0 6679#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 6680#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1 6681#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 6682#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2 6683#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 6684#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3 6685#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 6686#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4 6687#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 6688#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5 6689#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 6690#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6 6691#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 6692#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7 6693#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 6694#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8 6695#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 6696#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9 6697#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 6698#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa 6699#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6700#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab 6701#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6702#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac 6703#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6704#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad 6705#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6706#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae 6707#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6708#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af 6709#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6710#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0 6711#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 6712#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1 6713#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 6714#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2 6715#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 6716#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3 6717#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 6718#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4 6719#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 6720#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5 6721#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 6722#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6 6723#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 6724#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7 6725#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 6726#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8 6727#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 6728#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9 6729#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 6730#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba 6731#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 6732#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb 6733#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 6734#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc 6735#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 6736#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd 6737#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 6738#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be 6739#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 6740#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf 6741#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 6742#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0 6743#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 6744#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1 6745#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 6746#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2 6747#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 6748#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3 6749#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 6750#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4 6751#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 6752#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5 6753#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 6754#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6 6755#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 6756#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7 6757#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 6758#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8 6759#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 6760#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9 6761#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 6762#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca 6763#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6764#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb 6765#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 6766#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc 6767#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6768#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd 6769#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6770#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce 6771#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6772#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf 6773#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6774#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0 6775#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6776#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1 6777#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6778#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2 6779#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6780#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3 6781#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6782#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4 6783#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6784#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5 6785#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6786#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6 6787#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6788#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7 6789#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6790 6791 6792// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec 6793// base address: 0x400 6794#define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0200 6795#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 6796#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0201 6797#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 6798#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0202 6799#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 6800#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0203 6801#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 6802#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0204 6803#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 6804#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0205 6805#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 6806#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0206 6807#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 6808#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0207 6809#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6810#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0208 6811#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6812#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0209 6813#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6814#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x020a 6815#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6816#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x020b 6817#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6818#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x020c 6819#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6820#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x020d 6821#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 6822#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x020e 6823#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 6824#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x020f 6825#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 6826#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0210 6827#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 6828#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0211 6829#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 6830#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0212 6831#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 6832#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0213 6833#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 6834#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0214 6835#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 6836#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0215 6837#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 6838#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0216 6839#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 6840#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0217 6841#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 6842#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0218 6843#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 6844#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0219 6845#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 6846#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x021a 6847#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 6848#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x021b 6849#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 6850#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x021c 6851#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 6852#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x021d 6853#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 6854#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x021e 6855#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 6856#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x021f 6857#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 6858#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0220 6859#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 6860#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0221 6861#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 6862#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0222 6863#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 6864#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0223 6865#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 6866#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0224 6867#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 6868#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0225 6869#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 6870#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0226 6871#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 6872#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0227 6873#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 6874#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0228 6875#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 6876#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0229 6877#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 6878#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x022a 6879#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6880#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x022b 6881#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6882#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x022c 6883#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6884#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x022d 6885#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6886#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x022e 6887#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6888#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x022f 6889#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6890#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0230 6891#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 6892#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0231 6893#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 6894#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0232 6895#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 6896#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0233 6897#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 6898#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0234 6899#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 6900#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0235 6901#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 6902#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0236 6903#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 6904#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0237 6905#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 6906#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0238 6907#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 6908#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0239 6909#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 6910#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x023a 6911#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 6912#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x023b 6913#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 6914#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x023c 6915#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 6916#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x023d 6917#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 6918#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x023e 6919#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 6920#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x023f 6921#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 6922#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x0240 6923#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 6924#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x0241 6925#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 6926#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x0242 6927#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 6928#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x0243 6929#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 6930#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x0244 6931#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 6932#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x0245 6933#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 6934#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0246 6935#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 6936#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0247 6937#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 6938#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0248 6939#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 6940#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0249 6941#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 6942#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x024a 6943#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6944#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x024b 6945#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 6946#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x024c 6947#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6948#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x024d 6949#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6950#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x024e 6951#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6952#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x024f 6953#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6954#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x0250 6955#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6956#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x0251 6957#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6958#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x0252 6959#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6960#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x0253 6961#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6962#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x0254 6963#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6964#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x0255 6965#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6966#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0256 6967#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6968#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0257 6969#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6970 6971 6972// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec 6973// base address: 0x600 6974#define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0280 6975#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 6976#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0281 6977#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 6978#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x0282 6979#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 6980#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x0283 6981#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 6982#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x0284 6983#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 6984#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x0285 6985#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 6986#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x0286 6987#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 6988#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0287 6989#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6990#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0288 6991#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6992#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0289 6993#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6994#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x028a 6995#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6996#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x028b 6997#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6998#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x028c 6999#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 7000#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x028d 7001#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 7002#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x028e 7003#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 7004#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x028f 7005#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 7006#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x0290 7007#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 7008#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x0291 7009#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 7010#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x0292 7011#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 7012#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x0293 7013#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 7014#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x0294 7015#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 7016#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x0295 7017#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 7018#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x0296 7019#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 7020#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x0297 7021#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 7022#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x0298 7023#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 7024#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x0299 7025#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 7026#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x029a 7027#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 7028#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x029b 7029#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 7030#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x029c 7031#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 7032#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x029d 7033#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 7034#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x029e 7035#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 7036#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x029f 7037#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 7038#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x02a0 7039#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 7040#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x02a1 7041#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 7042#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x02a2 7043#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 7044#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x02a3 7045#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 7046#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x02a4 7047#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 7048#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x02a5 7049#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 7050#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x02a6 7051#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 7052#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x02a7 7053#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 7054#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x02a8 7055#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 7056#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x02a9 7057#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 7058#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x02aa 7059#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 7060#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x02ab 7061#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 7062#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x02ac 7063#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 7064#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x02ad 7065#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 7066#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x02ae 7067#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 7068#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x02af 7069#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 7070#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x02b0 7071#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 7072#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x02b1 7073#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 7074#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x02b2 7075#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 7076#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x02b3 7077#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 7078#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x02b4 7079#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 7080#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x02b5 7081#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 7082#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x02b6 7083#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 7084#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x02b7 7085#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 7086#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x02b8 7087#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 7088#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x02b9 7089#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 7090#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x02ba 7091#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 7092#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x02bb 7093#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 7094#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x02bc 7095#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 7096#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x02bd 7097#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 7098#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x02be 7099#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 7100#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x02bf 7101#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 7102#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x02c0 7103#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 7104#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x02c1 7105#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 7106#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x02c2 7107#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 7108#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x02c3 7109#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 7110#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x02c4 7111#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 7112#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x02c5 7113#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 7114#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x02c6 7115#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 7116#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x02c7 7117#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 7118#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x02c8 7119#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 7120#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x02c9 7121#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 7122#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x02ca 7123#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7124#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x02cb 7125#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 7126#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x02cc 7127#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7128#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x02cd 7129#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7130#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x02ce 7131#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7132#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x02cf 7133#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7134#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x02d0 7135#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7136#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x02d1 7137#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7138#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x02d2 7139#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7140#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x02d3 7141#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7142#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x02d4 7143#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7144#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x02d5 7145#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7146#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x02d6 7147#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7148#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x02d7 7149#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7150 7151 7152// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec 7153// base address: 0x0 7154#define regMPC_OUT0_MUX 0x0580 7155#define regMPC_OUT0_MUX_BASE_IDX 3 7156#define regMPC_OUT0_DENORM_CONTROL 0x0581 7157#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 7158#define regMPC_OUT0_DENORM_CLAMP_G_Y 0x0582 7159#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 7160#define regMPC_OUT0_DENORM_CLAMP_B_CB 0x0583 7161#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 7162#define regMPC_OUT1_MUX 0x0584 7163#define regMPC_OUT1_MUX_BASE_IDX 3 7164#define regMPC_OUT1_DENORM_CONTROL 0x0585 7165#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 7166#define regMPC_OUT1_DENORM_CLAMP_G_Y 0x0586 7167#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 7168#define regMPC_OUT1_DENORM_CLAMP_B_CB 0x0587 7169#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 7170#define regMPC_OUT2_MUX 0x0588 7171#define regMPC_OUT2_MUX_BASE_IDX 3 7172#define regMPC_OUT2_DENORM_CONTROL 0x0589 7173#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 7174#define regMPC_OUT2_DENORM_CLAMP_G_Y 0x058a 7175#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 7176#define regMPC_OUT2_DENORM_CLAMP_B_CB 0x058b 7177#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 7178#define regMPC_OUT3_MUX 0x058c 7179#define regMPC_OUT3_MUX_BASE_IDX 3 7180#define regMPC_OUT3_DENORM_CONTROL 0x058d 7181#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 7182#define regMPC_OUT3_DENORM_CLAMP_G_Y 0x058e 7183#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 7184#define regMPC_OUT3_DENORM_CLAMP_B_CB 0x058f 7185#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 7186#define regMPC_OUT_CSC_COEF_FORMAT 0x05a0 7187#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 7188#define regMPC_OUT0_CSC_MODE 0x05a1 7189#define regMPC_OUT0_CSC_MODE_BASE_IDX 3 7190#define regMPC_OUT0_CSC_C11_C12_A 0x05a2 7191#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 7192#define regMPC_OUT0_CSC_C13_C14_A 0x05a3 7193#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 7194#define regMPC_OUT0_CSC_C21_C22_A 0x05a4 7195#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 7196#define regMPC_OUT0_CSC_C23_C24_A 0x05a5 7197#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 7198#define regMPC_OUT0_CSC_C31_C32_A 0x05a6 7199#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 7200#define regMPC_OUT0_CSC_C33_C34_A 0x05a7 7201#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 7202#define regMPC_OUT0_CSC_C11_C12_B 0x05a8 7203#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 7204#define regMPC_OUT0_CSC_C13_C14_B 0x05a9 7205#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 7206#define regMPC_OUT0_CSC_C21_C22_B 0x05aa 7207#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 7208#define regMPC_OUT0_CSC_C23_C24_B 0x05ab 7209#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 7210#define regMPC_OUT0_CSC_C31_C32_B 0x05ac 7211#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 7212#define regMPC_OUT0_CSC_C33_C34_B 0x05ad 7213#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 7214#define regMPC_OUT1_CSC_MODE 0x05ae 7215#define regMPC_OUT1_CSC_MODE_BASE_IDX 3 7216#define regMPC_OUT1_CSC_C11_C12_A 0x05af 7217#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 7218#define regMPC_OUT1_CSC_C13_C14_A 0x05b0 7219#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 7220#define regMPC_OUT1_CSC_C21_C22_A 0x05b1 7221#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 7222#define regMPC_OUT1_CSC_C23_C24_A 0x05b2 7223#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 7224#define regMPC_OUT1_CSC_C31_C32_A 0x05b3 7225#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 7226#define regMPC_OUT1_CSC_C33_C34_A 0x05b4 7227#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 7228#define regMPC_OUT1_CSC_C11_C12_B 0x05b5 7229#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 7230#define regMPC_OUT1_CSC_C13_C14_B 0x05b6 7231#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 7232#define regMPC_OUT1_CSC_C21_C22_B 0x05b7 7233#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 7234#define regMPC_OUT1_CSC_C23_C24_B 0x05b8 7235#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 7236#define regMPC_OUT1_CSC_C31_C32_B 0x05b9 7237#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 7238#define regMPC_OUT1_CSC_C33_C34_B 0x05ba 7239#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 7240#define regMPC_OUT2_CSC_MODE 0x05bb 7241#define regMPC_OUT2_CSC_MODE_BASE_IDX 3 7242#define regMPC_OUT2_CSC_C11_C12_A 0x05bc 7243#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 7244#define regMPC_OUT2_CSC_C13_C14_A 0x05bd 7245#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 7246#define regMPC_OUT2_CSC_C21_C22_A 0x05be 7247#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 7248#define regMPC_OUT2_CSC_C23_C24_A 0x05bf 7249#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 7250#define regMPC_OUT2_CSC_C31_C32_A 0x05c0 7251#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 7252#define regMPC_OUT2_CSC_C33_C34_A 0x05c1 7253#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 7254#define regMPC_OUT2_CSC_C11_C12_B 0x05c2 7255#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 7256#define regMPC_OUT2_CSC_C13_C14_B 0x05c3 7257#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 7258#define regMPC_OUT2_CSC_C21_C22_B 0x05c4 7259#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 7260#define regMPC_OUT2_CSC_C23_C24_B 0x05c5 7261#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 7262#define regMPC_OUT2_CSC_C31_C32_B 0x05c6 7263#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 7264#define regMPC_OUT2_CSC_C33_C34_B 0x05c7 7265#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 7266#define regMPC_OUT3_CSC_MODE 0x05c8 7267#define regMPC_OUT3_CSC_MODE_BASE_IDX 3 7268#define regMPC_OUT3_CSC_C11_C12_A 0x05c9 7269#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 7270#define regMPC_OUT3_CSC_C13_C14_A 0x05ca 7271#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 7272#define regMPC_OUT3_CSC_C21_C22_A 0x05cb 7273#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 7274#define regMPC_OUT3_CSC_C23_C24_A 0x05cc 7275#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 7276#define regMPC_OUT3_CSC_C31_C32_A 0x05cd 7277#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 7278#define regMPC_OUT3_CSC_C33_C34_A 0x05ce 7279#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 7280#define regMPC_OUT3_CSC_C11_C12_B 0x05cf 7281#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 7282#define regMPC_OUT3_CSC_C13_C14_B 0x05d0 7283#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 7284#define regMPC_OUT3_CSC_C21_C22_B 0x05d1 7285#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 7286#define regMPC_OUT3_CSC_C23_C24_B 0x05d2 7287#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 7288#define regMPC_OUT3_CSC_C31_C32_B 0x05d3 7289#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 7290#define regMPC_OUT3_CSC_C33_C34_B 0x05d4 7291#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 7292#define regMPC_OCSC_TEST_DEBUG_INDEX 0x0605 7293#define regMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX 3 7294#define regMPC_OCSC_TEST_DEBUG_DATA 0x0606 7295#define regMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX 3 7296 7297 7298// addressBlock: dce_dc_mpc_mpc_rmu_dispdec 7299// base address: 0x0 7300#define regMPC_RMU_CONTROL 0x0680 7301#define regMPC_RMU_CONTROL_BASE_IDX 3 7302#define regMPC_RMU_MEM_PWR_CTRL 0x0681 7303#define regMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3 7304#define regMPC_RMU0_SHAPER_CONTROL 0x0682 7305#define regMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3 7306#define regMPC_RMU0_SHAPER_OFFSET_R 0x0683 7307#define regMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3 7308#define regMPC_RMU0_SHAPER_OFFSET_G 0x0684 7309#define regMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3 7310#define regMPC_RMU0_SHAPER_OFFSET_B 0x0685 7311#define regMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3 7312#define regMPC_RMU0_SHAPER_SCALE_R 0x0686 7313#define regMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3 7314#define regMPC_RMU0_SHAPER_SCALE_G_B 0x0687 7315#define regMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3 7316#define regMPC_RMU0_SHAPER_LUT_INDEX 0x0688 7317#define regMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3 7318#define regMPC_RMU0_SHAPER_LUT_DATA 0x0689 7319#define regMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3 7320#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a 7321#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 7322#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b 7323#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 7324#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c 7325#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 7326#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d 7327#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 7328#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e 7329#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 7330#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f 7331#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 7332#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690 7333#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 7334#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691 7335#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 7336#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692 7337#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 7338#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693 7339#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 7340#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694 7341#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 7342#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695 7343#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 7344#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696 7345#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 7346#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697 7347#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 7348#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698 7349#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 7350#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699 7351#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 7352#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a 7353#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 7354#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b 7355#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 7356#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c 7357#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 7358#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d 7359#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 7360#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e 7361#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 7362#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f 7363#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 7364#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0 7365#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 7366#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1 7367#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 7368#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2 7369#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 7370#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3 7371#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 7372#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4 7373#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 7374#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5 7375#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 7376#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6 7377#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 7378#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7 7379#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 7380#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8 7381#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 7382#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9 7383#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 7384#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa 7385#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 7386#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab 7387#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 7388#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac 7389#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 7390#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad 7391#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 7392#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae 7393#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 7394#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af 7395#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 7396#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0 7397#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 7398#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1 7399#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 7400#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2 7401#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 7402#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3 7403#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 7404#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4 7405#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 7406#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5 7407#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 7408#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6 7409#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 7410#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7 7411#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 7412#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8 7413#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 7414#define regMPC_RMU0_3DLUT_MODE 0x06b9 7415#define regMPC_RMU0_3DLUT_MODE_BASE_IDX 3 7416#define regMPC_RMU0_3DLUT_INDEX 0x06ba 7417#define regMPC_RMU0_3DLUT_INDEX_BASE_IDX 3 7418#define regMPC_RMU0_3DLUT_DATA 0x06bb 7419#define regMPC_RMU0_3DLUT_DATA_BASE_IDX 3 7420#define regMPC_RMU0_3DLUT_DATA_30BIT 0x06bc 7421#define regMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3 7422#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd 7423#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 7424#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be 7425#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 7426#define regMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf 7427#define regMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3 7428#define regMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0 7429#define regMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3 7430#define regMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1 7431#define regMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3 7432#define regMPC_RMU1_SHAPER_CONTROL 0x06c2 7433#define regMPC_RMU1_SHAPER_CONTROL_BASE_IDX 3 7434#define regMPC_RMU1_SHAPER_OFFSET_R 0x06c3 7435#define regMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX 3 7436#define regMPC_RMU1_SHAPER_OFFSET_G 0x06c4 7437#define regMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX 3 7438#define regMPC_RMU1_SHAPER_OFFSET_B 0x06c5 7439#define regMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX 3 7440#define regMPC_RMU1_SHAPER_SCALE_R 0x06c6 7441#define regMPC_RMU1_SHAPER_SCALE_R_BASE_IDX 3 7442#define regMPC_RMU1_SHAPER_SCALE_G_B 0x06c7 7443#define regMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX 3 7444#define regMPC_RMU1_SHAPER_LUT_INDEX 0x06c8 7445#define regMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX 3 7446#define regMPC_RMU1_SHAPER_LUT_DATA 0x06c9 7447#define regMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX 3 7448#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK 0x06ca 7449#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 7450#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B 0x06cb 7451#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 7452#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G 0x06cc 7453#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 7454#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R 0x06cd 7455#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 7456#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B 0x06ce 7457#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 7458#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G 0x06cf 7459#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 7460#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R 0x06d0 7461#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 7462#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1 0x06d1 7463#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 7464#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3 0x06d2 7465#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 7466#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5 0x06d3 7467#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 7468#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7 0x06d4 7469#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 7470#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9 0x06d5 7471#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 7472#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11 0x06d6 7473#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 7474#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13 0x06d7 7475#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 7476#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15 0x06d8 7477#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 7478#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17 0x06d9 7479#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 7480#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19 0x06da 7481#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 7482#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21 0x06db 7483#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 7484#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23 0x06dc 7485#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 7486#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25 0x06dd 7487#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 7488#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27 0x06de 7489#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 7490#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29 0x06df 7491#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 7492#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31 0x06e0 7493#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 7494#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33 0x06e1 7495#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 7496#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B 0x06e2 7497#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 7498#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G 0x06e3 7499#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 7500#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R 0x06e4 7501#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 7502#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B 0x06e5 7503#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 7504#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G 0x06e6 7505#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 7506#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R 0x06e7 7507#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 7508#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1 0x06e8 7509#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 7510#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3 0x06e9 7511#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 7512#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5 0x06ea 7513#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 7514#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7 0x06eb 7515#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 7516#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9 0x06ec 7517#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 7518#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11 0x06ed 7519#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 7520#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13 0x06ee 7521#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 7522#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15 0x06ef 7523#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 7524#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17 0x06f0 7525#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 7526#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19 0x06f1 7527#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 7528#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21 0x06f2 7529#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 7530#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23 0x06f3 7531#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 7532#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25 0x06f4 7533#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 7534#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27 0x06f5 7535#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 7536#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29 0x06f6 7537#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 7538#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31 0x06f7 7539#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 7540#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33 0x06f8 7541#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 7542#define regMPC_RMU1_3DLUT_MODE 0x06f9 7543#define regMPC_RMU1_3DLUT_MODE_BASE_IDX 3 7544#define regMPC_RMU1_3DLUT_INDEX 0x06fa 7545#define regMPC_RMU1_3DLUT_INDEX_BASE_IDX 3 7546#define regMPC_RMU1_3DLUT_DATA 0x06fb 7547#define regMPC_RMU1_3DLUT_DATA_BASE_IDX 3 7548#define regMPC_RMU1_3DLUT_DATA_30BIT 0x06fc 7549#define regMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX 3 7550#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL 0x06fd 7551#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 7552#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR 0x06fe 7553#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 7554#define regMPC_RMU1_3DLUT_OUT_OFFSET_R 0x06ff 7555#define regMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX 3 7556#define regMPC_RMU1_3DLUT_OUT_OFFSET_G 0x0700 7557#define regMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX 3 7558#define regMPC_RMU1_3DLUT_OUT_OFFSET_B 0x0701 7559#define regMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX 3 7560 7561 7562// addressBlock: dce_dc_opp_abm0_dispdec 7563// base address: 0x0 7564#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a 7565#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7566#define regABM0_BL1_PWM_USER_LEVEL 0x0e7b 7567#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 7568#define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c 7569#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7570#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d 7571#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7572#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e 7573#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7574#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f 7575#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7576#define regABM0_BL1_PWM_ABM_CNTL 0x0e80 7577#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 7578#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 7579#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7580#define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 7581#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7582#define regABM0_DC_ABM1_CNTL 0x0e83 7583#define regABM0_DC_ABM1_CNTL_BASE_IDX 3 7584#define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 7585#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7586#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 7587#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7588#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 7589#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7590#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 7591#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7592#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 7593#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7594#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 7595#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7596#define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a 7597#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7598#define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b 7599#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7600#define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c 7601#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7602#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e 7603#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7604#define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f 7605#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7606#define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 7607#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7608#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 7609#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7610#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 7611#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7612#define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 7613#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7614#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 7615#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7616#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 7617#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7618#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 7619#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7620#define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 7621#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7622#define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 7623#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7624#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 7625#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7626#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a 7627#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7628#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b 7629#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7630#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c 7631#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7632#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d 7633#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7634#define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e 7635#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7636#define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f 7637#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7638#define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 7639#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7640#define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 7641#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7642#define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 7643#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7644#define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 7645#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7646#define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 7647#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7648#define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 7649#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7650#define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 7651#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7652#define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 7653#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7654#define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 7655#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7656#define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 7657#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7658#define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa 7659#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7660#define regABM0_DC_ABM1_HG_RESULT_14 0x0eab 7661#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7662#define regABM0_DC_ABM1_HG_RESULT_15 0x0eac 7663#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7664#define regABM0_DC_ABM1_HG_RESULT_16 0x0ead 7665#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7666#define regABM0_DC_ABM1_HG_RESULT_17 0x0eae 7667#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7668#define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf 7669#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7670#define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 7671#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7672#define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 7673#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7674#define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 7675#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7676#define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 7677#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7678#define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 7679#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7680#define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 7681#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7682#define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 7683#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7684 7685 7686// addressBlock: dce_dc_opp_abm1_dispdec 7687// base address: 0x104 7688#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb 7689#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7690#define regABM1_BL1_PWM_USER_LEVEL 0x0ebc 7691#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 7692#define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd 7693#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7694#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe 7695#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7696#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf 7697#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7698#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 7699#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7700#define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 7701#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 7702#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 7703#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7704#define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 7705#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7706#define regABM1_DC_ABM1_CNTL 0x0ec4 7707#define regABM1_DC_ABM1_CNTL_BASE_IDX 3 7708#define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 7709#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7710#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 7711#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7712#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 7713#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7714#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 7715#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7716#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 7717#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7718#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca 7719#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7720#define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb 7721#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7722#define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc 7723#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7724#define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd 7725#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7726#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf 7727#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7728#define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 7729#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7730#define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 7731#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7732#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 7733#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7734#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 7735#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7736#define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 7737#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7738#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 7739#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7740#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 7741#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7742#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 7743#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7744#define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 7745#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7746#define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 7747#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7748#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda 7749#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7750#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb 7751#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7752#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc 7753#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7754#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd 7755#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7756#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede 7757#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7758#define regABM1_DC_ABM1_HG_RESULT_1 0x0edf 7759#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7760#define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 7761#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7762#define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 7763#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7764#define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 7765#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7766#define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 7767#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7768#define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 7769#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7770#define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 7771#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7772#define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 7773#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7774#define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 7775#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7776#define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 7777#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7778#define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 7779#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7780#define regABM1_DC_ABM1_HG_RESULT_12 0x0eea 7781#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7782#define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb 7783#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7784#define regABM1_DC_ABM1_HG_RESULT_14 0x0eec 7785#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7786#define regABM1_DC_ABM1_HG_RESULT_15 0x0eed 7787#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7788#define regABM1_DC_ABM1_HG_RESULT_16 0x0eee 7789#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7790#define regABM1_DC_ABM1_HG_RESULT_17 0x0eef 7791#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7792#define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 7793#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7794#define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 7795#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7796#define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 7797#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7798#define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 7799#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7800#define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 7801#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7802#define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 7803#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7804#define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 7805#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7806#define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 7807#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7808 7809 7810// addressBlock: dce_dc_opp_abm2_dispdec 7811// base address: 0x208 7812#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc 7813#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7814#define regABM2_BL1_PWM_USER_LEVEL 0x0efd 7815#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 7816#define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe 7817#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7818#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff 7819#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7820#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 7821#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7822#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 7823#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7824#define regABM2_BL1_PWM_ABM_CNTL 0x0f02 7825#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 7826#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 7827#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7828#define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 7829#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7830#define regABM2_DC_ABM1_CNTL 0x0f05 7831#define regABM2_DC_ABM1_CNTL_BASE_IDX 3 7832#define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 7833#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7834#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 7835#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7836#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 7837#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7838#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 7839#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7840#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a 7841#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7842#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b 7843#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7844#define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c 7845#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7846#define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d 7847#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7848#define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e 7849#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7850#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 7851#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7852#define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 7853#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7854#define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 7855#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7856#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 7857#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7858#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 7859#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7860#define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 7861#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7862#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 7863#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7864#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 7865#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7866#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 7867#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7868#define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 7869#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7870#define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a 7871#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7872#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b 7873#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7874#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c 7875#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7876#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d 7877#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7878#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e 7879#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7880#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f 7881#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7882#define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 7883#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7884#define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 7885#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7886#define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 7887#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7888#define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 7889#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7890#define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 7891#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7892#define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 7893#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7894#define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 7895#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7896#define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 7897#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7898#define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 7899#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7900#define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 7901#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7902#define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a 7903#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7904#define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b 7905#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7906#define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c 7907#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7908#define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d 7909#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7910#define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e 7911#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7912#define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f 7913#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7914#define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 7915#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7916#define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 7917#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7918#define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 7919#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7920#define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 7921#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7922#define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 7923#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7924#define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 7925#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7926#define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 7927#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7928#define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 7929#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7930#define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 7931#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7932 7933 7934// addressBlock: dce_dc_opp_abm3_dispdec 7935// base address: 0x30c 7936#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d 7937#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7938#define regABM3_BL1_PWM_USER_LEVEL 0x0f3e 7939#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 7940#define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f 7941#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7942#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 7943#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7944#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 7945#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7946#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 7947#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7948#define regABM3_BL1_PWM_ABM_CNTL 0x0f43 7949#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 7950#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 7951#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7952#define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 7953#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7954#define regABM3_DC_ABM1_CNTL 0x0f46 7955#define regABM3_DC_ABM1_CNTL_BASE_IDX 3 7956#define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 7957#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7958#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 7959#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7960#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 7961#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7962#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a 7963#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7964#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b 7965#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7966#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c 7967#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7968#define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d 7969#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7970#define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e 7971#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7972#define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f 7973#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7974#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 7975#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7976#define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 7977#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7978#define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 7979#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7980#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 7981#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7982#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 7983#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7984#define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 7985#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7986#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 7987#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7988#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 7989#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7990#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 7991#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7992#define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a 7993#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7994#define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b 7995#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7996#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c 7997#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7998#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d 7999#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 8000#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e 8001#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 8002#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f 8003#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 8004#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 8005#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 8006#define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 8007#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 8008#define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 8009#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 8010#define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 8011#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 8012#define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 8013#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 8014#define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 8015#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 8016#define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 8017#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 8018#define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 8019#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 8020#define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 8021#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 8022#define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 8023#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 8024#define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a 8025#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 8026#define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b 8027#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 8028#define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c 8029#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 8030#define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d 8031#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 8032#define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e 8033#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 8034#define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f 8035#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 8036#define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 8037#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 8038#define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 8039#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 8040#define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 8041#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 8042#define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 8043#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 8044#define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 8045#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 8046#define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 8047#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 8048#define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 8049#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 8050#define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 8051#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 8052#define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 8053#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 8054#define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 8055#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 8056 8057 8058// addressBlock: dce_dc_opp_dpg0_dispdec 8059// base address: 0x0 8060#define regDPG0_DPG_CONTROL 0x1854 8061#define regDPG0_DPG_CONTROL_BASE_IDX 2 8062#define regDPG0_DPG_RAMP_CONTROL 0x1855 8063#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 8064#define regDPG0_DPG_DIMENSIONS 0x1856 8065#define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 8066#define regDPG0_DPG_COLOUR_R_CR 0x1857 8067#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 8068#define regDPG0_DPG_COLOUR_G_Y 0x1858 8069#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 8070#define regDPG0_DPG_COLOUR_B_CB 0x1859 8071#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 8072#define regDPG0_DPG_OFFSET_SEGMENT 0x185a 8073#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 8074#define regDPG0_DPG_STATUS 0x185b 8075#define regDPG0_DPG_STATUS_BASE_IDX 2 8076 8077 8078// addressBlock: dce_dc_opp_fmt0_dispdec 8079// base address: 0x0 8080#define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c 8081#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8082#define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d 8083#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8084#define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e 8085#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8086#define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 8087#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8088#define regFMT0_FMT_CONTROL 0x1840 8089#define regFMT0_FMT_CONTROL_BASE_IDX 2 8090#define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 8091#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8092#define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 8093#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8094#define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 8095#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8096#define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 8097#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8098#define regFMT0_FMT_CLAMP_CNTL 0x1845 8099#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 8100#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 8101#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8102#define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 8103#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8104#define regFMT0_FMT_422_CONTROL 0x1849 8105#define regFMT0_FMT_422_CONTROL_BASE_IDX 2 8106 8107 8108// addressBlock: dce_dc_opp_oppbuf0_dispdec 8109// base address: 0x0 8110#define regOPPBUF0_OPPBUF_CONTROL 0x1884 8111#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 8112#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 8113#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8114#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 8115#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8116#define regOPPBUF0_OPPBUF_CONTROL1 0x1889 8117#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 8118 8119 8120// addressBlock: dce_dc_opp_opp_pipe0_dispdec 8121// base address: 0x0 8122#define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 8123#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 8124 8125 8126// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec 8127// base address: 0x0 8128#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 8129#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8130#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 8131#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 8132#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 8133#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8134#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 8135#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8136#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 8137#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8138 8139 8140// addressBlock: dce_dc_opp_dpg1_dispdec 8141// base address: 0x168 8142#define regDPG1_DPG_CONTROL 0x18ae 8143#define regDPG1_DPG_CONTROL_BASE_IDX 2 8144#define regDPG1_DPG_RAMP_CONTROL 0x18af 8145#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 8146#define regDPG1_DPG_DIMENSIONS 0x18b0 8147#define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 8148#define regDPG1_DPG_COLOUR_R_CR 0x18b1 8149#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 8150#define regDPG1_DPG_COLOUR_G_Y 0x18b2 8151#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 8152#define regDPG1_DPG_COLOUR_B_CB 0x18b3 8153#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 8154#define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 8155#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 8156#define regDPG1_DPG_STATUS 0x18b5 8157#define regDPG1_DPG_STATUS_BASE_IDX 2 8158 8159 8160// addressBlock: dce_dc_opp_fmt1_dispdec 8161// base address: 0x168 8162#define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 8163#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8164#define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 8165#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8166#define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 8167#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8168#define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 8169#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8170#define regFMT1_FMT_CONTROL 0x189a 8171#define regFMT1_FMT_CONTROL_BASE_IDX 2 8172#define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 8173#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8174#define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c 8175#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8176#define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d 8177#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8178#define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e 8179#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8180#define regFMT1_FMT_CLAMP_CNTL 0x189f 8181#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 8182#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 8183#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8184#define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 8185#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8186#define regFMT1_FMT_422_CONTROL 0x18a3 8187#define regFMT1_FMT_422_CONTROL_BASE_IDX 2 8188 8189 8190// addressBlock: dce_dc_opp_oppbuf1_dispdec 8191// base address: 0x168 8192#define regOPPBUF1_OPPBUF_CONTROL 0x18de 8193#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 8194#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 8195#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8196#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 8197#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8198#define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 8199#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 8200 8201 8202// addressBlock: dce_dc_opp_opp_pipe1_dispdec 8203// base address: 0x168 8204#define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 8205#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 8206 8207 8208// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec 8209// base address: 0x168 8210#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 8211#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8212#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 8213#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 8214#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 8215#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8216#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 8217#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8218#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 8219#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8220 8221 8222// addressBlock: dce_dc_opp_dpg2_dispdec 8223// base address: 0x2d0 8224#define regDPG2_DPG_CONTROL 0x1908 8225#define regDPG2_DPG_CONTROL_BASE_IDX 2 8226#define regDPG2_DPG_RAMP_CONTROL 0x1909 8227#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 8228#define regDPG2_DPG_DIMENSIONS 0x190a 8229#define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 8230#define regDPG2_DPG_COLOUR_R_CR 0x190b 8231#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 8232#define regDPG2_DPG_COLOUR_G_Y 0x190c 8233#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 8234#define regDPG2_DPG_COLOUR_B_CB 0x190d 8235#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 8236#define regDPG2_DPG_OFFSET_SEGMENT 0x190e 8237#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 8238#define regDPG2_DPG_STATUS 0x190f 8239#define regDPG2_DPG_STATUS_BASE_IDX 2 8240 8241 8242// addressBlock: dce_dc_opp_fmt2_dispdec 8243// base address: 0x2d0 8244#define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 8245#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8246#define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 8247#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8248#define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 8249#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8250#define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 8251#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8252#define regFMT2_FMT_CONTROL 0x18f4 8253#define regFMT2_FMT_CONTROL_BASE_IDX 2 8254#define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 8255#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8256#define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 8257#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8258#define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 8259#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8260#define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 8261#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8262#define regFMT2_FMT_CLAMP_CNTL 0x18f9 8263#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 8264#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa 8265#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8266#define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb 8267#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8268#define regFMT2_FMT_422_CONTROL 0x18fd 8269#define regFMT2_FMT_422_CONTROL_BASE_IDX 2 8270 8271 8272// addressBlock: dce_dc_opp_oppbuf2_dispdec 8273// base address: 0x2d0 8274#define regOPPBUF2_OPPBUF_CONTROL 0x1938 8275#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 8276#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 8277#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8278#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a 8279#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8280#define regOPPBUF2_OPPBUF_CONTROL1 0x193d 8281#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 8282 8283 8284// addressBlock: dce_dc_opp_opp_pipe2_dispdec 8285// base address: 0x2d0 8286#define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 8287#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 8288 8289 8290// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec 8291// base address: 0x2d0 8292#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 8293#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8294#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 8295#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 8296#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 8297#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8298#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 8299#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8300#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 8301#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8302 8303 8304// addressBlock: dce_dc_opp_dpg3_dispdec 8305// base address: 0x438 8306#define regDPG3_DPG_CONTROL 0x1962 8307#define regDPG3_DPG_CONTROL_BASE_IDX 2 8308#define regDPG3_DPG_RAMP_CONTROL 0x1963 8309#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 8310#define regDPG3_DPG_DIMENSIONS 0x1964 8311#define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 8312#define regDPG3_DPG_COLOUR_R_CR 0x1965 8313#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 8314#define regDPG3_DPG_COLOUR_G_Y 0x1966 8315#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 8316#define regDPG3_DPG_COLOUR_B_CB 0x1967 8317#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 8318#define regDPG3_DPG_OFFSET_SEGMENT 0x1968 8319#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 8320#define regDPG3_DPG_STATUS 0x1969 8321#define regDPG3_DPG_STATUS_BASE_IDX 2 8322 8323 8324// addressBlock: dce_dc_opp_fmt3_dispdec 8325// base address: 0x438 8326#define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a 8327#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8328#define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b 8329#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8330#define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c 8331#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8332#define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d 8333#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8334#define regFMT3_FMT_CONTROL 0x194e 8335#define regFMT3_FMT_CONTROL_BASE_IDX 2 8336#define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f 8337#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8338#define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 8339#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8340#define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 8341#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8342#define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 8343#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8344#define regFMT3_FMT_CLAMP_CNTL 0x1953 8345#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 8346#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 8347#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8348#define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 8349#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8350#define regFMT3_FMT_422_CONTROL 0x1957 8351#define regFMT3_FMT_422_CONTROL_BASE_IDX 2 8352 8353 8354// addressBlock: dce_dc_opp_oppbuf3_dispdec 8355// base address: 0x438 8356#define regOPPBUF3_OPPBUF_CONTROL 0x1992 8357#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 8358#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 8359#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8360#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 8361#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8362#define regOPPBUF3_OPPBUF_CONTROL1 0x1997 8363#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 8364 8365 8366// addressBlock: dce_dc_opp_opp_pipe3_dispdec 8367// base address: 0x438 8368#define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a 8369#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 8370 8371 8372// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec 8373// base address: 0x438 8374#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f 8375#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8376#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 8377#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 8378#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 8379#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8380#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 8381#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8382#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 8383#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8384 8385 8386// addressBlock: dce_dc_opp_dscrm0_dispdec 8387// base address: 0x0 8388#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 8389#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8390 8391 8392// addressBlock: dce_dc_opp_dscrm1_dispdec 8393// base address: 0x4 8394#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 8395#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8396 8397 8398// addressBlock: dce_dc_opp_dscrm2_dispdec 8399// base address: 0x8 8400#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 8401#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8402 8403 8404// addressBlock: dce_dc_opp_opp_top_dispdec 8405// base address: 0x0 8406#define regOPP_TOP_CLK_CONTROL 0x1a5e 8407#define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 8408#define regOPP_ABM_CONTROL 0x1a60 8409#define regOPP_ABM_CONTROL_BASE_IDX 2 8410 8411 8412// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec 8413// base address: 0x6af8 8414#define regDC_PERFMON16_PERFCOUNTER_CNTL 0x1abe 8415#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 8416#define regDC_PERFMON16_PERFCOUNTER_CNTL2 0x1abf 8417#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 8418#define regDC_PERFMON16_PERFCOUNTER_STATE 0x1ac0 8419#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 8420#define regDC_PERFMON16_PERFMON_CNTL 0x1ac1 8421#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 8422#define regDC_PERFMON16_PERFMON_CNTL2 0x1ac2 8423#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 8424#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1ac3 8425#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 8426#define regDC_PERFMON16_PERFMON_CVALUE_LOW 0x1ac4 8427#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 8428#define regDC_PERFMON16_PERFMON_HI 0x1ac5 8429#define regDC_PERFMON16_PERFMON_HI_BASE_IDX 2 8430#define regDC_PERFMON16_PERFMON_LOW 0x1ac6 8431#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 8432 8433 8434// addressBlock: dce_dc_optc_odm0_dispdec 8435// base address: 0x0 8436#define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 8437#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8438#define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 8439#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8440#define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 8441#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8442#define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd 8443#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8444#define regODM0_OPTC_WIDTH_CONTROL 0x1ace 8445#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 8446#define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf 8447#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8448#define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 8449#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 8450#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 8451#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8452 8453 8454// addressBlock: dce_dc_optc_odm1_dispdec 8455// base address: 0x40 8456#define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 8457#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8458#define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 8459#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8460#define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 8461#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8462#define regODM1_OPTC_BYTES_PER_PIXEL 0x1add 8463#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8464#define regODM1_OPTC_WIDTH_CONTROL 0x1ade 8465#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 8466#define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf 8467#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8468#define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 8469#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 8470#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 8471#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8472 8473 8474// addressBlock: dce_dc_optc_odm2_dispdec 8475// base address: 0x80 8476#define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea 8477#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8478#define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb 8479#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8480#define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec 8481#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8482#define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed 8483#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8484#define regODM2_OPTC_WIDTH_CONTROL 0x1aee 8485#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 8486#define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef 8487#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8488#define regODM2_OPTC_MEMORY_CONFIG 0x1af0 8489#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 8490#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 8491#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8492 8493 8494// addressBlock: dce_dc_optc_odm3_dispdec 8495// base address: 0xc0 8496#define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa 8497#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8498#define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb 8499#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8500#define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc 8501#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8502#define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd 8503#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8504#define regODM3_OPTC_WIDTH_CONTROL 0x1afe 8505#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 8506#define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff 8507#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8508#define regODM3_OPTC_MEMORY_CONFIG 0x1b00 8509#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 8510#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 8511#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8512 8513 8514// addressBlock: dce_dc_optc_otg0_dispdec 8515// base address: 0x0 8516#define regOTG0_OTG_H_TOTAL 0x1b2a 8517#define regOTG0_OTG_H_TOTAL_BASE_IDX 2 8518#define regOTG0_OTG_H_BLANK_START_END 0x1b2b 8519#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 8520#define regOTG0_OTG_H_SYNC_A 0x1b2c 8521#define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 8522#define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 8523#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8524#define regOTG0_OTG_H_TIMING_CNTL 0x1b2e 8525#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 8526#define regOTG0_OTG_V_TOTAL 0x1b2f 8527#define regOTG0_OTG_V_TOTAL_BASE_IDX 2 8528#define regOTG0_OTG_V_TOTAL_MIN 0x1b30 8529#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 8530#define regOTG0_OTG_V_TOTAL_MAX 0x1b31 8531#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 8532#define regOTG0_OTG_V_TOTAL_MID 0x1b32 8533#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 8534#define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 8535#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8536#define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 8537#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8538#define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 8539#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8540#define regOTG0_OTG_V_BLANK_START_END 0x1b36 8541#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 8542#define regOTG0_OTG_V_SYNC_A 0x1b37 8543#define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 8544#define regOTG0_OTG_V_SYNC_A_CNTL 0x1b38 8545#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8546#define regOTG0_OTG_TRIGA_CNTL 0x1b39 8547#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 8548#define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a 8549#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8550#define regOTG0_OTG_TRIGB_CNTL 0x1b3b 8551#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 8552#define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c 8553#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8554#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d 8555#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8556#define regOTG0_OTG_FLOW_CONTROL 0x1b3e 8557#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 8558#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f 8559#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8560#define regOTG0_OTG_CONTROL 0x1b41 8561#define regOTG0_OTG_CONTROL_BASE_IDX 2 8562#define regOTG0_OTG_INTERLACE_CONTROL 0x1b44 8563#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 8564#define regOTG0_OTG_INTERLACE_STATUS 0x1b45 8565#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 8566#define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 8567#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8568#define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 8569#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8570#define regOTG0_OTG_STATUS 0x1b49 8571#define regOTG0_OTG_STATUS_BASE_IDX 2 8572#define regOTG0_OTG_STATUS_POSITION 0x1b4a 8573#define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 8574#define regOTG0_OTG_NOM_VERT_POSITION 0x1b4b 8575#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 8576#define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c 8577#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8578#define regOTG0_OTG_STATUS_VF_COUNT 0x1b4d 8579#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 8580#define regOTG0_OTG_STATUS_HV_COUNT 0x1b4e 8581#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 8582#define regOTG0_OTG_COUNT_CONTROL 0x1b4f 8583#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 8584#define regOTG0_OTG_COUNT_RESET 0x1b50 8585#define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 8586#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 8587#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8588#define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 8589#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8590#define regOTG0_OTG_STEREO_STATUS 0x1b53 8591#define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 8592#define regOTG0_OTG_STEREO_CONTROL 0x1b54 8593#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 8594#define regOTG0_OTG_SNAPSHOT_STATUS 0x1b55 8595#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8596#define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 8597#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8598#define regOTG0_OTG_SNAPSHOT_POSITION 0x1b57 8599#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8600#define regOTG0_OTG_SNAPSHOT_FRAME 0x1b58 8601#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8602#define regOTG0_OTG_UPDATE_LOCK 0x1b5a 8603#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 8604#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b 8605#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8606#define regOTG0_OTG_MASTER_EN 0x1b5c 8607#define regOTG0_OTG_MASTER_EN_BASE_IDX 2 8608#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 8609#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8610#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 8611#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8612#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 8613#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8614#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 8615#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8616#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 8617#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8618#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 8619#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8620#define regOTG0_OTG_CRC_CNTL 0x1b68 8621#define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 8622#define regOTG0_OTG_CRC_CNTL2 0x1b69 8623#define regOTG0_OTG_CRC_CNTL2_BASE_IDX 2 8624#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a 8625#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8626#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b 8627#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8628#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c 8629#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8630#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d 8631#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8632#define regOTG0_OTG_CRC0_DATA_RG 0x1b6e 8633#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 8634#define regOTG0_OTG_CRC0_DATA_B 0x1b6f 8635#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 8636#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 8637#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8638#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 8639#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8640#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 8641#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8642#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 8643#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8644#define regOTG0_OTG_CRC1_DATA_RG 0x1b74 8645#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 8646#define regOTG0_OTG_CRC1_DATA_B 0x1b75 8647#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 8648#define regOTG0_OTG_CRC2_DATA_RG 0x1b76 8649#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 8650#define regOTG0_OTG_CRC2_DATA_B 0x1b77 8651#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 8652#define regOTG0_OTG_CRC3_DATA_RG 0x1b78 8653#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 8654#define regOTG0_OTG_CRC3_DATA_B 0x1b79 8655#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 8656#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a 8657#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8658#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b 8659#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8660#define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 8661#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8662#define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 8663#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8664#define regOTG0_OTG_GSL_VSYNC_GAP 0x1b84 8665#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8666#define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 8667#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8668#define regOTG0_OTG_CLOCK_CONTROL 0x1b86 8669#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 8670#define regOTG0_OTG_VSTARTUP_PARAM 0x1b87 8671#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 8672#define regOTG0_OTG_VUPDATE_PARAM 0x1b88 8673#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 8674#define regOTG0_OTG_VREADY_PARAM 0x1b89 8675#define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 8676#define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a 8677#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8678#define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b 8679#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8680#define regOTG0_OTG_GSL_CONTROL 0x1b8c 8681#define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 8682#define regOTG0_OTG_GSL_WINDOW_X 0x1b8d 8683#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 8684#define regOTG0_OTG_GSL_WINDOW_Y 0x1b8e 8685#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 8686#define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f 8687#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8688#define regOTG0_OTG_GLOBAL_CONTROL0 0x1b90 8689#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8690#define regOTG0_OTG_GLOBAL_CONTROL1 0x1b91 8691#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8692#define regOTG0_OTG_GLOBAL_CONTROL2 0x1b92 8693#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8694#define regOTG0_OTG_GLOBAL_CONTROL3 0x1b93 8695#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8696#define regOTG0_OTG_GLOBAL_CONTROL4 0x1b94 8697#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8698#define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b95 8699#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8700#define regOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b96 8701#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8702#define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b97 8703#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8704#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b98 8705#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8706#define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b99 8707#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8708#define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b9a 8709#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8710#define regOTG0_OTG_DRR_CONTROL 0x1b9b 8711#define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 8712#define regOTG0_OTG_M_CONST_DTO0 0x1b9c 8713#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 8714#define regOTG0_OTG_M_CONST_DTO1 0x1b9d 8715#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 8716#define regOTG0_OTG_REQUEST_CONTROL 0x1b9e 8717#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 8718#define regOTG0_OTG_DSC_START_POSITION 0x1b9f 8719#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 8720#define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba0 8721#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8722#define regOTG0_OTG_SPARE_REGISTER 0x1ba2 8723#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 8724 8725 8726// addressBlock: dce_dc_optc_otg1_dispdec 8727// base address: 0x200 8728#define regOTG1_OTG_H_TOTAL 0x1baa 8729#define regOTG1_OTG_H_TOTAL_BASE_IDX 2 8730#define regOTG1_OTG_H_BLANK_START_END 0x1bab 8731#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 8732#define regOTG1_OTG_H_SYNC_A 0x1bac 8733#define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 8734#define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad 8735#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8736#define regOTG1_OTG_H_TIMING_CNTL 0x1bae 8737#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 8738#define regOTG1_OTG_V_TOTAL 0x1baf 8739#define regOTG1_OTG_V_TOTAL_BASE_IDX 2 8740#define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 8741#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 8742#define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 8743#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 8744#define regOTG1_OTG_V_TOTAL_MID 0x1bb2 8745#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 8746#define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 8747#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8748#define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 8749#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8750#define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 8751#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8752#define regOTG1_OTG_V_BLANK_START_END 0x1bb6 8753#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 8754#define regOTG1_OTG_V_SYNC_A 0x1bb7 8755#define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 8756#define regOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 8757#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8758#define regOTG1_OTG_TRIGA_CNTL 0x1bb9 8759#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 8760#define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba 8761#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8762#define regOTG1_OTG_TRIGB_CNTL 0x1bbb 8763#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 8764#define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc 8765#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8766#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd 8767#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8768#define regOTG1_OTG_FLOW_CONTROL 0x1bbe 8769#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 8770#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf 8771#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8772#define regOTG1_OTG_CONTROL 0x1bc1 8773#define regOTG1_OTG_CONTROL_BASE_IDX 2 8774#define regOTG1_OTG_INTERLACE_CONTROL 0x1bc4 8775#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 8776#define regOTG1_OTG_INTERLACE_STATUS 0x1bc5 8777#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 8778#define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 8779#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8780#define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 8781#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8782#define regOTG1_OTG_STATUS 0x1bc9 8783#define regOTG1_OTG_STATUS_BASE_IDX 2 8784#define regOTG1_OTG_STATUS_POSITION 0x1bca 8785#define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 8786#define regOTG1_OTG_NOM_VERT_POSITION 0x1bcb 8787#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 8788#define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc 8789#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8790#define regOTG1_OTG_STATUS_VF_COUNT 0x1bcd 8791#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 8792#define regOTG1_OTG_STATUS_HV_COUNT 0x1bce 8793#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 8794#define regOTG1_OTG_COUNT_CONTROL 0x1bcf 8795#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 8796#define regOTG1_OTG_COUNT_RESET 0x1bd0 8797#define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 8798#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 8799#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8800#define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 8801#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8802#define regOTG1_OTG_STEREO_STATUS 0x1bd3 8803#define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 8804#define regOTG1_OTG_STEREO_CONTROL 0x1bd4 8805#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 8806#define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 8807#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8808#define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 8809#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8810#define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 8811#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8812#define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 8813#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8814#define regOTG1_OTG_UPDATE_LOCK 0x1bda 8815#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 8816#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb 8817#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8818#define regOTG1_OTG_MASTER_EN 0x1bdc 8819#define regOTG1_OTG_MASTER_EN_BASE_IDX 2 8820#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 8821#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8822#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 8823#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8824#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 8825#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8826#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 8827#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8828#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 8829#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8830#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 8831#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8832#define regOTG1_OTG_CRC_CNTL 0x1be8 8833#define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 8834#define regOTG1_OTG_CRC_CNTL2 0x1be9 8835#define regOTG1_OTG_CRC_CNTL2_BASE_IDX 2 8836#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea 8837#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8838#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb 8839#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8840#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec 8841#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8842#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed 8843#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8844#define regOTG1_OTG_CRC0_DATA_RG 0x1bee 8845#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 8846#define regOTG1_OTG_CRC0_DATA_B 0x1bef 8847#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 8848#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 8849#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8850#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 8851#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8852#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 8853#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8854#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 8855#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8856#define regOTG1_OTG_CRC1_DATA_RG 0x1bf4 8857#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 8858#define regOTG1_OTG_CRC1_DATA_B 0x1bf5 8859#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 8860#define regOTG1_OTG_CRC2_DATA_RG 0x1bf6 8861#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 8862#define regOTG1_OTG_CRC2_DATA_B 0x1bf7 8863#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 8864#define regOTG1_OTG_CRC3_DATA_RG 0x1bf8 8865#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 8866#define regOTG1_OTG_CRC3_DATA_B 0x1bf9 8867#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 8868#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa 8869#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8870#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb 8871#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8872#define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 8873#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8874#define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 8875#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8876#define regOTG1_OTG_GSL_VSYNC_GAP 0x1c04 8877#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8878#define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 8879#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8880#define regOTG1_OTG_CLOCK_CONTROL 0x1c06 8881#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 8882#define regOTG1_OTG_VSTARTUP_PARAM 0x1c07 8883#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 8884#define regOTG1_OTG_VUPDATE_PARAM 0x1c08 8885#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 8886#define regOTG1_OTG_VREADY_PARAM 0x1c09 8887#define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 8888#define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a 8889#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8890#define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b 8891#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8892#define regOTG1_OTG_GSL_CONTROL 0x1c0c 8893#define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 8894#define regOTG1_OTG_GSL_WINDOW_X 0x1c0d 8895#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 8896#define regOTG1_OTG_GSL_WINDOW_Y 0x1c0e 8897#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 8898#define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f 8899#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8900#define regOTG1_OTG_GLOBAL_CONTROL0 0x1c10 8901#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8902#define regOTG1_OTG_GLOBAL_CONTROL1 0x1c11 8903#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8904#define regOTG1_OTG_GLOBAL_CONTROL2 0x1c12 8905#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8906#define regOTG1_OTG_GLOBAL_CONTROL3 0x1c13 8907#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8908#define regOTG1_OTG_GLOBAL_CONTROL4 0x1c14 8909#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8910#define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c15 8911#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8912#define regOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c16 8913#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8914#define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c17 8915#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8916#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c18 8917#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8918#define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c19 8919#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8920#define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c1a 8921#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8922#define regOTG1_OTG_DRR_CONTROL 0x1c1b 8923#define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 8924#define regOTG1_OTG_M_CONST_DTO0 0x1c1c 8925#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 8926#define regOTG1_OTG_M_CONST_DTO1 0x1c1d 8927#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 8928#define regOTG1_OTG_REQUEST_CONTROL 0x1c1e 8929#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 8930#define regOTG1_OTG_DSC_START_POSITION 0x1c1f 8931#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 8932#define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c20 8933#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8934#define regOTG1_OTG_SPARE_REGISTER 0x1c22 8935#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 8936 8937 8938// addressBlock: dce_dc_optc_otg2_dispdec 8939// base address: 0x400 8940#define regOTG2_OTG_H_TOTAL 0x1c2a 8941#define regOTG2_OTG_H_TOTAL_BASE_IDX 2 8942#define regOTG2_OTG_H_BLANK_START_END 0x1c2b 8943#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 8944#define regOTG2_OTG_H_SYNC_A 0x1c2c 8945#define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 8946#define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d 8947#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8948#define regOTG2_OTG_H_TIMING_CNTL 0x1c2e 8949#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 8950#define regOTG2_OTG_V_TOTAL 0x1c2f 8951#define regOTG2_OTG_V_TOTAL_BASE_IDX 2 8952#define regOTG2_OTG_V_TOTAL_MIN 0x1c30 8953#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 8954#define regOTG2_OTG_V_TOTAL_MAX 0x1c31 8955#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 8956#define regOTG2_OTG_V_TOTAL_MID 0x1c32 8957#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 8958#define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 8959#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8960#define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 8961#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8962#define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 8963#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8964#define regOTG2_OTG_V_BLANK_START_END 0x1c36 8965#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 8966#define regOTG2_OTG_V_SYNC_A 0x1c37 8967#define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 8968#define regOTG2_OTG_V_SYNC_A_CNTL 0x1c38 8969#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8970#define regOTG2_OTG_TRIGA_CNTL 0x1c39 8971#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 8972#define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a 8973#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8974#define regOTG2_OTG_TRIGB_CNTL 0x1c3b 8975#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 8976#define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c 8977#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8978#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d 8979#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8980#define regOTG2_OTG_FLOW_CONTROL 0x1c3e 8981#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 8982#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f 8983#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8984#define regOTG2_OTG_CONTROL 0x1c41 8985#define regOTG2_OTG_CONTROL_BASE_IDX 2 8986#define regOTG2_OTG_INTERLACE_CONTROL 0x1c44 8987#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 8988#define regOTG2_OTG_INTERLACE_STATUS 0x1c45 8989#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 8990#define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 8991#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8992#define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 8993#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8994#define regOTG2_OTG_STATUS 0x1c49 8995#define regOTG2_OTG_STATUS_BASE_IDX 2 8996#define regOTG2_OTG_STATUS_POSITION 0x1c4a 8997#define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 8998#define regOTG2_OTG_NOM_VERT_POSITION 0x1c4b 8999#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 9000#define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c 9001#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9002#define regOTG2_OTG_STATUS_VF_COUNT 0x1c4d 9003#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 9004#define regOTG2_OTG_STATUS_HV_COUNT 0x1c4e 9005#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 9006#define regOTG2_OTG_COUNT_CONTROL 0x1c4f 9007#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 9008#define regOTG2_OTG_COUNT_RESET 0x1c50 9009#define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 9010#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 9011#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9012#define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 9013#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9014#define regOTG2_OTG_STEREO_STATUS 0x1c53 9015#define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 9016#define regOTG2_OTG_STEREO_CONTROL 0x1c54 9017#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 9018#define regOTG2_OTG_SNAPSHOT_STATUS 0x1c55 9019#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9020#define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 9021#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9022#define regOTG2_OTG_SNAPSHOT_POSITION 0x1c57 9023#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9024#define regOTG2_OTG_SNAPSHOT_FRAME 0x1c58 9025#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9026#define regOTG2_OTG_UPDATE_LOCK 0x1c5a 9027#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 9028#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b 9029#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9030#define regOTG2_OTG_MASTER_EN 0x1c5c 9031#define regOTG2_OTG_MASTER_EN_BASE_IDX 2 9032#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 9033#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9034#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 9035#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9036#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 9037#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9038#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 9039#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9040#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 9041#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9042#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 9043#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9044#define regOTG2_OTG_CRC_CNTL 0x1c68 9045#define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 9046#define regOTG2_OTG_CRC_CNTL2 0x1c69 9047#define regOTG2_OTG_CRC_CNTL2_BASE_IDX 2 9048#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a 9049#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9050#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b 9051#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9052#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c 9053#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9054#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d 9055#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9056#define regOTG2_OTG_CRC0_DATA_RG 0x1c6e 9057#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 9058#define regOTG2_OTG_CRC0_DATA_B 0x1c6f 9059#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 9060#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70 9061#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9062#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71 9063#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9064#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72 9065#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9066#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73 9067#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9068#define regOTG2_OTG_CRC1_DATA_RG 0x1c74 9069#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 9070#define regOTG2_OTG_CRC1_DATA_B 0x1c75 9071#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 9072#define regOTG2_OTG_CRC2_DATA_RG 0x1c76 9073#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 9074#define regOTG2_OTG_CRC2_DATA_B 0x1c77 9075#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 9076#define regOTG2_OTG_CRC3_DATA_RG 0x1c78 9077#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 9078#define regOTG2_OTG_CRC3_DATA_B 0x1c79 9079#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 9080#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a 9081#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9082#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b 9083#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9084#define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82 9085#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9086#define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83 9087#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9088#define regOTG2_OTG_GSL_VSYNC_GAP 0x1c84 9089#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9090#define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c85 9091#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9092#define regOTG2_OTG_CLOCK_CONTROL 0x1c86 9093#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 9094#define regOTG2_OTG_VSTARTUP_PARAM 0x1c87 9095#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 9096#define regOTG2_OTG_VUPDATE_PARAM 0x1c88 9097#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 9098#define regOTG2_OTG_VREADY_PARAM 0x1c89 9099#define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 9100#define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a 9101#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9102#define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b 9103#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9104#define regOTG2_OTG_GSL_CONTROL 0x1c8c 9105#define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 9106#define regOTG2_OTG_GSL_WINDOW_X 0x1c8d 9107#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 9108#define regOTG2_OTG_GSL_WINDOW_Y 0x1c8e 9109#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 9110#define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f 9111#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9112#define regOTG2_OTG_GLOBAL_CONTROL0 0x1c90 9113#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9114#define regOTG2_OTG_GLOBAL_CONTROL1 0x1c91 9115#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9116#define regOTG2_OTG_GLOBAL_CONTROL2 0x1c92 9117#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9118#define regOTG2_OTG_GLOBAL_CONTROL3 0x1c93 9119#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9120#define regOTG2_OTG_GLOBAL_CONTROL4 0x1c94 9121#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9122#define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c95 9123#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9124#define regOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c96 9125#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9126#define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c97 9127#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9128#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c98 9129#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9130#define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c99 9131#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9132#define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c9a 9133#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9134#define regOTG2_OTG_DRR_CONTROL 0x1c9b 9135#define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 9136#define regOTG2_OTG_M_CONST_DTO0 0x1c9c 9137#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 9138#define regOTG2_OTG_M_CONST_DTO1 0x1c9d 9139#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 9140#define regOTG2_OTG_REQUEST_CONTROL 0x1c9e 9141#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 9142#define regOTG2_OTG_DSC_START_POSITION 0x1c9f 9143#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 9144#define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1ca0 9145#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9146#define regOTG2_OTG_SPARE_REGISTER 0x1ca2 9147#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 9148 9149 9150// addressBlock: dce_dc_optc_otg3_dispdec 9151// base address: 0x600 9152#define regOTG3_OTG_H_TOTAL 0x1caa 9153#define regOTG3_OTG_H_TOTAL_BASE_IDX 2 9154#define regOTG3_OTG_H_BLANK_START_END 0x1cab 9155#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 9156#define regOTG3_OTG_H_SYNC_A 0x1cac 9157#define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 9158#define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad 9159#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9160#define regOTG3_OTG_H_TIMING_CNTL 0x1cae 9161#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 9162#define regOTG3_OTG_V_TOTAL 0x1caf 9163#define regOTG3_OTG_V_TOTAL_BASE_IDX 2 9164#define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 9165#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 9166#define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 9167#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 9168#define regOTG3_OTG_V_TOTAL_MID 0x1cb2 9169#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 9170#define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 9171#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9172#define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 9173#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9174#define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 9175#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9176#define regOTG3_OTG_V_BLANK_START_END 0x1cb6 9177#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 9178#define regOTG3_OTG_V_SYNC_A 0x1cb7 9179#define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 9180#define regOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 9181#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9182#define regOTG3_OTG_TRIGA_CNTL 0x1cb9 9183#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 9184#define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba 9185#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9186#define regOTG3_OTG_TRIGB_CNTL 0x1cbb 9187#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 9188#define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc 9189#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9190#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd 9191#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9192#define regOTG3_OTG_FLOW_CONTROL 0x1cbe 9193#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 9194#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf 9195#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9196#define regOTG3_OTG_CONTROL 0x1cc1 9197#define regOTG3_OTG_CONTROL_BASE_IDX 2 9198#define regOTG3_OTG_INTERLACE_CONTROL 0x1cc4 9199#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 9200#define regOTG3_OTG_INTERLACE_STATUS 0x1cc5 9201#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 9202#define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 9203#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9204#define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 9205#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9206#define regOTG3_OTG_STATUS 0x1cc9 9207#define regOTG3_OTG_STATUS_BASE_IDX 2 9208#define regOTG3_OTG_STATUS_POSITION 0x1cca 9209#define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 9210#define regOTG3_OTG_NOM_VERT_POSITION 0x1ccb 9211#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 9212#define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc 9213#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9214#define regOTG3_OTG_STATUS_VF_COUNT 0x1ccd 9215#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 9216#define regOTG3_OTG_STATUS_HV_COUNT 0x1cce 9217#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 9218#define regOTG3_OTG_COUNT_CONTROL 0x1ccf 9219#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 9220#define regOTG3_OTG_COUNT_RESET 0x1cd0 9221#define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 9222#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 9223#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9224#define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 9225#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9226#define regOTG3_OTG_STEREO_STATUS 0x1cd3 9227#define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 9228#define regOTG3_OTG_STEREO_CONTROL 0x1cd4 9229#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 9230#define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 9231#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9232#define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 9233#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9234#define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 9235#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9236#define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 9237#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9238#define regOTG3_OTG_UPDATE_LOCK 0x1cda 9239#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 9240#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb 9241#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9242#define regOTG3_OTG_MASTER_EN 0x1cdc 9243#define regOTG3_OTG_MASTER_EN_BASE_IDX 2 9244#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 9245#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9246#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 9247#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9248#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 9249#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9250#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 9251#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9252#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 9253#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9254#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 9255#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9256#define regOTG3_OTG_CRC_CNTL 0x1ce8 9257#define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 9258#define regOTG3_OTG_CRC_CNTL2 0x1ce9 9259#define regOTG3_OTG_CRC_CNTL2_BASE_IDX 2 9260#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea 9261#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9262#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb 9263#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9264#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec 9265#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9266#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced 9267#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9268#define regOTG3_OTG_CRC0_DATA_RG 0x1cee 9269#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 9270#define regOTG3_OTG_CRC0_DATA_B 0x1cef 9271#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 9272#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0 9273#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9274#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1 9275#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9276#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2 9277#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9278#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3 9279#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9280#define regOTG3_OTG_CRC1_DATA_RG 0x1cf4 9281#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 9282#define regOTG3_OTG_CRC1_DATA_B 0x1cf5 9283#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 9284#define regOTG3_OTG_CRC2_DATA_RG 0x1cf6 9285#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 9286#define regOTG3_OTG_CRC2_DATA_B 0x1cf7 9287#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 9288#define regOTG3_OTG_CRC3_DATA_RG 0x1cf8 9289#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 9290#define regOTG3_OTG_CRC3_DATA_B 0x1cf9 9291#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 9292#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa 9293#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9294#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb 9295#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9296#define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02 9297#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9298#define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03 9299#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9300#define regOTG3_OTG_GSL_VSYNC_GAP 0x1d04 9301#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9302#define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d05 9303#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9304#define regOTG3_OTG_CLOCK_CONTROL 0x1d06 9305#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 9306#define regOTG3_OTG_VSTARTUP_PARAM 0x1d07 9307#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 9308#define regOTG3_OTG_VUPDATE_PARAM 0x1d08 9309#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 9310#define regOTG3_OTG_VREADY_PARAM 0x1d09 9311#define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 9312#define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a 9313#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9314#define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b 9315#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9316#define regOTG3_OTG_GSL_CONTROL 0x1d0c 9317#define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 9318#define regOTG3_OTG_GSL_WINDOW_X 0x1d0d 9319#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 9320#define regOTG3_OTG_GSL_WINDOW_Y 0x1d0e 9321#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 9322#define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f 9323#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9324#define regOTG3_OTG_GLOBAL_CONTROL0 0x1d10 9325#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9326#define regOTG3_OTG_GLOBAL_CONTROL1 0x1d11 9327#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9328#define regOTG3_OTG_GLOBAL_CONTROL2 0x1d12 9329#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9330#define regOTG3_OTG_GLOBAL_CONTROL3 0x1d13 9331#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9332#define regOTG3_OTG_GLOBAL_CONTROL4 0x1d14 9333#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9334#define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d15 9335#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9336#define regOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d16 9337#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9338#define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d17 9339#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9340#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d18 9341#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9342#define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d19 9343#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9344#define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d1a 9345#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9346#define regOTG3_OTG_DRR_CONTROL 0x1d1b 9347#define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 9348#define regOTG3_OTG_M_CONST_DTO0 0x1d1c 9349#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 9350#define regOTG3_OTG_M_CONST_DTO1 0x1d1d 9351#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 9352#define regOTG3_OTG_REQUEST_CONTROL 0x1d1e 9353#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 9354#define regOTG3_OTG_DSC_START_POSITION 0x1d1f 9355#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 9356#define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d20 9357#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9358#define regOTG3_OTG_SPARE_REGISTER 0x1d22 9359#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 9360 9361 9362// addressBlock: dce_dc_optc_optc_misc_dispdec 9363// base address: 0x0 9364#define regDWB_SOURCE_SELECT 0x1e2a 9365#define regDWB_SOURCE_SELECT_BASE_IDX 2 9366#define regGSL_SOURCE_SELECT 0x1e2b 9367#define regGSL_SOURCE_SELECT_BASE_IDX 2 9368#define regOPTC_CLOCK_CONTROL 0x1e2c 9369#define regOPTC_CLOCK_CONTROL_BASE_IDX 2 9370#define regODM_MEM_PWR_CTRL 0x1e2d 9371#define regODM_MEM_PWR_CTRL_BASE_IDX 2 9372#define regODM_MEM_PWR_CTRL3 0x1e2f 9373#define regODM_MEM_PWR_CTRL3_BASE_IDX 2 9374#define regODM_MEM_PWR_STATUS 0x1e30 9375#define regODM_MEM_PWR_STATUS_BASE_IDX 2 9376#define regOPTC_MISC_SPARE_REGISTER 0x1e31 9377#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 9378 9379 9380// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec 9381// base address: 0x79a8 9382#define regDC_PERFMON17_PERFCOUNTER_CNTL 0x1e6a 9383#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 9384#define regDC_PERFMON17_PERFCOUNTER_CNTL2 0x1e6b 9385#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 9386#define regDC_PERFMON17_PERFCOUNTER_STATE 0x1e6c 9387#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 9388#define regDC_PERFMON17_PERFMON_CNTL 0x1e6d 9389#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 9390#define regDC_PERFMON17_PERFMON_CNTL2 0x1e6e 9391#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 9392#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1e6f 9393#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 9394#define regDC_PERFMON17_PERFMON_CVALUE_LOW 0x1e70 9395#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 9396#define regDC_PERFMON17_PERFMON_HI 0x1e71 9397#define regDC_PERFMON17_PERFMON_HI_BASE_IDX 2 9398#define regDC_PERFMON17_PERFMON_LOW 0x1e72 9399#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 9400 9401 9402// addressBlock: dce_dc_dio_hpd0_dispdec 9403// base address: 0x0 9404#define regHPD0_DC_HPD_INT_STATUS 0x1f14 9405#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 9406#define regHPD0_DC_HPD_INT_CONTROL 0x1f15 9407#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 9408#define regHPD0_DC_HPD_CONTROL 0x1f16 9409#define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 9410#define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 9411#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9412#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 9413#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9414 9415 9416// addressBlock: dce_dc_dio_hpd1_dispdec 9417// base address: 0x20 9418#define regHPD1_DC_HPD_INT_STATUS 0x1f1c 9419#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 9420#define regHPD1_DC_HPD_INT_CONTROL 0x1f1d 9421#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 9422#define regHPD1_DC_HPD_CONTROL 0x1f1e 9423#define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 9424#define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 9425#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9426#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 9427#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9428 9429 9430// addressBlock: dce_dc_dio_hpd2_dispdec 9431// base address: 0x40 9432#define regHPD2_DC_HPD_INT_STATUS 0x1f24 9433#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 9434#define regHPD2_DC_HPD_INT_CONTROL 0x1f25 9435#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 9436#define regHPD2_DC_HPD_CONTROL 0x1f26 9437#define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 9438#define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 9439#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9440#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 9441#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9442 9443 9444// addressBlock: dce_dc_dio_hpd3_dispdec 9445// base address: 0x60 9446#define regHPD3_DC_HPD_INT_STATUS 0x1f2c 9447#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 9448#define regHPD3_DC_HPD_INT_CONTROL 0x1f2d 9449#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 9450#define regHPD3_DC_HPD_CONTROL 0x1f2e 9451#define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 9452#define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f 9453#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9454#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 9455#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9456 9457 9458// addressBlock: dce_dc_dio_hpd4_dispdec 9459// base address: 0x80 9460#define regHPD4_DC_HPD_INT_STATUS 0x1f34 9461#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 9462#define regHPD4_DC_HPD_INT_CONTROL 0x1f35 9463#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 9464#define regHPD4_DC_HPD_CONTROL 0x1f36 9465#define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 9466#define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 9467#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9468#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 9469#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9470 9471 9472// addressBlock: dce_dc_dio_dp0_dispdec 9473// base address: 0x0 9474#define regDP0_DP_LINK_CNTL 0x2108 9475#define regDP0_DP_LINK_CNTL_BASE_IDX 2 9476#define regDP0_DP_PIXEL_FORMAT 0x2109 9477#define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 9478#define regDP0_DP_MSA_COLORIMETRY 0x210a 9479#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 9480#define regDP0_DP_CONFIG 0x210b 9481#define regDP0_DP_CONFIG_BASE_IDX 2 9482#define regDP0_DP_VID_STREAM_CNTL 0x210c 9483#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 9484#define regDP0_DP_STEER_FIFO 0x210d 9485#define regDP0_DP_STEER_FIFO_BASE_IDX 2 9486#define regDP0_DP_MSA_MISC 0x210e 9487#define regDP0_DP_MSA_MISC_BASE_IDX 2 9488#define regDP0_DP_DPHY_INTERNAL_CTRL 0x210f 9489#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9490#define regDP0_DP_VID_TIMING 0x2110 9491#define regDP0_DP_VID_TIMING_BASE_IDX 2 9492#define regDP0_DP_VID_N 0x2111 9493#define regDP0_DP_VID_N_BASE_IDX 2 9494#define regDP0_DP_VID_M 0x2112 9495#define regDP0_DP_VID_M_BASE_IDX 2 9496#define regDP0_DP_LINK_FRAMING_CNTL 0x2113 9497#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9498#define regDP0_DP_HBR2_EYE_PATTERN 0x2114 9499#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9500#define regDP0_DP_VID_MSA_VBID 0x2115 9501#define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 9502#define regDP0_DP_VID_INTERRUPT_CNTL 0x2116 9503#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9504#define regDP0_DP_DPHY_CNTL 0x2117 9505#define regDP0_DP_DPHY_CNTL_BASE_IDX 2 9506#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 9507#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9508#define regDP0_DP_DPHY_SYM0 0x2119 9509#define regDP0_DP_DPHY_SYM0_BASE_IDX 2 9510#define regDP0_DP_DPHY_SYM1 0x211a 9511#define regDP0_DP_DPHY_SYM1_BASE_IDX 2 9512#define regDP0_DP_DPHY_SYM2 0x211b 9513#define regDP0_DP_DPHY_SYM2_BASE_IDX 2 9514#define regDP0_DP_DPHY_8B10B_CNTL 0x211c 9515#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9516#define regDP0_DP_DPHY_PRBS_CNTL 0x211d 9517#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9518#define regDP0_DP_DPHY_SCRAM_CNTL 0x211e 9519#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9520#define regDP0_DP_DPHY_CRC_EN 0x211f 9521#define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 9522#define regDP0_DP_DPHY_CRC_CNTL 0x2120 9523#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 9524#define regDP0_DP_DPHY_CRC_RESULT 0x2121 9525#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 9526#define regDP0_DP_DPHY_CRC_MST_CNTL 0x2122 9527#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9528#define regDP0_DP_DPHY_CRC_MST_STATUS 0x2123 9529#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9530#define regDP0_DP_DPHY_FAST_TRAINING 0x2124 9531#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9532#define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 9533#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9534#define regDP0_DP_SEC_CNTL 0x212b 9535#define regDP0_DP_SEC_CNTL_BASE_IDX 2 9536#define regDP0_DP_SEC_CNTL1 0x212c 9537#define regDP0_DP_SEC_CNTL1_BASE_IDX 2 9538#define regDP0_DP_SEC_FRAMING1 0x212d 9539#define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 9540#define regDP0_DP_SEC_FRAMING2 0x212e 9541#define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 9542#define regDP0_DP_SEC_FRAMING3 0x212f 9543#define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 9544#define regDP0_DP_SEC_FRAMING4 0x2130 9545#define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 9546#define regDP0_DP_SEC_AUD_N 0x2131 9547#define regDP0_DP_SEC_AUD_N_BASE_IDX 2 9548#define regDP0_DP_SEC_AUD_N_READBACK 0x2132 9549#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9550#define regDP0_DP_SEC_AUD_M 0x2133 9551#define regDP0_DP_SEC_AUD_M_BASE_IDX 2 9552#define regDP0_DP_SEC_AUD_M_READBACK 0x2134 9553#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9554#define regDP0_DP_SEC_TIMESTAMP 0x2135 9555#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 9556#define regDP0_DP_SEC_PACKET_CNTL 0x2136 9557#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 9558#define regDP0_DP_MSE_RATE_CNTL 0x2137 9559#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 9560#define regDP0_DP_MSE_RATE_UPDATE 0x2139 9561#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 9562#define regDP0_DP_MSE_SAT0 0x213a 9563#define regDP0_DP_MSE_SAT0_BASE_IDX 2 9564#define regDP0_DP_MSE_SAT1 0x213b 9565#define regDP0_DP_MSE_SAT1_BASE_IDX 2 9566#define regDP0_DP_MSE_SAT2 0x213c 9567#define regDP0_DP_MSE_SAT2_BASE_IDX 2 9568#define regDP0_DP_MSE_SAT_UPDATE 0x213d 9569#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 9570#define regDP0_DP_MSE_LINK_TIMING 0x213e 9571#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 9572#define regDP0_DP_MSE_MISC_CNTL 0x213f 9573#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 9574#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 9575#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9576#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 9577#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9578#define regDP0_DP_MSE_SAT0_STATUS 0x2147 9579#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 9580#define regDP0_DP_MSE_SAT1_STATUS 0x2148 9581#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 9582#define regDP0_DP_MSE_SAT2_STATUS 0x2149 9583#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 9584#define regDP0_DP_MSA_TIMING_PARAM1 0x214c 9585#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9586#define regDP0_DP_MSA_TIMING_PARAM2 0x214d 9587#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9588#define regDP0_DP_MSA_TIMING_PARAM3 0x214e 9589#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9590#define regDP0_DP_MSA_TIMING_PARAM4 0x214f 9591#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9592#define regDP0_DP_MSO_CNTL 0x2150 9593#define regDP0_DP_MSO_CNTL_BASE_IDX 2 9594#define regDP0_DP_MSO_CNTL1 0x2151 9595#define regDP0_DP_MSO_CNTL1_BASE_IDX 2 9596#define regDP0_DP_DSC_CNTL 0x2152 9597#define regDP0_DP_DSC_CNTL_BASE_IDX 2 9598#define regDP0_DP_SEC_CNTL2 0x2153 9599#define regDP0_DP_SEC_CNTL2_BASE_IDX 2 9600#define regDP0_DP_SEC_CNTL3 0x2154 9601#define regDP0_DP_SEC_CNTL3_BASE_IDX 2 9602#define regDP0_DP_SEC_CNTL4 0x2155 9603#define regDP0_DP_SEC_CNTL4_BASE_IDX 2 9604#define regDP0_DP_SEC_CNTL5 0x2156 9605#define regDP0_DP_SEC_CNTL5_BASE_IDX 2 9606#define regDP0_DP_SEC_CNTL6 0x2157 9607#define regDP0_DP_SEC_CNTL6_BASE_IDX 2 9608#define regDP0_DP_SEC_CNTL7 0x2158 9609#define regDP0_DP_SEC_CNTL7_BASE_IDX 2 9610#define regDP0_DP_DB_CNTL 0x2159 9611#define regDP0_DP_DB_CNTL_BASE_IDX 2 9612#define regDP0_DP_MSA_VBID_MISC 0x215a 9613#define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 9614#define regDP0_DP_SEC_METADATA_TRANSMISSION 0x215b 9615#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9616#define regDP0_DP_DSC_BYTES_PER_PIXEL 0x215c 9617#define regDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 9618#define regDP0_DP_ALPM_CNTL 0x215d 9619#define regDP0_DP_ALPM_CNTL_BASE_IDX 2 9620#define regDP0_DP_GSP8_CNTL 0x215e 9621#define regDP0_DP_GSP8_CNTL_BASE_IDX 2 9622#define regDP0_DP_GSP9_CNTL 0x215f 9623#define regDP0_DP_GSP9_CNTL_BASE_IDX 2 9624#define regDP0_DP_GSP10_CNTL 0x2160 9625#define regDP0_DP_GSP10_CNTL_BASE_IDX 2 9626#define regDP0_DP_GSP11_CNTL 0x2161 9627#define regDP0_DP_GSP11_CNTL_BASE_IDX 2 9628#define regDP0_DP_GSP_EN_DB_STATUS 0x2162 9629#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9630 9631 9632// addressBlock: dce_dc_dio_dig0_dispdec 9633// base address: 0x0 9634#define regDIG0_DIG_FE_CNTL 0x208b 9635#define regDIG0_DIG_FE_CNTL_BASE_IDX 2 9636#define regDIG0_DIG_OUTPUT_CRC_CNTL 0x208c 9637#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9638#define regDIG0_DIG_OUTPUT_CRC_RESULT 0x208d 9639#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9640#define regDIG0_DIG_CLOCK_PATTERN 0x208e 9641#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 9642#define regDIG0_DIG_TEST_PATTERN 0x208f 9643#define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 9644#define regDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 9645#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9646#define regDIG0_DIG_FIFO_STATUS 0x2091 9647#define regDIG0_DIG_FIFO_STATUS_BASE_IDX 2 9648#define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x2092 9649#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9650#define regDIG0_HDMI_CONTROL 0x2093 9651#define regDIG0_HDMI_CONTROL_BASE_IDX 2 9652#define regDIG0_HDMI_STATUS 0x2094 9653#define regDIG0_HDMI_STATUS_BASE_IDX 2 9654#define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2095 9655#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9656#define regDIG0_HDMI_ACR_PACKET_CONTROL 0x2096 9657#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9658#define regDIG0_HDMI_VBI_PACKET_CONTROL 0x2097 9659#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9660#define regDIG0_HDMI_INFOFRAME_CONTROL0 0x2098 9661#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9662#define regDIG0_HDMI_INFOFRAME_CONTROL1 0x2099 9663#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9664#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209a 9665#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9666#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209b 9667#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9668#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209c 9669#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9670#define regDIG0_HDMI_GC 0x209d 9671#define regDIG0_HDMI_GC_BASE_IDX 2 9672#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209e 9673#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9674#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x209f 9675#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9676#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a0 9677#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9678#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a1 9679#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9680#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a2 9681#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9682#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a3 9683#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9684#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a4 9685#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9686#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a5 9687#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9688#define regDIG0_HDMI_DB_CONTROL 0x20a6 9689#define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 9690#define regDIG0_HDMI_ACR_32_0 0x20a7 9691#define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 9692#define regDIG0_HDMI_ACR_32_1 0x20a8 9693#define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 9694#define regDIG0_HDMI_ACR_44_0 0x20a9 9695#define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 9696#define regDIG0_HDMI_ACR_44_1 0x20aa 9697#define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 9698#define regDIG0_HDMI_ACR_48_0 0x20ab 9699#define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 9700#define regDIG0_HDMI_ACR_48_1 0x20ac 9701#define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 9702#define regDIG0_HDMI_ACR_STATUS_0 0x20ad 9703#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 9704#define regDIG0_HDMI_ACR_STATUS_1 0x20ae 9705#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 9706#define regDIG0_AFMT_CNTL 0x20af 9707#define regDIG0_AFMT_CNTL_BASE_IDX 2 9708#define regDIG0_DIG_BE_CNTL 0x20b0 9709#define regDIG0_DIG_BE_CNTL_BASE_IDX 2 9710#define regDIG0_DIG_BE_EN_CNTL 0x20b1 9711#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 9712#define regDIG0_TMDS_CNTL 0x20d7 9713#define regDIG0_TMDS_CNTL_BASE_IDX 2 9714#define regDIG0_TMDS_CONTROL_CHAR 0x20d8 9715#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 9716#define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20d9 9717#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9718#define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20da 9719#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9720#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20db 9721#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9722#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dc 9723#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9724#define regDIG0_TMDS_CTL_BITS 0x20de 9725#define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 9726#define regDIG0_TMDS_DCBALANCER_CONTROL 0x20df 9727#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9728#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e0 9729#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9730#define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e1 9731#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9732#define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e2 9733#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9734#define regDIG0_DIG_VERSION 0x20e4 9735#define regDIG0_DIG_VERSION_BASE_IDX 2 9736#define regDIG0_FORCE_DIG_DISABLE 0x20e5 9737#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 9738 9739 9740// addressBlock: dce_dc_dio_dp1_dispdec 9741// base address: 0x400 9742#define regDP1_DP_LINK_CNTL 0x2208 9743#define regDP1_DP_LINK_CNTL_BASE_IDX 2 9744#define regDP1_DP_PIXEL_FORMAT 0x2209 9745#define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 9746#define regDP1_DP_MSA_COLORIMETRY 0x220a 9747#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 9748#define regDP1_DP_CONFIG 0x220b 9749#define regDP1_DP_CONFIG_BASE_IDX 2 9750#define regDP1_DP_VID_STREAM_CNTL 0x220c 9751#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 9752#define regDP1_DP_STEER_FIFO 0x220d 9753#define regDP1_DP_STEER_FIFO_BASE_IDX 2 9754#define regDP1_DP_MSA_MISC 0x220e 9755#define regDP1_DP_MSA_MISC_BASE_IDX 2 9756#define regDP1_DP_DPHY_INTERNAL_CTRL 0x220f 9757#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9758#define regDP1_DP_VID_TIMING 0x2210 9759#define regDP1_DP_VID_TIMING_BASE_IDX 2 9760#define regDP1_DP_VID_N 0x2211 9761#define regDP1_DP_VID_N_BASE_IDX 2 9762#define regDP1_DP_VID_M 0x2212 9763#define regDP1_DP_VID_M_BASE_IDX 2 9764#define regDP1_DP_LINK_FRAMING_CNTL 0x2213 9765#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9766#define regDP1_DP_HBR2_EYE_PATTERN 0x2214 9767#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9768#define regDP1_DP_VID_MSA_VBID 0x2215 9769#define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 9770#define regDP1_DP_VID_INTERRUPT_CNTL 0x2216 9771#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9772#define regDP1_DP_DPHY_CNTL 0x2217 9773#define regDP1_DP_DPHY_CNTL_BASE_IDX 2 9774#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 9775#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9776#define regDP1_DP_DPHY_SYM0 0x2219 9777#define regDP1_DP_DPHY_SYM0_BASE_IDX 2 9778#define regDP1_DP_DPHY_SYM1 0x221a 9779#define regDP1_DP_DPHY_SYM1_BASE_IDX 2 9780#define regDP1_DP_DPHY_SYM2 0x221b 9781#define regDP1_DP_DPHY_SYM2_BASE_IDX 2 9782#define regDP1_DP_DPHY_8B10B_CNTL 0x221c 9783#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9784#define regDP1_DP_DPHY_PRBS_CNTL 0x221d 9785#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9786#define regDP1_DP_DPHY_SCRAM_CNTL 0x221e 9787#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9788#define regDP1_DP_DPHY_CRC_EN 0x221f 9789#define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 9790#define regDP1_DP_DPHY_CRC_CNTL 0x2220 9791#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 9792#define regDP1_DP_DPHY_CRC_RESULT 0x2221 9793#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 9794#define regDP1_DP_DPHY_CRC_MST_CNTL 0x2222 9795#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9796#define regDP1_DP_DPHY_CRC_MST_STATUS 0x2223 9797#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9798#define regDP1_DP_DPHY_FAST_TRAINING 0x2224 9799#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9800#define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 9801#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9802#define regDP1_DP_SEC_CNTL 0x222b 9803#define regDP1_DP_SEC_CNTL_BASE_IDX 2 9804#define regDP1_DP_SEC_CNTL1 0x222c 9805#define regDP1_DP_SEC_CNTL1_BASE_IDX 2 9806#define regDP1_DP_SEC_FRAMING1 0x222d 9807#define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 9808#define regDP1_DP_SEC_FRAMING2 0x222e 9809#define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 9810#define regDP1_DP_SEC_FRAMING3 0x222f 9811#define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 9812#define regDP1_DP_SEC_FRAMING4 0x2230 9813#define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 9814#define regDP1_DP_SEC_AUD_N 0x2231 9815#define regDP1_DP_SEC_AUD_N_BASE_IDX 2 9816#define regDP1_DP_SEC_AUD_N_READBACK 0x2232 9817#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9818#define regDP1_DP_SEC_AUD_M 0x2233 9819#define regDP1_DP_SEC_AUD_M_BASE_IDX 2 9820#define regDP1_DP_SEC_AUD_M_READBACK 0x2234 9821#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9822#define regDP1_DP_SEC_TIMESTAMP 0x2235 9823#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 9824#define regDP1_DP_SEC_PACKET_CNTL 0x2236 9825#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 9826#define regDP1_DP_MSE_RATE_CNTL 0x2237 9827#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 9828#define regDP1_DP_MSE_RATE_UPDATE 0x2239 9829#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 9830#define regDP1_DP_MSE_SAT0 0x223a 9831#define regDP1_DP_MSE_SAT0_BASE_IDX 2 9832#define regDP1_DP_MSE_SAT1 0x223b 9833#define regDP1_DP_MSE_SAT1_BASE_IDX 2 9834#define regDP1_DP_MSE_SAT2 0x223c 9835#define regDP1_DP_MSE_SAT2_BASE_IDX 2 9836#define regDP1_DP_MSE_SAT_UPDATE 0x223d 9837#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 9838#define regDP1_DP_MSE_LINK_TIMING 0x223e 9839#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 9840#define regDP1_DP_MSE_MISC_CNTL 0x223f 9841#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 9842#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 9843#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9844#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 9845#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9846#define regDP1_DP_MSE_SAT0_STATUS 0x2247 9847#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 9848#define regDP1_DP_MSE_SAT1_STATUS 0x2248 9849#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 9850#define regDP1_DP_MSE_SAT2_STATUS 0x2249 9851#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 9852#define regDP1_DP_MSA_TIMING_PARAM1 0x224c 9853#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9854#define regDP1_DP_MSA_TIMING_PARAM2 0x224d 9855#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9856#define regDP1_DP_MSA_TIMING_PARAM3 0x224e 9857#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9858#define regDP1_DP_MSA_TIMING_PARAM4 0x224f 9859#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9860#define regDP1_DP_MSO_CNTL 0x2250 9861#define regDP1_DP_MSO_CNTL_BASE_IDX 2 9862#define regDP1_DP_MSO_CNTL1 0x2251 9863#define regDP1_DP_MSO_CNTL1_BASE_IDX 2 9864#define regDP1_DP_DSC_CNTL 0x2252 9865#define regDP1_DP_DSC_CNTL_BASE_IDX 2 9866#define regDP1_DP_SEC_CNTL2 0x2253 9867#define regDP1_DP_SEC_CNTL2_BASE_IDX 2 9868#define regDP1_DP_SEC_CNTL3 0x2254 9869#define regDP1_DP_SEC_CNTL3_BASE_IDX 2 9870#define regDP1_DP_SEC_CNTL4 0x2255 9871#define regDP1_DP_SEC_CNTL4_BASE_IDX 2 9872#define regDP1_DP_SEC_CNTL5 0x2256 9873#define regDP1_DP_SEC_CNTL5_BASE_IDX 2 9874#define regDP1_DP_SEC_CNTL6 0x2257 9875#define regDP1_DP_SEC_CNTL6_BASE_IDX 2 9876#define regDP1_DP_SEC_CNTL7 0x2258 9877#define regDP1_DP_SEC_CNTL7_BASE_IDX 2 9878#define regDP1_DP_DB_CNTL 0x2259 9879#define regDP1_DP_DB_CNTL_BASE_IDX 2 9880#define regDP1_DP_MSA_VBID_MISC 0x225a 9881#define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 9882#define regDP1_DP_SEC_METADATA_TRANSMISSION 0x225b 9883#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9884#define regDP1_DP_DSC_BYTES_PER_PIXEL 0x225c 9885#define regDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 9886#define regDP1_DP_ALPM_CNTL 0x225d 9887#define regDP1_DP_ALPM_CNTL_BASE_IDX 2 9888#define regDP1_DP_GSP8_CNTL 0x225e 9889#define regDP1_DP_GSP8_CNTL_BASE_IDX 2 9890#define regDP1_DP_GSP9_CNTL 0x225f 9891#define regDP1_DP_GSP9_CNTL_BASE_IDX 2 9892#define regDP1_DP_GSP10_CNTL 0x2260 9893#define regDP1_DP_GSP10_CNTL_BASE_IDX 2 9894#define regDP1_DP_GSP11_CNTL 0x2261 9895#define regDP1_DP_GSP11_CNTL_BASE_IDX 2 9896#define regDP1_DP_GSP_EN_DB_STATUS 0x2262 9897#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9898 9899 9900// addressBlock: dce_dc_dio_dig1_dispdec 9901// base address: 0x400 9902#define regDIG1_DIG_FE_CNTL 0x218b 9903#define regDIG1_DIG_FE_CNTL_BASE_IDX 2 9904#define regDIG1_DIG_OUTPUT_CRC_CNTL 0x218c 9905#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9906#define regDIG1_DIG_OUTPUT_CRC_RESULT 0x218d 9907#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9908#define regDIG1_DIG_CLOCK_PATTERN 0x218e 9909#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 9910#define regDIG1_DIG_TEST_PATTERN 0x218f 9911#define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 9912#define regDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 9913#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9914#define regDIG1_DIG_FIFO_STATUS 0x2191 9915#define regDIG1_DIG_FIFO_STATUS_BASE_IDX 2 9916#define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x2192 9917#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9918#define regDIG1_HDMI_CONTROL 0x2193 9919#define regDIG1_HDMI_CONTROL_BASE_IDX 2 9920#define regDIG1_HDMI_STATUS 0x2194 9921#define regDIG1_HDMI_STATUS_BASE_IDX 2 9922#define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2195 9923#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9924#define regDIG1_HDMI_ACR_PACKET_CONTROL 0x2196 9925#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9926#define regDIG1_HDMI_VBI_PACKET_CONTROL 0x2197 9927#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9928#define regDIG1_HDMI_INFOFRAME_CONTROL0 0x2198 9929#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9930#define regDIG1_HDMI_INFOFRAME_CONTROL1 0x2199 9931#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9932#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219a 9933#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9934#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219b 9935#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9936#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219c 9937#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9938#define regDIG1_HDMI_GC 0x219d 9939#define regDIG1_HDMI_GC_BASE_IDX 2 9940#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219e 9941#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9942#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x219f 9943#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9944#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a0 9945#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9946#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a1 9947#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9948#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a2 9949#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9950#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a3 9951#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9952#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a4 9953#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9954#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a5 9955#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9956#define regDIG1_HDMI_DB_CONTROL 0x21a6 9957#define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 9958#define regDIG1_HDMI_ACR_32_0 0x21a7 9959#define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 9960#define regDIG1_HDMI_ACR_32_1 0x21a8 9961#define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 9962#define regDIG1_HDMI_ACR_44_0 0x21a9 9963#define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 9964#define regDIG1_HDMI_ACR_44_1 0x21aa 9965#define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 9966#define regDIG1_HDMI_ACR_48_0 0x21ab 9967#define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 9968#define regDIG1_HDMI_ACR_48_1 0x21ac 9969#define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 9970#define regDIG1_HDMI_ACR_STATUS_0 0x21ad 9971#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 9972#define regDIG1_HDMI_ACR_STATUS_1 0x21ae 9973#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 9974#define regDIG1_AFMT_CNTL 0x21af 9975#define regDIG1_AFMT_CNTL_BASE_IDX 2 9976#define regDIG1_DIG_BE_CNTL 0x21b0 9977#define regDIG1_DIG_BE_CNTL_BASE_IDX 2 9978#define regDIG1_DIG_BE_EN_CNTL 0x21b1 9979#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 9980#define regDIG1_TMDS_CNTL 0x21d7 9981#define regDIG1_TMDS_CNTL_BASE_IDX 2 9982#define regDIG1_TMDS_CONTROL_CHAR 0x21d8 9983#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 9984#define regDIG1_TMDS_CONTROL0_FEEDBACK 0x21d9 9985#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9986#define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21da 9987#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9988#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21db 9989#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9990#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dc 9991#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9992#define regDIG1_TMDS_CTL_BITS 0x21de 9993#define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 9994#define regDIG1_TMDS_DCBALANCER_CONTROL 0x21df 9995#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9996#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e0 9997#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9998#define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e1 9999#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10000#define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e2 10001#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10002#define regDIG1_DIG_VERSION 0x21e4 10003#define regDIG1_DIG_VERSION_BASE_IDX 2 10004#define regDIG1_FORCE_DIG_DISABLE 0x21e5 10005#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 10006 10007 10008// addressBlock: dce_dc_dio_dp2_dispdec 10009// base address: 0x800 10010#define regDP2_DP_LINK_CNTL 0x2308 10011#define regDP2_DP_LINK_CNTL_BASE_IDX 2 10012#define regDP2_DP_PIXEL_FORMAT 0x2309 10013#define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 10014#define regDP2_DP_MSA_COLORIMETRY 0x230a 10015#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 10016#define regDP2_DP_CONFIG 0x230b 10017#define regDP2_DP_CONFIG_BASE_IDX 2 10018#define regDP2_DP_VID_STREAM_CNTL 0x230c 10019#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 10020#define regDP2_DP_STEER_FIFO 0x230d 10021#define regDP2_DP_STEER_FIFO_BASE_IDX 2 10022#define regDP2_DP_MSA_MISC 0x230e 10023#define regDP2_DP_MSA_MISC_BASE_IDX 2 10024#define regDP2_DP_DPHY_INTERNAL_CTRL 0x230f 10025#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10026#define regDP2_DP_VID_TIMING 0x2310 10027#define regDP2_DP_VID_TIMING_BASE_IDX 2 10028#define regDP2_DP_VID_N 0x2311 10029#define regDP2_DP_VID_N_BASE_IDX 2 10030#define regDP2_DP_VID_M 0x2312 10031#define regDP2_DP_VID_M_BASE_IDX 2 10032#define regDP2_DP_LINK_FRAMING_CNTL 0x2313 10033#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10034#define regDP2_DP_HBR2_EYE_PATTERN 0x2314 10035#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10036#define regDP2_DP_VID_MSA_VBID 0x2315 10037#define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 10038#define regDP2_DP_VID_INTERRUPT_CNTL 0x2316 10039#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10040#define regDP2_DP_DPHY_CNTL 0x2317 10041#define regDP2_DP_DPHY_CNTL_BASE_IDX 2 10042#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 10043#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10044#define regDP2_DP_DPHY_SYM0 0x2319 10045#define regDP2_DP_DPHY_SYM0_BASE_IDX 2 10046#define regDP2_DP_DPHY_SYM1 0x231a 10047#define regDP2_DP_DPHY_SYM1_BASE_IDX 2 10048#define regDP2_DP_DPHY_SYM2 0x231b 10049#define regDP2_DP_DPHY_SYM2_BASE_IDX 2 10050#define regDP2_DP_DPHY_8B10B_CNTL 0x231c 10051#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10052#define regDP2_DP_DPHY_PRBS_CNTL 0x231d 10053#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10054#define regDP2_DP_DPHY_SCRAM_CNTL 0x231e 10055#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10056#define regDP2_DP_DPHY_CRC_EN 0x231f 10057#define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 10058#define regDP2_DP_DPHY_CRC_CNTL 0x2320 10059#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 10060#define regDP2_DP_DPHY_CRC_RESULT 0x2321 10061#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 10062#define regDP2_DP_DPHY_CRC_MST_CNTL 0x2322 10063#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10064#define regDP2_DP_DPHY_CRC_MST_STATUS 0x2323 10065#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10066#define regDP2_DP_DPHY_FAST_TRAINING 0x2324 10067#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10068#define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 10069#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10070#define regDP2_DP_SEC_CNTL 0x232b 10071#define regDP2_DP_SEC_CNTL_BASE_IDX 2 10072#define regDP2_DP_SEC_CNTL1 0x232c 10073#define regDP2_DP_SEC_CNTL1_BASE_IDX 2 10074#define regDP2_DP_SEC_FRAMING1 0x232d 10075#define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 10076#define regDP2_DP_SEC_FRAMING2 0x232e 10077#define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 10078#define regDP2_DP_SEC_FRAMING3 0x232f 10079#define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 10080#define regDP2_DP_SEC_FRAMING4 0x2330 10081#define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 10082#define regDP2_DP_SEC_AUD_N 0x2331 10083#define regDP2_DP_SEC_AUD_N_BASE_IDX 2 10084#define regDP2_DP_SEC_AUD_N_READBACK 0x2332 10085#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10086#define regDP2_DP_SEC_AUD_M 0x2333 10087#define regDP2_DP_SEC_AUD_M_BASE_IDX 2 10088#define regDP2_DP_SEC_AUD_M_READBACK 0x2334 10089#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10090#define regDP2_DP_SEC_TIMESTAMP 0x2335 10091#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 10092#define regDP2_DP_SEC_PACKET_CNTL 0x2336 10093#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 10094#define regDP2_DP_MSE_RATE_CNTL 0x2337 10095#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 10096#define regDP2_DP_MSE_RATE_UPDATE 0x2339 10097#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 10098#define regDP2_DP_MSE_SAT0 0x233a 10099#define regDP2_DP_MSE_SAT0_BASE_IDX 2 10100#define regDP2_DP_MSE_SAT1 0x233b 10101#define regDP2_DP_MSE_SAT1_BASE_IDX 2 10102#define regDP2_DP_MSE_SAT2 0x233c 10103#define regDP2_DP_MSE_SAT2_BASE_IDX 2 10104#define regDP2_DP_MSE_SAT_UPDATE 0x233d 10105#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 10106#define regDP2_DP_MSE_LINK_TIMING 0x233e 10107#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 10108#define regDP2_DP_MSE_MISC_CNTL 0x233f 10109#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 10110#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 10111#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10112#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 10113#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10114#define regDP2_DP_MSE_SAT0_STATUS 0x2347 10115#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 10116#define regDP2_DP_MSE_SAT1_STATUS 0x2348 10117#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 10118#define regDP2_DP_MSE_SAT2_STATUS 0x2349 10119#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 10120#define regDP2_DP_MSA_TIMING_PARAM1 0x234c 10121#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10122#define regDP2_DP_MSA_TIMING_PARAM2 0x234d 10123#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10124#define regDP2_DP_MSA_TIMING_PARAM3 0x234e 10125#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10126#define regDP2_DP_MSA_TIMING_PARAM4 0x234f 10127#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10128#define regDP2_DP_MSO_CNTL 0x2350 10129#define regDP2_DP_MSO_CNTL_BASE_IDX 2 10130#define regDP2_DP_MSO_CNTL1 0x2351 10131#define regDP2_DP_MSO_CNTL1_BASE_IDX 2 10132#define regDP2_DP_DSC_CNTL 0x2352 10133#define regDP2_DP_DSC_CNTL_BASE_IDX 2 10134#define regDP2_DP_SEC_CNTL2 0x2353 10135#define regDP2_DP_SEC_CNTL2_BASE_IDX 2 10136#define regDP2_DP_SEC_CNTL3 0x2354 10137#define regDP2_DP_SEC_CNTL3_BASE_IDX 2 10138#define regDP2_DP_SEC_CNTL4 0x2355 10139#define regDP2_DP_SEC_CNTL4_BASE_IDX 2 10140#define regDP2_DP_SEC_CNTL5 0x2356 10141#define regDP2_DP_SEC_CNTL5_BASE_IDX 2 10142#define regDP2_DP_SEC_CNTL6 0x2357 10143#define regDP2_DP_SEC_CNTL6_BASE_IDX 2 10144#define regDP2_DP_SEC_CNTL7 0x2358 10145#define regDP2_DP_SEC_CNTL7_BASE_IDX 2 10146#define regDP2_DP_DB_CNTL 0x2359 10147#define regDP2_DP_DB_CNTL_BASE_IDX 2 10148#define regDP2_DP_MSA_VBID_MISC 0x235a 10149#define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 10150#define regDP2_DP_SEC_METADATA_TRANSMISSION 0x235b 10151#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10152#define regDP2_DP_DSC_BYTES_PER_PIXEL 0x235c 10153#define regDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10154#define regDP2_DP_ALPM_CNTL 0x235d 10155#define regDP2_DP_ALPM_CNTL_BASE_IDX 2 10156#define regDP2_DP_GSP8_CNTL 0x235e 10157#define regDP2_DP_GSP8_CNTL_BASE_IDX 2 10158#define regDP2_DP_GSP9_CNTL 0x235f 10159#define regDP2_DP_GSP9_CNTL_BASE_IDX 2 10160#define regDP2_DP_GSP10_CNTL 0x2360 10161#define regDP2_DP_GSP10_CNTL_BASE_IDX 2 10162#define regDP2_DP_GSP11_CNTL 0x2361 10163#define regDP2_DP_GSP11_CNTL_BASE_IDX 2 10164#define regDP2_DP_GSP_EN_DB_STATUS 0x2362 10165#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10166 10167 10168// addressBlock: dce_dc_dio_dig2_dispdec 10169// base address: 0x800 10170#define regDIG2_DIG_FE_CNTL 0x228b 10171#define regDIG2_DIG_FE_CNTL_BASE_IDX 2 10172#define regDIG2_DIG_OUTPUT_CRC_CNTL 0x228c 10173#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10174#define regDIG2_DIG_OUTPUT_CRC_RESULT 0x228d 10175#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10176#define regDIG2_DIG_CLOCK_PATTERN 0x228e 10177#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 10178#define regDIG2_DIG_TEST_PATTERN 0x228f 10179#define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 10180#define regDIG2_DIG_RANDOM_PATTERN_SEED 0x2290 10181#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10182#define regDIG2_DIG_FIFO_STATUS 0x2291 10183#define regDIG2_DIG_FIFO_STATUS_BASE_IDX 2 10184#define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x2292 10185#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10186#define regDIG2_HDMI_CONTROL 0x2293 10187#define regDIG2_HDMI_CONTROL_BASE_IDX 2 10188#define regDIG2_HDMI_STATUS 0x2294 10189#define regDIG2_HDMI_STATUS_BASE_IDX 2 10190#define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2295 10191#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10192#define regDIG2_HDMI_ACR_PACKET_CONTROL 0x2296 10193#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10194#define regDIG2_HDMI_VBI_PACKET_CONTROL 0x2297 10195#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10196#define regDIG2_HDMI_INFOFRAME_CONTROL0 0x2298 10197#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10198#define regDIG2_HDMI_INFOFRAME_CONTROL1 0x2299 10199#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10200#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229a 10201#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10202#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229b 10203#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10204#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229c 10205#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10206#define regDIG2_HDMI_GC 0x229d 10207#define regDIG2_HDMI_GC_BASE_IDX 2 10208#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229e 10209#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10210#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x229f 10211#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10212#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a0 10213#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10214#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a1 10215#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10216#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a2 10217#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10218#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a3 10219#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10220#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a4 10221#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10222#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a5 10223#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10224#define regDIG2_HDMI_DB_CONTROL 0x22a6 10225#define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 10226#define regDIG2_HDMI_ACR_32_0 0x22a7 10227#define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 10228#define regDIG2_HDMI_ACR_32_1 0x22a8 10229#define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 10230#define regDIG2_HDMI_ACR_44_0 0x22a9 10231#define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 10232#define regDIG2_HDMI_ACR_44_1 0x22aa 10233#define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 10234#define regDIG2_HDMI_ACR_48_0 0x22ab 10235#define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 10236#define regDIG2_HDMI_ACR_48_1 0x22ac 10237#define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 10238#define regDIG2_HDMI_ACR_STATUS_0 0x22ad 10239#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 10240#define regDIG2_HDMI_ACR_STATUS_1 0x22ae 10241#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 10242#define regDIG2_AFMT_CNTL 0x22af 10243#define regDIG2_AFMT_CNTL_BASE_IDX 2 10244#define regDIG2_DIG_BE_CNTL 0x22b0 10245#define regDIG2_DIG_BE_CNTL_BASE_IDX 2 10246#define regDIG2_DIG_BE_EN_CNTL 0x22b1 10247#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 10248#define regDIG2_TMDS_CNTL 0x22d7 10249#define regDIG2_TMDS_CNTL_BASE_IDX 2 10250#define regDIG2_TMDS_CONTROL_CHAR 0x22d8 10251#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 10252#define regDIG2_TMDS_CONTROL0_FEEDBACK 0x22d9 10253#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10254#define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22da 10255#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10256#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22db 10257#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10258#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dc 10259#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10260#define regDIG2_TMDS_CTL_BITS 0x22de 10261#define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 10262#define regDIG2_TMDS_DCBALANCER_CONTROL 0x22df 10263#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10264#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e0 10265#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10266#define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e1 10267#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10268#define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e2 10269#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10270#define regDIG2_DIG_VERSION 0x22e4 10271#define regDIG2_DIG_VERSION_BASE_IDX 2 10272#define regDIG2_FORCE_DIG_DISABLE 0x22e5 10273#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 10274 10275 10276// addressBlock: dce_dc_dio_dp3_dispdec 10277// base address: 0xc00 10278#define regDP3_DP_LINK_CNTL 0x2408 10279#define regDP3_DP_LINK_CNTL_BASE_IDX 2 10280#define regDP3_DP_PIXEL_FORMAT 0x2409 10281#define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 10282#define regDP3_DP_MSA_COLORIMETRY 0x240a 10283#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 10284#define regDP3_DP_CONFIG 0x240b 10285#define regDP3_DP_CONFIG_BASE_IDX 2 10286#define regDP3_DP_VID_STREAM_CNTL 0x240c 10287#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 10288#define regDP3_DP_STEER_FIFO 0x240d 10289#define regDP3_DP_STEER_FIFO_BASE_IDX 2 10290#define regDP3_DP_MSA_MISC 0x240e 10291#define regDP3_DP_MSA_MISC_BASE_IDX 2 10292#define regDP3_DP_DPHY_INTERNAL_CTRL 0x240f 10293#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10294#define regDP3_DP_VID_TIMING 0x2410 10295#define regDP3_DP_VID_TIMING_BASE_IDX 2 10296#define regDP3_DP_VID_N 0x2411 10297#define regDP3_DP_VID_N_BASE_IDX 2 10298#define regDP3_DP_VID_M 0x2412 10299#define regDP3_DP_VID_M_BASE_IDX 2 10300#define regDP3_DP_LINK_FRAMING_CNTL 0x2413 10301#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10302#define regDP3_DP_HBR2_EYE_PATTERN 0x2414 10303#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10304#define regDP3_DP_VID_MSA_VBID 0x2415 10305#define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 10306#define regDP3_DP_VID_INTERRUPT_CNTL 0x2416 10307#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10308#define regDP3_DP_DPHY_CNTL 0x2417 10309#define regDP3_DP_DPHY_CNTL_BASE_IDX 2 10310#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 10311#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10312#define regDP3_DP_DPHY_SYM0 0x2419 10313#define regDP3_DP_DPHY_SYM0_BASE_IDX 2 10314#define regDP3_DP_DPHY_SYM1 0x241a 10315#define regDP3_DP_DPHY_SYM1_BASE_IDX 2 10316#define regDP3_DP_DPHY_SYM2 0x241b 10317#define regDP3_DP_DPHY_SYM2_BASE_IDX 2 10318#define regDP3_DP_DPHY_8B10B_CNTL 0x241c 10319#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10320#define regDP3_DP_DPHY_PRBS_CNTL 0x241d 10321#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10322#define regDP3_DP_DPHY_SCRAM_CNTL 0x241e 10323#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10324#define regDP3_DP_DPHY_CRC_EN 0x241f 10325#define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 10326#define regDP3_DP_DPHY_CRC_CNTL 0x2420 10327#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 10328#define regDP3_DP_DPHY_CRC_RESULT 0x2421 10329#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 10330#define regDP3_DP_DPHY_CRC_MST_CNTL 0x2422 10331#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10332#define regDP3_DP_DPHY_CRC_MST_STATUS 0x2423 10333#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10334#define regDP3_DP_DPHY_FAST_TRAINING 0x2424 10335#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10336#define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 10337#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10338#define regDP3_DP_SEC_CNTL 0x242b 10339#define regDP3_DP_SEC_CNTL_BASE_IDX 2 10340#define regDP3_DP_SEC_CNTL1 0x242c 10341#define regDP3_DP_SEC_CNTL1_BASE_IDX 2 10342#define regDP3_DP_SEC_FRAMING1 0x242d 10343#define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 10344#define regDP3_DP_SEC_FRAMING2 0x242e 10345#define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 10346#define regDP3_DP_SEC_FRAMING3 0x242f 10347#define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 10348#define regDP3_DP_SEC_FRAMING4 0x2430 10349#define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 10350#define regDP3_DP_SEC_AUD_N 0x2431 10351#define regDP3_DP_SEC_AUD_N_BASE_IDX 2 10352#define regDP3_DP_SEC_AUD_N_READBACK 0x2432 10353#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10354#define regDP3_DP_SEC_AUD_M 0x2433 10355#define regDP3_DP_SEC_AUD_M_BASE_IDX 2 10356#define regDP3_DP_SEC_AUD_M_READBACK 0x2434 10357#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10358#define regDP3_DP_SEC_TIMESTAMP 0x2435 10359#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 10360#define regDP3_DP_SEC_PACKET_CNTL 0x2436 10361#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 10362#define regDP3_DP_MSE_RATE_CNTL 0x2437 10363#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 10364#define regDP3_DP_MSE_RATE_UPDATE 0x2439 10365#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 10366#define regDP3_DP_MSE_SAT0 0x243a 10367#define regDP3_DP_MSE_SAT0_BASE_IDX 2 10368#define regDP3_DP_MSE_SAT1 0x243b 10369#define regDP3_DP_MSE_SAT1_BASE_IDX 2 10370#define regDP3_DP_MSE_SAT2 0x243c 10371#define regDP3_DP_MSE_SAT2_BASE_IDX 2 10372#define regDP3_DP_MSE_SAT_UPDATE 0x243d 10373#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 10374#define regDP3_DP_MSE_LINK_TIMING 0x243e 10375#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 10376#define regDP3_DP_MSE_MISC_CNTL 0x243f 10377#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 10378#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 10379#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10380#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 10381#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10382#define regDP3_DP_MSE_SAT0_STATUS 0x2447 10383#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 10384#define regDP3_DP_MSE_SAT1_STATUS 0x2448 10385#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 10386#define regDP3_DP_MSE_SAT2_STATUS 0x2449 10387#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 10388#define regDP3_DP_MSA_TIMING_PARAM1 0x244c 10389#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10390#define regDP3_DP_MSA_TIMING_PARAM2 0x244d 10391#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10392#define regDP3_DP_MSA_TIMING_PARAM3 0x244e 10393#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10394#define regDP3_DP_MSA_TIMING_PARAM4 0x244f 10395#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10396#define regDP3_DP_MSO_CNTL 0x2450 10397#define regDP3_DP_MSO_CNTL_BASE_IDX 2 10398#define regDP3_DP_MSO_CNTL1 0x2451 10399#define regDP3_DP_MSO_CNTL1_BASE_IDX 2 10400#define regDP3_DP_DSC_CNTL 0x2452 10401#define regDP3_DP_DSC_CNTL_BASE_IDX 2 10402#define regDP3_DP_SEC_CNTL2 0x2453 10403#define regDP3_DP_SEC_CNTL2_BASE_IDX 2 10404#define regDP3_DP_SEC_CNTL3 0x2454 10405#define regDP3_DP_SEC_CNTL3_BASE_IDX 2 10406#define regDP3_DP_SEC_CNTL4 0x2455 10407#define regDP3_DP_SEC_CNTL4_BASE_IDX 2 10408#define regDP3_DP_SEC_CNTL5 0x2456 10409#define regDP3_DP_SEC_CNTL5_BASE_IDX 2 10410#define regDP3_DP_SEC_CNTL6 0x2457 10411#define regDP3_DP_SEC_CNTL6_BASE_IDX 2 10412#define regDP3_DP_SEC_CNTL7 0x2458 10413#define regDP3_DP_SEC_CNTL7_BASE_IDX 2 10414#define regDP3_DP_DB_CNTL 0x2459 10415#define regDP3_DP_DB_CNTL_BASE_IDX 2 10416#define regDP3_DP_MSA_VBID_MISC 0x245a 10417#define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 10418#define regDP3_DP_SEC_METADATA_TRANSMISSION 0x245b 10419#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10420#define regDP3_DP_DSC_BYTES_PER_PIXEL 0x245c 10421#define regDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10422#define regDP3_DP_ALPM_CNTL 0x245d 10423#define regDP3_DP_ALPM_CNTL_BASE_IDX 2 10424#define regDP3_DP_GSP8_CNTL 0x245e 10425#define regDP3_DP_GSP8_CNTL_BASE_IDX 2 10426#define regDP3_DP_GSP9_CNTL 0x245f 10427#define regDP3_DP_GSP9_CNTL_BASE_IDX 2 10428#define regDP3_DP_GSP10_CNTL 0x2460 10429#define regDP3_DP_GSP10_CNTL_BASE_IDX 2 10430#define regDP3_DP_GSP11_CNTL 0x2461 10431#define regDP3_DP_GSP11_CNTL_BASE_IDX 2 10432#define regDP3_DP_GSP_EN_DB_STATUS 0x2462 10433#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10434 10435 10436// addressBlock: dce_dc_dio_dig3_dispdec 10437// base address: 0xc00 10438#define regDIG3_DIG_FE_CNTL 0x238b 10439#define regDIG3_DIG_FE_CNTL_BASE_IDX 2 10440#define regDIG3_DIG_OUTPUT_CRC_CNTL 0x238c 10441#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10442#define regDIG3_DIG_OUTPUT_CRC_RESULT 0x238d 10443#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10444#define regDIG3_DIG_CLOCK_PATTERN 0x238e 10445#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 10446#define regDIG3_DIG_TEST_PATTERN 0x238f 10447#define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 10448#define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2390 10449#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10450#define regDIG3_DIG_FIFO_STATUS 0x2391 10451#define regDIG3_DIG_FIFO_STATUS_BASE_IDX 2 10452#define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2392 10453#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10454#define regDIG3_HDMI_CONTROL 0x2393 10455#define regDIG3_HDMI_CONTROL_BASE_IDX 2 10456#define regDIG3_HDMI_STATUS 0x2394 10457#define regDIG3_HDMI_STATUS_BASE_IDX 2 10458#define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2395 10459#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10460#define regDIG3_HDMI_ACR_PACKET_CONTROL 0x2396 10461#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10462#define regDIG3_HDMI_VBI_PACKET_CONTROL 0x2397 10463#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10464#define regDIG3_HDMI_INFOFRAME_CONTROL0 0x2398 10465#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10466#define regDIG3_HDMI_INFOFRAME_CONTROL1 0x2399 10467#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10468#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239a 10469#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10470#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239b 10471#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10472#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239c 10473#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10474#define regDIG3_HDMI_GC 0x239d 10475#define regDIG3_HDMI_GC_BASE_IDX 2 10476#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239e 10477#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10478#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x239f 10479#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10480#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a0 10481#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10482#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a1 10483#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10484#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a2 10485#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10486#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a3 10487#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10488#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a4 10489#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10490#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a5 10491#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10492#define regDIG3_HDMI_DB_CONTROL 0x23a6 10493#define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 10494#define regDIG3_HDMI_ACR_32_0 0x23a7 10495#define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 10496#define regDIG3_HDMI_ACR_32_1 0x23a8 10497#define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 10498#define regDIG3_HDMI_ACR_44_0 0x23a9 10499#define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 10500#define regDIG3_HDMI_ACR_44_1 0x23aa 10501#define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 10502#define regDIG3_HDMI_ACR_48_0 0x23ab 10503#define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 10504#define regDIG3_HDMI_ACR_48_1 0x23ac 10505#define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 10506#define regDIG3_HDMI_ACR_STATUS_0 0x23ad 10507#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 10508#define regDIG3_HDMI_ACR_STATUS_1 0x23ae 10509#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 10510#define regDIG3_AFMT_CNTL 0x23af 10511#define regDIG3_AFMT_CNTL_BASE_IDX 2 10512#define regDIG3_DIG_BE_CNTL 0x23b0 10513#define regDIG3_DIG_BE_CNTL_BASE_IDX 2 10514#define regDIG3_DIG_BE_EN_CNTL 0x23b1 10515#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 10516#define regDIG3_TMDS_CNTL 0x23d7 10517#define regDIG3_TMDS_CNTL_BASE_IDX 2 10518#define regDIG3_TMDS_CONTROL_CHAR 0x23d8 10519#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 10520#define regDIG3_TMDS_CONTROL0_FEEDBACK 0x23d9 10521#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10522#define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23da 10523#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10524#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23db 10525#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10526#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dc 10527#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10528#define regDIG3_TMDS_CTL_BITS 0x23de 10529#define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 10530#define regDIG3_TMDS_DCBALANCER_CONTROL 0x23df 10531#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10532#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e0 10533#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10534#define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e1 10535#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10536#define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e2 10537#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10538#define regDIG3_DIG_VERSION 0x23e4 10539#define regDIG3_DIG_VERSION_BASE_IDX 2 10540#define regDIG3_FORCE_DIG_DISABLE 0x23e5 10541#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 10542 10543 10544// addressBlock: dce_dc_dio_dp4_dispdec 10545// base address: 0x1000 10546#define regDP4_DP_LINK_CNTL 0x2508 10547#define regDP4_DP_LINK_CNTL_BASE_IDX 2 10548#define regDP4_DP_PIXEL_FORMAT 0x2509 10549#define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 10550#define regDP4_DP_MSA_COLORIMETRY 0x250a 10551#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 10552#define regDP4_DP_CONFIG 0x250b 10553#define regDP4_DP_CONFIG_BASE_IDX 2 10554#define regDP4_DP_VID_STREAM_CNTL 0x250c 10555#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 10556#define regDP4_DP_STEER_FIFO 0x250d 10557#define regDP4_DP_STEER_FIFO_BASE_IDX 2 10558#define regDP4_DP_MSA_MISC 0x250e 10559#define regDP4_DP_MSA_MISC_BASE_IDX 2 10560#define regDP4_DP_DPHY_INTERNAL_CTRL 0x250f 10561#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10562#define regDP4_DP_VID_TIMING 0x2510 10563#define regDP4_DP_VID_TIMING_BASE_IDX 2 10564#define regDP4_DP_VID_N 0x2511 10565#define regDP4_DP_VID_N_BASE_IDX 2 10566#define regDP4_DP_VID_M 0x2512 10567#define regDP4_DP_VID_M_BASE_IDX 2 10568#define regDP4_DP_LINK_FRAMING_CNTL 0x2513 10569#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10570#define regDP4_DP_HBR2_EYE_PATTERN 0x2514 10571#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10572#define regDP4_DP_VID_MSA_VBID 0x2515 10573#define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 10574#define regDP4_DP_VID_INTERRUPT_CNTL 0x2516 10575#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10576#define regDP4_DP_DPHY_CNTL 0x2517 10577#define regDP4_DP_DPHY_CNTL_BASE_IDX 2 10578#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 10579#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10580#define regDP4_DP_DPHY_SYM0 0x2519 10581#define regDP4_DP_DPHY_SYM0_BASE_IDX 2 10582#define regDP4_DP_DPHY_SYM1 0x251a 10583#define regDP4_DP_DPHY_SYM1_BASE_IDX 2 10584#define regDP4_DP_DPHY_SYM2 0x251b 10585#define regDP4_DP_DPHY_SYM2_BASE_IDX 2 10586#define regDP4_DP_DPHY_8B10B_CNTL 0x251c 10587#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10588#define regDP4_DP_DPHY_PRBS_CNTL 0x251d 10589#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10590#define regDP4_DP_DPHY_SCRAM_CNTL 0x251e 10591#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10592#define regDP4_DP_DPHY_CRC_EN 0x251f 10593#define regDP4_DP_DPHY_CRC_EN_BASE_IDX 2 10594#define regDP4_DP_DPHY_CRC_CNTL 0x2520 10595#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 10596#define regDP4_DP_DPHY_CRC_RESULT 0x2521 10597#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 10598#define regDP4_DP_DPHY_CRC_MST_CNTL 0x2522 10599#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10600#define regDP4_DP_DPHY_CRC_MST_STATUS 0x2523 10601#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10602#define regDP4_DP_DPHY_FAST_TRAINING 0x2524 10603#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10604#define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 10605#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10606#define regDP4_DP_SEC_CNTL 0x252b 10607#define regDP4_DP_SEC_CNTL_BASE_IDX 2 10608#define regDP4_DP_SEC_CNTL1 0x252c 10609#define regDP4_DP_SEC_CNTL1_BASE_IDX 2 10610#define regDP4_DP_SEC_FRAMING1 0x252d 10611#define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 10612#define regDP4_DP_SEC_FRAMING2 0x252e 10613#define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 10614#define regDP4_DP_SEC_FRAMING3 0x252f 10615#define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 10616#define regDP4_DP_SEC_FRAMING4 0x2530 10617#define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 10618#define regDP4_DP_SEC_AUD_N 0x2531 10619#define regDP4_DP_SEC_AUD_N_BASE_IDX 2 10620#define regDP4_DP_SEC_AUD_N_READBACK 0x2532 10621#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10622#define regDP4_DP_SEC_AUD_M 0x2533 10623#define regDP4_DP_SEC_AUD_M_BASE_IDX 2 10624#define regDP4_DP_SEC_AUD_M_READBACK 0x2534 10625#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10626#define regDP4_DP_SEC_TIMESTAMP 0x2535 10627#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 10628#define regDP4_DP_SEC_PACKET_CNTL 0x2536 10629#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 10630#define regDP4_DP_MSE_RATE_CNTL 0x2537 10631#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 10632#define regDP4_DP_MSE_RATE_UPDATE 0x2539 10633#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 10634#define regDP4_DP_MSE_SAT0 0x253a 10635#define regDP4_DP_MSE_SAT0_BASE_IDX 2 10636#define regDP4_DP_MSE_SAT1 0x253b 10637#define regDP4_DP_MSE_SAT1_BASE_IDX 2 10638#define regDP4_DP_MSE_SAT2 0x253c 10639#define regDP4_DP_MSE_SAT2_BASE_IDX 2 10640#define regDP4_DP_MSE_SAT_UPDATE 0x253d 10641#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 10642#define regDP4_DP_MSE_LINK_TIMING 0x253e 10643#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 10644#define regDP4_DP_MSE_MISC_CNTL 0x253f 10645#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 10646#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 10647#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10648#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 10649#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10650#define regDP4_DP_MSE_SAT0_STATUS 0x2547 10651#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 10652#define regDP4_DP_MSE_SAT1_STATUS 0x2548 10653#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 10654#define regDP4_DP_MSE_SAT2_STATUS 0x2549 10655#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 10656#define regDP4_DP_MSA_TIMING_PARAM1 0x254c 10657#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10658#define regDP4_DP_MSA_TIMING_PARAM2 0x254d 10659#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10660#define regDP4_DP_MSA_TIMING_PARAM3 0x254e 10661#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10662#define regDP4_DP_MSA_TIMING_PARAM4 0x254f 10663#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10664#define regDP4_DP_MSO_CNTL 0x2550 10665#define regDP4_DP_MSO_CNTL_BASE_IDX 2 10666#define regDP4_DP_MSO_CNTL1 0x2551 10667#define regDP4_DP_MSO_CNTL1_BASE_IDX 2 10668#define regDP4_DP_DSC_CNTL 0x2552 10669#define regDP4_DP_DSC_CNTL_BASE_IDX 2 10670#define regDP4_DP_SEC_CNTL2 0x2553 10671#define regDP4_DP_SEC_CNTL2_BASE_IDX 2 10672#define regDP4_DP_SEC_CNTL3 0x2554 10673#define regDP4_DP_SEC_CNTL3_BASE_IDX 2 10674#define regDP4_DP_SEC_CNTL4 0x2555 10675#define regDP4_DP_SEC_CNTL4_BASE_IDX 2 10676#define regDP4_DP_SEC_CNTL5 0x2556 10677#define regDP4_DP_SEC_CNTL5_BASE_IDX 2 10678#define regDP4_DP_SEC_CNTL6 0x2557 10679#define regDP4_DP_SEC_CNTL6_BASE_IDX 2 10680#define regDP4_DP_SEC_CNTL7 0x2558 10681#define regDP4_DP_SEC_CNTL7_BASE_IDX 2 10682#define regDP4_DP_DB_CNTL 0x2559 10683#define regDP4_DP_DB_CNTL_BASE_IDX 2 10684#define regDP4_DP_MSA_VBID_MISC 0x255a 10685#define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 10686#define regDP4_DP_SEC_METADATA_TRANSMISSION 0x255b 10687#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10688#define regDP4_DP_DSC_BYTES_PER_PIXEL 0x255c 10689#define regDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10690#define regDP4_DP_ALPM_CNTL 0x255d 10691#define regDP4_DP_ALPM_CNTL_BASE_IDX 2 10692#define regDP4_DP_GSP8_CNTL 0x255e 10693#define regDP4_DP_GSP8_CNTL_BASE_IDX 2 10694#define regDP4_DP_GSP9_CNTL 0x255f 10695#define regDP4_DP_GSP9_CNTL_BASE_IDX 2 10696#define regDP4_DP_GSP10_CNTL 0x2560 10697#define regDP4_DP_GSP10_CNTL_BASE_IDX 2 10698#define regDP4_DP_GSP11_CNTL 0x2561 10699#define regDP4_DP_GSP11_CNTL_BASE_IDX 2 10700#define regDP4_DP_GSP_EN_DB_STATUS 0x2562 10701#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10702 10703 10704// addressBlock: dce_dc_dio_dig4_dispdec 10705// base address: 0x1000 10706#define regDIG4_DIG_FE_CNTL 0x248b 10707#define regDIG4_DIG_FE_CNTL_BASE_IDX 2 10708#define regDIG4_DIG_OUTPUT_CRC_CNTL 0x248c 10709#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10710#define regDIG4_DIG_OUTPUT_CRC_RESULT 0x248d 10711#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10712#define regDIG4_DIG_CLOCK_PATTERN 0x248e 10713#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 10714#define regDIG4_DIG_TEST_PATTERN 0x248f 10715#define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 10716#define regDIG4_DIG_RANDOM_PATTERN_SEED 0x2490 10717#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10718#define regDIG4_DIG_FIFO_STATUS 0x2491 10719#define regDIG4_DIG_FIFO_STATUS_BASE_IDX 2 10720#define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x2492 10721#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10722#define regDIG4_HDMI_CONTROL 0x2493 10723#define regDIG4_HDMI_CONTROL_BASE_IDX 2 10724#define regDIG4_HDMI_STATUS 0x2494 10725#define regDIG4_HDMI_STATUS_BASE_IDX 2 10726#define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2495 10727#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10728#define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2496 10729#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10730#define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2497 10731#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10732#define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2498 10733#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10734#define regDIG4_HDMI_INFOFRAME_CONTROL1 0x2499 10735#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10736#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249a 10737#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10738#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249b 10739#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10740#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249c 10741#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10742#define regDIG4_HDMI_GC 0x249d 10743#define regDIG4_HDMI_GC_BASE_IDX 2 10744#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249e 10745#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10746#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x249f 10747#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10748#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a0 10749#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10750#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a1 10751#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10752#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a2 10753#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10754#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a3 10755#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10756#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a4 10757#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10758#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a5 10759#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10760#define regDIG4_HDMI_DB_CONTROL 0x24a6 10761#define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 10762#define regDIG4_HDMI_ACR_32_0 0x24a7 10763#define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 10764#define regDIG4_HDMI_ACR_32_1 0x24a8 10765#define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 10766#define regDIG4_HDMI_ACR_44_0 0x24a9 10767#define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 10768#define regDIG4_HDMI_ACR_44_1 0x24aa 10769#define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 10770#define regDIG4_HDMI_ACR_48_0 0x24ab 10771#define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 10772#define regDIG4_HDMI_ACR_48_1 0x24ac 10773#define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 10774#define regDIG4_HDMI_ACR_STATUS_0 0x24ad 10775#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 10776#define regDIG4_HDMI_ACR_STATUS_1 0x24ae 10777#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 10778#define regDIG4_AFMT_CNTL 0x24af 10779#define regDIG4_AFMT_CNTL_BASE_IDX 2 10780#define regDIG4_DIG_BE_CNTL 0x24b0 10781#define regDIG4_DIG_BE_CNTL_BASE_IDX 2 10782#define regDIG4_DIG_BE_EN_CNTL 0x24b1 10783#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 10784#define regDIG4_TMDS_CNTL 0x24d7 10785#define regDIG4_TMDS_CNTL_BASE_IDX 2 10786#define regDIG4_TMDS_CONTROL_CHAR 0x24d8 10787#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 10788#define regDIG4_TMDS_CONTROL0_FEEDBACK 0x24d9 10789#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10790#define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24da 10791#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10792#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24db 10793#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10794#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dc 10795#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10796#define regDIG4_TMDS_CTL_BITS 0x24de 10797#define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 10798#define regDIG4_TMDS_DCBALANCER_CONTROL 0x24df 10799#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10800#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e0 10801#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10802#define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e1 10803#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10804#define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e2 10805#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10806#define regDIG4_DIG_VERSION 0x24e4 10807#define regDIG4_DIG_VERSION_BASE_IDX 2 10808#define regDIG4_FORCE_DIG_DISABLE 0x24e5 10809#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 10810 10811 10812// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec 10813// base address: 0x154cc 10814#define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 10815#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10816#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 10817#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10818#define regAFMT0_AFMT_AUDIO_INFO0 0x2076 10819#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 10820#define regAFMT0_AFMT_AUDIO_INFO1 0x2077 10821#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 10822#define regAFMT0_AFMT_60958_0 0x2078 10823#define regAFMT0_AFMT_60958_0_BASE_IDX 2 10824#define regAFMT0_AFMT_60958_1 0x2079 10825#define regAFMT0_AFMT_60958_1_BASE_IDX 2 10826#define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a 10827#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10828#define regAFMT0_AFMT_RAMP_CONTROL0 0x207b 10829#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 10830#define regAFMT0_AFMT_RAMP_CONTROL1 0x207c 10831#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 10832#define regAFMT0_AFMT_RAMP_CONTROL2 0x207d 10833#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 10834#define regAFMT0_AFMT_RAMP_CONTROL3 0x207e 10835#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 10836#define regAFMT0_AFMT_60958_2 0x207f 10837#define regAFMT0_AFMT_60958_2_BASE_IDX 2 10838#define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 10839#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10840#define regAFMT0_AFMT_STATUS 0x2081 10841#define regAFMT0_AFMT_STATUS_BASE_IDX 2 10842#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 10843#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10844#define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 10845#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10846#define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 10847#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10848#define regAFMT0_AFMT_MEM_PWR 0x2087 10849#define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 10850 10851 10852// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec 10853// base address: 0x158cc 10854#define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 10855#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10856#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 10857#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10858#define regAFMT1_AFMT_AUDIO_INFO0 0x2176 10859#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 10860#define regAFMT1_AFMT_AUDIO_INFO1 0x2177 10861#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 10862#define regAFMT1_AFMT_60958_0 0x2178 10863#define regAFMT1_AFMT_60958_0_BASE_IDX 2 10864#define regAFMT1_AFMT_60958_1 0x2179 10865#define regAFMT1_AFMT_60958_1_BASE_IDX 2 10866#define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a 10867#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10868#define regAFMT1_AFMT_RAMP_CONTROL0 0x217b 10869#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 10870#define regAFMT1_AFMT_RAMP_CONTROL1 0x217c 10871#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 10872#define regAFMT1_AFMT_RAMP_CONTROL2 0x217d 10873#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 10874#define regAFMT1_AFMT_RAMP_CONTROL3 0x217e 10875#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 10876#define regAFMT1_AFMT_60958_2 0x217f 10877#define regAFMT1_AFMT_60958_2_BASE_IDX 2 10878#define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 10879#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10880#define regAFMT1_AFMT_STATUS 0x2181 10881#define regAFMT1_AFMT_STATUS_BASE_IDX 2 10882#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 10883#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10884#define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 10885#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10886#define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 10887#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10888#define regAFMT1_AFMT_MEM_PWR 0x2187 10889#define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 10890 10891 10892// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec 10893// base address: 0x15ccc 10894#define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274 10895#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10896#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275 10897#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10898#define regAFMT2_AFMT_AUDIO_INFO0 0x2276 10899#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 10900#define regAFMT2_AFMT_AUDIO_INFO1 0x2277 10901#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 10902#define regAFMT2_AFMT_60958_0 0x2278 10903#define regAFMT2_AFMT_60958_0_BASE_IDX 2 10904#define regAFMT2_AFMT_60958_1 0x2279 10905#define regAFMT2_AFMT_60958_1_BASE_IDX 2 10906#define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a 10907#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10908#define regAFMT2_AFMT_RAMP_CONTROL0 0x227b 10909#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 10910#define regAFMT2_AFMT_RAMP_CONTROL1 0x227c 10911#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 10912#define regAFMT2_AFMT_RAMP_CONTROL2 0x227d 10913#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 10914#define regAFMT2_AFMT_RAMP_CONTROL3 0x227e 10915#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 10916#define regAFMT2_AFMT_60958_2 0x227f 10917#define regAFMT2_AFMT_60958_2_BASE_IDX 2 10918#define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280 10919#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10920#define regAFMT2_AFMT_STATUS 0x2281 10921#define regAFMT2_AFMT_STATUS_BASE_IDX 2 10922#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282 10923#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10924#define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283 10925#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10926#define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285 10927#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10928#define regAFMT2_AFMT_MEM_PWR 0x2287 10929#define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 10930 10931 10932// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec 10933// base address: 0x160cc 10934#define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374 10935#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10936#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375 10937#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10938#define regAFMT3_AFMT_AUDIO_INFO0 0x2376 10939#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 10940#define regAFMT3_AFMT_AUDIO_INFO1 0x2377 10941#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 10942#define regAFMT3_AFMT_60958_0 0x2378 10943#define regAFMT3_AFMT_60958_0_BASE_IDX 2 10944#define regAFMT3_AFMT_60958_1 0x2379 10945#define regAFMT3_AFMT_60958_1_BASE_IDX 2 10946#define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a 10947#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10948#define regAFMT3_AFMT_RAMP_CONTROL0 0x237b 10949#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 10950#define regAFMT3_AFMT_RAMP_CONTROL1 0x237c 10951#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 10952#define regAFMT3_AFMT_RAMP_CONTROL2 0x237d 10953#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 10954#define regAFMT3_AFMT_RAMP_CONTROL3 0x237e 10955#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 10956#define regAFMT3_AFMT_60958_2 0x237f 10957#define regAFMT3_AFMT_60958_2_BASE_IDX 2 10958#define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380 10959#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10960#define regAFMT3_AFMT_STATUS 0x2381 10961#define regAFMT3_AFMT_STATUS_BASE_IDX 2 10962#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382 10963#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10964#define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383 10965#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10966#define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385 10967#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10968#define regAFMT3_AFMT_MEM_PWR 0x2387 10969#define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 10970 10971 10972// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec 10973// base address: 0x164cc 10974#define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474 10975#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10976#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475 10977#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10978#define regAFMT4_AFMT_AUDIO_INFO0 0x2476 10979#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 10980#define regAFMT4_AFMT_AUDIO_INFO1 0x2477 10981#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 10982#define regAFMT4_AFMT_60958_0 0x2478 10983#define regAFMT4_AFMT_60958_0_BASE_IDX 2 10984#define regAFMT4_AFMT_60958_1 0x2479 10985#define regAFMT4_AFMT_60958_1_BASE_IDX 2 10986#define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a 10987#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10988#define regAFMT4_AFMT_RAMP_CONTROL0 0x247b 10989#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 10990#define regAFMT4_AFMT_RAMP_CONTROL1 0x247c 10991#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 10992#define regAFMT4_AFMT_RAMP_CONTROL2 0x247d 10993#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 10994#define regAFMT4_AFMT_RAMP_CONTROL3 0x247e 10995#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 10996#define regAFMT4_AFMT_60958_2 0x247f 10997#define regAFMT4_AFMT_60958_2_BASE_IDX 2 10998#define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480 10999#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11000#define regAFMT4_AFMT_STATUS 0x2481 11001#define regAFMT4_AFMT_STATUS_BASE_IDX 2 11002#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482 11003#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11004#define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483 11005#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11006#define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485 11007#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11008#define regAFMT4_AFMT_MEM_PWR 0x2487 11009#define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 11010 11011 11012// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec 11013// base address: 0x15524 11014#define regDME0_DME_CONTROL 0x2089 11015#define regDME0_DME_CONTROL_BASE_IDX 2 11016#define regDME0_DME_MEMORY_CONTROL 0x208a 11017#define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 11018 11019 11020// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec 11021// base address: 0x154a0 11022#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 11023#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11024#define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 11025#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11026#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a 11027#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11028#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b 11029#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11030#define regVPG0_VPG_GENERIC_STATUS 0x206c 11031#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 11032#define regVPG0_VPG_MEM_PWR 0x206d 11033#define regVPG0_VPG_MEM_PWR_BASE_IDX 2 11034#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e 11035#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11036#define regVPG0_VPG_ISRC1_2_DATA 0x206f 11037#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 11038#define regVPG0_VPG_MPEG_INFO0 0x2070 11039#define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 11040#define regVPG0_VPG_MPEG_INFO1 0x2071 11041#define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 11042 11043 11044// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec 11045// base address: 0x15924 11046#define regDME1_DME_CONTROL 0x2189 11047#define regDME1_DME_CONTROL_BASE_IDX 2 11048#define regDME1_DME_MEMORY_CONTROL 0x218a 11049#define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 11050 11051 11052// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec 11053// base address: 0x158a0 11054#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 11055#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11056#define regVPG1_VPG_GENERIC_PACKET_DATA 0x2169 11057#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11058#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a 11059#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11060#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b 11061#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11062#define regVPG1_VPG_GENERIC_STATUS 0x216c 11063#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 11064#define regVPG1_VPG_MEM_PWR 0x216d 11065#define regVPG1_VPG_MEM_PWR_BASE_IDX 2 11066#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e 11067#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11068#define regVPG1_VPG_ISRC1_2_DATA 0x216f 11069#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 11070#define regVPG1_VPG_MPEG_INFO0 0x2170 11071#define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 11072#define regVPG1_VPG_MPEG_INFO1 0x2171 11073#define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 11074 11075 11076// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec 11077// base address: 0x15d24 11078#define regDME2_DME_CONTROL 0x2289 11079#define regDME2_DME_CONTROL_BASE_IDX 2 11080#define regDME2_DME_MEMORY_CONTROL 0x228a 11081#define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 11082 11083 11084// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec 11085// base address: 0x15ca0 11086#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268 11087#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11088#define regVPG2_VPG_GENERIC_PACKET_DATA 0x2269 11089#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11090#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a 11091#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11092#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b 11093#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11094#define regVPG2_VPG_GENERIC_STATUS 0x226c 11095#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 11096#define regVPG2_VPG_MEM_PWR 0x226d 11097#define regVPG2_VPG_MEM_PWR_BASE_IDX 2 11098#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e 11099#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11100#define regVPG2_VPG_ISRC1_2_DATA 0x226f 11101#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 11102#define regVPG2_VPG_MPEG_INFO0 0x2270 11103#define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 11104#define regVPG2_VPG_MPEG_INFO1 0x2271 11105#define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 11106 11107 11108// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec 11109// base address: 0x16124 11110#define regDME3_DME_CONTROL 0x2389 11111#define regDME3_DME_CONTROL_BASE_IDX 2 11112#define regDME3_DME_MEMORY_CONTROL 0x238a 11113#define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 11114 11115 11116// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec 11117// base address: 0x160a0 11118#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368 11119#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11120#define regVPG3_VPG_GENERIC_PACKET_DATA 0x2369 11121#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11122#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a 11123#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11124#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b 11125#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11126#define regVPG3_VPG_GENERIC_STATUS 0x236c 11127#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 11128#define regVPG3_VPG_MEM_PWR 0x236d 11129#define regVPG3_VPG_MEM_PWR_BASE_IDX 2 11130#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e 11131#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11132#define regVPG3_VPG_ISRC1_2_DATA 0x236f 11133#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 11134#define regVPG3_VPG_MPEG_INFO0 0x2370 11135#define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 11136#define regVPG3_VPG_MPEG_INFO1 0x2371 11137#define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 11138 11139 11140// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec 11141// base address: 0x16524 11142#define regDME4_DME_CONTROL 0x2489 11143#define regDME4_DME_CONTROL_BASE_IDX 2 11144#define regDME4_DME_MEMORY_CONTROL 0x248a 11145#define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 11146 11147 11148// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec 11149// base address: 0x164a0 11150#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468 11151#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11152#define regVPG4_VPG_GENERIC_PACKET_DATA 0x2469 11153#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11154#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a 11155#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11156#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b 11157#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11158#define regVPG4_VPG_GENERIC_STATUS 0x246c 11159#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 11160#define regVPG4_VPG_MEM_PWR 0x246d 11161#define regVPG4_VPG_MEM_PWR_BASE_IDX 2 11162#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e 11163#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11164#define regVPG4_VPG_ISRC1_2_DATA 0x246f 11165#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 11166#define regVPG4_VPG_MPEG_INFO0 0x2470 11167#define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 11168#define regVPG4_VPG_MPEG_INFO1 0x2471 11169#define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 11170 11171 11172// addressBlock: dce_dc_dio_dp_aux0_dispdec 11173// base address: 0x0 11174#define regDP_AUX0_AUX_CONTROL 0x1f50 11175#define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 11176#define regDP_AUX0_AUX_SW_CONTROL 0x1f51 11177#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 11178#define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 11179#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 11180#define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 11181#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11182#define regDP_AUX0_AUX_SW_STATUS 0x1f54 11183#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 11184#define regDP_AUX0_AUX_LS_STATUS 0x1f55 11185#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 11186#define regDP_AUX0_AUX_SW_DATA 0x1f56 11187#define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 11188#define regDP_AUX0_AUX_LS_DATA 0x1f57 11189#define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 11190#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 11191#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11192#define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 11193#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11194#define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 11195#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11196#define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 11197#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11198#define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 11199#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 11200#define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 11201#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 11202#define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e 11203#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11204#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f 11205#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11206#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 11207#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11208#define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 11209#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11210#define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 11211#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11212 11213 11214// addressBlock: dce_dc_dio_dp_aux1_dispdec 11215// base address: 0x70 11216#define regDP_AUX1_AUX_CONTROL 0x1f6c 11217#define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 11218#define regDP_AUX1_AUX_SW_CONTROL 0x1f6d 11219#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 11220#define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e 11221#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 11222#define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 11223#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11224#define regDP_AUX1_AUX_SW_STATUS 0x1f70 11225#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 11226#define regDP_AUX1_AUX_LS_STATUS 0x1f71 11227#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 11228#define regDP_AUX1_AUX_SW_DATA 0x1f72 11229#define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 11230#define regDP_AUX1_AUX_LS_DATA 0x1f73 11231#define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 11232#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 11233#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11234#define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 11235#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11236#define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 11237#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11238#define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 11239#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11240#define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 11241#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 11242#define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 11243#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 11244#define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a 11245#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11246#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b 11247#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11248#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c 11249#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11250#define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d 11251#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11252#define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 11253#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11254 11255 11256// addressBlock: dce_dc_dio_dp_aux2_dispdec 11257// base address: 0xe0 11258#define regDP_AUX2_AUX_CONTROL 0x1f88 11259#define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 11260#define regDP_AUX2_AUX_SW_CONTROL 0x1f89 11261#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 11262#define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a 11263#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 11264#define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b 11265#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11266#define regDP_AUX2_AUX_SW_STATUS 0x1f8c 11267#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 11268#define regDP_AUX2_AUX_LS_STATUS 0x1f8d 11269#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 11270#define regDP_AUX2_AUX_SW_DATA 0x1f8e 11271#define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 11272#define regDP_AUX2_AUX_LS_DATA 0x1f8f 11273#define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 11274#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 11275#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11276#define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 11277#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11278#define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 11279#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11280#define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 11281#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11282#define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 11283#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 11284#define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 11285#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 11286#define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 11287#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11288#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 11289#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11290#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 11291#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11292#define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 11293#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11294#define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e 11295#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11296 11297 11298// addressBlock: dce_dc_dio_dp_aux3_dispdec 11299// base address: 0x150 11300#define regDP_AUX3_AUX_CONTROL 0x1fa4 11301#define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 11302#define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 11303#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 11304#define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 11305#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 11306#define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 11307#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11308#define regDP_AUX3_AUX_SW_STATUS 0x1fa8 11309#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 11310#define regDP_AUX3_AUX_LS_STATUS 0x1fa9 11311#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 11312#define regDP_AUX3_AUX_SW_DATA 0x1faa 11313#define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 11314#define regDP_AUX3_AUX_LS_DATA 0x1fab 11315#define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 11316#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac 11317#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11318#define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad 11319#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11320#define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae 11321#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11322#define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf 11323#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11324#define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 11325#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 11326#define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 11327#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 11328#define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 11329#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11330#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 11331#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11332#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 11333#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11334#define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 11335#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11336#define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba 11337#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11338 11339 11340// addressBlock: dce_dc_dio_dp_aux4_dispdec 11341// base address: 0x1c0 11342#define regDP_AUX4_AUX_CONTROL 0x1fc0 11343#define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 11344#define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 11345#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 11346#define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 11347#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 11348#define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 11349#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11350#define regDP_AUX4_AUX_SW_STATUS 0x1fc4 11351#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 11352#define regDP_AUX4_AUX_LS_STATUS 0x1fc5 11353#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 11354#define regDP_AUX4_AUX_SW_DATA 0x1fc6 11355#define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 11356#define regDP_AUX4_AUX_LS_DATA 0x1fc7 11357#define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 11358#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 11359#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11360#define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 11361#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11362#define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca 11363#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11364#define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb 11365#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11366#define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc 11367#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 11368#define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd 11369#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 11370#define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce 11371#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11372#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf 11373#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11374#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 11375#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11376#define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 11377#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11378#define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 11379#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11380 11381 11382// addressBlock: dce_dc_dio_dout_i2c_dispdec 11383// base address: 0x0 11384#define regDC_I2C_CONTROL 0x1e98 11385#define regDC_I2C_CONTROL_BASE_IDX 2 11386#define regDC_I2C_ARBITRATION 0x1e99 11387#define regDC_I2C_ARBITRATION_BASE_IDX 2 11388#define regDC_I2C_SW_STATUS 0x1e9b 11389#define regDC_I2C_SW_STATUS_BASE_IDX 2 11390#define regDC_I2C_DDC1_HW_STATUS 0x1e9c 11391#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 11392#define regDC_I2C_DDC2_HW_STATUS 0x1e9d 11393#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 11394#define regDC_I2C_DDC3_HW_STATUS 0x1e9e 11395#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 11396#define regDC_I2C_DDC4_HW_STATUS 0x1e9f 11397#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 11398#define regDC_I2C_DDC5_HW_STATUS 0x1ea0 11399#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 11400#define regDC_I2C_DDC1_SPEED 0x1ea2 11401#define regDC_I2C_DDC1_SPEED_BASE_IDX 2 11402#define regDC_I2C_DDC1_SETUP 0x1ea3 11403#define regDC_I2C_DDC1_SETUP_BASE_IDX 2 11404#define regDC_I2C_DDC2_SPEED 0x1ea4 11405#define regDC_I2C_DDC2_SPEED_BASE_IDX 2 11406#define regDC_I2C_DDC2_SETUP 0x1ea5 11407#define regDC_I2C_DDC2_SETUP_BASE_IDX 2 11408#define regDC_I2C_DDC3_SPEED 0x1ea6 11409#define regDC_I2C_DDC3_SPEED_BASE_IDX 2 11410#define regDC_I2C_DDC3_SETUP 0x1ea7 11411#define regDC_I2C_DDC3_SETUP_BASE_IDX 2 11412#define regDC_I2C_DDC4_SPEED 0x1ea8 11413#define regDC_I2C_DDC4_SPEED_BASE_IDX 2 11414#define regDC_I2C_DDC4_SETUP 0x1ea9 11415#define regDC_I2C_DDC4_SETUP_BASE_IDX 2 11416#define regDC_I2C_DDC5_SPEED 0x1eaa 11417#define regDC_I2C_DDC5_SPEED_BASE_IDX 2 11418#define regDC_I2C_DDC5_SETUP 0x1eab 11419#define regDC_I2C_DDC5_SETUP_BASE_IDX 2 11420#define regDC_I2C_TRANSACTION0 0x1eae 11421#define regDC_I2C_TRANSACTION0_BASE_IDX 2 11422#define regDC_I2C_TRANSACTION1 0x1eaf 11423#define regDC_I2C_TRANSACTION1_BASE_IDX 2 11424#define regDC_I2C_TRANSACTION2 0x1eb0 11425#define regDC_I2C_TRANSACTION2_BASE_IDX 2 11426#define regDC_I2C_TRANSACTION3 0x1eb1 11427#define regDC_I2C_TRANSACTION3_BASE_IDX 2 11428#define regDC_I2C_DATA 0x1eb2 11429#define regDC_I2C_DATA_BASE_IDX 2 11430#define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 11431#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 11432#define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 11433#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 11434 11435 11436// addressBlock: dce_dc_dio_dio_misc_dispdec 11437// base address: 0x0 11438#define regDIO_SCRATCH0 0x1eca 11439#define regDIO_SCRATCH0_BASE_IDX 2 11440#define regDIO_SCRATCH1 0x1ecb 11441#define regDIO_SCRATCH1_BASE_IDX 2 11442#define regDIO_SCRATCH2 0x1ecc 11443#define regDIO_SCRATCH2_BASE_IDX 2 11444#define regDIO_SCRATCH3 0x1ecd 11445#define regDIO_SCRATCH3_BASE_IDX 2 11446#define regDIO_SCRATCH4 0x1ece 11447#define regDIO_SCRATCH4_BASE_IDX 2 11448#define regDIO_SCRATCH5 0x1ecf 11449#define regDIO_SCRATCH5_BASE_IDX 2 11450#define regDIO_SCRATCH6 0x1ed0 11451#define regDIO_SCRATCH6_BASE_IDX 2 11452#define regDIO_SCRATCH7 0x1ed1 11453#define regDIO_SCRATCH7_BASE_IDX 2 11454#define regDIO_MEM_PWR_STATUS 0x1edd 11455#define regDIO_MEM_PWR_STATUS_BASE_IDX 2 11456#define regDIO_MEM_PWR_CTRL 0x1ede 11457#define regDIO_MEM_PWR_CTRL_BASE_IDX 2 11458#define regDIO_MEM_PWR_CTRL2 0x1edf 11459#define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 11460#define regDIO_CLK_CNTL 0x1ee0 11461#define regDIO_CLK_CNTL_BASE_IDX 2 11462#define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 11463#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 11464#define regDIG_SOFT_RESET 0x1eee 11465#define regDIG_SOFT_RESET_BASE_IDX 2 11466#define regDIO_CLK_CNTL2 0x1ef2 11467#define regDIO_CLK_CNTL2_BASE_IDX 2 11468#define regDIO_CLK_CNTL3 0x1ef3 11469#define regDIO_CLK_CNTL3_BASE_IDX 2 11470#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 11471#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 11472#define regDIO_PSP_INTERRUPT_CLEAR 0x1f01 11473#define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 11474#define regDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 11475#define regDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 11476#define regDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 11477#define regDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 11478#define regDIO_LINKA_CNTL 0x1f04 11479#define regDIO_LINKA_CNTL_BASE_IDX 2 11480#define regDIO_LINKB_CNTL 0x1f05 11481#define regDIO_LINKB_CNTL_BASE_IDX 2 11482#define regDIO_LINKC_CNTL 0x1f06 11483#define regDIO_LINKC_CNTL_BASE_IDX 2 11484#define regDIO_LINKD_CNTL 0x1f07 11485#define regDIO_LINKD_CNTL_BASE_IDX 2 11486#define regDIO_LINKE_CNTL 0x1f08 11487#define regDIO_LINKE_CNTL_BASE_IDX 2 11488#define regDIO_LINKF_CNTL 0x1f09 11489#define regDIO_LINKF_CNTL_BASE_IDX 2 11490 11491 11492// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec 11493// base address: 0x7d10 11494#define regDC_PERFMON18_PERFCOUNTER_CNTL 0x1f44 11495#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 11496#define regDC_PERFMON18_PERFCOUNTER_CNTL2 0x1f45 11497#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 11498#define regDC_PERFMON18_PERFCOUNTER_STATE 0x1f46 11499#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 11500#define regDC_PERFMON18_PERFMON_CNTL 0x1f47 11501#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 11502#define regDC_PERFMON18_PERFMON_CNTL2 0x1f48 11503#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 11504#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1f49 11505#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 11506#define regDC_PERFMON18_PERFMON_CVALUE_LOW 0x1f4a 11507#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 11508#define regDC_PERFMON18_PERFMON_HI 0x1f4b 11509#define regDC_PERFMON18_PERFMON_HI_BASE_IDX 2 11510#define regDC_PERFMON18_PERFMON_LOW 0x1f4c 11511#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 11512 11513 11514// addressBlock: dce_dc_dcio_dcio_dispdec 11515// base address: 0x0 11516#define regDC_GENERICA 0x2868 11517#define regDC_GENERICA_BASE_IDX 2 11518#define regDC_GENERICB 0x2869 11519#define regDC_GENERICB_BASE_IDX 2 11520#define regDCIO_CLOCK_CNTL 0x286a 11521#define regDCIO_CLOCK_CNTL_BASE_IDX 2 11522#define regDC_REF_CLK_CNTL 0x286b 11523#define regDC_REF_CLK_CNTL_BASE_IDX 2 11524#define regUNIPHYA_LINK_CNTL 0x286d 11525#define regUNIPHYA_LINK_CNTL_BASE_IDX 2 11526#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 11527#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 11528#define regUNIPHYB_LINK_CNTL 0x286f 11529#define regUNIPHYB_LINK_CNTL_BASE_IDX 2 11530#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 11531#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 11532#define regUNIPHYC_LINK_CNTL 0x2871 11533#define regUNIPHYC_LINK_CNTL_BASE_IDX 2 11534#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 11535#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 11536#define regUNIPHYD_LINK_CNTL 0x2873 11537#define regUNIPHYD_LINK_CNTL_BASE_IDX 2 11538#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 11539#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 11540#define regUNIPHYE_LINK_CNTL 0x2875 11541#define regUNIPHYE_LINK_CNTL_BASE_IDX 2 11542#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 11543#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 11544#define regDCIO_WRCMD_DELAY 0x287e 11545#define regDCIO_WRCMD_DELAY_BASE_IDX 2 11546#define regDC_PINSTRAPS 0x2880 11547#define regDC_PINSTRAPS_BASE_IDX 2 11548#define regINTERCEPT_STATE 0x2884 11549#define regINTERCEPT_STATE_BASE_IDX 2 11550#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b 11551#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 11552#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c 11553#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 11554#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 11555#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 11556#define regDCIO_SOFT_RESET 0x289e 11557#define regDCIO_SOFT_RESET_BASE_IDX 2 11558 11559 11560// addressBlock: dce_dc_dcio_dcio_chip_dispdec 11561// base address: 0x0 11562#define regDC_GPIO_GENERIC_MASK 0x28c8 11563#define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 11564#define regDC_GPIO_GENERIC_A 0x28c9 11565#define regDC_GPIO_GENERIC_A_BASE_IDX 2 11566#define regDC_GPIO_GENERIC_EN 0x28ca 11567#define regDC_GPIO_GENERIC_EN_BASE_IDX 2 11568#define regDC_GPIO_GENERIC_Y 0x28cb 11569#define regDC_GPIO_GENERIC_Y_BASE_IDX 2 11570#define regDC_GPIO_DDC1_MASK 0x28d0 11571#define regDC_GPIO_DDC1_MASK_BASE_IDX 2 11572#define regDC_GPIO_DDC1_A 0x28d1 11573#define regDC_GPIO_DDC1_A_BASE_IDX 2 11574#define regDC_GPIO_DDC1_EN 0x28d2 11575#define regDC_GPIO_DDC1_EN_BASE_IDX 2 11576#define regDC_GPIO_DDC1_Y 0x28d3 11577#define regDC_GPIO_DDC1_Y_BASE_IDX 2 11578#define regDC_GPIO_DDC2_MASK 0x28d4 11579#define regDC_GPIO_DDC2_MASK_BASE_IDX 2 11580#define regDC_GPIO_DDC2_A 0x28d5 11581#define regDC_GPIO_DDC2_A_BASE_IDX 2 11582#define regDC_GPIO_DDC2_EN 0x28d6 11583#define regDC_GPIO_DDC2_EN_BASE_IDX 2 11584#define regDC_GPIO_DDC2_Y 0x28d7 11585#define regDC_GPIO_DDC2_Y_BASE_IDX 2 11586#define regDC_GPIO_DDC3_MASK 0x28d8 11587#define regDC_GPIO_DDC3_MASK_BASE_IDX 2 11588#define regDC_GPIO_DDC3_A 0x28d9 11589#define regDC_GPIO_DDC3_A_BASE_IDX 2 11590#define regDC_GPIO_DDC3_EN 0x28da 11591#define regDC_GPIO_DDC3_EN_BASE_IDX 2 11592#define regDC_GPIO_DDC3_Y 0x28db 11593#define regDC_GPIO_DDC3_Y_BASE_IDX 2 11594#define regDC_GPIO_DDC4_MASK 0x28dc 11595#define regDC_GPIO_DDC4_MASK_BASE_IDX 2 11596#define regDC_GPIO_DDC4_A 0x28dd 11597#define regDC_GPIO_DDC4_A_BASE_IDX 2 11598#define regDC_GPIO_DDC4_EN 0x28de 11599#define regDC_GPIO_DDC4_EN_BASE_IDX 2 11600#define regDC_GPIO_DDC4_Y 0x28df 11601#define regDC_GPIO_DDC4_Y_BASE_IDX 2 11602#define regDC_GPIO_DDC5_MASK 0x28e0 11603#define regDC_GPIO_DDC5_MASK_BASE_IDX 2 11604#define regDC_GPIO_DDC5_A 0x28e1 11605#define regDC_GPIO_DDC5_A_BASE_IDX 2 11606#define regDC_GPIO_DDC5_EN 0x28e2 11607#define regDC_GPIO_DDC5_EN_BASE_IDX 2 11608#define regDC_GPIO_DDC5_Y 0x28e3 11609#define regDC_GPIO_DDC5_Y_BASE_IDX 2 11610#define regDC_GPIO_DDCVGA_MASK 0x28e8 11611#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 11612#define regDC_GPIO_DDCVGA_A 0x28e9 11613#define regDC_GPIO_DDCVGA_A_BASE_IDX 2 11614#define regDC_GPIO_DDCVGA_EN 0x28ea 11615#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 11616#define regDC_GPIO_DDCVGA_Y 0x28eb 11617#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 11618#define regDC_GPIO_GENLK_MASK 0x28f0 11619#define regDC_GPIO_GENLK_MASK_BASE_IDX 2 11620#define regDC_GPIO_GENLK_A 0x28f1 11621#define regDC_GPIO_GENLK_A_BASE_IDX 2 11622#define regDC_GPIO_GENLK_EN 0x28f2 11623#define regDC_GPIO_GENLK_EN_BASE_IDX 2 11624#define regDC_GPIO_GENLK_Y 0x28f3 11625#define regDC_GPIO_GENLK_Y_BASE_IDX 2 11626#define regDC_GPIO_HPD_MASK 0x28f4 11627#define regDC_GPIO_HPD_MASK_BASE_IDX 2 11628#define regDC_GPIO_HPD_A 0x28f5 11629#define regDC_GPIO_HPD_A_BASE_IDX 2 11630#define regDC_GPIO_HPD_EN 0x28f6 11631#define regDC_GPIO_HPD_EN_BASE_IDX 2 11632#define regDC_GPIO_HPD_Y 0x28f7 11633#define regDC_GPIO_HPD_Y_BASE_IDX 2 11634#define regDC_GPIO_PWRSEQ0_EN 0x28fa 11635#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 11636#define regDC_GPIO_PAD_STRENGTH_1 0x28fc 11637#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 11638#define regDC_GPIO_PAD_STRENGTH_2 0x28fd 11639#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 11640#define regPHY_AUX_CNTL 0x28ff 11641#define regPHY_AUX_CNTL_BASE_IDX 2 11642#define regDC_GPIO_PWRSEQ1_EN 0x2902 11643#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 11644#define regDC_GPIO_TX12_EN 0x2915 11645#define regDC_GPIO_TX12_EN_BASE_IDX 2 11646#define regDC_GPIO_AUX_CTRL_0 0x2916 11647#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 11648#define regDC_GPIO_AUX_CTRL_1 0x2917 11649#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 11650#define regDC_GPIO_AUX_CTRL_2 0x2918 11651#define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 11652#define regDC_GPIO_RXEN 0x2919 11653#define regDC_GPIO_RXEN_BASE_IDX 2 11654#define regDC_GPIO_PULLUPEN 0x291a 11655#define regDC_GPIO_PULLUPEN_BASE_IDX 2 11656#define regDC_GPIO_AUX_CTRL_3 0x291b 11657#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 11658#define regDC_GPIO_AUX_CTRL_4 0x291c 11659#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 11660#define regDC_GPIO_AUX_CTRL_5 0x291d 11661#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 11662#define regAUXI2C_PAD_ALL_PWR_OK 0x291e 11663#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 11664 11665 11666// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec 11667// base address: 0x0 11668#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928 11669#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11670#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929 11671#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11672#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a 11673#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11674#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b 11675#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11676#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c 11677#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11678#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d 11679#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11680#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e 11681#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11682#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f 11683#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11684#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930 11685#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11686#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931 11687#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11688#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932 11689#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11690#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933 11691#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11692#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934 11693#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11694#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935 11695#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11696#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936 11697#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11698#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937 11699#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11700#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938 11701#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11702#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939 11703#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11704#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a 11705#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11706#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b 11707#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11708#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c 11709#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11710#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d 11711#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11712#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e 11713#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11714#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f 11715#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11716#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940 11717#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11718#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941 11719#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11720#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942 11721#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11722#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943 11723#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11724#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944 11725#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11726#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945 11727#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11728#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946 11729#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11730#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947 11731#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11732#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948 11733#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11734#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949 11735#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11736#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a 11737#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11738#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b 11739#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11740#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c 11741#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11742#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d 11743#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11744#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e 11745#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11746#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f 11747#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11748#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950 11749#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11750#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951 11751#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11752#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952 11753#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11754#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953 11755#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11756#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954 11757#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11758#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955 11759#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11760#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956 11761#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11762#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957 11763#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11764#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x2958 11765#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11766#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x2959 11767#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11768#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x295a 11769#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11770#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x295b 11771#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11772#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x295c 11773#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11774#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x295d 11775#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11776#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x295e 11777#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11778#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x295f 11779#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11780#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2960 11781#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11782#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2961 11783#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11784 11785 11786// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec 11787// base address: 0x360 11788#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 11789#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11790#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 11791#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11792#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 11793#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11794#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 11795#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11796#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 11797#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11798#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 11799#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11800#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 11801#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11802#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 11803#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11804#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 11805#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11806#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 11807#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11808#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a 11809#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11810#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b 11811#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11812#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c 11813#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11814#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d 11815#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11816#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e 11817#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11818#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f 11819#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11820#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 11821#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11822#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 11823#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11824#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 11825#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11826#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 11827#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11828#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 11829#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11830#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 11831#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11832#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 11833#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11834#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 11835#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11836#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 11837#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11838#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 11839#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11840#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a 11841#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11842#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b 11843#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11844#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c 11845#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11846#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d 11847#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11848#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e 11849#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11850#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f 11851#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11852#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 11853#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11854#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 11855#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11856#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 11857#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11858#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 11859#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11860#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 11861#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11862#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 11863#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11864#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 11865#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11866#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 11867#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11868#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 11869#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11870#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 11871#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11872#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a 11873#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11874#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b 11875#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11876#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c 11877#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11878#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d 11879#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11880#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e 11881#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11882#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f 11883#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11884#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 11885#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11886#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 11887#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11888#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 11889#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11890#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 11891#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11892#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 11893#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11894#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 11895#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11896#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 11897#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11898#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 11899#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11900#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 11901#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11902#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 11903#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11904 11905 11906// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec 11907// base address: 0x6c0 11908#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 11909#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11910#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 11911#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11912#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada 11913#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11914#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb 11915#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11916#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc 11917#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11918#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add 11919#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11920#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade 11921#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11922#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf 11923#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11924#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 11925#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11926#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 11927#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11928#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 11929#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11930#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 11931#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11932#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 11933#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11934#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 11935#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11936#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 11937#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11938#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 11939#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11940#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 11941#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11942#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 11943#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11944#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea 11945#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11946#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb 11947#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11948#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec 11949#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11950#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed 11951#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11952#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee 11953#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11954#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef 11955#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11956#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 11957#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11958#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 11959#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11960#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 11961#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11962#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 11963#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11964#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 11965#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11966#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 11967#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11968#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 11969#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11970#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 11971#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11972#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 11973#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11974#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 11975#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11976#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa 11977#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11978#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb 11979#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11980#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc 11981#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11982#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd 11983#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11984#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe 11985#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11986#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff 11987#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11988#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 11989#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11990#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 11991#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11992#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 11993#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11994#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 11995#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11996#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 11997#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11998#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 11999#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12000#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 12001#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12002#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 12003#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12004#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 12005#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12006#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 12007#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12008#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a 12009#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12010#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b 12011#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12012#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c 12013#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12014#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d 12015#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12016#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e 12017#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12018#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f 12019#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12020#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 12021#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12022#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 12023#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12024 12025 12026// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec 12027// base address: 0xa20 12028#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 12029#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12030#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 12031#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12032#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 12033#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12034#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 12035#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12036#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 12037#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12038#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 12039#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12040#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 12041#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12042#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 12043#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12044#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 12045#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12046#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 12047#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12048#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba 12049#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12050#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb 12051#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12052#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc 12053#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12054#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd 12055#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12056#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe 12057#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12058#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf 12059#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12060#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 12061#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12062#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 12063#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12064#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 12065#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12066#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 12067#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12068#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 12069#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12070#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 12071#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12072#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 12073#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12074#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 12075#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12076#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 12077#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12078#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 12079#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12080#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca 12081#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12082#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb 12083#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12084#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc 12085#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12086#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd 12087#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12088#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce 12089#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12090#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf 12091#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12092#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 12093#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12094#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 12095#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12096#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 12097#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12098#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 12099#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12100#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 12101#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12102#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 12103#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12104#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 12105#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12106#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 12107#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12108#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 12109#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12110#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 12111#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12112#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda 12113#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12114#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb 12115#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12116#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc 12117#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12118#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd 12119#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12120#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde 12121#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12122#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf 12123#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12124#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 12125#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12126#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 12127#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12128#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 12129#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12130#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 12131#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12132#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 12133#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12134#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 12135#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12136#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 12137#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12138#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 12139#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12140#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 12141#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12142#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 12143#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12144 12145 12146// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec 12147// base address: 0xd80 12148#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 12149#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12150#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 12151#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12152#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a 12153#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12154#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b 12155#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12156#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c 12157#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12158#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d 12159#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12160#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e 12161#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12162#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f 12163#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12164#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 12165#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12166#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 12167#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12168#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 12169#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12170#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 12171#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12172#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 12173#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12174#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 12175#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12176#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 12177#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12178#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 12179#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12180#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 12181#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12182#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 12183#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12184#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a 12185#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12186#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b 12187#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12188#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c 12189#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12190#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d 12191#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12192#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e 12193#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12194#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f 12195#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12196#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 12197#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12198#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 12199#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12200#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 12201#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12202#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 12203#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12204#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 12205#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12206#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 12207#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12208#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 12209#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12210#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 12211#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12212#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 12213#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12214#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 12215#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12216#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa 12217#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12218#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab 12219#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12220#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac 12221#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12222#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad 12223#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12224#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae 12225#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12226#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf 12227#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12228#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 12229#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12230#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 12231#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12232#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 12233#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12234#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 12235#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12236#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 12237#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12238#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 12239#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12240#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 12241#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12242#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 12243#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12244#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 12245#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12246#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 12247#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12248#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba 12249#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12250#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb 12251#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12252#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc 12253#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12254#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd 12255#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12256#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe 12257#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12258#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf 12259#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12260#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 12261#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12262#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 12263#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12264 12265 12266// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec 12267// base address: 0x0 12268#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 12269#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 12270#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 12271#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 12272#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 12273#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 12274#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 12275#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 12276#define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 12277#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 12278#define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 12279#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 12280#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 12281#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 12282#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 12283#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 12284#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 12285#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 12286#define regPWRSEQ0_BL_PWM_CNTL 0x2f19 12287#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 12288#define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a 12289#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 12290#define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b 12291#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 12292#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c 12293#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 12294#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d 12295#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 12296#define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 12297#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 12298 12299 12300// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec 12301// base address: 0x1b0 12302#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c 12303#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 12304#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d 12305#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 12306#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e 12307#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 12308#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f 12309#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 12310#define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 12311#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 12312#define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 12313#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 12314#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 12315#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 12316#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 12317#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 12318#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 12319#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 12320#define regPWRSEQ1_BL_PWM_CNTL 0x2f85 12321#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 12322#define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 12323#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 12324#define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 12325#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 12326#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 12327#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 12328#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 12329#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 12330#define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d 12331#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 12332 12333 12334// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec 12335// base address: 0x0 12336#define regDSCC0_DSCC_CONFIG0 0x300a 12337#define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 12338#define regDSCC0_DSCC_CONFIG1 0x300b 12339#define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 12340#define regDSCC0_DSCC_STATUS 0x300c 12341#define regDSCC0_DSCC_STATUS_BASE_IDX 2 12342#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d 12343#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12344#define regDSCC0_DSCC_PPS_CONFIG0 0x300e 12345#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 12346#define regDSCC0_DSCC_PPS_CONFIG1 0x300f 12347#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 12348#define regDSCC0_DSCC_PPS_CONFIG2 0x3010 12349#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 12350#define regDSCC0_DSCC_PPS_CONFIG3 0x3011 12351#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 12352#define regDSCC0_DSCC_PPS_CONFIG4 0x3012 12353#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 12354#define regDSCC0_DSCC_PPS_CONFIG5 0x3013 12355#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 12356#define regDSCC0_DSCC_PPS_CONFIG6 0x3014 12357#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 12358#define regDSCC0_DSCC_PPS_CONFIG7 0x3015 12359#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 12360#define regDSCC0_DSCC_PPS_CONFIG8 0x3016 12361#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 12362#define regDSCC0_DSCC_PPS_CONFIG9 0x3017 12363#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 12364#define regDSCC0_DSCC_PPS_CONFIG10 0x3018 12365#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 12366#define regDSCC0_DSCC_PPS_CONFIG11 0x3019 12367#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 12368#define regDSCC0_DSCC_PPS_CONFIG12 0x301a 12369#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 12370#define regDSCC0_DSCC_PPS_CONFIG13 0x301b 12371#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 12372#define regDSCC0_DSCC_PPS_CONFIG14 0x301c 12373#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 12374#define regDSCC0_DSCC_PPS_CONFIG15 0x301d 12375#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 12376#define regDSCC0_DSCC_PPS_CONFIG16 0x301e 12377#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 12378#define regDSCC0_DSCC_PPS_CONFIG17 0x301f 12379#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 12380#define regDSCC0_DSCC_PPS_CONFIG18 0x3020 12381#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 12382#define regDSCC0_DSCC_PPS_CONFIG19 0x3021 12383#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 12384#define regDSCC0_DSCC_PPS_CONFIG20 0x3022 12385#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 12386#define regDSCC0_DSCC_PPS_CONFIG21 0x3023 12387#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 12388#define regDSCC0_DSCC_PPS_CONFIG22 0x3024 12389#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 12390#define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 12391#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12392#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 12393#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12394#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 12395#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12396#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 12397#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12398#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 12399#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12400#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a 12401#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12402#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b 12403#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12404#define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c 12405#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12406#define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d 12407#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12408#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e 12409#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12410#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f 12411#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12412#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 12413#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12414#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 12415#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12416#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 12417#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12418#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 12419#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12420#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 12421#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12422#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 12423#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12424#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a 12425#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12426 12427 12428// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec 12429// base address: 0x0 12430#define regDSCCIF0_DSCCIF_CONFIG0 0x3005 12431#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 12432#define regDSCCIF0_DSCCIF_CONFIG1 0x3006 12433#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 12434 12435 12436// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec 12437// base address: 0x0 12438#define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 12439#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 12440#define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 12441#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 12442 12443 12444// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12445// base address: 0xc140 12446#define regDC_PERFMON19_PERFCOUNTER_CNTL 0x3050 12447#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 12448#define regDC_PERFMON19_PERFCOUNTER_CNTL2 0x3051 12449#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 12450#define regDC_PERFMON19_PERFCOUNTER_STATE 0x3052 12451#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 12452#define regDC_PERFMON19_PERFMON_CNTL 0x3053 12453#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 12454#define regDC_PERFMON19_PERFMON_CNTL2 0x3054 12455#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 12456#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x3055 12457#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12458#define regDC_PERFMON19_PERFMON_CVALUE_LOW 0x3056 12459#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 12460#define regDC_PERFMON19_PERFMON_HI 0x3057 12461#define regDC_PERFMON19_PERFMON_HI_BASE_IDX 2 12462#define regDC_PERFMON19_PERFMON_LOW 0x3058 12463#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 12464 12465 12466// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec 12467// base address: 0x170 12468#define regDSCC1_DSCC_CONFIG0 0x3066 12469#define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 12470#define regDSCC1_DSCC_CONFIG1 0x3067 12471#define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 12472#define regDSCC1_DSCC_STATUS 0x3068 12473#define regDSCC1_DSCC_STATUS_BASE_IDX 2 12474#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 12475#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12476#define regDSCC1_DSCC_PPS_CONFIG0 0x306a 12477#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 12478#define regDSCC1_DSCC_PPS_CONFIG1 0x306b 12479#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 12480#define regDSCC1_DSCC_PPS_CONFIG2 0x306c 12481#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 12482#define regDSCC1_DSCC_PPS_CONFIG3 0x306d 12483#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 12484#define regDSCC1_DSCC_PPS_CONFIG4 0x306e 12485#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 12486#define regDSCC1_DSCC_PPS_CONFIG5 0x306f 12487#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 12488#define regDSCC1_DSCC_PPS_CONFIG6 0x3070 12489#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 12490#define regDSCC1_DSCC_PPS_CONFIG7 0x3071 12491#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 12492#define regDSCC1_DSCC_PPS_CONFIG8 0x3072 12493#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 12494#define regDSCC1_DSCC_PPS_CONFIG9 0x3073 12495#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 12496#define regDSCC1_DSCC_PPS_CONFIG10 0x3074 12497#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 12498#define regDSCC1_DSCC_PPS_CONFIG11 0x3075 12499#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 12500#define regDSCC1_DSCC_PPS_CONFIG12 0x3076 12501#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 12502#define regDSCC1_DSCC_PPS_CONFIG13 0x3077 12503#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 12504#define regDSCC1_DSCC_PPS_CONFIG14 0x3078 12505#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 12506#define regDSCC1_DSCC_PPS_CONFIG15 0x3079 12507#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 12508#define regDSCC1_DSCC_PPS_CONFIG16 0x307a 12509#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 12510#define regDSCC1_DSCC_PPS_CONFIG17 0x307b 12511#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 12512#define regDSCC1_DSCC_PPS_CONFIG18 0x307c 12513#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 12514#define regDSCC1_DSCC_PPS_CONFIG19 0x307d 12515#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 12516#define regDSCC1_DSCC_PPS_CONFIG20 0x307e 12517#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 12518#define regDSCC1_DSCC_PPS_CONFIG21 0x307f 12519#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 12520#define regDSCC1_DSCC_PPS_CONFIG22 0x3080 12521#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 12522#define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 12523#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12524#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 12525#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12526#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 12527#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12528#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 12529#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12530#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 12531#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12532#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 12533#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12534#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 12535#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12536#define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 12537#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12538#define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 12539#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12540#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a 12541#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12542#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b 12543#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12544#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c 12545#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12546#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d 12547#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12548#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e 12549#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12550#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f 12551#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12552#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 12553#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12554#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 12555#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12556#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 12557#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12558 12559 12560// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec 12561// base address: 0x170 12562#define regDSCCIF1_DSCCIF_CONFIG0 0x3061 12563#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 12564#define regDSCCIF1_DSCCIF_CONFIG1 0x3062 12565#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 12566 12567 12568// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec 12569// base address: 0x170 12570#define regDSC_TOP1_DSC_TOP_CONTROL 0x305c 12571#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 12572#define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d 12573#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 12574 12575 12576// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12577// base address: 0xc2b0 12578#define regDC_PERFMON20_PERFCOUNTER_CNTL 0x30ac 12579#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 12580#define regDC_PERFMON20_PERFCOUNTER_CNTL2 0x30ad 12581#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 12582#define regDC_PERFMON20_PERFCOUNTER_STATE 0x30ae 12583#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 12584#define regDC_PERFMON20_PERFMON_CNTL 0x30af 12585#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 12586#define regDC_PERFMON20_PERFMON_CNTL2 0x30b0 12587#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 12588#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x30b1 12589#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12590#define regDC_PERFMON20_PERFMON_CVALUE_LOW 0x30b2 12591#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 12592#define regDC_PERFMON20_PERFMON_HI 0x30b3 12593#define regDC_PERFMON20_PERFMON_HI_BASE_IDX 2 12594#define regDC_PERFMON20_PERFMON_LOW 0x30b4 12595#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 12596 12597 12598// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec 12599// base address: 0x2e0 12600#define regDSCC2_DSCC_CONFIG0 0x30c2 12601#define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 12602#define regDSCC2_DSCC_CONFIG1 0x30c3 12603#define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 12604#define regDSCC2_DSCC_STATUS 0x30c4 12605#define regDSCC2_DSCC_STATUS_BASE_IDX 2 12606#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 12607#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12608#define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 12609#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 12610#define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 12611#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 12612#define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 12613#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 12614#define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 12615#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 12616#define regDSCC2_DSCC_PPS_CONFIG4 0x30ca 12617#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 12618#define regDSCC2_DSCC_PPS_CONFIG5 0x30cb 12619#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 12620#define regDSCC2_DSCC_PPS_CONFIG6 0x30cc 12621#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 12622#define regDSCC2_DSCC_PPS_CONFIG7 0x30cd 12623#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 12624#define regDSCC2_DSCC_PPS_CONFIG8 0x30ce 12625#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 12626#define regDSCC2_DSCC_PPS_CONFIG9 0x30cf 12627#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 12628#define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 12629#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 12630#define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 12631#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 12632#define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 12633#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 12634#define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 12635#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 12636#define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 12637#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 12638#define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 12639#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 12640#define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 12641#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 12642#define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 12643#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 12644#define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 12645#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 12646#define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 12647#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 12648#define regDSCC2_DSCC_PPS_CONFIG20 0x30da 12649#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 12650#define regDSCC2_DSCC_PPS_CONFIG21 0x30db 12651#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 12652#define regDSCC2_DSCC_PPS_CONFIG22 0x30dc 12653#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 12654#define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd 12655#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12656#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de 12657#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12658#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df 12659#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12660#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 12661#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12662#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 12663#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12664#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 12665#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12666#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 12667#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12668#define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 12669#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12670#define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 12671#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12672#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 12673#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12674#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 12675#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12676#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 12677#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12678#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 12679#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12680#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea 12681#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12682#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb 12683#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12684#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec 12685#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12686#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed 12687#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12688#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 12689#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12690 12691 12692// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec 12693// base address: 0x2e0 12694#define regDSCCIF2_DSCCIF_CONFIG0 0x30bd 12695#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 12696#define regDSCCIF2_DSCCIF_CONFIG1 0x30be 12697#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 12698 12699 12700// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec 12701// base address: 0x2e0 12702#define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 12703#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 12704#define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 12705#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 12706 12707 12708// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12709// base address: 0xc420 12710#define regDC_PERFMON21_PERFCOUNTER_CNTL 0x3108 12711#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 12712#define regDC_PERFMON21_PERFCOUNTER_CNTL2 0x3109 12713#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 12714#define regDC_PERFMON21_PERFCOUNTER_STATE 0x310a 12715#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 12716#define regDC_PERFMON21_PERFMON_CNTL 0x310b 12717#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 12718#define regDC_PERFMON21_PERFMON_CNTL2 0x310c 12719#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 12720#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x310d 12721#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12722#define regDC_PERFMON21_PERFMON_CVALUE_LOW 0x310e 12723#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 12724#define regDC_PERFMON21_PERFMON_HI 0x310f 12725#define regDC_PERFMON21_PERFMON_HI_BASE_IDX 2 12726#define regDC_PERFMON21_PERFMON_LOW 0x3110 12727#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 12728 12729 12730// addressBlock: dce_dc_hpo_hpo_top_dispdec 12731// base address: 0x2790c 12732#define regHPO_TOP_CLOCK_CONTROL 0x0e43 12733#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 12734#define regHPO_TOP_HW_CONTROL 0x0e4a 12735#define regHPO_TOP_HW_CONTROL_BASE_IDX 3 12736 12737 12738// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec 12739// base address: 0x27958 12740#define regDP_STREAM_MAPPER_CONTROL0 0x0e56 12741#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 12742#define regDP_STREAM_MAPPER_CONTROL1 0x0e57 12743#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 12744#define regDP_STREAM_MAPPER_CONTROL2 0x0e58 12745#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 12746#define regDP_STREAM_MAPPER_CONTROL3 0x0e59 12747#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 12748 12749 12750// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec 12751// base address: 0x1a698 12752#define regDC_PERFMON22_PERFCOUNTER_CNTL 0x0e66 12753#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 3 12754#define regDC_PERFMON22_PERFCOUNTER_CNTL2 0x0e67 12755#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 3 12756#define regDC_PERFMON22_PERFCOUNTER_STATE 0x0e68 12757#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 3 12758#define regDC_PERFMON22_PERFMON_CNTL 0x0e69 12759#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX 3 12760#define regDC_PERFMON22_PERFMON_CNTL2 0x0e6a 12761#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 3 12762#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x0e6b 12763#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 12764#define regDC_PERFMON22_PERFMON_CVALUE_LOW 0x0e6c 12765#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 3 12766#define regDC_PERFMON22_PERFMON_HI 0x0e6d 12767#define regDC_PERFMON22_PERFMON_HI_BASE_IDX 3 12768#define regDC_PERFMON22_PERFMON_LOW 0x0e6e 12769#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 12770 12771 12772// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec 12773// base address: 0x2646c 12774#define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c 12775#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 12776#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d 12777#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 12778#define regAFMT5_AFMT_AUDIO_INFO0 0x091e 12779#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 12780#define regAFMT5_AFMT_AUDIO_INFO1 0x091f 12781#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 12782#define regAFMT5_AFMT_60958_0 0x0920 12783#define regAFMT5_AFMT_60958_0_BASE_IDX 3 12784#define regAFMT5_AFMT_60958_1 0x0921 12785#define regAFMT5_AFMT_60958_1_BASE_IDX 3 12786#define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 12787#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 12788#define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 12789#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 12790#define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 12791#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 12792#define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 12793#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 12794#define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 12795#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 12796#define regAFMT5_AFMT_60958_2 0x0927 12797#define regAFMT5_AFMT_60958_2_BASE_IDX 3 12798#define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 12799#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 12800#define regAFMT5_AFMT_STATUS 0x0929 12801#define regAFMT5_AFMT_STATUS_BASE_IDX 3 12802#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a 12803#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 12804#define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b 12805#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 12806#define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d 12807#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 12808#define regAFMT5_AFMT_MEM_PWR 0x092f 12809#define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 12810 12811 12812// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec 12813// base address: 0x264f0 12814#define regDME5_DME_CONTROL 0x093c 12815#define regDME5_DME_CONTROL_BASE_IDX 3 12816#define regDME5_DME_MEMORY_CONTROL 0x093d 12817#define regDME5_DME_MEMORY_CONTROL_BASE_IDX 3 12818 12819 12820// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec 12821// base address: 0x264c4 12822#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 12823#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 12824#define regVPG5_VPG_GENERIC_PACKET_DATA 0x0932 12825#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 12826#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 12827#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 12828#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 12829#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 12830#define regVPG5_VPG_GENERIC_STATUS 0x0935 12831#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 3 12832#define regVPG5_VPG_MEM_PWR 0x0936 12833#define regVPG5_VPG_MEM_PWR_BASE_IDX 3 12834#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x0937 12835#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 12836#define regVPG5_VPG_ISRC1_2_DATA 0x0938 12837#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 3 12838#define regVPG5_VPG_MPEG_INFO0 0x0939 12839#define regVPG5_VPG_MPEG_INFO0_BASE_IDX 3 12840#define regVPG5_VPG_MPEG_INFO1 0x093a 12841#define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 12842 12843 12844// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec 12845// base address: 0x1ab8c 12846#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 12847#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 12848#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 12849#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 12850#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 12851#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 12852#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 12853#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 12854#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 12855#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 12856#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 12857#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 12858 12859 12860// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec 12861// base address: 0x1abc0 12862#define regAPG0_APG_CONTROL 0x3630 12863#define regAPG0_APG_CONTROL_BASE_IDX 2 12864#define regAPG0_APG_CONTROL2 0x3631 12865#define regAPG0_APG_CONTROL2_BASE_IDX 2 12866#define regAPG0_APG_DBG_GEN_CONTROL 0x3632 12867#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 12868#define regAPG0_APG_PACKET_CONTROL 0x3633 12869#define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 12870#define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a 12871#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 12872#define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b 12873#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 12874#define regAPG0_APG_AUDIO_CRC_RESULT 0x363c 12875#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 12876#define regAPG0_APG_STATUS 0x3641 12877#define regAPG0_APG_STATUS_BASE_IDX 2 12878#define regAPG0_APG_STATUS2 0x3642 12879#define regAPG0_APG_STATUS2_BASE_IDX 2 12880#define regAPG0_APG_MEM_PWR 0x3644 12881#define regAPG0_APG_MEM_PWR_BASE_IDX 2 12882#define regAPG0_APG_SPARE 0x3646 12883#define regAPG0_APG_SPARE_BASE_IDX 2 12884 12885 12886// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec 12887// base address: 0x1ac38 12888#define regDME6_DME_CONTROL 0x364e 12889#define regDME6_DME_CONTROL_BASE_IDX 2 12890#define regDME6_DME_MEMORY_CONTROL 0x364f 12891#define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 12892 12893 12894// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec 12895// base address: 0x1ac44 12896#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 12897#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 12898#define regVPG6_VPG_GENERIC_PACKET_DATA 0x3652 12899#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 12900#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 12901#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 12902#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 12903#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 12904#define regVPG6_VPG_GENERIC_STATUS 0x3655 12905#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 12906#define regVPG6_VPG_MEM_PWR 0x3656 12907#define regVPG6_VPG_MEM_PWR_BASE_IDX 2 12908#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x3657 12909#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 12910#define regVPG6_VPG_ISRC1_2_DATA 0x3658 12911#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 12912#define regVPG6_VPG_MPEG_INFO0 0x3659 12913#define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 12914#define regVPG6_VPG_MPEG_INFO1 0x365a 12915#define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 12916 12917 12918// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec 12919// base address: 0x1ac74 12920#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d 12921#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 12922#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e 12923#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 12924#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f 12925#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12926#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 12927#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12928#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 12929#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 12930#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 12931#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 12932#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 12933#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 12934#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 12935#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 12936#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 12937#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 12938#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 12939#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 12940#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 12941#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 12942#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 12943#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 12944#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 12945#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 12946#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a 12947#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 12948#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b 12949#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 12950#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c 12951#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 12952#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d 12953#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 12954#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e 12955#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 12956#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f 12957#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 12958#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 12959#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 12960#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 12961#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 12962#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 12963#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 12964#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 12965#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 12966#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 12967#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 12968#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 12969#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 12970#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 12971#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 12972#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 12973#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 12974#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 12975#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 12976#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 12977#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 12978#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a 12979#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 12980#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b 12981#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 12982#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c 12983#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 12984#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d 12985#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 12986#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e 12987#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 12988#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 12989#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 12990#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 12991#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 12992#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 12993#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 12994#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 12995#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 12996#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 12997#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 12998#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 12999#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13000#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 13001#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13002#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a 13003#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13004#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368b 13005#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13006#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368c 13007#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 13008 13009 13010// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec 13011// base address: 0x1aedc 13012#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 13013#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13014#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 13015#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13016#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 13017#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13018#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa 13019#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13020#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb 13021#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13022#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc 13023#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 13024 13025 13026// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec 13027// base address: 0x1af10 13028#define regAPG1_APG_CONTROL 0x3704 13029#define regAPG1_APG_CONTROL_BASE_IDX 2 13030#define regAPG1_APG_CONTROL2 0x3705 13031#define regAPG1_APG_CONTROL2_BASE_IDX 2 13032#define regAPG1_APG_DBG_GEN_CONTROL 0x3706 13033#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 13034#define regAPG1_APG_PACKET_CONTROL 0x3707 13035#define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 13036#define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e 13037#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13038#define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f 13039#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13040#define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 13041#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13042#define regAPG1_APG_STATUS 0x3715 13043#define regAPG1_APG_STATUS_BASE_IDX 2 13044#define regAPG1_APG_STATUS2 0x3716 13045#define regAPG1_APG_STATUS2_BASE_IDX 2 13046#define regAPG1_APG_MEM_PWR 0x3718 13047#define regAPG1_APG_MEM_PWR_BASE_IDX 2 13048#define regAPG1_APG_SPARE 0x371a 13049#define regAPG1_APG_SPARE_BASE_IDX 2 13050 13051 13052// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec 13053// base address: 0x1af88 13054#define regDME7_DME_CONTROL 0x3722 13055#define regDME7_DME_CONTROL_BASE_IDX 2 13056#define regDME7_DME_MEMORY_CONTROL 0x3723 13057#define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 13058 13059 13060// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec 13061// base address: 0x1af94 13062#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 13063#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13064#define regVPG7_VPG_GENERIC_PACKET_DATA 0x3726 13065#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13066#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 13067#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13068#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 13069#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13070#define regVPG7_VPG_GENERIC_STATUS 0x3729 13071#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 13072#define regVPG7_VPG_MEM_PWR 0x372a 13073#define regVPG7_VPG_MEM_PWR_BASE_IDX 2 13074#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x372b 13075#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13076#define regVPG7_VPG_ISRC1_2_DATA 0x372c 13077#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 13078#define regVPG7_VPG_MPEG_INFO0 0x372d 13079#define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 13080#define regVPG7_VPG_MPEG_INFO1 0x372e 13081#define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 13082 13083 13084// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec 13085// base address: 0x1afc4 13086#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 13087#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13088#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 13089#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13090#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 13091#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13092#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 13093#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13094#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 13095#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13096#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 13097#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13098#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 13099#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13100#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 13101#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13102#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 13103#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13104#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a 13105#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13106#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b 13107#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13108#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c 13109#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13110#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d 13111#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13112#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e 13113#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13114#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f 13115#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13116#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 13117#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13118#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 13119#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13120#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 13121#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13122#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 13123#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13124#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 13125#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13126#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 13127#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13128#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 13129#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13130#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 13131#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13132#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 13133#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13134#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 13135#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13136#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a 13137#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13138#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b 13139#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13140#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c 13141#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13142#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d 13143#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13144#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e 13145#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13146#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f 13147#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13148#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 13149#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13150#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 13151#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13152#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 13153#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13154#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 13155#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13156#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 13157#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13158#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 13159#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13160#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a 13161#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13162#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b 13163#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13164#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c 13165#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13166#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d 13167#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13168#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e 13169#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13170#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x375f 13171#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13172#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3760 13173#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 13174 13175 13176// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec 13177// base address: 0x1b22c 13178#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb 13179#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13180#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc 13181#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13182#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd 13183#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13184#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce 13185#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13186#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf 13187#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13188#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 13189#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 13190 13191 13192// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec 13193// base address: 0x1b260 13194#define regAPG2_APG_CONTROL 0x37d8 13195#define regAPG2_APG_CONTROL_BASE_IDX 2 13196#define regAPG2_APG_CONTROL2 0x37d9 13197#define regAPG2_APG_CONTROL2_BASE_IDX 2 13198#define regAPG2_APG_DBG_GEN_CONTROL 0x37da 13199#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 13200#define regAPG2_APG_PACKET_CONTROL 0x37db 13201#define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 13202#define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 13203#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13204#define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 13205#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13206#define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 13207#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13208#define regAPG2_APG_STATUS 0x37e9 13209#define regAPG2_APG_STATUS_BASE_IDX 2 13210#define regAPG2_APG_STATUS2 0x37ea 13211#define regAPG2_APG_STATUS2_BASE_IDX 2 13212#define regAPG2_APG_MEM_PWR 0x37ec 13213#define regAPG2_APG_MEM_PWR_BASE_IDX 2 13214#define regAPG2_APG_SPARE 0x37ee 13215#define regAPG2_APG_SPARE_BASE_IDX 2 13216 13217 13218// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec 13219// base address: 0x1b2d8 13220#define regDME8_DME_CONTROL 0x37f6 13221#define regDME8_DME_CONTROL_BASE_IDX 2 13222#define regDME8_DME_MEMORY_CONTROL 0x37f7 13223#define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 13224 13225 13226// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec 13227// base address: 0x1b2e4 13228#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 13229#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13230#define regVPG8_VPG_GENERIC_PACKET_DATA 0x37fa 13231#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13232#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb 13233#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13234#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc 13235#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13236#define regVPG8_VPG_GENERIC_STATUS 0x37fd 13237#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 13238#define regVPG8_VPG_MEM_PWR 0x37fe 13239#define regVPG8_VPG_MEM_PWR_BASE_IDX 2 13240#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x37ff 13241#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13242#define regVPG8_VPG_ISRC1_2_DATA 0x3800 13243#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 13244#define regVPG8_VPG_MPEG_INFO0 0x3801 13245#define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 13246#define regVPG8_VPG_MPEG_INFO1 0x3802 13247#define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 13248 13249 13250// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec 13251// base address: 0x1b314 13252#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 13253#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13254#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 13255#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13256#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 13257#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13258#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 13259#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13260#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 13261#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13262#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a 13263#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13264#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b 13265#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13266#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c 13267#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13268#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d 13269#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13270#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e 13271#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13272#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f 13273#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13274#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 13275#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13276#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 13277#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13278#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 13279#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13280#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 13281#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13282#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 13283#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13284#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 13285#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13286#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 13287#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13288#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 13289#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13290#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 13291#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13292#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 13293#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13294#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a 13295#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13296#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b 13297#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13298#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c 13299#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13300#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d 13301#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13302#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e 13303#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13304#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f 13305#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13306#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 13307#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13308#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 13309#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13310#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 13311#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13312#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 13313#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13314#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 13315#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13316#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 13317#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13318#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 13319#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13320#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b 13321#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13322#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c 13323#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13324#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d 13325#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13326#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e 13327#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13328#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f 13329#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13330#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 13331#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13332#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 13333#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13334#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 13335#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13336#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3833 13337#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13338#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3834 13339#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 13340 13341 13342// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec 13343// base address: 0x1b57c 13344#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f 13345#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13346#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 13347#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13348#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 13349#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13350#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 13351#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13352#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 13353#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13354#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 13355#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 13356 13357 13358// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec 13359// base address: 0x1b5b0 13360#define regAPG3_APG_CONTROL 0x38ac 13361#define regAPG3_APG_CONTROL_BASE_IDX 2 13362#define regAPG3_APG_CONTROL2 0x38ad 13363#define regAPG3_APG_CONTROL2_BASE_IDX 2 13364#define regAPG3_APG_DBG_GEN_CONTROL 0x38ae 13365#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 13366#define regAPG3_APG_PACKET_CONTROL 0x38af 13367#define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 13368#define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 13369#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13370#define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 13371#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13372#define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 13373#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13374#define regAPG3_APG_STATUS 0x38bd 13375#define regAPG3_APG_STATUS_BASE_IDX 2 13376#define regAPG3_APG_STATUS2 0x38be 13377#define regAPG3_APG_STATUS2_BASE_IDX 2 13378#define regAPG3_APG_MEM_PWR 0x38c0 13379#define regAPG3_APG_MEM_PWR_BASE_IDX 2 13380#define regAPG3_APG_SPARE 0x38c2 13381#define regAPG3_APG_SPARE_BASE_IDX 2 13382 13383 13384// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec 13385// base address: 0x1b628 13386#define regDME9_DME_CONTROL 0x38ca 13387#define regDME9_DME_CONTROL_BASE_IDX 2 13388#define regDME9_DME_MEMORY_CONTROL 0x38cb 13389#define regDME9_DME_MEMORY_CONTROL_BASE_IDX 2 13390 13391 13392// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec 13393// base address: 0x1b634 13394#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd 13395#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13396#define regVPG9_VPG_GENERIC_PACKET_DATA 0x38ce 13397#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13398#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf 13399#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13400#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 13401#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13402#define regVPG9_VPG_GENERIC_STATUS 0x38d1 13403#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 2 13404#define regVPG9_VPG_MEM_PWR 0x38d2 13405#define regVPG9_VPG_MEM_PWR_BASE_IDX 2 13406#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 13407#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13408#define regVPG9_VPG_ISRC1_2_DATA 0x38d4 13409#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 2 13410#define regVPG9_VPG_MPEG_INFO0 0x38d5 13411#define regVPG9_VPG_MPEG_INFO0_BASE_IDX 2 13412#define regVPG9_VPG_MPEG_INFO1 0x38d6 13413#define regVPG9_VPG_MPEG_INFO1_BASE_IDX 2 13414 13415 13416// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec 13417// base address: 0x1b664 13418#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 13419#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13420#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da 13421#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13422#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db 13423#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13424#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc 13425#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13426#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd 13427#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13428#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de 13429#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13430#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df 13431#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13432#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 13433#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13434#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 13435#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13436#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 13437#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13438#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 13439#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13440#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 13441#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13442#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 13443#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13444#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 13445#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13446#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 13447#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13448#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 13449#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13450#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 13451#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13452#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea 13453#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13454#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb 13455#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13456#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec 13457#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13458#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed 13459#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13460#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee 13461#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13462#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef 13463#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13464#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 13465#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13466#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 13467#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13468#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 13469#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13470#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 13471#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13472#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 13473#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13474#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 13475#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13476#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 13477#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13478#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 13479#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13480#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 13481#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13482#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 13483#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13484#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa 13485#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13486#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff 13487#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13488#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 13489#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13490#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 13491#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13492#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 13493#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13494#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 13495#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13496#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 13497#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13498#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 13499#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13500#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 13501#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13502#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3907 13503#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13504#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3908 13505#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 13506 13507 13508// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec 13509// base address: 0x1ad5c 13510#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 13511#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 13512#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 13513#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 13514 13515 13516// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec 13517// base address: 0x1ae00 13518#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 13519#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 13520#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 13521#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 13522#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 13523#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 13524#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 13525#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 13526#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 13527#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 13528#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 13529#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 13530#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 13531#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 13532#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb 13533#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 13534#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc 13535#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 13536#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd 13537#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 13538#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce 13539#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 13540#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 13541#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 13542#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 13543#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 13544#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 13545#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 13546#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 13547#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 13548#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 13549#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 13550#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 13551#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 13552#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 13553#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 13554#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da 13555#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 13556#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db 13557#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 13558#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc 13559#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 13560#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd 13561#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 13562#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de 13563#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 13564#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df 13565#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 13566#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 13567#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 13568#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 13569#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 13570#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 13571#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 13572#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 13573#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 13574#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 13575#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 13576#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 13577#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 13578#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 13579#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 13580#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 13581#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 13582#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 13583#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 13584#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea 13585#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 13586#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36eb 13587#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 13588#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ec 13589#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 13590#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36ed 13591#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 13592#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36ee 13593#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 13594 13595 13596// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec 13597// base address: 0x1b0ac 13598#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b 13599#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 13600#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c 13601#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 13602 13603 13604// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec 13605// base address: 0x1b150 13606#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 13607#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 13608#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 13609#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 13610#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 13611#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 13612#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 13613#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 13614#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a 13615#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 13616#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b 13617#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 13618#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c 13619#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 13620#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f 13621#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 13622#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 13623#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 13624#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 13625#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 13626#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 13627#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 13628#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 13629#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 13630#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 13631#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 13632#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 13633#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 13634#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 13635#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 13636#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab 13637#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 13638#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac 13639#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 13640#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad 13641#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 13642#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae 13643#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 13644#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af 13645#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 13646#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 13647#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 13648#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 13649#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 13650#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 13651#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 13652#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 13653#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 13654#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 13655#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 13656#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 13657#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 13658#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 13659#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 13660#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 13661#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 13662#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 13663#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 13664#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 13665#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 13666#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba 13667#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 13668#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb 13669#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 13670#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc 13671#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 13672#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be 13673#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 13674#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37bf 13675#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 13676#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c0 13677#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 13678#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c1 13679#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 13680#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c2 13681#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 13682 13683 13684// addressBlock: dce_dc_dchvm_hvm_dispdec 13685// base address: 0x0 13686#define regDCHVM_CTRL0 0x3603 13687#define regDCHVM_CTRL0_BASE_IDX 2 13688#define regDCHVM_CTRL1 0x3604 13689#define regDCHVM_CTRL1_BASE_IDX 2 13690#define regDCHVM_CLK_CTRL 0x3605 13691#define regDCHVM_CLK_CTRL_BASE_IDX 2 13692#define regDCHVM_MEM_CTRL 0x3606 13693#define regDCHVM_MEM_CTRL_BASE_IDX 2 13694#define regDCHVM_RIOMMU_CTRL0 0x3607 13695#define regDCHVM_RIOMMU_CTRL0_BASE_IDX 2 13696#define regDCHVM_RIOMMU_STAT0 0x3608 13697#define regDCHVM_RIOMMU_STAT0_BASE_IDX 2 13698 13699 13700// addressBlock: dce_dc_hda_azcontroller_azdec 13701// base address: 0x1300000 13702#define regCORB_WRITE_POINTER 0x4b7012 13703#define regCORB_WRITE_POINTER_BASE_IDX 3 13704#define regCORB_READ_POINTER 0x4b7012 13705#define regCORB_READ_POINTER_BASE_IDX 3 13706#define regCORB_CONTROL 0x4b7013 13707#define regCORB_CONTROL_BASE_IDX 3 13708#define regCORB_STATUS 0x4b7013 13709#define regCORB_STATUS_BASE_IDX 3 13710#define regCORB_SIZE 0x4b7013 13711#define regCORB_SIZE_BASE_IDX 3 13712#define regRIRB_LOWER_BASE_ADDRESS 0x4b7014 13713#define regRIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 13714#define regRIRB_UPPER_BASE_ADDRESS 0x4b7015 13715#define regRIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 13716#define regRIRB_WRITE_POINTER 0x4b7016 13717#define regRIRB_WRITE_POINTER_BASE_IDX 3 13718#define regRESPONSE_INTERRUPT_COUNT 0x4b7016 13719#define regRESPONSE_INTERRUPT_COUNT_BASE_IDX 3 13720#define regRIRB_CONTROL 0x4b7017 13721#define regRIRB_CONTROL_BASE_IDX 3 13722#define regRIRB_STATUS 0x4b7017 13723#define regRIRB_STATUS_BASE_IDX 3 13724#define regRIRB_SIZE 0x4b7017 13725#define regRIRB_SIZE_BASE_IDX 3 13726#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 13727#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 13728#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 13729#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 13730#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 13731#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 13732#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 13733#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 13734#define regIMMEDIATE_COMMAND_STATUS 0x4b701a 13735#define regIMMEDIATE_COMMAND_STATUS_BASE_IDX 3 13736#define regDMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c 13737#define regDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 13738#define regDMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d 13739#define regDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 13740 13741 13742// addressBlock: dce_dc_hda_azendpoint_azdec 13743// base address: 0x1300000 13744#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 13745#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 13746#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 13747#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 13748 13749 13750// addressBlock: dce_dc_hda_azinputendpoint_azdec 13751// base address: 0x1300000 13752#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 13753#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 13754#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 13755#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 13756 13757 13758// addressBlock: dce_dc_hda_azroot_azdec 13759// base address: 0x1300000 13760#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 13761#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 13762#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 13763#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 13764 13765 13766// addressBlock: dce_dc_hda_azstream0_azdec 13767// base address: 0x1300000 13768#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7020 13769#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 13770#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7021 13771#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 13772#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7022 13773#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 13774#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7023 13775#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 13776#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7024 13777#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 13778#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7024 13779#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 13780#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7026 13781#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 13782#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7027 13783#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 13784#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7821 13785#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 13786 13787 13788// addressBlock: dce_dc_hda_azstream1_azdec 13789// base address: 0x1300020 13790#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7028 13791#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 13792#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7029 13793#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 13794#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b702a 13795#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 13796#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b702b 13797#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 13798#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b702c 13799#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 13800#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b702c 13801#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 13802#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b702e 13803#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 13804#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b702f 13805#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 13806#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7829 13807#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 13808 13809 13810// addressBlock: dce_dc_hda_azstream2_azdec 13811// base address: 0x1300040 13812#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7030 13813#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 13814#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7031 13815#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 13816#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7032 13817#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 13818#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7033 13819#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 13820#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7034 13821#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 13822#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7034 13823#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 13824#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7036 13825#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 13826#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7037 13827#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 13828#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7831 13829#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 13830 13831 13832// addressBlock: dce_dc_hda_azstream3_azdec 13833// base address: 0x1300060 13834#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7038 13835#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 13836#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7039 13837#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 13838#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b703a 13839#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 13840#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b703b 13841#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 13842#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b703c 13843#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 13844#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b703c 13845#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 13846#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b703e 13847#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 13848#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b703f 13849#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 13850#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7839 13851#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 13852 13853 13854// addressBlock: dce_dc_hda_azstream4_azdec 13855// base address: 0x1300080 13856#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7040 13857#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 13858#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7041 13859#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 13860#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7042 13861#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 13862#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7043 13863#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 13864#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7044 13865#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 13866#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7044 13867#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 13868#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7046 13869#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 13870#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7047 13871#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 13872#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7841 13873#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 13874 13875 13876// addressBlock: dce_dc_hda_azstream5_azdec 13877// base address: 0x13000a0 13878#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7048 13879#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 13880#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7049 13881#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 13882#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b704a 13883#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 13884#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b704b 13885#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 13886#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b704c 13887#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 13888#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b704c 13889#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 13890#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b704e 13891#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 13892#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b704f 13893#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 13894#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7849 13895#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 13896 13897 13898// addressBlock: dce_dc_hda_azstream6_azdec 13899// base address: 0x13000c0 13900#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7050 13901#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 13902#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7051 13903#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 13904#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7052 13905#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 13906#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7053 13907#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 13908#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7054 13909#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 13910#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7054 13911#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 13912#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7056 13913#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 13914#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7057 13915#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 13916#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7851 13917#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 13918 13919 13920// addressBlock: dce_dc_hda_azstream7_azdec 13921// base address: 0x13000e0 13922#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7058 13923#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 13924#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7059 13925#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 13926#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b705a 13927#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 13928#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b705b 13929#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 13930#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b705c 13931#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 13932#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b705c 13933#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 13934#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b705e 13935#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 13936#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b705f 13937#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 13938#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7859 13939#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 13940 13941 13942// addressBlock: vga_vgaseqind 13943// base address: 0x0 13944#define ixSEQ00 0x0000 13945#define ixSEQ01 0x0001 13946#define ixSEQ02 0x0002 13947#define ixSEQ03 0x0003 13948#define ixSEQ04 0x0004 13949 13950 13951// addressBlock: vga_vgacrtind 13952// base address: 0x0 13953#define ixCRT00 0x0000 13954#define ixCRT01 0x0001 13955#define ixCRT02 0x0002 13956#define ixCRT03 0x0003 13957#define ixCRT04 0x0004 13958#define ixCRT05 0x0005 13959#define ixCRT06 0x0006 13960#define ixCRT07 0x0007 13961#define ixCRT08 0x0008 13962#define ixCRT09 0x0009 13963#define ixCRT0A 0x000a 13964#define ixCRT0B 0x000b 13965#define ixCRT0C 0x000c 13966#define ixCRT0D 0x000d 13967#define ixCRT0E 0x000e 13968#define ixCRT0F 0x000f 13969#define ixCRT10 0x0010 13970#define ixCRT11 0x0011 13971#define ixCRT12 0x0012 13972#define ixCRT13 0x0013 13973#define ixCRT14 0x0014 13974#define ixCRT15 0x0015 13975#define ixCRT16 0x0016 13976#define ixCRT17 0x0017 13977#define ixCRT18 0x0018 13978#define ixCRT1E 0x001e 13979#define ixCRT1F 0x001f 13980#define ixCRT22 0x0022 13981 13982 13983// addressBlock: vga_vgagrphind 13984// base address: 0x0 13985#define ixGRA00 0x0000 13986#define ixGRA01 0x0001 13987#define ixGRA02 0x0002 13988#define ixGRA03 0x0003 13989#define ixGRA04 0x0004 13990#define ixGRA05 0x0005 13991#define ixGRA06 0x0006 13992#define ixGRA07 0x0007 13993#define ixGRA08 0x0008 13994 13995 13996// addressBlock: vga_vgaattrind 13997// base address: 0x0 13998#define ixATTR00 0x0000 13999#define ixATTR01 0x0001 14000#define ixATTR02 0x0002 14001#define ixATTR03 0x0003 14002#define ixATTR04 0x0004 14003#define ixATTR05 0x0005 14004#define ixATTR06 0x0006 14005#define ixATTR07 0x0007 14006#define ixATTR08 0x0008 14007#define ixATTR09 0x0009 14008#define ixATTR0A 0x000a 14009#define ixATTR0B 0x000b 14010#define ixATTR0C 0x000c 14011#define ixATTR0D 0x000d 14012#define ixATTR0E 0x000e 14013#define ixATTR0F 0x000f 14014#define ixATTR10 0x0010 14015#define ixATTR11 0x0011 14016#define ixATTR12 0x0012 14017#define ixATTR13 0x0013 14018#define ixATTR14 0x0014 14019 14020 14021// addressBlock: azendpoint_f2codecind 14022// base address: 0x0 14023#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 14024#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 14025#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 14026#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 14027#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 14028#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 14029#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 14030#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 14031#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 14032#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 14033#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 14034#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 14035#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 14036#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 14037#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 14038#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 14039#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 14040#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 14041#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 14042#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 14043#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 14044#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 14045#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 14046#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 14047#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 14048#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 14049#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 14050#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 14051#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 14052#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 14053#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 14054#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 14055#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 14056#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 14057#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 14058#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 14059#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 14060#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 14061#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 14062#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 14063#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 14064#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 14065#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 14066#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 14067#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 14068#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 14069#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 14070#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 14071#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 14072#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 14073#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 14074#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 14075#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 14076#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 14077#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 14078#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 14079#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 14080#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 14081 14082 14083// addressBlock: azendpoint_descriptorind 14084// base address: 0x0 14085#define ixAUDIO_DESCRIPTOR0 0x0001 14086#define ixAUDIO_DESCRIPTOR1 0x0002 14087#define ixAUDIO_DESCRIPTOR2 0x0003 14088#define ixAUDIO_DESCRIPTOR3 0x0004 14089#define ixAUDIO_DESCRIPTOR4 0x0005 14090#define ixAUDIO_DESCRIPTOR5 0x0006 14091#define ixAUDIO_DESCRIPTOR6 0x0007 14092#define ixAUDIO_DESCRIPTOR7 0x0008 14093#define ixAUDIO_DESCRIPTOR8 0x0009 14094#define ixAUDIO_DESCRIPTOR9 0x000a 14095#define ixAUDIO_DESCRIPTOR10 0x000b 14096#define ixAUDIO_DESCRIPTOR11 0x000c 14097#define ixAUDIO_DESCRIPTOR12 0x000d 14098#define ixAUDIO_DESCRIPTOR13 0x000e 14099 14100 14101// addressBlock: azendpoint_sinkinfoind 14102// base address: 0x0 14103#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 14104#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 14105#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 14106#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 14107#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 14108#define ixSINK_DESCRIPTION0 0x0005 14109#define ixSINK_DESCRIPTION1 0x0006 14110#define ixSINK_DESCRIPTION2 0x0007 14111#define ixSINK_DESCRIPTION3 0x0008 14112#define ixSINK_DESCRIPTION4 0x0009 14113#define ixSINK_DESCRIPTION5 0x000a 14114#define ixSINK_DESCRIPTION6 0x000b 14115#define ixSINK_DESCRIPTION7 0x000c 14116#define ixSINK_DESCRIPTION8 0x000d 14117#define ixSINK_DESCRIPTION9 0x000e 14118#define ixSINK_DESCRIPTION10 0x000f 14119#define ixSINK_DESCRIPTION11 0x0010 14120#define ixSINK_DESCRIPTION12 0x0011 14121#define ixSINK_DESCRIPTION13 0x0012 14122#define ixSINK_DESCRIPTION14 0x0013 14123#define ixSINK_DESCRIPTION15 0x0014 14124#define ixSINK_DESCRIPTION16 0x0015 14125#define ixSINK_DESCRIPTION17 0x0016 14126 14127 14128// addressBlock: azf0controller_azinputcrc0resultind 14129// base address: 0x0 14130#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 14131#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 14132#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 14133#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 14134#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 14135#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 14136#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 14137#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 14138 14139 14140// addressBlock: azf0controller_azinputcrc1resultind 14141// base address: 0x0 14142#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 14143#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 14144#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 14145#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 14146#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 14147#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 14148#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 14149#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 14150 14151 14152// addressBlock: azf0controller_azcrc0resultind 14153// base address: 0x0 14154#define ixAZALIA_CRC0_CHANNEL0 0x0000 14155#define ixAZALIA_CRC0_CHANNEL1 0x0001 14156#define ixAZALIA_CRC0_CHANNEL2 0x0002 14157#define ixAZALIA_CRC0_CHANNEL3 0x0003 14158#define ixAZALIA_CRC0_CHANNEL4 0x0004 14159#define ixAZALIA_CRC0_CHANNEL5 0x0005 14160#define ixAZALIA_CRC0_CHANNEL6 0x0006 14161#define ixAZALIA_CRC0_CHANNEL7 0x0007 14162 14163 14164// addressBlock: azf0controller_azcrc1resultind 14165// base address: 0x0 14166#define ixAZALIA_CRC1_CHANNEL0 0x0000 14167#define ixAZALIA_CRC1_CHANNEL1 0x0001 14168#define ixAZALIA_CRC1_CHANNEL2 0x0002 14169#define ixAZALIA_CRC1_CHANNEL3 0x0003 14170#define ixAZALIA_CRC1_CHANNEL4 0x0004 14171#define ixAZALIA_CRC1_CHANNEL5 0x0005 14172#define ixAZALIA_CRC1_CHANNEL6 0x0006 14173#define ixAZALIA_CRC1_CHANNEL7 0x0007 14174 14175 14176// addressBlock: azinputendpoint_f2codecind 14177// base address: 0x0 14178#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 14179#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 14180#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 14181#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 14182#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 14183#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 14184#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 14185#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 14186#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 14187#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 14188#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 14189#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 14190#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 14191#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 14192#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 14193#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 14194#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 14195#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 14196#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 14197#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 14198#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 14199#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 14200#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 14201#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 14202#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 14203#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 14204#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 14205#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 14206#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 14207#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 14208#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 14209#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 14210 14211 14212// addressBlock: azroot_f2codecind 14213// base address: 0x0 14214#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 14215#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 14216#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 14217#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 14218#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 14219#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 14220#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 14221#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 14222#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 14223#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 14224#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 14225#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 14226#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 14227#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 14228#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 14229 14230 14231// addressBlock: azf0stream0_streamind 14232// base address: 0x0 14233#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 14234#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14235#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14236#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14237#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14238 14239 14240// addressBlock: azf0stream1_streamind 14241// base address: 0x0 14242#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 14243#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14244#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14245#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14246#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14247 14248 14249// addressBlock: azf0stream2_streamind 14250// base address: 0x0 14251#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 14252#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14253#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14254#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14255#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14256 14257 14258// addressBlock: azf0stream3_streamind 14259// base address: 0x0 14260#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 14261#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14262#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14263#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14264#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14265 14266 14267// addressBlock: azf0stream4_streamind 14268// base address: 0x0 14269#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 14270#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14271#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14272#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14273#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14274 14275 14276// addressBlock: azf0stream5_streamind 14277// base address: 0x0 14278#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 14279#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14280#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14281#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14282#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14283 14284 14285// addressBlock: azf0stream6_streamind 14286// base address: 0x0 14287#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 14288#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14289#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14290#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14291#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14292 14293 14294// addressBlock: azf0stream7_streamind 14295// base address: 0x0 14296#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 14297#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14298#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14299#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14300#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14301 14302 14303// addressBlock: azf0stream8_streamind 14304// base address: 0x0 14305#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 14306#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14307#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14308#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14309#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14310 14311 14312// addressBlock: azf0stream9_streamind 14313// base address: 0x0 14314#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 14315#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14316#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14317#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14318#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14319 14320 14321// addressBlock: azf0stream10_streamind 14322// base address: 0x0 14323#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 14324#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14325#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14326#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14327#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14328 14329 14330// addressBlock: azf0stream11_streamind 14331// base address: 0x0 14332#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 14333#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14334#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14335#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14336#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14337 14338 14339// addressBlock: azf0stream12_streamind 14340// base address: 0x0 14341#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 14342#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14343#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14344#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14345#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14346 14347 14348// addressBlock: azf0stream13_streamind 14349// base address: 0x0 14350#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 14351#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14352#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14353#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14354#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14355 14356 14357// addressBlock: azf0stream14_streamind 14358// base address: 0x0 14359#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 14360#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14361#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14362#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14363#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14364 14365 14366// addressBlock: azf0stream15_streamind 14367// base address: 0x0 14368#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 14369#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14370#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14371#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14372#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14373 14374 14375// addressBlock: azf0endpoint0_endpointind 14376// base address: 0x0 14377#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14378#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14379#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14380#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14381#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14382#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14383#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14384#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14385#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14386#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14387#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14388#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14389#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14390#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14391#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14392#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14393#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14394#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14395#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14396#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14397#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14398#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14399#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14400#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14401#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14402#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14403#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14404#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14405#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14406#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14407#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14408#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14409#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14410#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14411#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14412#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14413#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14414#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14415#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14416#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14417#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14418#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14419#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14420#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14421#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14422#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14423#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14424#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14425#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14426#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14427#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14428#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14429#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14430#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14431#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14432#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14433#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14434#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14435#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14436#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14437#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14438#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14439#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14440#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14441#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14442#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14443#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14444#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14445#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14446#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14447#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14448 14449 14450// addressBlock: azf0endpoint1_endpointind 14451// base address: 0x0 14452#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14453#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14454#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14455#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14456#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14457#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14458#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14459#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14460#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14461#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14462#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14463#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14464#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14465#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14466#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14467#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14468#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14469#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14470#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14471#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14472#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14473#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14474#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14475#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14476#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14477#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14478#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14479#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14480#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14481#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14482#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14483#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14484#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14485#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14486#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14487#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14488#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14489#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14490#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14491#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14492#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14493#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14494#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14495#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14496#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14497#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14498#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14499#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14500#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14501#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14502#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14503#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14504#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14505#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14506#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14507#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14508#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14509#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14510#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14511#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14512#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14513#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14514#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14515#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14516#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14517#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14518#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14519#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14520#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14521#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14522#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14523 14524 14525// addressBlock: azf0endpoint2_endpointind 14526// base address: 0x0 14527#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14528#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14529#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14530#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14531#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14532#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14533#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14534#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14535#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14536#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14537#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14538#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14539#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14540#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14541#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14542#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14543#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14544#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14545#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14546#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14547#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14548#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14549#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14550#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14551#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14552#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14553#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14554#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14555#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14556#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14557#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14558#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14559#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14560#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14561#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14562#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14563#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14564#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14565#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14566#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14567#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14568#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14569#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14570#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14571#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14572#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14573#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14574#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14575#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14576#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14577#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14578#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14579#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14580#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14581#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14582#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14583#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14584#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14585#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14586#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14587#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14588#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14589#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14590#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14591#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14592#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14593#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14594#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14595#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14596#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14597#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14598 14599 14600// addressBlock: azf0endpoint3_endpointind 14601// base address: 0x0 14602#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14603#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14604#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14605#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14606#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14607#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14608#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14609#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14610#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14611#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14612#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14613#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14614#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14615#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14616#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14617#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14618#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14619#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14620#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14621#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14622#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14623#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14624#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14625#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14626#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14627#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14628#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14629#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14630#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14631#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14632#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14633#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14634#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14635#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14636#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14637#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14638#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14639#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14640#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14641#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14642#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14643#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14644#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14645#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14646#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14647#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14648#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14649#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14650#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14651#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14652#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14653#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14654#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14655#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14656#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14657#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14658#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14659#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14660#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14661#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14662#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14663#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14664#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14665#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14666#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14667#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14668#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14669#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14670#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14671#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14672#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14673 14674 14675// addressBlock: azf0endpoint4_endpointind 14676// base address: 0x0 14677#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14678#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14679#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14680#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14681#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14682#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14683#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14684#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14685#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14686#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14687#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14688#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14689#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14690#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14691#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14692#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14693#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14694#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14695#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14696#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14697#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14698#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14699#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14700#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14701#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14702#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14703#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14704#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14705#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14706#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14707#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14708#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14709#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14710#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14711#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14712#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14713#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14714#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14715#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14716#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14717#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14718#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14719#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14720#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14721#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14722#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14723#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14724#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14725#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14726#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14727#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14728#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14729#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14730#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14731#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14732#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14733#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14734#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14735#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14736#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14737#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14738#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14739#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14740#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14741#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14742#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14743#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14744#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14745#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14746#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14747#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14748 14749 14750// addressBlock: azf0endpoint5_endpointind 14751// base address: 0x0 14752#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14753#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14754#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14755#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14756#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14757#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14758#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14759#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14760#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14761#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14762#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14763#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14764#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14765#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14766#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14767#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14768#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14769#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14770#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14771#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14772#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14773#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14774#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14775#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14776#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14777#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14778#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14779#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14780#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14781#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14782#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14783#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14784#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14785#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14786#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14787#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14788#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14789#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14790#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14791#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14792#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14793#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14794#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14795#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14796#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14797#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14798#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14799#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14800#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14801#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14802#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14803#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14804#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14805#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14806#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14807#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14808#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14809#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14810#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14811#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14812#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14813#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14814#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14815#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14816#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14817#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14818#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14819#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14820#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14821#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14822#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14823 14824 14825// addressBlock: azf0endpoint6_endpointind 14826// base address: 0x0 14827#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14828#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14829#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14830#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14831#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14832#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14833#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14834#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14835#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14836#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14837#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14838#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14839#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14840#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14841#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14842#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14843#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14844#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14845#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14846#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14847#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14848#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14849#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14850#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14851#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14852#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14853#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14854#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14855#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14856#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14857#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14858#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14859#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14860#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14861#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14862#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14863#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14864#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14865#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14866#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14867#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14868#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14869#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14870#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14871#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14872#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14873#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14874#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14875#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14876#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14877#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14878#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14879#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14880#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14881#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14882#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14883#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14884#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14885#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14886#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14887#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14888#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14889#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14890#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14891#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14892#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14893#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14894#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14895#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14896#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14897#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14898 14899 14900// addressBlock: azf0endpoint7_endpointind 14901// base address: 0x0 14902#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14903#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14904#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14905#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14906#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14907#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14908#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14909#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14910#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14911#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14912#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14913#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14914#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14915#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14916#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14917#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14918#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14919#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14920#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14921#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14922#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14923#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14924#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14925#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14926#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14927#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14928#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14929#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14930#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14931#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14932#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14933#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14934#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14935#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14936#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14937#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14938#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14939#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14940#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14941#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14942#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14943#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14944#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14945#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14946#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14947#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14948#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14949#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14950#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14951#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14952#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14953#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14954#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14955#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14956#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14957#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14958#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14959#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14960#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14961#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14962#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14963#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14964#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14965#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14966#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14967#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14968#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14969#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14970#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14971#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14972#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14973 14974 14975// addressBlock: azf0inputendpoint0_inputendpointind 14976// base address: 0x0 14977#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14978#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14979#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14980#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14981#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14982#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14983#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14984#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14985#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14986#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14987#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14988#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14989#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14990#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14991#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14992#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14993#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14994#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14995#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14996#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14997#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14998#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14999#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15000 15001 15002// addressBlock: azf0inputendpoint1_inputendpointind 15003// base address: 0x0 15004#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15005#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15006#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15007#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15008#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15009#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15010#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15011#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15012#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15013#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15014#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15015#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15016#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15017#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15018#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15019#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15020#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15021#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15022#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15023#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15024#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15025#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15026#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15027 15028 15029// addressBlock: azf0inputendpoint2_inputendpointind 15030// base address: 0x0 15031#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15032#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15033#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15034#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15035#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15036#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15037#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15038#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15039#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15040#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15041#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15042#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15043#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15044#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15045#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15046#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15047#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15048#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15049#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15050#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15051#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15052#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15053#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15054 15055 15056// addressBlock: azf0inputendpoint3_inputendpointind 15057// base address: 0x0 15058#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15059#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15060#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15061#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15062#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15063#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15064#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15065#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15066#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15067#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15068#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15069#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15070#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15071#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15072#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15073#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15074#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15075#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15076#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15077#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15078#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15079#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15080#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15081 15082 15083// addressBlock: azf0inputendpoint4_inputendpointind 15084// base address: 0x0 15085#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15086#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15087#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15088#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15089#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15090#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15091#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15092#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15093#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15094#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15095#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15096#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15097#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15098#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15099#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15100#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15101#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15102#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15103#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15104#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15105#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15106#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15107#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15108 15109 15110// addressBlock: azf0inputendpoint5_inputendpointind 15111// base address: 0x0 15112#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15113#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15114#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15115#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15116#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15117#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15118#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15119#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15120#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15121#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15122#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15123#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15124#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15125#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15126#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15127#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15128#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15129#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15130#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15131#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15132#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15133#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15134#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15135 15136 15137// addressBlock: azf0inputendpoint6_inputendpointind 15138// base address: 0x0 15139#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15140#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15141#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15142#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15143#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15144#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15145#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15146#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15147#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15148#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15149#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15150#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15151#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15152#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15153#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15154#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15155#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15156#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15157#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15158#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15159#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15160#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15161#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15162 15163 15164// addressBlock: azf0inputendpoint7_inputendpointind 15165// base address: 0x0 15166#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15167#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15168#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15169#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15170#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15171#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15172#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15173#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15174#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15175#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15176#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15177#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15178#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15179#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15180#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15181#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15182#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15183#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15184#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15185#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15186#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15187#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15188#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15189 15190 15191#endif 15192