display_mode_enums.h revision 1.6 
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#ifndef __DISPLAY_MODE_ENUMS_H__
26#define __DISPLAY_MODE_ENUMS_H__
27
28enum output_encoder_class {
29	dm_dp = 0,
30	dm_hdmi = 1,
31	dm_wb = 2,
32	dm_edp = 3,
33	dm_dp2p0 = 5,
34};
35enum output_format_class {
36	dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
37};
38enum source_format_class {
39	dm_444_16 = 0,
40	dm_444_32 = 1,
41	dm_444_64 = 2,
42	dm_420_8 = 3,
43	dm_420_10 = 4,
44	dm_420_12 = 5,
45	dm_422_8 = 6,
46	dm_422_10 = 7,
47	dm_444_8 = 8,
48	dm_mono_8 = dm_444_8,
49	dm_mono_16 = dm_444_16,
50	dm_rgbe = 9,
51	dm_rgbe_alpha = 10,
52};
53enum output_bpc_class {
54	dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
55};
56enum scan_direction_class {
57	dm_horz = 0, dm_vert = 1
58};
59enum dm_swizzle_mode {
60	dm_sw_linear = 0,
61	dm_sw_256b_s = 1,
62	dm_sw_256b_d = 2,
63	dm_sw_SPARE_0 = 3,
64	dm_sw_SPARE_1 = 4,
65	dm_sw_4kb_s = 5,
66	dm_sw_4kb_d = 6,
67	dm_sw_SPARE_2 = 7,
68	dm_sw_SPARE_3 = 8,
69	dm_sw_64kb_s = 9,
70	dm_sw_64kb_d = 10,
71	dm_sw_SPARE_4 = 11,
72	dm_sw_SPARE_5 = 12,
73	dm_sw_var_s = 13,
74	dm_sw_var_d = 14,
75	dm_sw_SPARE_6 = 15,
76	dm_sw_SPARE_7 = 16,
77	dm_sw_64kb_s_t = 17,
78	dm_sw_64kb_d_t = 18,
79	dm_sw_SPARE_10 = 19,
80	dm_sw_SPARE_11 = 20,
81	dm_sw_4kb_s_x = 21,
82	dm_sw_4kb_d_x = 22,
83	dm_sw_SPARE_12 = 23,
84	dm_sw_SPARE_13 = 24,
85	dm_sw_64kb_s_x = 25,
86	dm_sw_64kb_d_x = 26,
87	dm_sw_64kb_r_x = 27,
88	dm_sw_SPARE_15 = 28,
89	dm_sw_var_s_x = 29,
90	dm_sw_var_d_x = 30,
91	dm_sw_var_r_x = 31,
92	dm_sw_gfx7_2d_thin_l_vp,
93	dm_sw_gfx7_2d_thin_gl,
94};
95enum lb_depth {
96	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
97	dm_lb_19 = 5
98};
99enum voltage_state {
100	dm_vmin = 0, dm_vmid = 1, dm_vnom = 2, dm_vmax = 3
101};
102enum source_macro_tile_size {
103	dm_4k_tile = 0, dm_64k_tile = 1, dm_256k_tile = 2
104};
105enum cursor_bpp {
106	dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2
107};
108enum clock_change_support {
109	dm_dram_clock_change_uninitialized = 0,
110	dm_dram_clock_change_vactive,
111	dm_dram_clock_change_vblank,
112	dm_dram_clock_change_vactive_w_mall_full_frame,
113	dm_dram_clock_change_vactive_w_mall_sub_vp,
114	dm_dram_clock_change_vblank_w_mall_full_frame,
115	dm_dram_clock_change_vblank_w_mall_sub_vp,
116	dm_dram_clock_change_unsupported
117};
118
119enum output_standard {
120	dm_std_uninitialized = 0,
121	dm_std_cvtr2,
122	dm_std_cvt
123};
124
125enum mpc_combine_affinity {
126	dm_mpc_always_when_possible,
127	dm_mpc_reduce_voltage,
128	dm_mpc_reduce_voltage_and_clocks,
129	dm_mpc_never
130};
131
132enum RequestType {
133	REQ_256Bytes, REQ_128BytesNonContiguous, REQ_128BytesContiguous, REQ_NA
134};
135
136enum self_refresh_affinity {
137	dm_try_to_allow_self_refresh_and_mclk_switch,
138	dm_allow_self_refresh_and_mclk_switch,
139	dm_allow_self_refresh,
140	dm_neither_self_refresh_nor_mclk_switch
141};
142
143enum dm_validation_status {
144	DML_VALIDATION_OK,
145	DML_FAIL_SCALE_RATIO_TAP,
146	DML_FAIL_SOURCE_PIXEL_FORMAT,
147	DML_FAIL_VIEWPORT_SIZE,
148	DML_FAIL_TOTAL_V_ACTIVE_BW,
149	DML_FAIL_DIO_SUPPORT,
150	DML_FAIL_NOT_ENOUGH_DSC,
151	DML_FAIL_DSC_CLK_REQUIRED,
152	DML_FAIL_DSC_VALIDATION_FAILURE,
153	DML_FAIL_URGENT_LATENCY,
154	DML_FAIL_REORDERING_BUFFER,
155	DML_FAIL_DISPCLK_DPPCLK,
156	DML_FAIL_TOTAL_AVAILABLE_PIPES,
157	DML_FAIL_NUM_OTG,
158	DML_FAIL_WRITEBACK_MODE,
159	DML_FAIL_WRITEBACK_LATENCY,
160	DML_FAIL_WRITEBACK_SCALE_RATIO_TAP,
161	DML_FAIL_CURSOR_SUPPORT,
162	DML_FAIL_PITCH_SUPPORT,
163	DML_FAIL_PTE_BUFFER_SIZE,
164	DML_FAIL_HOST_VM_IMMEDIATE_FLIP,
165	DML_FAIL_DSC_INPUT_BPC,
166	DML_FAIL_PREFETCH_SUPPORT,
167	DML_FAIL_V_RATIO_PREFETCH,
168};
169
170enum writeback_config {
171	dm_normal,
172	dm_whole_buffer_for_single_stream_no_interleave,
173	dm_whole_buffer_for_single_stream_interleave,
174};
175
176enum odm_combine_mode {
177	dm_odm_combine_mode_disabled,
178	dm_odm_combine_mode_2to1,
179	dm_odm_combine_mode_4to1,
180	dm_odm_split_mode_1to2,
181	dm_odm_mode_mso_1to2,
182	dm_odm_mode_mso_1to4
183};
184
185enum odm_combine_policy {
186	dm_odm_combine_policy_dal,
187	dm_odm_combine_policy_none,
188	dm_odm_combine_policy_2to1,
189	dm_odm_combine_policy_4to1,
190	dm_odm_split_policy_1to2,
191	dm_odm_mso_policy_1to2,
192	dm_odm_mso_policy_1to4,
193};
194
195enum immediate_flip_requirement {
196	dm_immediate_flip_not_required,
197	dm_immediate_flip_required,
198	dm_immediate_flip_opportunistic,
199};
200
201enum unbounded_requesting_policy {
202	dm_unbounded_requesting,
203	dm_unbounded_requesting_edp_only,
204	dm_unbounded_requesting_disable
205};
206
207enum dm_rotation_angle {
208	dm_rotation_0,
209	dm_rotation_90,
210	dm_rotation_180,
211	dm_rotation_270,
212	dm_rotation_0m,
213	dm_rotation_90m,
214	dm_rotation_180m,
215	dm_rotation_270m,
216};
217
218enum dm_use_mall_for_pstate_change_mode {
219	dm_use_mall_pstate_change_disable,
220	dm_use_mall_pstate_change_full_frame,
221	dm_use_mall_pstate_change_sub_viewport,
222	dm_use_mall_pstate_change_phantom_pipe
223};
224
225enum dm_use_mall_for_static_screen_mode {
226	dm_use_mall_static_screen_disable,
227	dm_use_mall_static_screen_optimize,
228	dm_use_mall_static_screen_enable,
229};
230
231enum dm_output_link_dp_rate {
232	dm_dp_rate_na,
233	dm_dp_rate_hbr,
234	dm_dp_rate_hbr2,
235	dm_dp_rate_hbr3,
236	dm_dp_rate_uhbr10,
237	dm_dp_rate_uhbr13p5,
238	dm_dp_rate_uhbr20,
239};
240
241enum dm_fclock_change_support {
242	dm_fclock_change_vactive,
243	dm_fclock_change_vblank,
244	dm_fclock_change_unsupported,
245};
246
247enum dm_prefetch_modes {
248	dm_prefetch_support_uclk_fclk_and_stutter_if_possible,
249	dm_prefetch_support_uclk_fclk_and_stutter,
250	dm_prefetch_support_fclk_and_stutter,
251	dm_prefetch_support_stutter,
252	dm_prefetch_support_none,
253};
254enum dm_output_type {
255	dm_output_type_unknown,
256	dm_output_type_dp,
257	dm_output_type_edp,
258	dm_output_type_dp2p0,
259	dm_output_type_hdmi,
260	dm_output_type_hdmifrl,
261};
262
263enum dm_output_rate {
264	dm_output_rate_unknown,
265	dm_output_rate_dp_rate_hbr,
266	dm_output_rate_dp_rate_hbr2,
267	dm_output_rate_dp_rate_hbr3,
268	dm_output_rate_dp_rate_uhbr10,
269	dm_output_rate_dp_rate_uhbr13p5,
270	dm_output_rate_dp_rate_uhbr20,
271	dm_output_rate_hdmi_rate_3x3,
272	dm_output_rate_hdmi_rate_6x3,
273	dm_output_rate_hdmi_rate_6x4,
274	dm_output_rate_hdmi_rate_8x4,
275	dm_output_rate_hdmi_rate_10x4,
276	dm_output_rate_hdmi_rate_12x4,
277};
278#endif
279