1254721Semaste/* 2254721Semaste * Copyright 2021 Advanced Micro Devices, Inc. 3254721Semaste * 4254721Semaste * Permission is hereby granted, free of charge, to any person obtaining a 5254721Semaste * copy of this software and associated documentation files (the "Software"), 6254721Semaste * to deal in the Software without restriction, including without limitation 7254721Semaste * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8254721Semaste * and/or sell copies of the Software, and to permit persons to whom the 9254721Semaste * Software is furnished to do so, subject to the following conditions: 10254721Semaste * 11254721Semaste * The above copyright notice and this permission notice shall be included in 12254721Semaste * all copies or substantial portions of the Software. 13254721Semaste * 14254721Semaste * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15254721Semaste * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16254721Semaste * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17254721Semaste * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18254721Semaste * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19254721Semaste * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20254721Semaste * OTHER DEALINGS IN THE SOFTWARE. 21254721Semaste * 22254721Semaste * Authors: AMD 23254721Semaste * 24254721Semaste */ 25254721Semaste 26254721Semaste#ifndef __DC_OPTC_DCN32_H__ 27254721Semaste#define __DC_OPTC_DCN32_H__ 28254721Semaste 29254721Semaste#include "dcn10/dcn10_optc.h" 30254721Semaste 31254721Semaste#define OPTC_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\ 32254721Semaste SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ 33254721Semaste SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ 34254721Semaste SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ 35254721Semaste SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ 36254721Semaste SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ 37254721Semaste SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ 38254721Semaste SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\ 39254721Semaste SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\ 40254721Semaste SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\ 41254721Semaste SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\ 42254721Semaste SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\ 43254721Semaste SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ 44254721Semaste SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\ 45254721Semaste SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\ 46254721Semaste SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ 47254721Semaste SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ 48254721Semaste SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ 49254721Semaste SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ 50254721Semaste SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ 51254721Semaste SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ 52254721Semaste SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ 53254721Semaste SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ 54254721Semaste SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ 55254721Semaste SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ 56254721Semaste SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ 57254721Semaste SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ 58254721Semaste SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ 59254721Semaste SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\ 60254721Semaste SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ 61254721Semaste SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ 62254721Semaste SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ 63254721Semaste SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ 64254721Semaste SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\ 65254721Semaste SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ 66254721Semaste SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ 67254721Semaste SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ 68254721Semaste SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ 69254721Semaste SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ 70254721Semaste SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ 71254721Semaste SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ 72254721Semaste SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ 73254721Semaste SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ 74254721Semaste SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ 75254721Semaste SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ 76254721Semaste SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ 77254721Semaste SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ 78254721Semaste SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ 79254721Semaste SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ 80254721Semaste SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\ 81254721Semaste SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ 82254721Semaste SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ 83254721Semaste SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ 84254721Semaste SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ 85254721Semaste SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ 86254721Semaste SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ 87254721Semaste SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ 88254721Semaste SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ 89254721Semaste SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ 90254721Semaste SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ 91254721Semaste SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ 92254721Semaste SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ 93254721Semaste SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ 94254721Semaste SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ 95254721Semaste SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ 96254721Semaste SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ 97254721Semaste SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ 98254721Semaste SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ 99254721Semaste SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ 100254721Semaste SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ 101254721Semaste SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\ 102254721Semaste SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\ 103254721Semaste SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ 104254721Semaste SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ 105254721Semaste SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ 106254721Semaste SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ 107254721Semaste SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ 108254721Semaste SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ 109254721Semaste SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ 110254721Semaste SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ 111254721Semaste SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ 112254721Semaste SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ 113254721Semaste SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ 114254721Semaste SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ 115254721Semaste SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ 116254721Semaste SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ 117254721Semaste SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ 118254721Semaste SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ 119254721Semaste SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ 120254721Semaste SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ 121254721Semaste SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ 122254721Semaste SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ 123254721Semaste SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ 124254721Semaste SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ 125254721Semaste SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ 126254721Semaste SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ 127254721Semaste SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ 128254721Semaste SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ 129254721Semaste SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ 130254721Semaste SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ 131254721Semaste SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ 132254721Semaste SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ 133254721Semaste SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ 134254721Semaste SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ 135254721Semaste SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ 136254721Semaste SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ 137254721Semaste SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ 138254721Semaste SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ 139254721Semaste SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ 140254721Semaste SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ 141254721Semaste SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ 142254721Semaste SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ 143254721Semaste SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ 144254721Semaste SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ 145254721Semaste SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ 146254721Semaste SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ 147254721Semaste SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ 148254721Semaste SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ 149254721Semaste SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\ 150254721Semaste SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ 151254721Semaste SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ 152254721Semaste SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ 153254721Semaste SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ 154254721Semaste SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\ 155254721Semaste SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ 156254721Semaste SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ 157254721Semaste SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ 158254721Semaste SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \ 159254721Semaste SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \ 160254721Semaste SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \ 161 SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\ 162 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\ 163 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\ 164 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\ 165 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\ 166 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\ 167 SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\ 168 SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\ 169 SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\ 170 SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\ 171 SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\ 172 SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\ 173 SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\ 174 SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\ 175 SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ 176 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ 177 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\ 178 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ 179 SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) 180 181void dcn32_timing_generator_init(struct optc *optc1); 182void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode); 183 184#endif /* __DC_OPTC_DCN32_H__ */ 185