dcn314_resource.c revision 1.5
1// SPDX-License-Identifier: MIT 2/* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28#include "dm_services.h" 29#include "dc.h" 30 31#include "dcn31/dcn31_init.h" 32#include "dcn314/dcn314_init.h" 33 34#include "resource.h" 35#include "include/irq_service_interface.h" 36#include "dcn314_resource.h" 37 38#include "dcn20/dcn20_resource.h" 39#include "dcn30/dcn30_resource.h" 40#include "dcn31/dcn31_resource.h" 41 42#include "dcn10/dcn10_ipp.h" 43#include "dcn30/dcn30_hubbub.h" 44#include "dcn31/dcn31_hubbub.h" 45#include "dcn30/dcn30_mpc.h" 46#include "dcn31/dcn31_hubp.h" 47#include "irq/dcn31/irq_service_dcn31.h" 48#include "irq/dcn314/irq_service_dcn314.h" 49#include "dcn30/dcn30_dpp.h" 50#include "dcn314/dcn314_optc.h" 51#include "dcn20/dcn20_hwseq.h" 52#include "dcn30/dcn30_hwseq.h" 53#include "dce110/dce110_hw_sequencer.h" 54#include "dcn30/dcn30_opp.h" 55#include "dcn20/dcn20_dsc.h" 56#include "dcn30/dcn30_vpg.h" 57#include "dcn30/dcn30_afmt.h" 58#include "dcn31/dcn31_dio_link_encoder.h" 59#include "dcn314/dcn314_dio_stream_encoder.h" 60#include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61#include "dcn31/dcn31_hpo_dp_link_encoder.h" 62#include "dcn31/dcn31_apg.h" 63#include "dcn31/dcn31_vpg.h" 64#include "dcn31/dcn31_afmt.h" 65#include "dce/dce_clock_source.h" 66#include "dce/dce_audio.h" 67#include "dce/dce_hwseq.h" 68#include "clk_mgr.h" 69#include "virtual/virtual_stream_encoder.h" 70#include "dce110/dce110_resource.h" 71#include "dml/display_mode_vba.h" 72#include "dml/dcn31/dcn31_fpu.h" 73#include "dml/dcn314/dcn314_fpu.h" 74#include "dcn314/dcn314_dccg.h" 75#include "dcn10/dcn10_resource.h" 76#include "dcn31/dcn31_panel_cntl.h" 77#include "dcn314/dcn314_hwseq.h" 78 79#include "dcn30/dcn30_dwb.h" 80#include "dcn30/dcn30_mmhubbub.h" 81 82#include "dcn/dcn_3_1_4_offset.h" 83#include "dcn/dcn_3_1_4_sh_mask.h" 84#include "dpcs/dpcs_3_1_4_offset.h" 85#include "dpcs/dpcs_3_1_4_sh_mask.h" 86 87#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 88#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 89 90#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 91#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL 92 93#include "reg_helper.h" 94#include "dce/dmub_abm.h" 95#include "dce/dmub_psr.h" 96#include "dce/dce_aux.h" 97#include "dce/dce_i2c.h" 98#include "dml/dcn314/display_mode_vba_314.h" 99#include "vm_helper.h" 100#include "dcn20/dcn20_vmid.h" 101 102#include "link_enc_cfg.h" 103 104#define DCN_BASE__INST0_SEG1 0x000000C0 105#define DCN_BASE__INST0_SEG2 0x000034C0 106#define DCN_BASE__INST0_SEG3 0x00009000 107 108#define NBIO_BASE__INST0_SEG1 0x00000014 109 110#define MAX_INSTANCE 7 111#define MAX_SEGMENT 8 112 113#define regBIF_BX2_BIOS_SCRATCH_2 0x003a 114#define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 115#define regBIF_BX2_BIOS_SCRATCH_3 0x003b 116#define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 117#define regBIF_BX2_BIOS_SCRATCH_6 0x003e 118#define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 119 120struct IP_BASE_INSTANCE { 121 unsigned int segment[MAX_SEGMENT]; 122}; 123 124struct IP_BASE { 125 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 126}; 127 128static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0, 0, 0, 0 } } } }; 135 136 137#define DC_LOGGER_INIT(logger) 138 139enum dcn31_clk_src_array_id { 140 DCN31_CLK_SRC_PLL0, 141 DCN31_CLK_SRC_PLL1, 142 DCN31_CLK_SRC_PLL2, 143 DCN31_CLK_SRC_PLL3, 144 DCN31_CLK_SRC_PLL4, 145 DCN30_CLK_SRC_TOTAL 146}; 147 148/* begin ********************* 149 * macros to expend register list macro defined in HW object header file 150 */ 151 152/* DCN */ 153/* TODO awful hack. fixup dcn20_dwb.h */ 154#undef BASE_INNER 155#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 156 157#define BASE(seg) BASE_INNER(seg) 158 159#define SR(reg_name)\ 160 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 161 reg ## reg_name 162 163#define SRI(reg_name, block, id)\ 164 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## reg_name 166 167#define SRI2(reg_name, block, id)\ 168 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 169 reg ## reg_name 170 171#define SRIR(var_name, reg_name, block, id)\ 172 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 173 reg ## block ## id ## _ ## reg_name 174 175#define SRII(reg_name, block, id)\ 176 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 reg ## block ## id ## _ ## reg_name 178 179#define SRII_MPC_RMU(reg_name, block, id)\ 180 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 181 reg ## block ## id ## _ ## reg_name 182 183#define SRII_DWB(reg_name, temp_name, block, id)\ 184 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 185 reg ## block ## id ## _ ## temp_name 186 187#define DCCG_SRII(reg_name, block, id)\ 188 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 189 reg ## block ## id ## _ ## reg_name 190 191#define VUPDATE_SRII(reg_name, block, id)\ 192 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 193 reg ## reg_name ## _ ## block ## id 194 195/* NBIO */ 196#define NBIO_BASE_INNER(seg) \ 197 NBIO_BASE__INST0_SEG ## seg 198 199#define NBIO_BASE(seg) \ 200 NBIO_BASE_INNER(seg) 201 202#define NBIO_SR(reg_name)\ 203 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 204 regBIF_BX2_ ## reg_name 205 206/* MMHUB */ 207#define MMHUB_BASE_INNER(seg) \ 208 MMHUB_BASE__INST0_SEG ## seg 209 210#define MMHUB_BASE(seg) \ 211 MMHUB_BASE_INNER(seg) 212 213#define MMHUB_SR(reg_name)\ 214 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \ 215 reg ## reg_name 216 217/* CLOCK */ 218#define CLK_BASE_INNER(seg) \ 219 CLK_BASE__INST0_SEG ## seg 220 221#define CLK_BASE(seg) \ 222 CLK_BASE_INNER(seg) 223 224#define CLK_SRI(reg_name, block, inst)\ 225 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 226 reg ## block ## _ ## inst ## _ ## reg_name 227 228 229static const struct bios_registers bios_regs = { 230 NBIO_SR(BIOS_SCRATCH_3), 231 NBIO_SR(BIOS_SCRATCH_6) 232}; 233 234#define clk_src_regs(index, pllid)\ 235[index] = {\ 236 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 237} 238 239static const struct dce110_clk_src_regs clk_src_regs[] = { 240 clk_src_regs(0, A), 241 clk_src_regs(1, B), 242 clk_src_regs(2, C), 243 clk_src_regs(3, D), 244 clk_src_regs(4, E) 245}; 246 247static const struct dce110_clk_src_shift cs_shift = { 248 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 249}; 250 251static const struct dce110_clk_src_mask cs_mask = { 252 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 253}; 254 255#define abm_regs(id)\ 256[id] = {\ 257 ABM_DCN302_REG_LIST(id)\ 258} 259 260static const struct dce_abm_registers abm_regs[] = { 261 abm_regs(0), 262 abm_regs(1), 263 abm_regs(2), 264 abm_regs(3), 265}; 266 267static const struct dce_abm_shift abm_shift = { 268 ABM_MASK_SH_LIST_DCN30(__SHIFT) 269}; 270 271static const struct dce_abm_mask abm_mask = { 272 ABM_MASK_SH_LIST_DCN30(_MASK) 273}; 274 275#define audio_regs(id)\ 276[id] = {\ 277 AUD_COMMON_REG_LIST(id)\ 278} 279 280static const struct dce_audio_registers audio_regs[] = { 281 audio_regs(0), 282 audio_regs(1), 283 audio_regs(2), 284 audio_regs(3), 285 audio_regs(4), 286 audio_regs(5), 287 audio_regs(6) 288}; 289 290#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 291 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 292 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 293 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 294 295static const struct dce_audio_shift audio_shift = { 296 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 297}; 298 299static const struct dce_audio_mask audio_mask = { 300 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 301}; 302 303#define vpg_regs(id)\ 304[id] = {\ 305 VPG_DCN31_REG_LIST(id)\ 306} 307 308static const struct dcn31_vpg_registers vpg_regs[] = { 309 vpg_regs(0), 310 vpg_regs(1), 311 vpg_regs(2), 312 vpg_regs(3), 313 vpg_regs(4), 314 vpg_regs(5), 315 vpg_regs(6), 316 vpg_regs(7), 317 vpg_regs(8), 318 vpg_regs(9), 319}; 320 321static const struct dcn31_vpg_shift vpg_shift = { 322 DCN31_VPG_MASK_SH_LIST(__SHIFT) 323}; 324 325static const struct dcn31_vpg_mask vpg_mask = { 326 DCN31_VPG_MASK_SH_LIST(_MASK) 327}; 328 329#define afmt_regs(id)\ 330[id] = {\ 331 AFMT_DCN31_REG_LIST(id)\ 332} 333 334static const struct dcn31_afmt_registers afmt_regs[] = { 335 afmt_regs(0), 336 afmt_regs(1), 337 afmt_regs(2), 338 afmt_regs(3), 339 afmt_regs(4), 340 afmt_regs(5) 341}; 342 343static const struct dcn31_afmt_shift afmt_shift = { 344 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 345}; 346 347static const struct dcn31_afmt_mask afmt_mask = { 348 DCN31_AFMT_MASK_SH_LIST(_MASK) 349}; 350 351#define apg_regs(id)\ 352[id] = {\ 353 APG_DCN31_REG_LIST(id)\ 354} 355 356static const struct dcn31_apg_registers apg_regs[] = { 357 apg_regs(0), 358 apg_regs(1), 359 apg_regs(2), 360 apg_regs(3) 361}; 362 363static const struct dcn31_apg_shift apg_shift = { 364 DCN31_APG_MASK_SH_LIST(__SHIFT) 365}; 366 367static const struct dcn31_apg_mask apg_mask = { 368 DCN31_APG_MASK_SH_LIST(_MASK) 369}; 370 371#define stream_enc_regs(id)\ 372[id] = {\ 373 SE_DCN314_REG_LIST(id)\ 374} 375 376static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 377 stream_enc_regs(0), 378 stream_enc_regs(1), 379 stream_enc_regs(2), 380 stream_enc_regs(3), 381 stream_enc_regs(4) 382}; 383 384static const struct dcn10_stream_encoder_shift se_shift = { 385 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT) 386}; 387 388static const struct dcn10_stream_encoder_mask se_mask = { 389 SE_COMMON_MASK_SH_LIST_DCN314(_MASK) 390}; 391 392 393#define aux_regs(id)\ 394[id] = {\ 395 DCN2_AUX_REG_LIST(id)\ 396} 397 398static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 399 aux_regs(0), 400 aux_regs(1), 401 aux_regs(2), 402 aux_regs(3), 403 aux_regs(4) 404}; 405 406#define hpd_regs(id)\ 407[id] = {\ 408 HPD_REG_LIST(id)\ 409} 410 411static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 412 hpd_regs(0), 413 hpd_regs(1), 414 hpd_regs(2), 415 hpd_regs(3), 416 hpd_regs(4) 417}; 418 419#define link_regs(id, phyid)\ 420[id] = {\ 421 LE_DCN31_REG_LIST(id), \ 422 UNIPHY_DCN2_REG_LIST(phyid), \ 423} 424 425static const struct dce110_aux_registers_shift aux_shift = { 426 DCN_AUX_MASK_SH_LIST(__SHIFT) 427}; 428 429static const struct dce110_aux_registers_mask aux_mask = { 430 DCN_AUX_MASK_SH_LIST(_MASK) 431}; 432 433static const struct dcn10_link_enc_registers link_enc_regs[] = { 434 link_regs(0, A), 435 link_regs(1, B), 436 link_regs(2, C), 437 link_regs(3, D), 438 link_regs(4, E) 439}; 440 441static const struct dcn10_link_enc_shift le_shift = { 442 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), 443 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 444}; 445 446static const struct dcn10_link_enc_mask le_mask = { 447 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), 448 DPCS_DCN31_MASK_SH_LIST(_MASK) 449}; 450 451#define hpo_dp_stream_encoder_reg_list(id)\ 452[id] = {\ 453 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 454} 455 456static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 457 hpo_dp_stream_encoder_reg_list(0), 458 hpo_dp_stream_encoder_reg_list(1), 459 hpo_dp_stream_encoder_reg_list(2), 460 hpo_dp_stream_encoder_reg_list(3) 461}; 462 463static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 464 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 465}; 466 467static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 468 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 469}; 470 471 472#define hpo_dp_link_encoder_reg_list(id)\ 473[id] = {\ 474 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 475 DCN3_1_RDPCSTX_REG_LIST(0),\ 476 DCN3_1_RDPCSTX_REG_LIST(1),\ 477 DCN3_1_RDPCSTX_REG_LIST(2),\ 478} 479 480static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 481 hpo_dp_link_encoder_reg_list(0), 482 hpo_dp_link_encoder_reg_list(1), 483}; 484 485static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 486 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 487}; 488 489static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 490 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 491}; 492 493#define dpp_regs(id)\ 494[id] = {\ 495 DPP_REG_LIST_DCN30(id),\ 496} 497 498static const struct dcn3_dpp_registers dpp_regs[] = { 499 dpp_regs(0), 500 dpp_regs(1), 501 dpp_regs(2), 502 dpp_regs(3) 503}; 504 505static const struct dcn3_dpp_shift tf_shift = { 506 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 507}; 508 509static const struct dcn3_dpp_mask tf_mask = { 510 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 511}; 512 513#define opp_regs(id)\ 514[id] = {\ 515 OPP_REG_LIST_DCN30(id),\ 516} 517 518static const struct dcn20_opp_registers opp_regs[] = { 519 opp_regs(0), 520 opp_regs(1), 521 opp_regs(2), 522 opp_regs(3) 523}; 524 525static const struct dcn20_opp_shift opp_shift = { 526 OPP_MASK_SH_LIST_DCN20(__SHIFT) 527}; 528 529static const struct dcn20_opp_mask opp_mask = { 530 OPP_MASK_SH_LIST_DCN20(_MASK) 531}; 532 533#define aux_engine_regs(id)\ 534[id] = {\ 535 AUX_COMMON_REG_LIST0(id), \ 536 .AUXN_IMPCAL = 0, \ 537 .AUXP_IMPCAL = 0, \ 538 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 539} 540 541static const struct dce110_aux_registers aux_engine_regs[] = { 542 aux_engine_regs(0), 543 aux_engine_regs(1), 544 aux_engine_regs(2), 545 aux_engine_regs(3), 546 aux_engine_regs(4) 547}; 548 549#define dwbc_regs_dcn3(id)\ 550[id] = {\ 551 DWBC_COMMON_REG_LIST_DCN30(id),\ 552} 553 554static const struct dcn30_dwbc_registers dwbc30_regs[] = { 555 dwbc_regs_dcn3(0), 556}; 557 558static const struct dcn30_dwbc_shift dwbc30_shift = { 559 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 560}; 561 562static const struct dcn30_dwbc_mask dwbc30_mask = { 563 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 564}; 565 566#define mcif_wb_regs_dcn3(id)\ 567[id] = {\ 568 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 569} 570 571static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 572 mcif_wb_regs_dcn3(0) 573}; 574 575static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 576 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 577}; 578 579static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 580 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 581}; 582 583#define dsc_regsDCN314(id)\ 584[id] = {\ 585 DSC_REG_LIST_DCN20(id)\ 586} 587 588static const struct dcn20_dsc_registers dsc_regs[] = { 589 dsc_regsDCN314(0), 590 dsc_regsDCN314(1), 591 dsc_regsDCN314(2), 592 dsc_regsDCN314(3) 593}; 594 595static const struct dcn20_dsc_shift dsc_shift = { 596 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 597}; 598 599static const struct dcn20_dsc_mask dsc_mask = { 600 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 601}; 602 603static const struct dcn30_mpc_registers mpc_regs = { 604 MPC_REG_LIST_DCN3_0(0), 605 MPC_REG_LIST_DCN3_0(1), 606 MPC_REG_LIST_DCN3_0(2), 607 MPC_REG_LIST_DCN3_0(3), 608 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 609 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 610 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 611 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 612 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 613 MPC_RMU_REG_LIST_DCN3AG(0), 614 MPC_RMU_REG_LIST_DCN3AG(1), 615 //MPC_RMU_REG_LIST_DCN3AG(2), 616 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 617}; 618 619static const struct dcn30_mpc_shift mpc_shift = { 620 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 621}; 622 623static const struct dcn30_mpc_mask mpc_mask = { 624 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 625}; 626 627#define optc_regs(id)\ 628[id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)} 629 630static const struct dcn_optc_registers optc_regs[] = { 631 optc_regs(0), 632 optc_regs(1), 633 optc_regs(2), 634 optc_regs(3) 635}; 636 637static const struct dcn_optc_shift optc_shift = { 638 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT) 639}; 640 641static const struct dcn_optc_mask optc_mask = { 642 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK) 643}; 644 645#define hubp_regs(id)\ 646[id] = {\ 647 HUBP_REG_LIST_DCN30(id)\ 648} 649 650static const struct dcn_hubp2_registers hubp_regs[] = { 651 hubp_regs(0), 652 hubp_regs(1), 653 hubp_regs(2), 654 hubp_regs(3) 655}; 656 657 658static const struct dcn_hubp2_shift hubp_shift = { 659 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 660}; 661 662static const struct dcn_hubp2_mask hubp_mask = { 663 HUBP_MASK_SH_LIST_DCN31(_MASK) 664}; 665static const struct dcn_hubbub_registers hubbub_reg = { 666 HUBBUB_REG_LIST_DCN31(0) 667}; 668 669static const struct dcn_hubbub_shift hubbub_shift = { 670 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 671}; 672 673static const struct dcn_hubbub_mask hubbub_mask = { 674 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 675}; 676 677static const struct dccg_registers dccg_regs = { 678 DCCG_REG_LIST_DCN314() 679}; 680 681static const struct dccg_shift dccg_shift = { 682 DCCG_MASK_SH_LIST_DCN314(__SHIFT) 683}; 684 685static const struct dccg_mask dccg_mask = { 686 DCCG_MASK_SH_LIST_DCN314(_MASK) 687}; 688 689 690#define SRII2(reg_name_pre, reg_name_post, id)\ 691 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 692 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 693 reg ## reg_name_pre ## id ## _ ## reg_name_post 694 695 696#define HWSEQ_DCN31_REG_LIST()\ 697 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 698 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 699 SR(DIO_MEM_PWR_CTRL), \ 700 SR(ODM_MEM_PWR_CTRL3), \ 701 SR(DMU_MEM_PWR_CNTL), \ 702 SR(MMHUBBUB_MEM_PWR_CNTL), \ 703 SR(DCCG_GATE_DISABLE_CNTL), \ 704 SR(DCCG_GATE_DISABLE_CNTL2), \ 705 SR(DCFCLK_CNTL),\ 706 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 707 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 708 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 709 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 710 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 711 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 712 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 713 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 714 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 715 SR(MICROSECOND_TIME_BASE_DIV), \ 716 SR(MILLISECOND_TIME_BASE_DIV), \ 717 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 718 SR(RBBMIF_TIMEOUT_DIS), \ 719 SR(RBBMIF_TIMEOUT_DIS_2), \ 720 SR(DCHUBBUB_CRC_CTRL), \ 721 SR(DPP_TOP0_DPP_CRC_CTRL), \ 722 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 723 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 724 SR(MPC_CRC_CTRL), \ 725 SR(MPC_CRC_RESULT_GB), \ 726 SR(MPC_CRC_RESULT_C), \ 727 SR(MPC_CRC_RESULT_AR), \ 728 SR(DOMAIN0_PG_CONFIG), \ 729 SR(DOMAIN1_PG_CONFIG), \ 730 SR(DOMAIN2_PG_CONFIG), \ 731 SR(DOMAIN3_PG_CONFIG), \ 732 SR(DOMAIN16_PG_CONFIG), \ 733 SR(DOMAIN17_PG_CONFIG), \ 734 SR(DOMAIN18_PG_CONFIG), \ 735 SR(DOMAIN19_PG_CONFIG), \ 736 SR(DOMAIN0_PG_STATUS), \ 737 SR(DOMAIN1_PG_STATUS), \ 738 SR(DOMAIN2_PG_STATUS), \ 739 SR(DOMAIN3_PG_STATUS), \ 740 SR(DOMAIN16_PG_STATUS), \ 741 SR(DOMAIN17_PG_STATUS), \ 742 SR(DOMAIN18_PG_STATUS), \ 743 SR(DOMAIN19_PG_STATUS), \ 744 SR(D1VGA_CONTROL), \ 745 SR(D2VGA_CONTROL), \ 746 SR(D3VGA_CONTROL), \ 747 SR(D4VGA_CONTROL), \ 748 SR(D5VGA_CONTROL), \ 749 SR(D6VGA_CONTROL), \ 750 SR(DC_IP_REQUEST_CNTL), \ 751 SR(AZALIA_AUDIO_DTO), \ 752 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 753 SR(HPO_TOP_HW_CONTROL) 754 755static const struct dce_hwseq_registers hwseq_reg = { 756 HWSEQ_DCN31_REG_LIST() 757}; 758 759#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 760 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 761 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 762 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 763 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 764 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 765 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 766 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 767 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 768 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 769 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 770 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 771 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 772 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 773 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 774 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 775 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 776 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 777 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 778 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 779 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 780 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 781 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 782 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 783 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 784 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 785 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 786 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 787 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 788 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 789 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 790 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 791 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 792 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 793 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 794 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 795 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 796 797static const struct dce_hwseq_shift hwseq_shift = { 798 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 799}; 800 801static const struct dce_hwseq_mask hwseq_mask = { 802 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 803}; 804#define vmid_regs(id)\ 805[id] = {\ 806 DCN20_VMID_REG_LIST(id)\ 807} 808 809static const struct dcn_vmid_registers vmid_regs[] = { 810 vmid_regs(0), 811 vmid_regs(1), 812 vmid_regs(2), 813 vmid_regs(3), 814 vmid_regs(4), 815 vmid_regs(5), 816 vmid_regs(6), 817 vmid_regs(7), 818 vmid_regs(8), 819 vmid_regs(9), 820 vmid_regs(10), 821 vmid_regs(11), 822 vmid_regs(12), 823 vmid_regs(13), 824 vmid_regs(14), 825 vmid_regs(15) 826}; 827 828static const struct dcn20_vmid_shift vmid_shifts = { 829 DCN20_VMID_MASK_SH_LIST(__SHIFT) 830}; 831 832static const struct dcn20_vmid_mask vmid_masks = { 833 DCN20_VMID_MASK_SH_LIST(_MASK) 834}; 835 836static const struct resource_caps res_cap_dcn314 = { 837 .num_timing_generator = 4, 838 .num_opp = 4, 839 .num_video_plane = 4, 840 .num_audio = 5, 841 .num_stream_encoder = 5, 842 .num_dig_link_enc = 5, 843 .num_hpo_dp_stream_encoder = 4, 844 .num_hpo_dp_link_encoder = 2, 845 .num_pll = 5, 846 .num_dwb = 1, 847 .num_ddc = 5, 848 .num_vmid = 16, 849 .num_mpc_3dlut = 2, 850 .num_dsc = 4, 851}; 852 853static const struct dc_plane_cap plane_cap = { 854 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 855 .blends_with_above = true, 856 .blends_with_below = true, 857 .per_pixel_alpha = true, 858 859 .pixel_format_support = { 860 .argb8888 = true, 861 .nv12 = true, 862 .fp16 = true, 863 .p010 = true, 864 .ayuv = false, 865 }, 866 867 .max_upscale_factor = { 868 .argb8888 = 16000, 869 .nv12 = 16000, 870 .fp16 = 16000 871 }, 872 873 // 6:1 downscaling ratio: 1000/6 = 166.666 874 // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250 875 .max_downscale_factor = { 876 .argb8888 = 250, 877 .nv12 = 167, 878 .fp16 = 167 879 }, 880 64, 881 64 882}; 883 884static const struct dc_debug_options debug_defaults_drv = { 885 .disable_z10 = false, 886 .enable_z9_disable_interface = true, 887 .disable_dmcu = true, 888 .force_abm_enable = false, 889 .timing_trace = false, 890 .clock_trace = true, 891 .disable_dpp_power_gate = true, 892 .disable_hubp_power_gate = true, 893 .disable_pplib_clock_request = false, 894 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 895 .force_single_disp_pipe_split = false, 896 .disable_dcc = DCC_ENABLE, 897 .vsr_support = true, 898 .performance_trace = false, 899 .max_downscale_src_width = 4096,/*upto true 4k*/ 900 .disable_pplib_wm_range = false, 901 .scl_reset_length10 = true, 902 .sanity_checks = true, 903 .underflow_assert_delay_us = 0xFFFFFFFF, 904 .dwb_fi_phase = -1, // -1 = disable, 905 .dmub_command_table = true, 906 .pstate_enabled = true, 907 .use_max_lb = true, 908 .enable_mem_low_power = { 909 .bits = { 910 .vga = true, 911 .i2c = true, 912 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 913 .dscl = true, 914 .cm = true, 915 .mpc = true, 916 .optc = true, 917 .vpg = true, 918 .afmt = true, 919 } 920 }, 921 .seamless_boot_odm_combine = true 922}; 923 924static const struct dc_debug_options debug_defaults_diags = { 925 .disable_dmcu = true, 926 .force_abm_enable = false, 927 .timing_trace = true, 928 .clock_trace = true, 929 .disable_dpp_power_gate = true, 930 .disable_hubp_power_gate = true, 931 .disable_clock_gate = true, 932 .disable_pplib_clock_request = true, 933 .disable_pplib_wm_range = true, 934 .disable_stutter = false, 935 .scl_reset_length10 = true, 936 .dwb_fi_phase = -1, // -1 = disable 937 .dmub_command_table = true, 938 .enable_tri_buf = true, 939 .use_max_lb = true 940}; 941 942static const struct dc_panel_config panel_config_defaults = { 943 .ilr = { 944 .optimize_edp_link_rate = true, 945 }, 946}; 947 948static void dcn31_dpp_destroy(struct dpp **dpp) 949{ 950 kfree(TO_DCN20_DPP(*dpp)); 951 *dpp = NULL; 952} 953 954static struct dpp *dcn31_dpp_create( 955 struct dc_context *ctx, 956 uint32_t inst) 957{ 958 struct dcn3_dpp *dpp = 959 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 960 961 if (!dpp) 962 return NULL; 963 964 if (dpp3_construct(dpp, ctx, inst, 965 &dpp_regs[inst], &tf_shift, &tf_mask)) 966 return &dpp->base; 967 968 BREAK_TO_DEBUGGER(); 969 kfree(dpp); 970 return NULL; 971} 972 973static struct output_pixel_processor *dcn31_opp_create( 974 struct dc_context *ctx, uint32_t inst) 975{ 976 struct dcn20_opp *opp = 977 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 978 979 if (!opp) { 980 BREAK_TO_DEBUGGER(); 981 return NULL; 982 } 983 984 dcn20_opp_construct(opp, ctx, inst, 985 &opp_regs[inst], &opp_shift, &opp_mask); 986 return &opp->base; 987} 988 989static struct dce_aux *dcn31_aux_engine_create( 990 struct dc_context *ctx, 991 uint32_t inst) 992{ 993 struct aux_engine_dce110 *aux_engine = 994 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 995 996 if (!aux_engine) 997 return NULL; 998 999 dce110_aux_engine_construct(aux_engine, ctx, inst, 1000 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1001 &aux_engine_regs[inst], 1002 &aux_mask, 1003 &aux_shift, 1004 ctx->dc->caps.extended_aux_timeout_support); 1005 1006 return &aux_engine->base; 1007} 1008#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1009 1010static const struct dce_i2c_registers i2c_hw_regs[] = { 1011 i2c_inst_regs(1), 1012 i2c_inst_regs(2), 1013 i2c_inst_regs(3), 1014 i2c_inst_regs(4), 1015 i2c_inst_regs(5), 1016}; 1017 1018static const struct dce_i2c_shift i2c_shifts = { 1019 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1020}; 1021 1022static const struct dce_i2c_mask i2c_masks = { 1023 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1024}; 1025 1026static struct dce_i2c_hw *dcn31_i2c_hw_create( 1027 struct dc_context *ctx, 1028 uint32_t inst) 1029{ 1030 struct dce_i2c_hw *dce_i2c_hw = 1031 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1032 1033 if (!dce_i2c_hw) 1034 return NULL; 1035 1036 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1037 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1038 1039 return dce_i2c_hw; 1040} 1041static struct mpc *dcn31_mpc_create( 1042 struct dc_context *ctx, 1043 int num_mpcc, 1044 int num_rmu) 1045{ 1046 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1047 GFP_KERNEL); 1048 1049 if (!mpc30) 1050 return NULL; 1051 1052 dcn30_mpc_construct(mpc30, ctx, 1053 &mpc_regs, 1054 &mpc_shift, 1055 &mpc_mask, 1056 num_mpcc, 1057 num_rmu); 1058 1059 return &mpc30->base; 1060} 1061 1062static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1063{ 1064 int i; 1065 1066 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1067 GFP_KERNEL); 1068 1069 if (!hubbub3) 1070 return NULL; 1071 1072 hubbub31_construct(hubbub3, ctx, 1073 &hubbub_reg, 1074 &hubbub_shift, 1075 &hubbub_mask, 1076 dcn3_14_ip.det_buffer_size_kbytes, 1077 dcn3_14_ip.pixel_chunk_size_kbytes, 1078 dcn3_14_ip.config_return_buffer_size_in_kbytes); 1079 1080 1081 for (i = 0; i < res_cap_dcn314.num_vmid; i++) { 1082 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1083 1084 vmid->ctx = ctx; 1085 1086 vmid->regs = &vmid_regs[i]; 1087 vmid->shifts = &vmid_shifts; 1088 vmid->masks = &vmid_masks; 1089 } 1090 1091 return &hubbub3->base; 1092} 1093 1094static struct timing_generator *dcn31_timing_generator_create( 1095 struct dc_context *ctx, 1096 uint32_t instance) 1097{ 1098 struct optc *tgn10 = 1099 kzalloc(sizeof(struct optc), GFP_KERNEL); 1100 1101 if (!tgn10) 1102 return NULL; 1103 1104 tgn10->base.inst = instance; 1105 tgn10->base.ctx = ctx; 1106 1107 tgn10->tg_regs = &optc_regs[instance]; 1108 tgn10->tg_shift = &optc_shift; 1109 tgn10->tg_mask = &optc_mask; 1110 1111 dcn314_timing_generator_init(tgn10); 1112 1113 return &tgn10->base; 1114} 1115 1116static const struct encoder_feature_support link_enc_feature = { 1117 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1118 .max_hdmi_pixel_clock = 600000, 1119 .hdmi_ycbcr420_supported = true, 1120 .dp_ycbcr420_supported = true, 1121 .fec_supported = true, 1122 .flags.bits.IS_HBR2_CAPABLE = true, 1123 .flags.bits.IS_HBR3_CAPABLE = true, 1124 .flags.bits.IS_TPS3_CAPABLE = true, 1125 .flags.bits.IS_TPS4_CAPABLE = true 1126}; 1127 1128static struct link_encoder *dcn31_link_encoder_create( 1129 struct dc_context *ctx, 1130 const struct encoder_init_data *enc_init_data) 1131{ 1132 struct dcn20_link_encoder *enc20 = 1133 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1134 1135 if (!enc20) 1136 return NULL; 1137 1138 dcn31_link_encoder_construct(enc20, 1139 enc_init_data, 1140 &link_enc_feature, 1141 &link_enc_regs[enc_init_data->transmitter], 1142 &link_enc_aux_regs[enc_init_data->channel - 1], 1143 &link_enc_hpd_regs[enc_init_data->hpd_source], 1144 &le_shift, 1145 &le_mask); 1146 1147 return &enc20->enc10.base; 1148} 1149 1150/* Create a minimal link encoder object not associated with a particular 1151 * physical connector. 1152 * resource_funcs.link_enc_create_minimal 1153 */ 1154static struct link_encoder *dcn31_link_enc_create_minimal( 1155 struct dc_context *ctx, enum engine_id eng_id) 1156{ 1157 struct dcn20_link_encoder *enc20; 1158 1159 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1160 return NULL; 1161 1162 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1163 if (!enc20) 1164 return NULL; 1165 1166 dcn31_link_encoder_construct_minimal( 1167 enc20, 1168 ctx, 1169 &link_enc_feature, 1170 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1171 eng_id); 1172 1173 return &enc20->enc10.base; 1174} 1175 1176static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1177{ 1178 struct dcn31_panel_cntl *panel_cntl = 1179 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1180 1181 if (!panel_cntl) 1182 return NULL; 1183 1184 dcn31_panel_cntl_construct(panel_cntl, init_data); 1185 1186 return &panel_cntl->base; 1187} 1188 1189static void read_dce_straps( 1190 struct dc_context *ctx, 1191 struct resource_straps *straps) 1192{ 1193 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1194 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1195 1196} 1197 1198static struct audio *dcn31_create_audio( 1199 struct dc_context *ctx, unsigned int inst) 1200{ 1201 return dce_audio_create(ctx, inst, 1202 &audio_regs[inst], &audio_shift, &audio_mask); 1203} 1204 1205static struct vpg *dcn31_vpg_create( 1206 struct dc_context *ctx, 1207 uint32_t inst) 1208{ 1209 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1210 1211 if (!vpg31) 1212 return NULL; 1213 1214 vpg31_construct(vpg31, ctx, inst, 1215 &vpg_regs[inst], 1216 &vpg_shift, 1217 &vpg_mask); 1218 1219 return &vpg31->base; 1220} 1221 1222static struct afmt *dcn31_afmt_create( 1223 struct dc_context *ctx, 1224 uint32_t inst) 1225{ 1226 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1227 1228 if (!afmt31) 1229 return NULL; 1230 1231 afmt31_construct(afmt31, ctx, inst, 1232 &afmt_regs[inst], 1233 &afmt_shift, 1234 &afmt_mask); 1235 1236 // Light sleep by default, no need to power down here 1237 1238 return &afmt31->base; 1239} 1240 1241static struct apg *dcn31_apg_create( 1242 struct dc_context *ctx, 1243 uint32_t inst) 1244{ 1245 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1246 1247 if (!apg31) 1248 return NULL; 1249 1250 apg31_construct(apg31, ctx, inst, 1251 &apg_regs[inst], 1252 &apg_shift, 1253 &apg_mask); 1254 1255 return &apg31->base; 1256} 1257 1258static struct stream_encoder *dcn314_stream_encoder_create( 1259 enum engine_id eng_id, 1260 struct dc_context *ctx) 1261{ 1262 struct dcn10_stream_encoder *enc1; 1263 struct vpg *vpg; 1264 struct afmt *afmt; 1265 int vpg_inst; 1266 int afmt_inst; 1267 1268 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1269 if (eng_id < ENGINE_ID_DIGF) { 1270 vpg_inst = eng_id; 1271 afmt_inst = eng_id; 1272 } else 1273 return NULL; 1274 1275 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1276 vpg = dcn31_vpg_create(ctx, vpg_inst); 1277 afmt = dcn31_afmt_create(ctx, afmt_inst); 1278 1279 if (!enc1 || !vpg || !afmt) { 1280 kfree(enc1); 1281 kfree(vpg); 1282 kfree(afmt); 1283 return NULL; 1284 } 1285 1286 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1287 eng_id, vpg, afmt, 1288 &stream_enc_regs[eng_id], 1289 &se_shift, &se_mask); 1290 1291 return &enc1->base; 1292} 1293 1294static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1295 enum engine_id eng_id, 1296 struct dc_context *ctx) 1297{ 1298 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1299 struct vpg *vpg; 1300 struct apg *apg; 1301 uint32_t hpo_dp_inst; 1302 uint32_t vpg_inst; 1303 uint32_t apg_inst; 1304 1305 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1306 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1307 1308 /* Mapping of VPG register blocks to HPO DP block instance: 1309 * VPG[6] -> HPO_DP[0] 1310 * VPG[7] -> HPO_DP[1] 1311 * VPG[8] -> HPO_DP[2] 1312 * VPG[9] -> HPO_DP[3] 1313 */ 1314 //Uses offset index 5-8, but actually maps to vpg_inst 6-9 1315 vpg_inst = hpo_dp_inst + 5; 1316 1317 /* Mapping of APG register blocks to HPO DP block instance: 1318 * APG[0] -> HPO_DP[0] 1319 * APG[1] -> HPO_DP[1] 1320 * APG[2] -> HPO_DP[2] 1321 * APG[3] -> HPO_DP[3] 1322 */ 1323 apg_inst = hpo_dp_inst; 1324 1325 /* allocate HPO stream encoder and create VPG sub-block */ 1326 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1327 vpg = dcn31_vpg_create(ctx, vpg_inst); 1328 apg = dcn31_apg_create(ctx, apg_inst); 1329 1330 if (!hpo_dp_enc31 || !vpg || !apg) { 1331 kfree(hpo_dp_enc31); 1332 kfree(vpg); 1333 kfree(apg); 1334 return NULL; 1335 } 1336 1337 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1338 hpo_dp_inst, eng_id, vpg, apg, 1339 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1340 &hpo_dp_se_shift, &hpo_dp_se_mask); 1341 1342 return &hpo_dp_enc31->base; 1343} 1344 1345static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1346 uint8_t inst, 1347 struct dc_context *ctx) 1348{ 1349 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1350 1351 /* allocate HPO link encoder */ 1352 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1353 1354 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1355 &hpo_dp_link_enc_regs[inst], 1356 &hpo_dp_le_shift, &hpo_dp_le_mask); 1357 1358 return &hpo_dp_enc31->base; 1359} 1360 1361static struct dce_hwseq *dcn314_hwseq_create( 1362 struct dc_context *ctx) 1363{ 1364 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1365 1366 if (hws) { 1367 hws->ctx = ctx; 1368 hws->regs = &hwseq_reg; 1369 hws->shifts = &hwseq_shift; 1370 hws->masks = &hwseq_mask; 1371 /* DCN3.1 FPGA Workaround 1372 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1373 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1374 * function core_link_enable_stream 1375 */ 1376 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1377 hws->wa.dp_hpo_and_otg_sequence = true; 1378 } 1379 return hws; 1380} 1381static const struct resource_create_funcs res_create_funcs = { 1382 .read_dce_straps = read_dce_straps, 1383 .create_audio = dcn31_create_audio, 1384 .create_stream_encoder = dcn314_stream_encoder_create, 1385 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1386 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1387 .create_hwseq = dcn314_hwseq_create, 1388}; 1389 1390static const struct resource_create_funcs res_create_maximus_funcs = { 1391 .read_dce_straps = NULL, 1392 .create_audio = NULL, 1393 .create_stream_encoder = NULL, 1394 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1395 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1396 .create_hwseq = dcn314_hwseq_create, 1397}; 1398 1399static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) 1400{ 1401 unsigned int i; 1402 1403 for (i = 0; i < pool->base.stream_enc_count; i++) { 1404 if (pool->base.stream_enc[i] != NULL) { 1405 if (pool->base.stream_enc[i]->vpg != NULL) { 1406 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1407 pool->base.stream_enc[i]->vpg = NULL; 1408 } 1409 if (pool->base.stream_enc[i]->afmt != NULL) { 1410 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1411 pool->base.stream_enc[i]->afmt = NULL; 1412 } 1413 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1414 pool->base.stream_enc[i] = NULL; 1415 } 1416 } 1417 1418 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1419 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1420 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1421 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1422 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1423 } 1424 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1425 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1426 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1427 } 1428 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1429 pool->base.hpo_dp_stream_enc[i] = NULL; 1430 } 1431 } 1432 1433 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1434 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1435 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1436 pool->base.hpo_dp_link_enc[i] = NULL; 1437 } 1438 } 1439 1440 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1441 if (pool->base.dscs[i] != NULL) 1442 dcn20_dsc_destroy(&pool->base.dscs[i]); 1443 } 1444 1445 if (pool->base.mpc != NULL) { 1446 kfree(TO_DCN20_MPC(pool->base.mpc)); 1447 pool->base.mpc = NULL; 1448 } 1449 if (pool->base.hubbub != NULL) { 1450 kfree(pool->base.hubbub); 1451 pool->base.hubbub = NULL; 1452 } 1453 for (i = 0; i < pool->base.pipe_count; i++) { 1454 if (pool->base.dpps[i] != NULL) 1455 dcn31_dpp_destroy(&pool->base.dpps[i]); 1456 1457 if (pool->base.ipps[i] != NULL) 1458 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1459 1460 if (pool->base.hubps[i] != NULL) { 1461 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1462 pool->base.hubps[i] = NULL; 1463 } 1464 1465 if (pool->base.irqs != NULL) 1466 dal_irq_service_destroy(&pool->base.irqs); 1467 } 1468 1469 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1470 if (pool->base.engines[i] != NULL) 1471 dce110_engine_destroy(&pool->base.engines[i]); 1472 if (pool->base.hw_i2cs[i] != NULL) { 1473 kfree(pool->base.hw_i2cs[i]); 1474 pool->base.hw_i2cs[i] = NULL; 1475 } 1476 if (pool->base.sw_i2cs[i] != NULL) { 1477 kfree(pool->base.sw_i2cs[i]); 1478 pool->base.sw_i2cs[i] = NULL; 1479 } 1480 } 1481 1482 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1483 if (pool->base.opps[i] != NULL) 1484 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1485 } 1486 1487 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1488 if (pool->base.timing_generators[i] != NULL) { 1489 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1490 pool->base.timing_generators[i] = NULL; 1491 } 1492 } 1493 1494 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1495 if (pool->base.dwbc[i] != NULL) { 1496 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1497 pool->base.dwbc[i] = NULL; 1498 } 1499 if (pool->base.mcif_wb[i] != NULL) { 1500 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1501 pool->base.mcif_wb[i] = NULL; 1502 } 1503 } 1504 1505 for (i = 0; i < pool->base.audio_count; i++) { 1506 if (pool->base.audios[i]) 1507 dce_aud_destroy(&pool->base.audios[i]); 1508 } 1509 1510 for (i = 0; i < pool->base.clk_src_count; i++) { 1511 if (pool->base.clock_sources[i] != NULL) { 1512 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1513 pool->base.clock_sources[i] = NULL; 1514 } 1515 } 1516 1517 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1518 if (pool->base.mpc_lut[i] != NULL) { 1519 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1520 pool->base.mpc_lut[i] = NULL; 1521 } 1522 if (pool->base.mpc_shaper[i] != NULL) { 1523 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1524 pool->base.mpc_shaper[i] = NULL; 1525 } 1526 } 1527 1528 if (pool->base.dp_clock_source != NULL) { 1529 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1530 pool->base.dp_clock_source = NULL; 1531 } 1532 1533 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1534 if (pool->base.multiple_abms[i] != NULL) 1535 dce_abm_destroy(&pool->base.multiple_abms[i]); 1536 } 1537 1538 if (pool->base.psr != NULL) 1539 dmub_psr_destroy(&pool->base.psr); 1540 1541 if (pool->base.dccg != NULL) 1542 dcn_dccg_destroy(&pool->base.dccg); 1543} 1544 1545static struct hubp *dcn31_hubp_create( 1546 struct dc_context *ctx, 1547 uint32_t inst) 1548{ 1549 struct dcn20_hubp *hubp2 = 1550 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1551 1552 if (!hubp2) 1553 return NULL; 1554 1555 if (hubp31_construct(hubp2, ctx, inst, 1556 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1557 return &hubp2->base; 1558 1559 BREAK_TO_DEBUGGER(); 1560 kfree(hubp2); 1561 return NULL; 1562} 1563 1564static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1565{ 1566 int i; 1567 uint32_t pipe_count = pool->res_cap->num_dwb; 1568 1569 for (i = 0; i < pipe_count; i++) { 1570 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1571 GFP_KERNEL); 1572 1573 if (!dwbc30) { 1574 dm_error("DC: failed to create dwbc30!\n"); 1575 return false; 1576 } 1577 1578 dcn30_dwbc_construct(dwbc30, ctx, 1579 &dwbc30_regs[i], 1580 &dwbc30_shift, 1581 &dwbc30_mask, 1582 i); 1583 1584 pool->dwbc[i] = &dwbc30->base; 1585 } 1586 return true; 1587} 1588 1589static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1590{ 1591 int i; 1592 uint32_t pipe_count = pool->res_cap->num_dwb; 1593 1594 for (i = 0; i < pipe_count; i++) { 1595 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1596 GFP_KERNEL); 1597 1598 if (!mcif_wb30) { 1599 dm_error("DC: failed to create mcif_wb30!\n"); 1600 return false; 1601 } 1602 1603 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1604 &mcif_wb30_regs[i], 1605 &mcif_wb30_shift, 1606 &mcif_wb30_mask, 1607 i); 1608 1609 pool->mcif_wb[i] = &mcif_wb30->base; 1610 } 1611 return true; 1612} 1613 1614static struct display_stream_compressor *dcn314_dsc_create( 1615 struct dc_context *ctx, uint32_t inst) 1616{ 1617 struct dcn20_dsc *dsc = 1618 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1619 1620 if (!dsc) { 1621 BREAK_TO_DEBUGGER(); 1622 return NULL; 1623 } 1624 1625 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1626 return &dsc->base; 1627} 1628 1629static void dcn314_destroy_resource_pool(struct resource_pool **pool) 1630{ 1631 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool); 1632 1633 dcn314_resource_destruct(dcn314_pool); 1634 kfree(dcn314_pool); 1635 *pool = NULL; 1636} 1637 1638static struct clock_source *dcn31_clock_source_create( 1639 struct dc_context *ctx, 1640 struct dc_bios *bios, 1641 enum clock_source_id id, 1642 const struct dce110_clk_src_regs *regs, 1643 bool dp_clk_src) 1644{ 1645 struct dce110_clk_src *clk_src = 1646 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1647 1648 if (!clk_src) 1649 return NULL; 1650 1651 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1652 regs, &cs_shift, &cs_mask)) { 1653 clk_src->base.dp_clk_src = dp_clk_src; 1654 return &clk_src->base; 1655 } 1656 1657 BREAK_TO_DEBUGGER(); 1658 kfree(clk_src); 1659 return NULL; 1660} 1661 1662static int dcn314_populate_dml_pipes_from_context( 1663 struct dc *dc, struct dc_state *context, 1664 display_e2e_pipe_params_st *pipes, 1665 bool fast_validate) 1666{ 1667 int pipe_cnt; 1668 1669 DC_FP_START(); 1670 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate); 1671 DC_FP_END(); 1672 1673 return pipe_cnt; 1674} 1675 1676static struct dc_cap_funcs cap_funcs = { 1677 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1678}; 1679 1680static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1681{ 1682 DC_FP_START(); 1683 dcn314_update_bw_bounding_box_fpu(dc, bw_params); 1684 DC_FP_END(); 1685} 1686 1687static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config) 1688{ 1689 *panel_config = panel_config_defaults; 1690} 1691 1692bool dcn314_validate_bandwidth(struct dc *dc, 1693 struct dc_state *context, 1694 bool fast_validate) 1695{ 1696 bool out = false; 1697 1698 BW_VAL_TRACE_SETUP(); 1699 1700 int vlevel = 0; 1701 int pipe_cnt = 0; 1702 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1703 DC_LOGGER_INIT(dc->ctx->logger); 1704 1705 BW_VAL_TRACE_COUNT(); 1706 1707 DC_FP_START(); 1708 // do not support self refresh only 1709 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false); 1710 DC_FP_END(); 1711 1712 // Disable fast_validate to set min dcfclk in calculate_wm_and_dlg 1713 if (pipe_cnt == 0) 1714 fast_validate = false; 1715 1716 if (!out) 1717 goto validate_fail; 1718 1719 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1720 1721 if (fast_validate) { 1722 BW_VAL_TRACE_SKIP(fast); 1723 goto validate_out; 1724 } 1725 1726 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1727 1728 BW_VAL_TRACE_END_WATERMARKS(); 1729 1730 goto validate_out; 1731 1732validate_fail: 1733 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1734 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1735 1736 BW_VAL_TRACE_SKIP(fail); 1737 out = false; 1738 1739validate_out: 1740 kfree(pipes); 1741 1742 BW_VAL_TRACE_FINISH(); 1743 1744 return out; 1745} 1746 1747static struct resource_funcs dcn314_res_pool_funcs = { 1748 .destroy = dcn314_destroy_resource_pool, 1749 .link_enc_create = dcn31_link_encoder_create, 1750 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1751 .link_encs_assign = link_enc_cfg_link_encs_assign, 1752 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1753 .panel_cntl_create = dcn31_panel_cntl_create, 1754 .validate_bandwidth = dcn314_validate_bandwidth, 1755 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1756 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1757 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context, 1758 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1759 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1760 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1761 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1762 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1763 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1764 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1765 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1766 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1767 .update_bw_bounding_box = dcn314_update_bw_bounding_box, 1768 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1769 .get_panel_config_defaults = dcn314_get_panel_config_defaults, 1770}; 1771 1772static struct clock_source *dcn30_clock_source_create( 1773 struct dc_context *ctx, 1774 struct dc_bios *bios, 1775 enum clock_source_id id, 1776 const struct dce110_clk_src_regs *regs, 1777 bool dp_clk_src) 1778{ 1779 struct dce110_clk_src *clk_src = 1780 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1781 1782 if (!clk_src) 1783 return NULL; 1784 1785 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1786 regs, &cs_shift, &cs_mask)) { 1787 clk_src->base.dp_clk_src = dp_clk_src; 1788 return &clk_src->base; 1789 } 1790 1791 BREAK_TO_DEBUGGER(); 1792 kfree(clk_src); 1793 return NULL; 1794} 1795 1796static bool dcn314_resource_construct( 1797 uint8_t num_virtual_links, 1798 struct dc *dc, 1799 struct dcn314_resource_pool *pool) 1800{ 1801 int i; 1802 struct dc_context *ctx = dc->ctx; 1803 struct irq_service_init_data init_data; 1804 1805 ctx->dc_bios->regs = &bios_regs; 1806 1807 pool->base.res_cap = &res_cap_dcn314; 1808 pool->base.funcs = &dcn314_res_pool_funcs; 1809 1810 /************************************************* 1811 * Resource + asic cap harcoding * 1812 *************************************************/ 1813 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1814 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1815 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1816 dc->caps.max_downscale_ratio = 400; 1817 dc->caps.i2c_speed_in_khz = 100; 1818 dc->caps.i2c_speed_in_khz_hdcp = 100; 1819 dc->caps.max_cursor_size = 256; 1820 dc->caps.min_horizontal_blanking_period = 80; 1821 dc->caps.dmdata_alloc_size = 2048; 1822 dc->caps.max_slave_planes = 2; 1823 dc->caps.max_slave_yuv_planes = 2; 1824 dc->caps.max_slave_rgb_planes = 2; 1825 dc->caps.post_blend_color_processing = true; 1826 dc->caps.force_dp_tps4_for_cp2520 = true; 1827 dc->caps.dp_hpo = true; 1828 dc->caps.dp_hdmi21_pcon_support = true; 1829 dc->caps.edp_dsc_support = true; 1830 dc->caps.extended_aux_timeout_support = true; 1831 dc->caps.dmcub_support = true; 1832 dc->caps.is_apu = true; 1833 dc->caps.seamless_odm = true; 1834 1835 dc->caps.zstate_support = true; 1836 1837 /* Color pipeline capabilities */ 1838 dc->caps.color.dpp.dcn_arch = 1; 1839 dc->caps.color.dpp.input_lut_shared = 0; 1840 dc->caps.color.dpp.icsc = 1; 1841 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1842 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1843 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1844 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1845 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1846 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1847 dc->caps.color.dpp.post_csc = 1; 1848 dc->caps.color.dpp.gamma_corr = 1; 1849 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1850 1851 dc->caps.color.dpp.hw_3d_lut = 1; 1852 dc->caps.color.dpp.ogam_ram = 1; 1853 // no OGAM ROM on DCN301 1854 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1855 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1856 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1857 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1858 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1859 dc->caps.color.dpp.ocsc = 0; 1860 1861 dc->caps.color.mpc.gamut_remap = 1; 1862 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1863 dc->caps.color.mpc.ogam_ram = 1; 1864 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1865 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1866 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1867 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1868 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1869 dc->caps.color.mpc.ocsc = 1; 1870 1871 /* Use pipe context based otg sync logic */ 1872 dc->config.use_pipe_ctx_sync_logic = true; 1873 1874 /* read VBIOS LTTPR caps */ 1875 { 1876 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1877 enum bp_result bp_query_result; 1878 uint8_t is_vbios_lttpr_enable = 0; 1879 1880 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1881 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1882 } 1883 1884 /* interop bit is implicit */ 1885 { 1886 dc->caps.vbios_lttpr_aware = true; 1887 } 1888 } 1889 1890 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1891 dc->debug = debug_defaults_drv; 1892 else 1893 dc->debug = debug_defaults_diags; 1894 // Init the vm_helper 1895 if (dc->vm_helper) 1896 vm_helper_init(dc->vm_helper, 16); 1897 1898 /************************************************* 1899 * Create resources * 1900 *************************************************/ 1901 1902 /* Clock Sources for Pixel Clock*/ 1903 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1904 dcn30_clock_source_create(ctx, ctx->dc_bios, 1905 CLOCK_SOURCE_COMBO_PHY_PLL0, 1906 &clk_src_regs[0], false); 1907 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1908 dcn30_clock_source_create(ctx, ctx->dc_bios, 1909 CLOCK_SOURCE_COMBO_PHY_PLL1, 1910 &clk_src_regs[1], false); 1911 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1912 dcn30_clock_source_create(ctx, ctx->dc_bios, 1913 CLOCK_SOURCE_COMBO_PHY_PLL2, 1914 &clk_src_regs[2], false); 1915 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1916 dcn30_clock_source_create(ctx, ctx->dc_bios, 1917 CLOCK_SOURCE_COMBO_PHY_PLL3, 1918 &clk_src_regs[3], false); 1919 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1920 dcn30_clock_source_create(ctx, ctx->dc_bios, 1921 CLOCK_SOURCE_COMBO_PHY_PLL4, 1922 &clk_src_regs[4], false); 1923 1924 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1925 1926 /* todo: not reuse phy_pll registers */ 1927 pool->base.dp_clock_source = 1928 dcn31_clock_source_create(ctx, ctx->dc_bios, 1929 CLOCK_SOURCE_ID_DP_DTO, 1930 &clk_src_regs[0], true); 1931 1932 for (i = 0; i < pool->base.clk_src_count; i++) { 1933 if (pool->base.clock_sources[i] == NULL) { 1934 dm_error("DC: failed to create clock sources!\n"); 1935 BREAK_TO_DEBUGGER(); 1936 goto create_fail; 1937 } 1938 } 1939 1940 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1941 if (pool->base.dccg == NULL) { 1942 dm_error("DC: failed to create dccg!\n"); 1943 BREAK_TO_DEBUGGER(); 1944 goto create_fail; 1945 } 1946 1947 init_data.ctx = dc->ctx; 1948 pool->base.irqs = dal_irq_service_dcn314_create(&init_data); 1949 if (!pool->base.irqs) 1950 goto create_fail; 1951 1952 /* HUBBUB */ 1953 pool->base.hubbub = dcn31_hubbub_create(ctx); 1954 if (pool->base.hubbub == NULL) { 1955 BREAK_TO_DEBUGGER(); 1956 dm_error("DC: failed to create hubbub!\n"); 1957 goto create_fail; 1958 } 1959 1960 /* HUBPs, DPPs, OPPs and TGs */ 1961 for (i = 0; i < pool->base.pipe_count; i++) { 1962 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1963 if (pool->base.hubps[i] == NULL) { 1964 BREAK_TO_DEBUGGER(); 1965 dm_error( 1966 "DC: failed to create hubps!\n"); 1967 goto create_fail; 1968 } 1969 1970 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 1971 if (pool->base.dpps[i] == NULL) { 1972 BREAK_TO_DEBUGGER(); 1973 dm_error( 1974 "DC: failed to create dpps!\n"); 1975 goto create_fail; 1976 } 1977 } 1978 1979 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1980 pool->base.opps[i] = dcn31_opp_create(ctx, i); 1981 if (pool->base.opps[i] == NULL) { 1982 BREAK_TO_DEBUGGER(); 1983 dm_error( 1984 "DC: failed to create output pixel processor!\n"); 1985 goto create_fail; 1986 } 1987 } 1988 1989 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1990 pool->base.timing_generators[i] = dcn31_timing_generator_create( 1991 ctx, i); 1992 if (pool->base.timing_generators[i] == NULL) { 1993 BREAK_TO_DEBUGGER(); 1994 dm_error("DC: failed to create tg!\n"); 1995 goto create_fail; 1996 } 1997 } 1998 pool->base.timing_generator_count = i; 1999 2000 /* PSR */ 2001 pool->base.psr = dmub_psr_create(ctx); 2002 if (pool->base.psr == NULL) { 2003 dm_error("DC: failed to create psr obj!\n"); 2004 BREAK_TO_DEBUGGER(); 2005 goto create_fail; 2006 } 2007 2008 /* ABM */ 2009 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2010 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2011 &abm_regs[i], 2012 &abm_shift, 2013 &abm_mask); 2014 if (pool->base.multiple_abms[i] == NULL) { 2015 dm_error("DC: failed to create abm for pipe %d!\n", i); 2016 BREAK_TO_DEBUGGER(); 2017 goto create_fail; 2018 } 2019 } 2020 2021 /* MPC and DSC */ 2022 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2023 if (pool->base.mpc == NULL) { 2024 BREAK_TO_DEBUGGER(); 2025 dm_error("DC: failed to create mpc!\n"); 2026 goto create_fail; 2027 } 2028 2029 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2030 pool->base.dscs[i] = dcn314_dsc_create(ctx, i); 2031 if (pool->base.dscs[i] == NULL) { 2032 BREAK_TO_DEBUGGER(); 2033 dm_error("DC: failed to create display stream compressor %d!\n", i); 2034 goto create_fail; 2035 } 2036 } 2037 2038 /* DWB and MMHUBBUB */ 2039 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2040 BREAK_TO_DEBUGGER(); 2041 dm_error("DC: failed to create dwbc!\n"); 2042 goto create_fail; 2043 } 2044 2045 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2046 BREAK_TO_DEBUGGER(); 2047 dm_error("DC: failed to create mcif_wb!\n"); 2048 goto create_fail; 2049 } 2050 2051 /* AUX and I2C */ 2052 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2053 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2054 if (pool->base.engines[i] == NULL) { 2055 BREAK_TO_DEBUGGER(); 2056 dm_error( 2057 "DC:failed to create aux engine!!\n"); 2058 goto create_fail; 2059 } 2060 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2061 if (pool->base.hw_i2cs[i] == NULL) { 2062 BREAK_TO_DEBUGGER(); 2063 dm_error( 2064 "DC:failed to create hw i2c!!\n"); 2065 goto create_fail; 2066 } 2067 pool->base.sw_i2cs[i] = NULL; 2068 } 2069 2070 /* DCN314 has 4 DPIA */ 2071 pool->base.usb4_dpia_count = 4; 2072 2073 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2074 if (!resource_construct(num_virtual_links, dc, &pool->base, 2075 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2076 &res_create_funcs : &res_create_maximus_funcs))) 2077 goto create_fail; 2078 2079 /* HW Sequencer and Plane caps */ 2080 dcn314_hw_sequencer_construct(dc); 2081 2082 dc->caps.max_planes = pool->base.pipe_count; 2083 2084 for (i = 0; i < dc->caps.max_planes; ++i) 2085 dc->caps.planes[i] = plane_cap; 2086 2087 dc->cap_funcs = cap_funcs; 2088 2089 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp; 2090 2091 return true; 2092 2093create_fail: 2094 2095 dcn314_resource_destruct(pool); 2096 2097 return false; 2098} 2099 2100struct resource_pool *dcn314_create_resource_pool( 2101 const struct dc_init_data *init_data, 2102 struct dc *dc) 2103{ 2104 struct dcn314_resource_pool *pool = 2105 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL); 2106 2107 if (!pool) 2108 return NULL; 2109 2110 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool)) 2111 return &pool->base; 2112 2113 BREAK_TO_DEBUGGER(); 2114 kfree(pool); 2115 return NULL; 2116} 2117