dcn314_init.c revision 1.1 
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#include "dce110/dce110_hw_sequencer.h"
28#include "dcn10/dcn10_hw_sequencer.h"
29#include "dcn20/dcn20_hwseq.h"
30#include "dcn21/dcn21_hwseq.h"
31#include "dcn30/dcn30_hwseq.h"
32#include "dcn301/dcn301_hwseq.h"
33#include "dcn31/dcn31_hwseq.h"
34#include "dcn314/dcn314_hwseq.h"
35
36#include "dcn314_init.h"
37
38static const struct hw_sequencer_funcs dcn314_funcs = {
39	.program_gamut_remap = dcn10_program_gamut_remap,
40	.init_hw = dcn31_init_hw,
41	.power_down_on_boot = dcn10_power_down_on_boot,
42	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
43	.apply_ctx_for_surface = NULL,
44	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
45	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
46	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
47	.update_plane_addr = dcn20_update_plane_addr,
48	.update_dchub = dcn10_update_dchub,
49	.update_pending_status = dcn10_update_pending_status,
50	.program_output_csc = dcn20_program_output_csc,
51	.enable_accelerated_mode = dce110_enable_accelerated_mode,
52	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
53	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
54	.update_info_frame = dcn31_update_info_frame,
55	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
56	.enable_stream = dcn20_enable_stream,
57	.disable_stream = dce110_disable_stream,
58	.unblank_stream = dcn20_unblank_stream,
59	.blank_stream = dce110_blank_stream,
60	.enable_audio_stream = dce110_enable_audio_stream,
61	.disable_audio_stream = dce110_disable_audio_stream,
62	.disable_plane = dcn20_disable_plane,
63	.pipe_control_lock = dcn20_pipe_control_lock,
64	.interdependent_update_lock = dcn10_lock_all_pipes,
65	.cursor_lock = dcn10_cursor_lock,
66	.prepare_bandwidth = dcn20_prepare_bandwidth,
67	.optimize_bandwidth = dcn20_optimize_bandwidth,
68	.update_bandwidth = dcn20_update_bandwidth,
69	.set_drr = dcn10_set_drr,
70	.get_position = dcn10_get_position,
71	.set_static_screen_control = dcn10_set_static_screen_control,
72	.setup_stereo = dcn10_setup_stereo,
73	.set_avmute = dcn30_set_avmute,
74	.log_hw_state = dcn10_log_hw_state,
75	.get_hw_state = dcn10_get_hw_state,
76	.clear_status_bits = dcn10_clear_status_bits,
77	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
78	.edp_backlight_control = dce110_edp_backlight_control,
79	.edp_power_control = dce110_edp_power_control,
80	.edp_wait_for_T12 = dce110_edp_wait_for_T12,
81	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
82	.set_cursor_position = dcn10_set_cursor_position,
83	.set_cursor_attribute = dcn10_set_cursor_attribute,
84	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
85	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
86	.set_clock = dcn10_set_clock,
87	.get_clock = dcn10_get_clock,
88	.program_triplebuffer = dcn20_program_triple_buffer,
89	.enable_writeback = dcn30_enable_writeback,
90	.disable_writeback = dcn30_disable_writeback,
91	.update_writeback = dcn30_update_writeback,
92	.mmhubbub_warmup = dcn30_mmhubbub_warmup,
93	.dmdata_status_done = dcn20_dmdata_status_done,
94	.program_dmdata_engine = dcn30_program_dmdata_engine,
95	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
96	.init_sys_ctx = dcn31_init_sys_ctx,
97	.init_vm_ctx = dcn20_init_vm_ctx,
98	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
99	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
100	.calc_vupdate_position = dcn10_calc_vupdate_position,
101	.power_down = dce110_power_down,
102	.set_backlight_level = dcn21_set_backlight_level,
103	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
104	.set_pipe = dcn21_set_pipe,
105	.enable_lvds_link_output = dce110_enable_lvds_link_output,
106	.enable_tmds_link_output = dce110_enable_tmds_link_output,
107	.enable_dp_link_output = dce110_enable_dp_link_output,
108	.disable_link_output = dce110_disable_link_output,
109	.z10_restore = dcn31_z10_restore,
110	.z10_save_init = dcn31_z10_save_init,
111	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
112	.optimize_pwr_state = dcn21_optimize_pwr_state,
113	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
114	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
115};
116
117static const struct hwseq_private_funcs dcn314_private_funcs = {
118	.init_pipes = dcn10_init_pipes,
119	.update_plane_addr = dcn20_update_plane_addr,
120	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
121	.update_mpcc = dcn20_update_mpcc,
122	.set_input_transfer_func = dcn30_set_input_transfer_func,
123	.set_output_transfer_func = dcn30_set_output_transfer_func,
124	.power_down = dce110_power_down,
125	.enable_display_power_gating = dcn10_dummy_display_power_gating,
126	.blank_pixel_data = dcn20_blank_pixel_data,
127	.reset_hw_ctx_wrap = dcn31_reset_hw_ctx_wrap,
128	.enable_stream_timing = dcn20_enable_stream_timing,
129	.edp_backlight_control = dce110_edp_backlight_control,
130	.disable_stream_gating = dcn20_disable_stream_gating,
131	.enable_stream_gating = dcn20_enable_stream_gating,
132	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
133	.did_underflow_occur = dcn10_did_underflow_occur,
134	.init_blank = dcn20_init_blank,
135	.disable_vga = dcn20_disable_vga,
136	.bios_golden_init = dcn10_bios_golden_init,
137	.plane_atomic_disable = dcn20_plane_atomic_disable,
138	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
139	.enable_power_gating_plane = dcn314_enable_power_gating_plane,
140	.hubp_pg_control = dcn31_hubp_pg_control,
141	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
142	.update_odm = dcn314_update_odm,
143	.dsc_pg_control = dcn314_dsc_pg_control,
144	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
145	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
146	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
147	.dccg_init = dcn20_dccg_init,
148	.set_blend_lut = dcn30_set_blend_lut,
149	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
150	.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,
151	.calculate_dccg_k1_k2_values = dcn314_calculate_dccg_k1_k2_values,
152	.set_pixels_per_cycle = dcn314_set_pixels_per_cycle,
153};
154
155void dcn314_hw_sequencer_construct(struct dc *dc)
156{
157	dc->hwss = dcn314_funcs;
158	dc->hwseq->funcs = dcn314_private_funcs;
159
160	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
161		dc->hwss.init_hw = dcn20_fpga_init_hw;
162		dc->hwseq->funcs.init_pipes = NULL;
163	}
164}
165