1// SPDX-License-Identifier: MIT
2/*
3 * Copyright (C) 2021 Advanced Micro Devices, Inc.
4 *
5 * Authors: AMD
6 */
7
8#ifndef __DCN303_DCCG_H__
9#define __DCN303_DCCG_H__
10
11#include "dcn30/dcn30_dccg.h"
12
13
14#define DCCG_REG_LIST_DCN3_03() \
15	SR(DPPCLK_DTO_CTRL),\
16	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
17	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
18	SR(REFCLK_CNTL),\
19	SR(DISPCLK_FREQ_CHANGE_CNTL),\
20	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
21	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1)
22
23
24#define DCCG_MASK_SH_LIST_DCN3_03(mask_sh) \
25		DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
26		DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
27		DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
28		DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
29		DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
30		DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
31		DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
32		DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
33		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
34		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
35		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
36		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
37		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
38		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
39		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
40		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
41		DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
42		DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
43		DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
44		DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
45
46#endif //__DCN303_DCCG_H__
47