command_table_helper2.c revision 1.3 
1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27
28#include "ObjectID.h"
29#include "atomfirmware.h"
30
31#include "include/bios_parser_types.h"
32
33#include "command_table_helper2.h"
34
35bool dal_bios_parser_init_cmd_tbl_helper2(
36	const struct command_table_helper **h,
37	enum dce_version dce)
38{
39	switch (dce) {
40#if defined(CONFIG_DRM_AMD_DC_SI)
41	case DCE_VERSION_6_0:
42	case DCE_VERSION_6_1:
43	case DCE_VERSION_6_4:
44		*h = dal_cmd_tbl_helper_dce60_get_table();
45		return true;
46#endif
47
48	case DCE_VERSION_8_0:
49	case DCE_VERSION_8_1:
50	case DCE_VERSION_8_3:
51		*h = dal_cmd_tbl_helper_dce80_get_table();
52		return true;
53
54	case DCE_VERSION_10_0:
55		*h = dal_cmd_tbl_helper_dce110_get_table();
56		return true;
57
58	case DCE_VERSION_11_0:
59		*h = dal_cmd_tbl_helper_dce110_get_table();
60		return true;
61
62	case DCE_VERSION_11_2:
63	case DCE_VERSION_11_22:
64	case DCE_VERSION_12_0:
65	case DCE_VERSION_12_1:
66		*h = dal_cmd_tbl_helper_dce112_get_table2();
67		return true;
68#if defined(CONFIG_DRM_AMD_DC_DCN)
69	case DCN_VERSION_1_0:
70	case DCN_VERSION_1_01:
71	case DCN_VERSION_2_0:
72	case DCN_VERSION_2_1:
73		*h = dal_cmd_tbl_helper_dce112_get_table2();
74		return true;
75#endif
76#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
77	case DCN_VERSION_3_0:
78		*h = dal_cmd_tbl_helper_dce112_get_table2();
79		return true;
80#endif
81
82	default:
83		/* Unsupported DCE */
84		BREAK_TO_DEBUGGER();
85		return false;
86	}
87}
88
89/* real implementations */
90
91bool dal_cmd_table_helper_controller_id_to_atom2(
92	enum controller_id id,
93	uint8_t *atom_id)
94{
95	if (atom_id == NULL) {
96		BREAK_TO_DEBUGGER();
97		return false;
98	}
99
100	switch (id) {
101	case CONTROLLER_ID_D0:
102		*atom_id = ATOM_CRTC1;
103		return true;
104	case CONTROLLER_ID_D1:
105		*atom_id = ATOM_CRTC2;
106		return true;
107	case CONTROLLER_ID_D2:
108		*atom_id = ATOM_CRTC3;
109		return true;
110	case CONTROLLER_ID_D3:
111		*atom_id = ATOM_CRTC4;
112		return true;
113	case CONTROLLER_ID_D4:
114		*atom_id = ATOM_CRTC5;
115		return true;
116	case CONTROLLER_ID_D5:
117		*atom_id = ATOM_CRTC6;
118		return true;
119	/* TODO :case CONTROLLER_ID_UNDERLAY0:
120		*atom_id = ATOM_UNDERLAY_PIPE0;
121		return true;
122	*/
123	case CONTROLLER_ID_UNDEFINED:
124		*atom_id = ATOM_CRTC_INVALID;
125		return true;
126	default:
127		/* Wrong controller id */
128		BREAK_TO_DEBUGGER();
129		return false;
130	}
131}
132
133/**
134* translate_transmitter_bp_to_atom
135*
136* @brief
137*  Translate the Transmitter to the corresponding ATOM BIOS value
138*
139* @param
140*   input transmitter
141*   output digitalTransmitter
142*    // =00: Digital Transmitter1 ( UNIPHY linkAB )
143*    // =01: Digital Transmitter2 ( UNIPHY linkCD )
144*    // =02: Digital Transmitter3 ( UNIPHY linkEF )
145*/
146uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2(
147	enum transmitter t)
148{
149	switch (t) {
150	case TRANSMITTER_UNIPHY_A:
151	case TRANSMITTER_UNIPHY_B:
152	case TRANSMITTER_TRAVIS_LCD:
153		return 0;
154	case TRANSMITTER_UNIPHY_C:
155	case TRANSMITTER_UNIPHY_D:
156		return 1;
157	case TRANSMITTER_UNIPHY_E:
158	case TRANSMITTER_UNIPHY_F:
159		return 2;
160	default:
161		/* Invalid Transmitter Type! */
162		BREAK_TO_DEBUGGER();
163		return 0;
164	}
165}
166
167uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2(
168	enum amd_signal_type s,
169	bool enable_dp_audio)
170{
171	switch (s) {
172	case SIGNAL_TYPE_DVI_SINGLE_LINK:
173	case SIGNAL_TYPE_DVI_DUAL_LINK:
174		return ATOM_ENCODER_MODE_DVI;
175	case SIGNAL_TYPE_HDMI_TYPE_A:
176		return ATOM_ENCODER_MODE_HDMI;
177	case SIGNAL_TYPE_LVDS:
178		return ATOM_ENCODER_MODE_LVDS;
179	case SIGNAL_TYPE_EDP:
180	case SIGNAL_TYPE_DISPLAY_PORT_MST:
181	case SIGNAL_TYPE_DISPLAY_PORT:
182	case SIGNAL_TYPE_VIRTUAL:
183		if (enable_dp_audio)
184			return ATOM_ENCODER_MODE_DP_AUDIO;
185		else
186			return ATOM_ENCODER_MODE_DP;
187	case SIGNAL_TYPE_RGB:
188		return ATOM_ENCODER_MODE_CRT;
189	default:
190		return ATOM_ENCODER_MODE_CRT;
191	}
192}
193
194bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2(
195	enum clock_source_id id,
196	uint32_t *ref_clk_src_id)
197{
198	if (ref_clk_src_id == NULL) {
199		BREAK_TO_DEBUGGER();
200		return false;
201	}
202
203	switch (id) {
204	case CLOCK_SOURCE_ID_PLL1:
205		*ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL;
206		return true;
207	case CLOCK_SOURCE_ID_PLL2:
208		*ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL;
209		return true;
210	/*TODO:case CLOCK_SOURCE_ID_DCPLL:
211		*ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL;
212		return true;
213	*/
214	case CLOCK_SOURCE_ID_EXTERNAL:
215		*ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK;
216		return true;
217	case CLOCK_SOURCE_ID_UNDEFINED:
218		*ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID;
219		return true;
220	default:
221		/* Unsupported clock source id */
222		BREAK_TO_DEBUGGER();
223		return false;
224	}
225}
226
227uint8_t dal_cmd_table_helper_encoder_id_to_atom2(
228	enum encoder_id id)
229{
230	switch (id) {
231	case ENCODER_ID_INTERNAL_LVDS:
232		return ENCODER_OBJECT_ID_INTERNAL_LVDS;
233	case ENCODER_ID_INTERNAL_TMDS1:
234		return ENCODER_OBJECT_ID_INTERNAL_TMDS1;
235	case ENCODER_ID_INTERNAL_TMDS2:
236		return ENCODER_OBJECT_ID_INTERNAL_TMDS2;
237	case ENCODER_ID_INTERNAL_DAC1:
238		return ENCODER_OBJECT_ID_INTERNAL_DAC1;
239	case ENCODER_ID_INTERNAL_DAC2:
240		return ENCODER_OBJECT_ID_INTERNAL_DAC2;
241	case ENCODER_ID_INTERNAL_LVTM1:
242		return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
243	case ENCODER_ID_INTERNAL_HDMI:
244		return ENCODER_OBJECT_ID_HDMI_INTERNAL;
245	case ENCODER_ID_EXTERNAL_TRAVIS:
246		return ENCODER_OBJECT_ID_TRAVIS;
247	case ENCODER_ID_EXTERNAL_NUTMEG:
248		return ENCODER_OBJECT_ID_NUTMEG;
249	case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
250		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
251	case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
252		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
253	case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
254		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
255	case ENCODER_ID_EXTERNAL_MVPU_FPGA:
256		return ENCODER_OBJECT_ID_MVPU_FPGA;
257	case ENCODER_ID_INTERNAL_DDI:
258		return ENCODER_OBJECT_ID_INTERNAL_DDI;
259	case ENCODER_ID_INTERNAL_UNIPHY:
260		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
261	case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
262		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA;
263	case ENCODER_ID_INTERNAL_UNIPHY1:
264		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1;
265	case ENCODER_ID_INTERNAL_UNIPHY2:
266		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2;
267	case ENCODER_ID_INTERNAL_UNIPHY3:
268		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
269	case ENCODER_ID_INTERNAL_WIRELESS:
270		return ENCODER_OBJECT_ID_INTERNAL_VCE;
271	case ENCODER_ID_INTERNAL_VIRTUAL:
272		return ENCODER_OBJECT_ID_NONE;
273	case ENCODER_ID_UNKNOWN:
274		return ENCODER_OBJECT_ID_NONE;
275	default:
276		/* Invalid encoder id */
277		BREAK_TO_DEBUGGER();
278		return ENCODER_OBJECT_ID_NONE;
279	}
280}
281