nbio_v7_0.c revision 1.3 
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "nbio_v7_0.h"
26
27#include "nbio/nbio_7_0_default.h"
28#include "nbio/nbio_7_0_offset.h"
29#include "nbio/nbio_7_0_sh_mask.h"
30#include "nbio/nbio_7_0_smn.h"
31#include "vega10_enum.h"
32#include <uapi/linux/kfd_ioctl.h>
33
34#define smnNBIF_MGCG_CTRL_LCLK	0x1013a05c
35
36static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev)
37{
38	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
39		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
40	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
41		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
42}
43
44static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
45{
46        u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
47
48	tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
49	tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
50
51	return tmp;
52}
53
54static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
55{
56	if (enable)
57		WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
58			BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
59	else
60		WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
61}
62
63static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
64				struct amdgpu_ring *ring)
65{
66	if (!ring || !ring->funcs->emit_wreg)
67		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
68	else
69		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
70}
71
72static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
73{
74	return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
75}
76
77static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
78			bool use_doorbell, int doorbell_index, int doorbell_size)
79{
80	u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
81			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
82
83	u32 doorbell_range = RREG32(reg);
84
85	if (use_doorbell) {
86		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
87		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
88	} else
89		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
90
91	WREG32(reg, doorbell_range);
92}
93
94static void nbio_v7_0_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
95					 int doorbell_index, int instance)
96{
97	u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
98
99	u32 doorbell_range = RREG32(reg);
100
101	if (use_doorbell) {
102		doorbell_range = REG_SET_FIELD(doorbell_range,
103					       BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
104					       doorbell_index);
105		doorbell_range = REG_SET_FIELD(doorbell_range,
106					       BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
107	} else
108		doorbell_range = REG_SET_FIELD(doorbell_range,
109					       BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
110
111	WREG32(reg, doorbell_range);
112}
113
114static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
115					       bool enable)
116{
117	WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
118}
119
120static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
121							bool enable)
122{
123
124}
125
126static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
127					bool use_doorbell, int doorbell_index)
128{
129	u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
130
131	if (use_doorbell) {
132		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
133		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
134	} else
135		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
136
137	WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
138}
139
140static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
141{
142	uint32_t data;
143
144	WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
145	data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);
146
147	return data;
148}
149
150static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
151				       uint32_t data)
152{
153	WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
154	WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
155}
156
157static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
158						       bool enable)
159{
160	uint32_t def, data;
161
162	/* NBIF_MGCG_CTRL_LCLK */
163	def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
164
165	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
166		data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
167	else
168		data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
169
170	if (def != data)
171		WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
172
173	/* SYSHUB_MGCG_CTRL_SOCCLK */
174	def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);
175
176	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
177		data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
178	else
179		data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
180
181	if (def != data)
182		nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);
183
184	/* SYSHUB_MGCG_CTRL_SHUBCLK */
185	def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);
186
187	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
188		data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
189	else
190		data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
191
192	if (def != data)
193		nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
194}
195
196static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
197						      bool enable)
198{
199	uint32_t def, data;
200
201	def = data = RREG32_PCIE(smnPCIE_CNTL2);
202	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
203		data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
204			 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
205			 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
206	} else {
207		data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
208			  PCIE_CNTL2__MST_MEM_LS_EN_MASK |
209			  PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
210	}
211
212	if (def != data)
213		WREG32_PCIE(smnPCIE_CNTL2, data);
214}
215
216static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev,
217					    u32 *flags)
218{
219	int data;
220
221	/* AMD_CG_SUPPORT_BIF_MGCG */
222	data = RREG32_PCIE(smnCPM_CONTROL);
223	if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
224		*flags |= AMD_CG_SUPPORT_BIF_MGCG;
225
226	/* AMD_CG_SUPPORT_BIF_LS */
227	data = RREG32_PCIE(smnPCIE_CNTL2);
228	if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
229		*flags |= AMD_CG_SUPPORT_BIF_LS;
230}
231
232static void nbio_v7_0_ih_control(struct amdgpu_device *adev)
233{
234	u32 interrupt_cntl;
235
236	/* setup interrupt control */
237	WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
238	interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
239	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
240	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
241	 */
242	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
243	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
244	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
245	WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
246}
247
248static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
249{
250	return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
251}
252
253static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
254{
255	return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
256}
257
258static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
259{
260	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
261}
262
263static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
264{
265	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
266}
267
268const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
269	.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
270	.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
271	.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
272	.ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
273	.ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
274	.ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
275	.ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
276	.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
277	.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
278	.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
279	.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
280	.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
281};
282
283static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
284{
285
286}
287
288const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
289	.get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
290	.get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
291	.get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
292	.get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
293	.get_rev_id = nbio_v7_0_get_rev_id,
294	.mc_access_enable = nbio_v7_0_mc_access_enable,
295	.hdp_flush = nbio_v7_0_hdp_flush,
296	.get_memsize = nbio_v7_0_get_memsize,
297	.sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
298	.vcn_doorbell_range = nbio_v7_0_vcn_doorbell_range,
299	.enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
300	.enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
301	.ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
302	.update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating,
303	.update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep,
304	.get_clockgating_state = nbio_v7_0_get_clockgating_state,
305	.ih_control = nbio_v7_0_ih_control,
306	.init_registers = nbio_v7_0_init_registers,
307	.remap_hdp_registers = nbio_v7_0_remap_hdp_registers,
308};
309