gmc_v8_0.c revision 1.4
1/* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <linux/firmware.h> 25#include <linux/module.h> 26#include <linux/pci.h> 27 28#include <drm/drm_cache.h> 29#include "amdgpu.h" 30#include "gmc_v8_0.h" 31#include "amdgpu_ucode.h" 32#include "amdgpu_amdkfd.h" 33#include "amdgpu_gem.h" 34 35#include "gmc/gmc_8_1_d.h" 36#include "gmc/gmc_8_1_sh_mask.h" 37 38#include "bif/bif_5_0_d.h" 39#include "bif/bif_5_0_sh_mask.h" 40 41#include "oss/oss_3_0_d.h" 42#include "oss/oss_3_0_sh_mask.h" 43 44#include "dce/dce_10_0_d.h" 45#include "dce/dce_10_0_sh_mask.h" 46 47#include "vid.h" 48#include "vi.h" 49 50#include "amdgpu_atombios.h" 51 52#include "ivsrcid/ivsrcid_vislands30.h" 53 54static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); 55static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 56static int gmc_v8_0_wait_for_idle(void *handle); 57 58MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 59MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 60MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 61MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 62MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin"); 63MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin"); 64MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin"); 65 66static const u32 golden_settings_tonga_a11[] = 67{ 68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 75}; 76 77static const u32 tonga_mgcg_cgcg_init[] = 78{ 79 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 80}; 81 82static const u32 golden_settings_fiji_a10[] = 83{ 84 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 85 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 86 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 87 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 88}; 89 90static const u32 fiji_mgcg_cgcg_init[] = 91{ 92 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 93}; 94 95static const u32 golden_settings_polaris11_a11[] = 96{ 97 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 98 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 99 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 100 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 101}; 102 103static const u32 golden_settings_polaris10_a11[] = 104{ 105 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 106 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 107 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 108 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 109 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 110}; 111 112static const u32 cz_mgcg_cgcg_init[] = 113{ 114 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 115}; 116 117static const u32 stoney_mgcg_cgcg_init[] = 118{ 119 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 120 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 121}; 122 123static const u32 golden_settings_stoney_common[] = 124{ 125 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 126 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 127}; 128 129static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 130{ 131 switch (adev->asic_type) { 132 case CHIP_FIJI: 133 amdgpu_device_program_register_sequence(adev, 134 fiji_mgcg_cgcg_init, 135 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 136 amdgpu_device_program_register_sequence(adev, 137 golden_settings_fiji_a10, 138 ARRAY_SIZE(golden_settings_fiji_a10)); 139 break; 140 case CHIP_TONGA: 141 amdgpu_device_program_register_sequence(adev, 142 tonga_mgcg_cgcg_init, 143 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 144 amdgpu_device_program_register_sequence(adev, 145 golden_settings_tonga_a11, 146 ARRAY_SIZE(golden_settings_tonga_a11)); 147 break; 148 case CHIP_POLARIS11: 149 case CHIP_POLARIS12: 150 case CHIP_VEGAM: 151 amdgpu_device_program_register_sequence(adev, 152 golden_settings_polaris11_a11, 153 ARRAY_SIZE(golden_settings_polaris11_a11)); 154 break; 155 case CHIP_POLARIS10: 156 amdgpu_device_program_register_sequence(adev, 157 golden_settings_polaris10_a11, 158 ARRAY_SIZE(golden_settings_polaris10_a11)); 159 break; 160 case CHIP_CARRIZO: 161 amdgpu_device_program_register_sequence(adev, 162 cz_mgcg_cgcg_init, 163 ARRAY_SIZE(cz_mgcg_cgcg_init)); 164 break; 165 case CHIP_STONEY: 166 amdgpu_device_program_register_sequence(adev, 167 stoney_mgcg_cgcg_init, 168 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 169 amdgpu_device_program_register_sequence(adev, 170 golden_settings_stoney_common, 171 ARRAY_SIZE(golden_settings_stoney_common)); 172 break; 173 default: 174 break; 175 } 176} 177 178static void gmc_v8_0_mc_stop(struct amdgpu_device *adev) 179{ 180 u32 blackout; 181 182 gmc_v8_0_wait_for_idle(adev); 183 184 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 185 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 186 /* Block CPU access */ 187 WREG32(mmBIF_FB_EN, 0); 188 /* blackout the MC */ 189 blackout = REG_SET_FIELD(blackout, 190 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 191 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 192 } 193 /* wait for the MC to settle */ 194 udelay(100); 195} 196 197static void gmc_v8_0_mc_resume(struct amdgpu_device *adev) 198{ 199 u32 tmp; 200 201 /* unblackout the MC */ 202 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 203 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 204 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 205 /* allow CPU access */ 206 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 207 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 208 WREG32(mmBIF_FB_EN, tmp); 209} 210 211/** 212 * gmc_v8_0_init_microcode - load ucode images from disk 213 * 214 * @adev: amdgpu_device pointer 215 * 216 * Use the firmware interface to load the ucode images into 217 * the driver (not loaded into hw). 218 * Returns 0 on success, error on failure. 219 */ 220static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 221{ 222 const char *chip_name; 223 char fw_name[30]; 224 int err; 225 226 DRM_DEBUG("\n"); 227 228 switch (adev->asic_type) { 229 case CHIP_TONGA: 230 chip_name = "tonga"; 231 break; 232 case CHIP_POLARIS11: 233 if (((adev->pdev->device == 0x67ef) && 234 ((adev->pdev->revision == 0xe0) || 235 (adev->pdev->revision == 0xe5))) || 236 ((adev->pdev->device == 0x67ff) && 237 ((adev->pdev->revision == 0xcf) || 238 (adev->pdev->revision == 0xef) || 239 (adev->pdev->revision == 0xff)))) 240 chip_name = "polaris11_k"; 241 else if ((adev->pdev->device == 0x67ef) && 242 (adev->pdev->revision == 0xe2)) 243 chip_name = "polaris11_k"; 244 else 245 chip_name = "polaris11"; 246 break; 247 case CHIP_POLARIS10: 248 if ((adev->pdev->device == 0x67df) && 249 ((adev->pdev->revision == 0xe1) || 250 (adev->pdev->revision == 0xf7))) 251 chip_name = "polaris10_k"; 252 else 253 chip_name = "polaris10"; 254 break; 255 case CHIP_POLARIS12: 256 if (((adev->pdev->device == 0x6987) && 257 ((adev->pdev->revision == 0xc0) || 258 (adev->pdev->revision == 0xc3))) || 259 ((adev->pdev->device == 0x6981) && 260 ((adev->pdev->revision == 0x00) || 261 (adev->pdev->revision == 0x01) || 262 (adev->pdev->revision == 0x10)))) 263 chip_name = "polaris12_k"; 264 else 265 chip_name = "polaris12"; 266 break; 267 case CHIP_FIJI: 268 case CHIP_CARRIZO: 269 case CHIP_STONEY: 270 case CHIP_VEGAM: 271 return 0; 272 default: BUG(); 273 } 274 275 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 276 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 277 if (err) 278 goto out; 279 err = amdgpu_ucode_validate(adev->gmc.fw); 280 281out: 282 if (err) { 283 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); 284 release_firmware(adev->gmc.fw); 285 adev->gmc.fw = NULL; 286 } 287 return err; 288} 289 290/** 291 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 292 * 293 * @adev: amdgpu_device pointer 294 * 295 * Load the GDDR MC ucode into the hw (VI). 296 * Returns 0 on success, error on failure. 297 */ 298static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 299{ 300 const struct mc_firmware_header_v1_0 *hdr; 301 const __le32 *fw_data = NULL; 302 const __le32 *io_mc_regs = NULL; 303 u32 running; 304 int i, ucode_size, regs_size; 305 306 /* Skip MC ucode loading on SR-IOV capable boards. 307 * vbios does this for us in asic_init in that case. 308 * Skip MC ucode loading on VF, because hypervisor will do that 309 * for this adaptor. 310 */ 311 if (amdgpu_sriov_bios(adev)) 312 return 0; 313 314 if (!adev->gmc.fw) 315 return -EINVAL; 316 317 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 318 amdgpu_ucode_print_mc_hdr(&hdr->header); 319 320 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 321 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 322 io_mc_regs = (const __le32 *) 323 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 324 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 325 fw_data = (const __le32 *) 326 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 327 328 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 329 330 if (running == 0) { 331 /* reset the engine and set to writable */ 332 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 333 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 334 335 /* load mc io regs */ 336 for (i = 0; i < regs_size; i++) { 337 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 338 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 339 } 340 /* load the MC ucode */ 341 for (i = 0; i < ucode_size; i++) 342 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 343 344 /* put the engine back into the active state */ 345 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 346 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 347 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 348 349 /* wait for training to complete */ 350 for (i = 0; i < adev->usec_timeout; i++) { 351 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 352 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 353 break; 354 udelay(1); 355 } 356 for (i = 0; i < adev->usec_timeout; i++) { 357 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 358 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 359 break; 360 udelay(1); 361 } 362 } 363 364 return 0; 365} 366 367static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 368{ 369 const struct mc_firmware_header_v1_0 *hdr; 370 const __le32 *fw_data = NULL; 371 const __le32 *io_mc_regs = NULL; 372 u32 data; 373 int i, ucode_size, regs_size; 374 375 /* Skip MC ucode loading on SR-IOV capable boards. 376 * vbios does this for us in asic_init in that case. 377 * Skip MC ucode loading on VF, because hypervisor will do that 378 * for this adaptor. 379 */ 380 if (amdgpu_sriov_bios(adev)) 381 return 0; 382 383 if (!adev->gmc.fw) 384 return -EINVAL; 385 386 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 387 amdgpu_ucode_print_mc_hdr(&hdr->header); 388 389 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 390 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 391 io_mc_regs = (const __le32 *) 392 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 393 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 394 fw_data = (const __le32 *) 395 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 396 397 data = RREG32(mmMC_SEQ_MISC0); 398 data &= ~(0x40); 399 WREG32(mmMC_SEQ_MISC0, data); 400 401 /* load mc io regs */ 402 for (i = 0; i < regs_size; i++) { 403 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 404 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 405 } 406 407 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 408 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 409 410 /* load the MC ucode */ 411 for (i = 0; i < ucode_size; i++) 412 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 413 414 /* put the engine back into the active state */ 415 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 416 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 417 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 418 419 /* wait for training to complete */ 420 for (i = 0; i < adev->usec_timeout; i++) { 421 data = RREG32(mmMC_SEQ_MISC0); 422 if (data & 0x80) 423 break; 424 udelay(1); 425 } 426 427 return 0; 428} 429 430static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 431 struct amdgpu_gmc *mc) 432{ 433 u64 base = 0; 434 435 if (!amdgpu_sriov_vf(adev)) 436 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 437 base <<= 24; 438 439 amdgpu_gmc_vram_location(adev, mc, base); 440 amdgpu_gmc_gart_location(adev, mc); 441} 442 443/** 444 * gmc_v8_0_mc_program - program the GPU memory controller 445 * 446 * @adev: amdgpu_device pointer 447 * 448 * Set the location of vram, gart, and AGP in the GPU's 449 * physical address space (VI). 450 */ 451static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 452{ 453 u32 tmp; 454 int i, j; 455 456 /* Initialize HDP */ 457 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 458 WREG32((0xb05 + j), 0x00000000); 459 WREG32((0xb06 + j), 0x00000000); 460 WREG32((0xb07 + j), 0x00000000); 461 WREG32((0xb08 + j), 0x00000000); 462 WREG32((0xb09 + j), 0x00000000); 463 } 464 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 465 466 if (gmc_v8_0_wait_for_idle((void *)adev)) { 467 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 468 } 469 if (adev->mode_info.num_crtc) { 470 /* Lockout access through VGA aperture*/ 471 tmp = RREG32(mmVGA_HDP_CONTROL); 472 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 473 WREG32(mmVGA_HDP_CONTROL, tmp); 474 475 /* disable VGA render */ 476 tmp = RREG32(mmVGA_RENDER_CONTROL); 477 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 478 WREG32(mmVGA_RENDER_CONTROL, tmp); 479 } 480 /* Update configuration */ 481 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 482 adev->gmc.vram_start >> 12); 483 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 484 adev->gmc.vram_end >> 12); 485 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 486 adev->vram_scratch.gpu_addr >> 12); 487 488 if (amdgpu_sriov_vf(adev)) { 489 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; 490 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); 491 WREG32(mmMC_VM_FB_LOCATION, tmp); 492 /* XXX double check these! */ 493 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 494 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 495 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 496 } 497 498 WREG32(mmMC_VM_AGP_BASE, 0); 499 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 500 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 501 if (gmc_v8_0_wait_for_idle((void *)adev)) { 502 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 503 } 504 505 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 506 507 tmp = RREG32(mmHDP_MISC_CNTL); 508 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 509 WREG32(mmHDP_MISC_CNTL, tmp); 510 511 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 512 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 513} 514 515/** 516 * gmc_v8_0_mc_init - initialize the memory controller driver params 517 * 518 * @adev: amdgpu_device pointer 519 * 520 * Look up the amount of vram, vram width, and decide how to place 521 * vram and gart within the GPU's physical address space (VI). 522 * Returns 0 for success. 523 */ 524static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 525{ 526 int r; 527 528 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 529 if (!adev->gmc.vram_width) { 530 u32 tmp; 531 int chansize, numchan; 532 533 /* Get VRAM informations */ 534 tmp = RREG32(mmMC_ARB_RAMCFG); 535 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 536 chansize = 64; 537 } else { 538 chansize = 32; 539 } 540 tmp = RREG32(mmMC_SHARED_CHMAP); 541 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 542 case 0: 543 default: 544 numchan = 1; 545 break; 546 case 1: 547 numchan = 2; 548 break; 549 case 2: 550 numchan = 4; 551 break; 552 case 3: 553 numchan = 8; 554 break; 555 case 4: 556 numchan = 3; 557 break; 558 case 5: 559 numchan = 6; 560 break; 561 case 6: 562 numchan = 10; 563 break; 564 case 7: 565 numchan = 12; 566 break; 567 case 8: 568 numchan = 16; 569 break; 570 } 571 adev->gmc.vram_width = numchan * chansize; 572 } 573 /* size in MB on si */ 574 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 575 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 576 577 if (!(adev->flags & AMD_IS_APU)) { 578 r = amdgpu_device_resize_fb_bar(adev); 579 if (r) 580 return r; 581 } 582 adev->gmc.aper_base = adev->fb_aper_offset; 583 adev->gmc.aper_size = adev->fb_aper_size; 584 585#ifdef CONFIG_X86_64 586 if (adev->flags & AMD_IS_APU) { 587 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 588 adev->gmc.aper_size = adev->gmc.real_vram_size; 589 } 590#endif 591 592 /* In case the PCI BAR is larger than the actual amount of vram */ 593 adev->gmc.visible_vram_size = adev->gmc.aper_size; 594 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 595 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 596 597 /* set the gart size */ 598 if (amdgpu_gart_size == -1) { 599 switch (adev->asic_type) { 600 case CHIP_POLARIS10: /* all engines support GPUVM */ 601 case CHIP_POLARIS11: /* all engines support GPUVM */ 602 case CHIP_POLARIS12: /* all engines support GPUVM */ 603 case CHIP_VEGAM: /* all engines support GPUVM */ 604 default: 605 adev->gmc.gart_size = 256ULL << 20; 606 break; 607 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ 608 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ 609 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ 610 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ 611 adev->gmc.gart_size = 1024ULL << 20; 612 break; 613 } 614 } else { 615 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 616 } 617 618 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); 619 620 return 0; 621} 622 623/** 624 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid 625 * 626 * @adev: amdgpu_device pointer 627 * @pasid: pasid to be flush 628 * 629 * Flush the TLB for the requested pasid. 630 */ 631static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 632 uint16_t pasid, uint32_t flush_type, 633 bool all_hub) 634{ 635 int vmid; 636 unsigned int tmp; 637 638 if (amdgpu_in_reset(adev)) 639 return -EIO; 640 641 for (vmid = 1; vmid < 16; vmid++) { 642 643 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 644 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 645 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { 646 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 647 RREG32(mmVM_INVALIDATE_RESPONSE); 648 break; 649 } 650 } 651 652 return 0; 653 654} 655 656/* 657 * GART 658 * VMID 0 is the physical GPU addresses as used by the kernel. 659 * VMIDs 1-15 are used for userspace clients and are handled 660 * by the amdgpu vm/hsa code. 661 */ 662 663/** 664 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback 665 * 666 * @adev: amdgpu_device pointer 667 * @vmid: vm instance to flush 668 * 669 * Flush the TLB for the requested page table (VI). 670 */ 671static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 672 uint32_t vmhub, uint32_t flush_type) 673{ 674 /* bits 0-15 are the VM contexts0-15 */ 675 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 676} 677 678static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 679 unsigned vmid, uint64_t pd_addr) 680{ 681 uint32_t reg; 682 683 if (vmid < 8) 684 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 685 else 686 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 687 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 688 689 /* bits 0-15 are the VM contexts0-15 */ 690 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 691 692 return pd_addr; 693} 694 695static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 696 unsigned pasid) 697{ 698 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 699} 700 701/* 702 * PTE format on VI: 703 * 63:40 reserved 704 * 39:12 4k physical page base address 705 * 11:7 fragment 706 * 6 write 707 * 5 read 708 * 4 exe 709 * 3 reserved 710 * 2 snooped 711 * 1 system 712 * 0 valid 713 * 714 * PDE format on VI: 715 * 63:59 block fragment size 716 * 58:40 reserved 717 * 39:1 physical base address of PTE 718 * bits 5:1 must be 0. 719 * 0 valid 720 */ 721 722static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, 723 uint64_t *addr, uint64_t *flags) 724{ 725 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 726} 727 728static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev, 729 struct amdgpu_bo_va_mapping *mapping, 730 uint64_t *flags) 731{ 732 *flags &= ~AMDGPU_PTE_EXECUTABLE; 733 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 734 *flags &= ~AMDGPU_PTE_PRT; 735} 736 737/** 738 * gmc_v8_0_set_fault_enable_default - update VM fault handling 739 * 740 * @adev: amdgpu_device pointer 741 * @value: true redirects VM faults to the default page 742 */ 743static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 744 bool value) 745{ 746 u32 tmp; 747 748 tmp = RREG32(mmVM_CONTEXT1_CNTL); 749 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 750 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 751 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 752 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 753 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 754 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 755 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 756 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 757 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 758 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 759 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 760 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 761 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 762 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 763 WREG32(mmVM_CONTEXT1_CNTL, tmp); 764} 765 766/** 767 * gmc_v8_0_set_prt - set PRT VM fault 768 * 769 * @adev: amdgpu_device pointer 770 * @enable: enable/disable VM fault handling for PRT 771*/ 772static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 773{ 774 u32 tmp; 775 776 if (enable && !adev->gmc.prt_warning) { 777 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 778 adev->gmc.prt_warning = true; 779 } 780 781 tmp = RREG32(mmVM_PRT_CNTL); 782 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 783 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 784 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 785 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 786 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 787 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 788 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 789 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 790 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 791 L2_CACHE_STORE_INVALID_ENTRIES, enable); 792 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 793 L1_TLB_STORE_INVALID_ENTRIES, enable); 794 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 795 MASK_PDE0_FAULT, enable); 796 WREG32(mmVM_PRT_CNTL, tmp); 797 798 if (enable) { 799 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 800 uint32_t high = adev->vm_manager.max_pfn - 801 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 802 803 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 804 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 805 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 806 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 807 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 808 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 809 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 810 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 811 } else { 812 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 813 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 814 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 815 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 816 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 817 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 818 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 819 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 820 } 821} 822 823/** 824 * gmc_v8_0_gart_enable - gart enable 825 * 826 * @adev: amdgpu_device pointer 827 * 828 * This sets up the TLBs, programs the page tables for VMID0, 829 * sets up the hw for VMIDs 1-15 which are allocated on 830 * demand, and sets up the global locations for the LDS, GDS, 831 * and GPUVM for FSA64 clients (VI). 832 * Returns 0 for success, errors for failure. 833 */ 834static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 835{ 836 uint64_t table_addr; 837 int r, i; 838 u32 tmp, field; 839 840 if (adev->gart.bo == NULL) { 841 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 842 return -EINVAL; 843 } 844 r = amdgpu_gart_table_vram_pin(adev); 845 if (r) 846 return r; 847 848 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 849 850 /* Setup TLB control */ 851 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 852 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 853 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 854 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 855 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 856 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 857 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 858 /* Setup L2 cache */ 859 tmp = RREG32(mmVM_L2_CNTL); 860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 863 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 864 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 865 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 867 WREG32(mmVM_L2_CNTL, tmp); 868 tmp = RREG32(mmVM_L2_CNTL2); 869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 871 WREG32(mmVM_L2_CNTL2, tmp); 872 873 field = adev->vm_manager.fragment_size; 874 tmp = RREG32(mmVM_L2_CNTL3); 875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 876 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 877 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 878 WREG32(mmVM_L2_CNTL3, tmp); 879 /* XXX: set to enable PTE/PDE in system memory */ 880 tmp = RREG32(mmVM_L2_CNTL4); 881 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 882 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 883 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 884 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 885 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 886 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 887 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 888 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 889 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 890 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 891 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 892 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 893 WREG32(mmVM_L2_CNTL4, tmp); 894 /* setup context0 */ 895 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 896 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 897 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 898 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 899 (u32)(adev->dummy_page_addr >> 12)); 900 WREG32(mmVM_CONTEXT0_CNTL2, 0); 901 tmp = RREG32(mmVM_CONTEXT0_CNTL); 902 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 903 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 904 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 905 WREG32(mmVM_CONTEXT0_CNTL, tmp); 906 907 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 908 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 909 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 910 911 /* empty context1-15 */ 912 /* FIXME start with 4G, once using 2 level pt switch to full 913 * vm size space 914 */ 915 /* set vm size, must be a multiple of 4 */ 916 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 917 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 918 for (i = 1; i < 16; i++) { 919 if (i < 8) 920 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 921 table_addr >> 12); 922 else 923 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 924 table_addr >> 12); 925 } 926 927 /* enable context1-15 */ 928 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 929 (u32)(adev->dummy_page_addr >> 12)); 930 WREG32(mmVM_CONTEXT1_CNTL2, 4); 931 tmp = RREG32(mmVM_CONTEXT1_CNTL); 932 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 933 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 934 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 935 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 936 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 937 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 938 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 939 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 940 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 941 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 942 adev->vm_manager.block_size - 9); 943 WREG32(mmVM_CONTEXT1_CNTL, tmp); 944 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 945 gmc_v8_0_set_fault_enable_default(adev, false); 946 else 947 gmc_v8_0_set_fault_enable_default(adev, true); 948 949 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0); 950 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 951 (unsigned)(adev->gmc.gart_size >> 20), 952 (unsigned long long)table_addr); 953 adev->gart.ready = true; 954 return 0; 955} 956 957static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 958{ 959 int r; 960 961 if (adev->gart.bo) { 962 WARN(1, "R600 PCIE GART already initialized\n"); 963 return 0; 964 } 965 /* Initialize common gart structure */ 966 r = amdgpu_gart_init(adev); 967 if (r) 968 return r; 969 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 970 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 971 return amdgpu_gart_table_vram_alloc(adev); 972} 973 974/** 975 * gmc_v8_0_gart_disable - gart disable 976 * 977 * @adev: amdgpu_device pointer 978 * 979 * This disables all VM page table (VI). 980 */ 981static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 982{ 983 u32 tmp; 984 985 /* Disable all tables */ 986 WREG32(mmVM_CONTEXT0_CNTL, 0); 987 WREG32(mmVM_CONTEXT1_CNTL, 0); 988 /* Setup TLB control */ 989 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 990 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 991 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 992 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 993 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 994 /* Setup L2 cache */ 995 tmp = RREG32(mmVM_L2_CNTL); 996 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 997 WREG32(mmVM_L2_CNTL, tmp); 998 WREG32(mmVM_L2_CNTL2, 0); 999 amdgpu_gart_table_vram_unpin(adev); 1000} 1001 1002/** 1003 * gmc_v8_0_vm_decode_fault - print human readable fault info 1004 * 1005 * @adev: amdgpu_device pointer 1006 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 1007 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 1008 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value 1009 * 1010 * Print human readable fault information (VI). 1011 */ 1012static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 1013 u32 addr, u32 mc_client, unsigned pasid) 1014{ 1015 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 1016 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1017 PROTECTIONS); 1018 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 1019 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 1020 u32 mc_id; 1021 1022 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1023 MEMORY_CLIENT_ID); 1024 1025 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 1026 protections, vmid, pasid, addr, 1027 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1028 MEMORY_CLIENT_RW) ? 1029 "write" : "read", block, mc_client, mc_id); 1030} 1031 1032static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 1033{ 1034 switch (mc_seq_vram_type) { 1035 case MC_SEQ_MISC0__MT__GDDR1: 1036 return AMDGPU_VRAM_TYPE_GDDR1; 1037 case MC_SEQ_MISC0__MT__DDR2: 1038 return AMDGPU_VRAM_TYPE_DDR2; 1039 case MC_SEQ_MISC0__MT__GDDR3: 1040 return AMDGPU_VRAM_TYPE_GDDR3; 1041 case MC_SEQ_MISC0__MT__GDDR4: 1042 return AMDGPU_VRAM_TYPE_GDDR4; 1043 case MC_SEQ_MISC0__MT__GDDR5: 1044 return AMDGPU_VRAM_TYPE_GDDR5; 1045 case MC_SEQ_MISC0__MT__HBM: 1046 return AMDGPU_VRAM_TYPE_HBM; 1047 case MC_SEQ_MISC0__MT__DDR3: 1048 return AMDGPU_VRAM_TYPE_DDR3; 1049 default: 1050 return AMDGPU_VRAM_TYPE_UNKNOWN; 1051 } 1052} 1053 1054static int gmc_v8_0_early_init(void *handle) 1055{ 1056 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1057 1058 gmc_v8_0_set_gmc_funcs(adev); 1059 gmc_v8_0_set_irq_funcs(adev); 1060 1061 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1062 adev->gmc.shared_aperture_end = 1063 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1064 adev->gmc.private_aperture_start = 1065 adev->gmc.shared_aperture_end + 1; 1066 adev->gmc.private_aperture_end = 1067 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1068 1069 return 0; 1070} 1071 1072static int gmc_v8_0_late_init(void *handle) 1073{ 1074 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1075 1076 amdgpu_bo_late_init(adev); 1077 1078 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1079 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1080 else 1081 return 0; 1082} 1083 1084static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) 1085{ 1086 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 1087 unsigned size; 1088 1089 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1090 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1091 } else { 1092 u32 viewport = RREG32(mmVIEWPORT_SIZE); 1093 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1094 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1095 4); 1096 } 1097 1098 return size; 1099} 1100 1101#define mmMC_SEQ_MISC0_FIJI 0xA71 1102 1103static int gmc_v8_0_sw_init(void *handle) 1104{ 1105 int r; 1106 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1107 1108 adev->num_vmhubs = 1; 1109 1110 if (adev->flags & AMD_IS_APU) { 1111 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1112 } else { 1113 u32 tmp; 1114 1115 if ((adev->asic_type == CHIP_FIJI) || 1116 (adev->asic_type == CHIP_VEGAM)) 1117 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1118 else 1119 tmp = RREG32(mmMC_SEQ_MISC0); 1120 tmp &= MC_SEQ_MISC0__MT__MASK; 1121 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1122 } 1123 1124 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1125 if (r) 1126 return r; 1127 1128 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1129 if (r) 1130 return r; 1131 1132 /* Adjust VM size here. 1133 * Currently set to 4GB ((1 << 20) 4k pages). 1134 * Max GPUVM size for cayman and SI is 40 bits. 1135 */ 1136 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1137 1138 /* Set the internal MC address mask 1139 * This is the max address of the GPU's 1140 * internal address space. 1141 */ 1142 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1143 1144 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 1145 if (r) { 1146 pr_warn("No suitable DMA available\n"); 1147 return r; 1148 } 1149 adev->need_swiotlb = drm_need_swiotlb(40); 1150 1151 r = gmc_v8_0_init_microcode(adev); 1152 if (r) { 1153 DRM_ERROR("Failed to load mc firmware!\n"); 1154 return r; 1155 } 1156 1157 r = gmc_v8_0_mc_init(adev); 1158 if (r) 1159 return r; 1160 1161 amdgpu_gmc_get_vbios_allocations(adev); 1162 1163 /* Memory manager */ 1164 r = amdgpu_bo_init(adev); 1165 if (r) 1166 return r; 1167 1168 r = gmc_v8_0_gart_init(adev); 1169 if (r) 1170 return r; 1171 1172 /* 1173 * number of VMs 1174 * VMID 0 is reserved for System 1175 * amdgpu graphics/compute will use VMIDs 1-7 1176 * amdkfd will use VMIDs 8-15 1177 */ 1178 adev->vm_manager.first_kfd_vmid = 8; 1179 amdgpu_vm_manager_init(adev); 1180 1181 /* base offset of vram pages */ 1182 if (adev->flags & AMD_IS_APU) { 1183 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1184 1185 tmp <<= 22; 1186 adev->vm_manager.vram_base_offset = tmp; 1187 } else { 1188 adev->vm_manager.vram_base_offset = 0; 1189 } 1190 1191 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1192 GFP_KERNEL); 1193 if (!adev->gmc.vm_fault_info) 1194 return -ENOMEM; 1195 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1196 1197 return 0; 1198} 1199 1200static int gmc_v8_0_sw_fini(void *handle) 1201{ 1202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1203 1204 amdgpu_gem_force_release(adev); 1205 amdgpu_vm_manager_fini(adev); 1206 kfree(adev->gmc.vm_fault_info); 1207 amdgpu_gart_table_vram_free(adev); 1208 amdgpu_bo_fini(adev); 1209 amdgpu_gart_fini(adev); 1210 release_firmware(adev->gmc.fw); 1211 adev->gmc.fw = NULL; 1212 1213 return 0; 1214} 1215 1216static int gmc_v8_0_hw_init(void *handle) 1217{ 1218 int r; 1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1220 1221 gmc_v8_0_init_golden_registers(adev); 1222 1223 gmc_v8_0_mc_program(adev); 1224 1225 if (adev->asic_type == CHIP_TONGA) { 1226 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1227 if (r) { 1228 DRM_ERROR("Failed to load MC firmware!\n"); 1229 return r; 1230 } 1231 } else if (adev->asic_type == CHIP_POLARIS11 || 1232 adev->asic_type == CHIP_POLARIS10 || 1233 adev->asic_type == CHIP_POLARIS12) { 1234 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1235 if (r) { 1236 DRM_ERROR("Failed to load MC firmware!\n"); 1237 return r; 1238 } 1239 } 1240 1241 r = gmc_v8_0_gart_enable(adev); 1242 if (r) 1243 return r; 1244 1245 return r; 1246} 1247 1248static int gmc_v8_0_hw_fini(void *handle) 1249{ 1250 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1251 1252 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1253 gmc_v8_0_gart_disable(adev); 1254 1255 return 0; 1256} 1257 1258static int gmc_v8_0_suspend(void *handle) 1259{ 1260 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1261 1262 gmc_v8_0_hw_fini(adev); 1263 1264 return 0; 1265} 1266 1267static int gmc_v8_0_resume(void *handle) 1268{ 1269 int r; 1270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1271 1272 r = gmc_v8_0_hw_init(adev); 1273 if (r) 1274 return r; 1275 1276 amdgpu_vmid_reset_all(adev); 1277 1278 return 0; 1279} 1280 1281static bool gmc_v8_0_is_idle(void *handle) 1282{ 1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1284 u32 tmp = RREG32(mmSRBM_STATUS); 1285 1286 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1287 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1288 return false; 1289 1290 return true; 1291} 1292 1293static int gmc_v8_0_wait_for_idle(void *handle) 1294{ 1295 unsigned i; 1296 u32 tmp; 1297 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1298 1299 for (i = 0; i < adev->usec_timeout; i++) { 1300 /* read MC_STATUS */ 1301 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1302 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1303 SRBM_STATUS__MCC_BUSY_MASK | 1304 SRBM_STATUS__MCD_BUSY_MASK | 1305 SRBM_STATUS__VMC_BUSY_MASK | 1306 SRBM_STATUS__VMC1_BUSY_MASK); 1307 if (!tmp) 1308 return 0; 1309 udelay(1); 1310 } 1311 return -ETIMEDOUT; 1312 1313} 1314 1315static bool gmc_v8_0_check_soft_reset(void *handle) 1316{ 1317 u32 srbm_soft_reset = 0; 1318 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1319 u32 tmp = RREG32(mmSRBM_STATUS); 1320 1321 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1322 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1323 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1324 1325 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1326 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1327 if (!(adev->flags & AMD_IS_APU)) 1328 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1329 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1330 } 1331 if (srbm_soft_reset) { 1332 adev->gmc.srbm_soft_reset = srbm_soft_reset; 1333 return true; 1334 } else { 1335 adev->gmc.srbm_soft_reset = 0; 1336 return false; 1337 } 1338} 1339 1340static int gmc_v8_0_pre_soft_reset(void *handle) 1341{ 1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1343 1344 if (!adev->gmc.srbm_soft_reset) 1345 return 0; 1346 1347 gmc_v8_0_mc_stop(adev); 1348 if (gmc_v8_0_wait_for_idle(adev)) { 1349 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1350 } 1351 1352 return 0; 1353} 1354 1355static int gmc_v8_0_soft_reset(void *handle) 1356{ 1357 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1358 u32 srbm_soft_reset; 1359 1360 if (!adev->gmc.srbm_soft_reset) 1361 return 0; 1362 srbm_soft_reset = adev->gmc.srbm_soft_reset; 1363 1364 if (srbm_soft_reset) { 1365 u32 tmp; 1366 1367 tmp = RREG32(mmSRBM_SOFT_RESET); 1368 tmp |= srbm_soft_reset; 1369 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1370 WREG32(mmSRBM_SOFT_RESET, tmp); 1371 tmp = RREG32(mmSRBM_SOFT_RESET); 1372 1373 udelay(50); 1374 1375 tmp &= ~srbm_soft_reset; 1376 WREG32(mmSRBM_SOFT_RESET, tmp); 1377 tmp = RREG32(mmSRBM_SOFT_RESET); 1378 1379 /* Wait a little for things to settle down */ 1380 udelay(50); 1381 } 1382 1383 return 0; 1384} 1385 1386static int gmc_v8_0_post_soft_reset(void *handle) 1387{ 1388 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1389 1390 if (!adev->gmc.srbm_soft_reset) 1391 return 0; 1392 1393 gmc_v8_0_mc_resume(adev); 1394 return 0; 1395} 1396 1397static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1398 struct amdgpu_irq_src *src, 1399 unsigned type, 1400 enum amdgpu_interrupt_state state) 1401{ 1402 u32 tmp; 1403 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1404 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1405 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1406 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1407 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1408 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1409 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1410 1411 switch (state) { 1412 case AMDGPU_IRQ_STATE_DISABLE: 1413 /* system context */ 1414 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1415 tmp &= ~bits; 1416 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1417 /* VMs */ 1418 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1419 tmp &= ~bits; 1420 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1421 break; 1422 case AMDGPU_IRQ_STATE_ENABLE: 1423 /* system context */ 1424 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1425 tmp |= bits; 1426 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1427 /* VMs */ 1428 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1429 tmp |= bits; 1430 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1431 break; 1432 default: 1433 break; 1434 } 1435 1436 return 0; 1437} 1438 1439static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1440 struct amdgpu_irq_src *source, 1441 struct amdgpu_iv_entry *entry) 1442{ 1443 u32 addr, status, mc_client, vmid; 1444 1445 if (amdgpu_sriov_vf(adev)) { 1446 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1447 entry->src_id, entry->src_data[0]); 1448 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1449 return 0; 1450 } 1451 1452 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1453 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1454 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1455 /* reset addr and status */ 1456 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1457 1458 if (!addr && !status) 1459 return 0; 1460 1461 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1462 gmc_v8_0_set_fault_enable_default(adev, false); 1463 1464 if (printk_ratelimit()) { 1465 struct amdgpu_task_info task_info; 1466 1467 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 1468 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 1469 1470 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n", 1471 entry->src_id, entry->src_data[0], task_info.process_name, 1472 task_info.tgid, task_info.task_name, task_info.pid); 1473 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1474 addr); 1475 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1476 status); 1477 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client, 1478 entry->pasid); 1479 } 1480 1481 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1482 VMID); 1483 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1484 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1485 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1486 u32 protections = REG_GET_FIELD(status, 1487 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1488 PROTECTIONS); 1489 1490 info->vmid = vmid; 1491 info->mc_id = REG_GET_FIELD(status, 1492 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1493 MEMORY_CLIENT_ID); 1494 info->status = status; 1495 info->page_addr = addr; 1496 info->prot_valid = protections & 0x7 ? true : false; 1497 info->prot_read = protections & 0x8 ? true : false; 1498 info->prot_write = protections & 0x10 ? true : false; 1499 info->prot_exec = protections & 0x20 ? true : false; 1500 mb(); 1501 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1502 } 1503 1504 return 0; 1505} 1506 1507static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1508 bool enable) 1509{ 1510 uint32_t data; 1511 1512 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1513 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1514 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1515 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1516 1517 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1518 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1519 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1520 1521 data = RREG32(mmMC_HUB_MISC_VM_CG); 1522 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1523 WREG32(mmMC_HUB_MISC_VM_CG, data); 1524 1525 data = RREG32(mmMC_XPB_CLK_GAT); 1526 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1527 WREG32(mmMC_XPB_CLK_GAT, data); 1528 1529 data = RREG32(mmATC_MISC_CG); 1530 data |= ATC_MISC_CG__ENABLE_MASK; 1531 WREG32(mmATC_MISC_CG, data); 1532 1533 data = RREG32(mmMC_CITF_MISC_WR_CG); 1534 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1535 WREG32(mmMC_CITF_MISC_WR_CG, data); 1536 1537 data = RREG32(mmMC_CITF_MISC_RD_CG); 1538 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1539 WREG32(mmMC_CITF_MISC_RD_CG, data); 1540 1541 data = RREG32(mmMC_CITF_MISC_VM_CG); 1542 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1543 WREG32(mmMC_CITF_MISC_VM_CG, data); 1544 1545 data = RREG32(mmVM_L2_CG); 1546 data |= VM_L2_CG__ENABLE_MASK; 1547 WREG32(mmVM_L2_CG, data); 1548 } else { 1549 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1550 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1551 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1552 1553 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1554 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1555 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1556 1557 data = RREG32(mmMC_HUB_MISC_VM_CG); 1558 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1559 WREG32(mmMC_HUB_MISC_VM_CG, data); 1560 1561 data = RREG32(mmMC_XPB_CLK_GAT); 1562 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1563 WREG32(mmMC_XPB_CLK_GAT, data); 1564 1565 data = RREG32(mmATC_MISC_CG); 1566 data &= ~ATC_MISC_CG__ENABLE_MASK; 1567 WREG32(mmATC_MISC_CG, data); 1568 1569 data = RREG32(mmMC_CITF_MISC_WR_CG); 1570 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1571 WREG32(mmMC_CITF_MISC_WR_CG, data); 1572 1573 data = RREG32(mmMC_CITF_MISC_RD_CG); 1574 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1575 WREG32(mmMC_CITF_MISC_RD_CG, data); 1576 1577 data = RREG32(mmMC_CITF_MISC_VM_CG); 1578 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1579 WREG32(mmMC_CITF_MISC_VM_CG, data); 1580 1581 data = RREG32(mmVM_L2_CG); 1582 data &= ~VM_L2_CG__ENABLE_MASK; 1583 WREG32(mmVM_L2_CG, data); 1584 } 1585} 1586 1587static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1588 bool enable) 1589{ 1590 uint32_t data; 1591 1592 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1593 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1594 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1595 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1596 1597 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1598 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1599 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1600 1601 data = RREG32(mmMC_HUB_MISC_VM_CG); 1602 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1603 WREG32(mmMC_HUB_MISC_VM_CG, data); 1604 1605 data = RREG32(mmMC_XPB_CLK_GAT); 1606 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1607 WREG32(mmMC_XPB_CLK_GAT, data); 1608 1609 data = RREG32(mmATC_MISC_CG); 1610 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1611 WREG32(mmATC_MISC_CG, data); 1612 1613 data = RREG32(mmMC_CITF_MISC_WR_CG); 1614 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1615 WREG32(mmMC_CITF_MISC_WR_CG, data); 1616 1617 data = RREG32(mmMC_CITF_MISC_RD_CG); 1618 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1619 WREG32(mmMC_CITF_MISC_RD_CG, data); 1620 1621 data = RREG32(mmMC_CITF_MISC_VM_CG); 1622 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1623 WREG32(mmMC_CITF_MISC_VM_CG, data); 1624 1625 data = RREG32(mmVM_L2_CG); 1626 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1627 WREG32(mmVM_L2_CG, data); 1628 } else { 1629 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1630 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1631 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1632 1633 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1634 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1635 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1636 1637 data = RREG32(mmMC_HUB_MISC_VM_CG); 1638 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1639 WREG32(mmMC_HUB_MISC_VM_CG, data); 1640 1641 data = RREG32(mmMC_XPB_CLK_GAT); 1642 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1643 WREG32(mmMC_XPB_CLK_GAT, data); 1644 1645 data = RREG32(mmATC_MISC_CG); 1646 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1647 WREG32(mmATC_MISC_CG, data); 1648 1649 data = RREG32(mmMC_CITF_MISC_WR_CG); 1650 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1651 WREG32(mmMC_CITF_MISC_WR_CG, data); 1652 1653 data = RREG32(mmMC_CITF_MISC_RD_CG); 1654 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1655 WREG32(mmMC_CITF_MISC_RD_CG, data); 1656 1657 data = RREG32(mmMC_CITF_MISC_VM_CG); 1658 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1659 WREG32(mmMC_CITF_MISC_VM_CG, data); 1660 1661 data = RREG32(mmVM_L2_CG); 1662 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1663 WREG32(mmVM_L2_CG, data); 1664 } 1665} 1666 1667static int gmc_v8_0_set_clockgating_state(void *handle, 1668 enum amd_clockgating_state state) 1669{ 1670 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1671 1672 if (amdgpu_sriov_vf(adev)) 1673 return 0; 1674 1675 switch (adev->asic_type) { 1676 case CHIP_FIJI: 1677 fiji_update_mc_medium_grain_clock_gating(adev, 1678 state == AMD_CG_STATE_GATE); 1679 fiji_update_mc_light_sleep(adev, 1680 state == AMD_CG_STATE_GATE); 1681 break; 1682 default: 1683 break; 1684 } 1685 return 0; 1686} 1687 1688static int gmc_v8_0_set_powergating_state(void *handle, 1689 enum amd_powergating_state state) 1690{ 1691 return 0; 1692} 1693 1694static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags) 1695{ 1696 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1697 int data; 1698 1699 if (amdgpu_sriov_vf(adev)) 1700 *flags = 0; 1701 1702 /* AMD_CG_SUPPORT_MC_MGCG */ 1703 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1704 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1705 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1706 1707 /* AMD_CG_SUPPORT_MC_LS */ 1708 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1709 *flags |= AMD_CG_SUPPORT_MC_LS; 1710} 1711 1712static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1713 .name = "gmc_v8_0", 1714 .early_init = gmc_v8_0_early_init, 1715 .late_init = gmc_v8_0_late_init, 1716 .sw_init = gmc_v8_0_sw_init, 1717 .sw_fini = gmc_v8_0_sw_fini, 1718 .hw_init = gmc_v8_0_hw_init, 1719 .hw_fini = gmc_v8_0_hw_fini, 1720 .suspend = gmc_v8_0_suspend, 1721 .resume = gmc_v8_0_resume, 1722 .is_idle = gmc_v8_0_is_idle, 1723 .wait_for_idle = gmc_v8_0_wait_for_idle, 1724 .check_soft_reset = gmc_v8_0_check_soft_reset, 1725 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1726 .soft_reset = gmc_v8_0_soft_reset, 1727 .post_soft_reset = gmc_v8_0_post_soft_reset, 1728 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1729 .set_powergating_state = gmc_v8_0_set_powergating_state, 1730 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1731}; 1732 1733static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { 1734 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb, 1735 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid, 1736 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, 1737 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, 1738 .set_prt = gmc_v8_0_set_prt, 1739 .get_vm_pde = gmc_v8_0_get_vm_pde, 1740 .get_vm_pte = gmc_v8_0_get_vm_pte, 1741 .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size, 1742}; 1743 1744static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1745 .set = gmc_v8_0_vm_fault_interrupt_state, 1746 .process = gmc_v8_0_process_interrupt, 1747}; 1748 1749static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) 1750{ 1751 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; 1752} 1753 1754static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1755{ 1756 adev->gmc.vm_fault.num_types = 1; 1757 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1758} 1759 1760const struct amdgpu_ip_block_version gmc_v8_0_ip_block = 1761{ 1762 .type = AMD_IP_BLOCK_TYPE_GMC, 1763 .major = 8, 1764 .minor = 0, 1765 .rev = 0, 1766 .funcs = &gmc_v8_0_ip_funcs, 1767}; 1768 1769const struct amdgpu_ip_block_version gmc_v8_1_ip_block = 1770{ 1771 .type = AMD_IP_BLOCK_TYPE_GMC, 1772 .major = 8, 1773 .minor = 1, 1774 .rev = 0, 1775 .funcs = &gmc_v8_0_ip_funcs, 1776}; 1777 1778const struct amdgpu_ip_block_version gmc_v8_5_ip_block = 1779{ 1780 .type = AMD_IP_BLOCK_TYPE_GMC, 1781 .major = 8, 1782 .minor = 5, 1783 .rev = 0, 1784 .funcs = &gmc_v8_0_ip_funcs, 1785}; 1786