1169689Skan/*
2169689Skan * Copyright 2019 Advanced Micro Devices, Inc.
3169689Skan *
4169689Skan * Permission is hereby granted, free of charge, to any person obtaining a
5169689Skan * copy of this software and associated documentation files (the "Software"),
6169689Skan * to deal in the Software without restriction, including without limitation
7169689Skan * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8169689Skan * and/or sell copies of the Software, and to permit persons to whom the
9169689Skan * Software is furnished to do so, subject to the following conditions:
10169689Skan *
11169689Skan * The above copyright notice and this permission notice shall be included in
12169689Skan * all copies or substantial portions of the Software.
13169689Skan *
14169689Skan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15169689Skan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16169689Skan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17169689Skan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18169689Skan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19169689Skan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20169689Skan * OTHER DEALINGS IN THE SOFTWARE.
21169689Skan *
22169689Skan */
23169689Skan
24169689Skan#include "amdgpu.h"
25169689Skan#include "athub_v2_1.h"
26169689Skan
27169689Skan#include "athub/athub_2_1_0_offset.h"
28169689Skan#include "athub/athub_2_1_0_sh_mask.h"
29169689Skan
30169689Skan#include "soc15_common.h"
31169689Skan
32169689Skanstatic void
33169689Skanathub_v2_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
34169689Skan					    bool enable)
35169689Skan{
36169689Skan	uint32_t def, data;
37169689Skan
38169689Skan	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
39169689Skan
40169689Skan	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
41169689Skan		data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
42169689Skan	else
43169689Skan		data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
44169689Skan
45169689Skan	if (def != data)
46169689Skan		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
47}
48
49static void
50athub_v2_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
51					   bool enable)
52{
53	uint32_t def, data;
54
55	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
56
57	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
58	    (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
59		data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
60	else
61		data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
62
63	if(def != data)
64		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
65}
66
67int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
68			       enum amd_clockgating_state state)
69{
70	if (amdgpu_sriov_vf(adev))
71		return 0;
72
73	switch (adev->ip_versions[ATHUB_HWIP][0]) {
74	case IP_VERSION(2, 1, 0):
75	case IP_VERSION(2, 1, 1):
76	case IP_VERSION(2, 1, 2):
77	case IP_VERSION(2, 4, 0):
78		athub_v2_1_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE);
79		athub_v2_1_update_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE);
80		break;
81	default:
82		break;
83	}
84
85	return 0;
86}
87
88void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u64 *flags)
89{
90	int data;
91
92	/* AMD_CG_SUPPORT_ATHUB_MGCG */
93	data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
94	if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
95		*flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
96
97	/* AMD_CG_SUPPORT_ATHUB_LS */
98	if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
99		*flags |= AMD_CG_SUPPORT_ATHUB_LS;
100}
101