1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian K��nig 23 */ 24#ifndef __AMDGPU_RING_H__ 25#define __AMDGPU_RING_H__ 26 27#include <drm/amdgpu_drm.h> 28#include <drm/gpu_scheduler.h> 29#include <drm/drm_print.h> 30#include <drm/drm_suballoc.h> 31 32struct amdgpu_device; 33struct amdgpu_ring; 34struct amdgpu_ib; 35struct amdgpu_cs_parser; 36struct amdgpu_job; 37struct amdgpu_vm; 38 39/* max number of rings */ 40#define AMDGPU_MAX_RINGS 124 41#define AMDGPU_MAX_HWIP_RINGS 64 42#define AMDGPU_MAX_GFX_RINGS 2 43#define AMDGPU_MAX_SW_GFX_RINGS 2 44#define AMDGPU_MAX_COMPUTE_RINGS 8 45#define AMDGPU_MAX_VCE_RINGS 3 46#define AMDGPU_MAX_UVD_ENC_RINGS 2 47 48enum amdgpu_ring_priority_level { 49 AMDGPU_RING_PRIO_0, 50 AMDGPU_RING_PRIO_1, 51 AMDGPU_RING_PRIO_DEFAULT = 1, 52 AMDGPU_RING_PRIO_2, 53 AMDGPU_RING_PRIO_MAX 54}; 55 56/* some special values for the owner field */ 57#define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) 58#define AMDGPU_FENCE_OWNER_VM ((void *)1ul) 59#define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) 60 61#define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 62#define AMDGPU_FENCE_FLAG_INT (1 << 1) 63#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) 64#define AMDGPU_FENCE_FLAG_EXEC (1 << 3) 65 66#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) 67 68#define AMDGPU_IB_POOL_SIZE (1024 * 1024) 69 70enum amdgpu_ring_type { 71 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX, 72 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE, 73 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA, 74 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD, 75 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE, 76 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC, 77 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC, 78 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC, 79 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG, 80 AMDGPU_RING_TYPE_KIQ, 81 AMDGPU_RING_TYPE_MES 82}; 83 84enum amdgpu_ib_pool_type { 85 /* Normal submissions to the top of the pipeline. */ 86 AMDGPU_IB_POOL_DELAYED, 87 /* Immediate submissions to the bottom of the pipeline. */ 88 AMDGPU_IB_POOL_IMMEDIATE, 89 /* Direct submission to the ring buffer during init and reset. */ 90 AMDGPU_IB_POOL_DIRECT, 91 92 AMDGPU_IB_POOL_MAX 93}; 94 95struct amdgpu_ib { 96 struct drm_suballoc *sa_bo; 97 uint32_t length_dw; 98 uint64_t gpu_addr; 99 uint32_t *ptr; 100 uint32_t flags; 101}; 102 103struct amdgpu_sched { 104 u32 num_scheds; 105 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS]; 106}; 107 108/* 109 * Fences. 110 */ 111struct amdgpu_fence_driver { 112 uint64_t gpu_addr; 113 volatile uint32_t *cpu_addr; 114 /* sync_seq is protected by ring emission lock */ 115 uint32_t sync_seq; 116 atomic_t last_seq; 117 bool initialized; 118 struct amdgpu_irq_src *irq_src; 119 unsigned irq_type; 120 struct timeout fallback_timer; 121 unsigned num_fences_mask; 122 spinlock_t lock; 123 struct dma_fence **fences; 124}; 125 126extern const struct drm_sched_backend_ops amdgpu_sched_ops; 127 128void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring); 129void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); 130void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 131 132int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 133int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 134 struct amdgpu_irq_src *irq_src, 135 unsigned irq_type); 136void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev); 137void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev); 138int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev); 139void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev); 140int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job, 141 unsigned flags); 142int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, 143 uint32_t timeout); 144bool amdgpu_fence_process(struct amdgpu_ring *ring); 145int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 146signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 147 uint32_t wait_seq, 148 signed long timeout); 149unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 150 151void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop); 152 153u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring); 154void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, 155 ktime_t timestamp); 156 157/* 158 * Rings. 159 */ 160 161/* provided by hw blocks that expose a ring buffer for commands */ 162struct amdgpu_ring_funcs { 163 enum amdgpu_ring_type type; 164 uint32_t align_mask; 165 u32 nop; 166 bool support_64bit_ptrs; 167 bool no_user_fence; 168 bool secure_submission_supported; 169 unsigned extra_dw; 170 171 /* ring read/write ptr handling */ 172 u64 (*get_rptr)(struct amdgpu_ring *ring); 173 u64 (*get_wptr)(struct amdgpu_ring *ring); 174 void (*set_wptr)(struct amdgpu_ring *ring); 175 /* validating and patching of IBs */ 176 int (*parse_cs)(struct amdgpu_cs_parser *p, 177 struct amdgpu_job *job, 178 struct amdgpu_ib *ib); 179 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, 180 struct amdgpu_job *job, 181 struct amdgpu_ib *ib); 182 /* constants to calculate how many DW are needed for an emit */ 183 unsigned emit_frame_size; 184 unsigned emit_ib_size; 185 /* command emit functions */ 186 void (*emit_ib)(struct amdgpu_ring *ring, 187 struct amdgpu_job *job, 188 struct amdgpu_ib *ib, 189 uint32_t flags); 190 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 191 uint64_t seq, unsigned flags); 192 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 193 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 194 uint64_t pd_addr); 195 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 196 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 197 uint32_t gds_base, uint32_t gds_size, 198 uint32_t gws_base, uint32_t gws_size, 199 uint32_t oa_base, uint32_t oa_size); 200 /* testing functions */ 201 int (*test_ring)(struct amdgpu_ring *ring); 202 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 203 /* insert NOP packets */ 204 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 205 void (*insert_start)(struct amdgpu_ring *ring); 206 void (*insert_end)(struct amdgpu_ring *ring); 207 /* pad the indirect buffer to the necessary number of dw */ 208 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 209 unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 210 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 211 /* note usage for clock and power gating */ 212 void (*begin_use)(struct amdgpu_ring *ring); 213 void (*end_use)(struct amdgpu_ring *ring); 214 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 215 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 216 void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va, 217 u64 gds_va, bool init_shadow, int vmid); 218 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg, 219 uint32_t reg_val_offs); 220 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 221 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, 222 uint32_t val, uint32_t mask); 223 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, 224 uint32_t reg0, uint32_t reg1, 225 uint32_t ref, uint32_t mask); 226 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start, 227 bool secure); 228 /* Try to soft recover the ring to make the fence signal */ 229 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); 230 int (*preempt_ib)(struct amdgpu_ring *ring); 231 void (*emit_mem_sync)(struct amdgpu_ring *ring); 232 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable); 233 void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset); 234 void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset); 235 void (*patch_de)(struct amdgpu_ring *ring, unsigned offset); 236}; 237 238struct amdgpu_ring { 239 struct amdgpu_device *adev; 240 const struct amdgpu_ring_funcs *funcs; 241 struct amdgpu_fence_driver fence_drv; 242 struct drm_gpu_scheduler sched; 243 244 struct amdgpu_bo *ring_obj; 245 volatile uint32_t *ring; 246 unsigned rptr_offs; 247 u64 rptr_gpu_addr; 248 volatile u32 *rptr_cpu_addr; 249 u64 wptr; 250 u64 wptr_old; 251 unsigned ring_size; 252 unsigned max_dw; 253 int count_dw; 254 uint64_t gpu_addr; 255 uint64_t ptr_mask; 256 uint32_t buf_mask; 257 u32 idx; 258 u32 xcc_id; 259 u32 xcp_id; 260 u32 me; 261 u32 pipe; 262 u32 queue; 263 struct amdgpu_bo *mqd_obj; 264 uint64_t mqd_gpu_addr; 265 void *mqd_ptr; 266 unsigned mqd_size; 267 uint64_t eop_gpu_addr; 268 u32 doorbell_index; 269 bool use_doorbell; 270 bool use_pollmem; 271 unsigned wptr_offs; 272 u64 wptr_gpu_addr; 273 volatile u32 *wptr_cpu_addr; 274 unsigned fence_offs; 275 u64 fence_gpu_addr; 276 volatile u32 *fence_cpu_addr; 277 uint64_t current_ctx; 278 char name[16]; 279 u32 trail_seq; 280 unsigned trail_fence_offs; 281 u64 trail_fence_gpu_addr; 282 volatile u32 *trail_fence_cpu_addr; 283 unsigned cond_exe_offs; 284 u64 cond_exe_gpu_addr; 285 volatile u32 *cond_exe_cpu_addr; 286 unsigned vm_hub; 287 unsigned vm_inv_eng; 288 struct dma_fence *vmid_wait; 289 bool has_compute_vm_bug; 290 bool no_scheduler; 291 int hw_prio; 292 unsigned num_hw_submission; 293 atomic_t *sched_score; 294 295 /* used for mes */ 296 bool is_mes_queue; 297 uint32_t hw_queue_id; 298 struct amdgpu_mes_ctx_data *mes_ctx; 299 300 bool is_sw_ring; 301 unsigned int entry_index; 302 303}; 304 305#define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib))) 306#define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib))) 307#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 308#define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0) 309#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 310#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 311#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 312#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags))) 313#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 314#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 315#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 316#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 317#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 318#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 319#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 320#define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v))) 321#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o)) 322#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 323#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) 324#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) 325#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s)) 326#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 327#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 328#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 329#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) 330#define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o))) 331#define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o))) 332#define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o))) 333 334unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type); 335int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 336void amdgpu_ring_ib_begin(struct amdgpu_ring *ring); 337void amdgpu_ring_ib_end(struct amdgpu_ring *ring); 338void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring); 339void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring); 340void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring); 341 342void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 343void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 344void amdgpu_ring_commit(struct amdgpu_ring *ring); 345void amdgpu_ring_undo(struct amdgpu_ring *ring); 346int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 347 unsigned int max_dw, struct amdgpu_irq_src *irq_src, 348 unsigned int irq_type, unsigned int hw_prio, 349 atomic_t *sched_score); 350void amdgpu_ring_fini(struct amdgpu_ring *ring); 351void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 352 uint32_t reg0, uint32_t val0, 353 uint32_t reg1, uint32_t val1); 354bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 355 struct dma_fence *fence); 356 357static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, 358 bool cond_exec) 359{ 360 *ring->cond_exe_cpu_addr = cond_exec; 361} 362 363static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 364{ 365 int i = 0; 366 while (i <= ring->buf_mask) 367 ring->ring[i++] = ring->funcs->nop; 368 369} 370 371static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 372{ 373 if (ring->count_dw <= 0) 374 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 375 ring->ring[ring->wptr++ & ring->buf_mask] = v; 376 ring->wptr &= ring->ptr_mask; 377 ring->count_dw--; 378} 379 380static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 381 void *src, int count_dw) 382{ 383 unsigned occupied, chunk1, chunk2; 384 void *dst; 385 386 if (unlikely(ring->count_dw < count_dw)) 387 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 388 389 occupied = ring->wptr & ring->buf_mask; 390 dst = (void *)&ring->ring[occupied]; 391 chunk1 = ring->buf_mask + 1 - occupied; 392 chunk1 = (chunk1 >= count_dw) ? count_dw : chunk1; 393 chunk2 = count_dw - chunk1; 394 chunk1 <<= 2; 395 chunk2 <<= 2; 396 397 if (chunk1) 398 memcpy(dst, src, chunk1); 399 400 if (chunk2) { 401 src += chunk1; 402 dst = (void *)ring->ring; 403 memcpy(dst, src, chunk2); 404 } 405 406 ring->wptr += count_dw; 407 ring->wptr &= ring->ptr_mask; 408 ring->count_dw -= count_dw; 409} 410 411#define amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset) \ 412 (ring->is_mes_queue && ring->mes_ctx ? \ 413 (ring->mes_ctx->meta_data_gpu_addr + offset) : 0) 414 415#define amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset) \ 416 (ring->is_mes_queue && ring->mes_ctx ? \ 417 (void *)((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : \ 418 NULL) 419 420int amdgpu_ring_test_helper(struct amdgpu_ring *ring); 421 422void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 423 struct amdgpu_ring *ring); 424 425int amdgpu_ring_init_mqd(struct amdgpu_ring *ring); 426 427static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx) 428{ 429 return ib->ptr[idx]; 430} 431 432static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx, 433 uint32_t value) 434{ 435 ib->ptr[idx] = value; 436} 437 438int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 439 unsigned size, 440 enum amdgpu_ib_pool_type pool, 441 struct amdgpu_ib *ib); 442void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 443 struct dma_fence *f); 444int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 445 struct amdgpu_ib *ibs, struct amdgpu_job *job, 446 struct dma_fence **f); 447int amdgpu_ib_pool_init(struct amdgpu_device *adev); 448void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 449int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 450 451#endif 452