amdgpu_atom.c revision 1.5
1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Stanislaw Skowronek 23 */ 24 25#include <linux/module.h> 26#include <linux/sched.h> 27#include <linux/slab.h> 28#include <asm/unaligned.h> 29 30#include <drm/drm_util.h> 31 32#define ATOM_DEBUG 33 34#include "atom.h" 35#include "atom-names.h" 36#include "atom-bits.h" 37#include "amdgpu.h" 38 39#define ATOM_COND_ABOVE 0 40#define ATOM_COND_ABOVEOREQUAL 1 41#define ATOM_COND_ALWAYS 2 42#define ATOM_COND_BELOW 3 43#define ATOM_COND_BELOWOREQUAL 4 44#define ATOM_COND_EQUAL 5 45#define ATOM_COND_NOTEQUAL 6 46 47#define ATOM_PORT_ATI 0 48#define ATOM_PORT_PCI 1 49#define ATOM_PORT_SYSIO 2 50 51#define ATOM_UNIT_MICROSEC 0 52#define ATOM_UNIT_MILLISEC 1 53 54#define PLL_INDEX 2 55#define PLL_DATA 3 56 57#define ATOM_CMD_TIMEOUT_SEC 20 58 59typedef struct { 60 struct atom_context *ctx; 61 uint32_t *ps, *ws; 62 int ps_shift; 63 uint16_t start; 64 unsigned last_jump; 65 unsigned long last_jump_jiffies; 66 bool abort; 67} atom_exec_context; 68 69int amdgpu_atom_debug = 0; 70static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); 71int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); 72 73static uint32_t atom_arg_mask[8] = 74 { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, 750xFF000000 }; 76static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; 77 78static int atom_dst_to_src[8][4] = { 79 /* translate destination alignment field to the source alignment encoding */ 80 {0, 0, 0, 0}, 81 {1, 2, 3, 0}, 82 {1, 2, 3, 0}, 83 {1, 2, 3, 0}, 84 {4, 5, 6, 7}, 85 {4, 5, 6, 7}, 86 {4, 5, 6, 7}, 87 {4, 5, 6, 7}, 88}; 89static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 }; 90 91static int debug_depth = 0; 92#ifdef ATOM_DEBUG 93static void debug_print_spaces(int n) 94{ 95 while (n--) 96 printk(" "); 97} 98 99#ifdef DEBUG 100#undef DEBUG 101#endif 102 103#define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0) 104#define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0) 105#else 106#define DEBUG(...) do { } while (0) 107#define SDEBUG(...) do { } while (0) 108#endif 109 110static uint32_t atom_iio_execute(struct atom_context *ctx, int base, 111 uint32_t index, uint32_t data) 112{ 113 uint32_t temp = 0xCDCDCDCD; 114 115 while (1) 116 switch (CU8(base)) { 117 case ATOM_IIO_NOP: 118 base++; 119 break; 120 case ATOM_IIO_READ: 121 temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1)); 122 base += 3; 123 break; 124 case ATOM_IIO_WRITE: 125 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp); 126 base += 3; 127 break; 128 case ATOM_IIO_CLEAR: 129 temp &= 130 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 131 CU8(base + 2)); 132 base += 3; 133 break; 134 case ATOM_IIO_SET: 135 temp |= 136 (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 137 2); 138 base += 3; 139 break; 140 case ATOM_IIO_MOVE_INDEX: 141 temp &= 142 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 143 CU8(base + 3)); 144 temp |= 145 ((index >> CU8(base + 2)) & 146 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 147 3); 148 base += 4; 149 break; 150 case ATOM_IIO_MOVE_DATA: 151 temp &= 152 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 153 CU8(base + 3)); 154 temp |= 155 ((data >> CU8(base + 2)) & 156 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 157 3); 158 base += 4; 159 break; 160 case ATOM_IIO_MOVE_ATTR: 161 temp &= 162 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 163 CU8(base + 3)); 164 temp |= 165 ((ctx-> 166 io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - 167 CU8 168 (base 169 + 170 1)))) 171 << CU8(base + 3); 172 base += 4; 173 break; 174 case ATOM_IIO_END: 175 return temp; 176 default: 177 pr_info("Unknown IIO opcode\n"); 178 return 0; 179 } 180} 181 182static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, 183 int *ptr, uint32_t *saved, int print) 184{ 185 uint32_t idx, val = 0xCDCDCDCD, align, arg; 186 struct atom_context *gctx = ctx->ctx; 187 arg = attr & 7; 188 align = (attr >> 3) & 7; 189 switch (arg) { 190 case ATOM_ARG_REG: 191 idx = U16(*ptr); 192 (*ptr) += 2; 193 if (print) 194 DEBUG("REG[0x%04X]", idx); 195 idx += gctx->reg_block; 196 switch (gctx->io_mode) { 197 case ATOM_IO_MM: 198 val = gctx->card->reg_read(gctx->card, idx); 199 break; 200 case ATOM_IO_PCI: 201 pr_info("PCI registers are not implemented\n"); 202 return 0; 203 case ATOM_IO_SYSIO: 204 pr_info("SYSIO registers are not implemented\n"); 205 return 0; 206 default: 207 if (!(gctx->io_mode & 0x80)) { 208 pr_info("Bad IO mode\n"); 209 return 0; 210 } 211 if (!gctx->iio[gctx->io_mode & 0x7F]) { 212 pr_info("Undefined indirect IO read method %d\n", 213 gctx->io_mode & 0x7F); 214 return 0; 215 } 216 val = 217 atom_iio_execute(gctx, 218 gctx->iio[gctx->io_mode & 0x7F], 219 idx, 0); 220 } 221 break; 222 case ATOM_ARG_PS: 223 idx = U8(*ptr); 224 (*ptr)++; 225 /* get_unaligned_le32 avoids unaligned accesses from atombios 226 * tables, noticed on a DEC Alpha. */ 227 val = get_unaligned_le32((u32 *)&ctx->ps[idx]); 228 if (print) 229 DEBUG("PS[0x%02X,0x%04X]", idx, val); 230 break; 231 case ATOM_ARG_WS: 232 idx = U8(*ptr); 233 (*ptr)++; 234 if (print) 235 DEBUG("WS[0x%02X]", idx); 236 switch (idx) { 237 case ATOM_WS_QUOTIENT: 238 val = gctx->divmul[0]; 239 break; 240 case ATOM_WS_REMAINDER: 241 val = gctx->divmul[1]; 242 break; 243 case ATOM_WS_DATAPTR: 244 val = gctx->data_block; 245 break; 246 case ATOM_WS_SHIFT: 247 val = gctx->shift; 248 break; 249 case ATOM_WS_OR_MASK: 250 val = 1 << gctx->shift; 251 break; 252 case ATOM_WS_AND_MASK: 253 val = ~(1 << gctx->shift); 254 break; 255 case ATOM_WS_FB_WINDOW: 256 val = gctx->fb_base; 257 break; 258 case ATOM_WS_ATTRIBUTES: 259 val = gctx->io_attr; 260 break; 261 case ATOM_WS_REGPTR: 262 val = gctx->reg_block; 263 break; 264 default: 265 val = ctx->ws[idx]; 266 } 267 break; 268 case ATOM_ARG_ID: 269 idx = U16(*ptr); 270 (*ptr) += 2; 271 if (print) { 272 if (gctx->data_block) 273 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block); 274 else 275 DEBUG("ID[0x%04X]", idx); 276 } 277 val = U32(idx + gctx->data_block); 278 break; 279 case ATOM_ARG_FB: 280 idx = U8(*ptr); 281 (*ptr)++; 282 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 283 DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n", 284 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 285 val = 0; 286 } else 287 val = gctx->scratch[(gctx->fb_base / 4) + idx]; 288 if (print) 289 DEBUG("FB[0x%02X]", idx); 290 break; 291 case ATOM_ARG_IMM: 292 switch (align) { 293 case ATOM_SRC_DWORD: 294 val = U32(*ptr); 295 (*ptr) += 4; 296 if (print) 297 DEBUG("IMM 0x%08X\n", val); 298 return val; 299 case ATOM_SRC_WORD0: 300 case ATOM_SRC_WORD8: 301 case ATOM_SRC_WORD16: 302 val = U16(*ptr); 303 (*ptr) += 2; 304 if (print) 305 DEBUG("IMM 0x%04X\n", val); 306 return val; 307 case ATOM_SRC_BYTE0: 308 case ATOM_SRC_BYTE8: 309 case ATOM_SRC_BYTE16: 310 case ATOM_SRC_BYTE24: 311 val = U8(*ptr); 312 (*ptr)++; 313 if (print) 314 DEBUG("IMM 0x%02X\n", val); 315 return val; 316 } 317 return 0; 318 case ATOM_ARG_PLL: 319 idx = U8(*ptr); 320 (*ptr)++; 321 if (print) 322 DEBUG("PLL[0x%02X]", idx); 323 val = gctx->card->pll_read(gctx->card, idx); 324 break; 325 case ATOM_ARG_MC: 326 idx = U8(*ptr); 327 (*ptr)++; 328 if (print) 329 DEBUG("MC[0x%02X]", idx); 330 val = gctx->card->mc_read(gctx->card, idx); 331 break; 332 } 333 if (saved) 334 *saved = val; 335 val &= atom_arg_mask[align]; 336 val >>= atom_arg_shift[align]; 337 if (print) 338 switch (align) { 339 case ATOM_SRC_DWORD: 340 DEBUG(".[31:0] -> 0x%08X\n", val); 341 break; 342 case ATOM_SRC_WORD0: 343 DEBUG(".[15:0] -> 0x%04X\n", val); 344 break; 345 case ATOM_SRC_WORD8: 346 DEBUG(".[23:8] -> 0x%04X\n", val); 347 break; 348 case ATOM_SRC_WORD16: 349 DEBUG(".[31:16] -> 0x%04X\n", val); 350 break; 351 case ATOM_SRC_BYTE0: 352 DEBUG(".[7:0] -> 0x%02X\n", val); 353 break; 354 case ATOM_SRC_BYTE8: 355 DEBUG(".[15:8] -> 0x%02X\n", val); 356 break; 357 case ATOM_SRC_BYTE16: 358 DEBUG(".[23:16] -> 0x%02X\n", val); 359 break; 360 case ATOM_SRC_BYTE24: 361 DEBUG(".[31:24] -> 0x%02X\n", val); 362 break; 363 } 364 return val; 365} 366 367static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr) 368{ 369 uint32_t align = (attr >> 3) & 7, arg = attr & 7; 370 switch (arg) { 371 case ATOM_ARG_REG: 372 case ATOM_ARG_ID: 373 (*ptr) += 2; 374 break; 375 case ATOM_ARG_PLL: 376 case ATOM_ARG_MC: 377 case ATOM_ARG_PS: 378 case ATOM_ARG_WS: 379 case ATOM_ARG_FB: 380 (*ptr)++; 381 break; 382 case ATOM_ARG_IMM: 383 switch (align) { 384 case ATOM_SRC_DWORD: 385 (*ptr) += 4; 386 return; 387 case ATOM_SRC_WORD0: 388 case ATOM_SRC_WORD8: 389 case ATOM_SRC_WORD16: 390 (*ptr) += 2; 391 return; 392 case ATOM_SRC_BYTE0: 393 case ATOM_SRC_BYTE8: 394 case ATOM_SRC_BYTE16: 395 case ATOM_SRC_BYTE24: 396 (*ptr)++; 397 return; 398 } 399 return; 400 } 401} 402 403static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr) 404{ 405 return atom_get_src_int(ctx, attr, ptr, NULL, 1); 406} 407 408static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr) 409{ 410 uint32_t val = 0xCDCDCDCD; 411 412 switch (align) { 413 case ATOM_SRC_DWORD: 414 val = U32(*ptr); 415 (*ptr) += 4; 416 break; 417 case ATOM_SRC_WORD0: 418 case ATOM_SRC_WORD8: 419 case ATOM_SRC_WORD16: 420 val = U16(*ptr); 421 (*ptr) += 2; 422 break; 423 case ATOM_SRC_BYTE0: 424 case ATOM_SRC_BYTE8: 425 case ATOM_SRC_BYTE16: 426 case ATOM_SRC_BYTE24: 427 val = U8(*ptr); 428 (*ptr)++; 429 break; 430 } 431 return val; 432} 433 434static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, 435 int *ptr, uint32_t *saved, int print) 436{ 437 return atom_get_src_int(ctx, 438 arg | atom_dst_to_src[(attr >> 3) & 439 7][(attr >> 6) & 3] << 3, 440 ptr, saved, print); 441} 442 443static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr) 444{ 445 atom_skip_src_int(ctx, 446 arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 447 3] << 3, ptr); 448} 449 450static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, 451 int *ptr, uint32_t val, uint32_t saved) 452{ 453 uint32_t align = 454 atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val = 455 val, idx; 456 struct atom_context *gctx = ctx->ctx; 457 old_val &= atom_arg_mask[align] >> atom_arg_shift[align]; 458 val <<= atom_arg_shift[align]; 459 val &= atom_arg_mask[align]; 460 saved &= ~atom_arg_mask[align]; 461 val |= saved; 462 switch (arg) { 463 case ATOM_ARG_REG: 464 idx = U16(*ptr); 465 (*ptr) += 2; 466 DEBUG("REG[0x%04X]", idx); 467 idx += gctx->reg_block; 468 switch (gctx->io_mode) { 469 case ATOM_IO_MM: 470 if (idx == 0) 471 gctx->card->reg_write(gctx->card, idx, 472 val << 2); 473 else 474 gctx->card->reg_write(gctx->card, idx, val); 475 break; 476 case ATOM_IO_PCI: 477 pr_info("PCI registers are not implemented\n"); 478 return; 479 case ATOM_IO_SYSIO: 480 pr_info("SYSIO registers are not implemented\n"); 481 return; 482 default: 483 if (!(gctx->io_mode & 0x80)) { 484 pr_info("Bad IO mode\n"); 485 return; 486 } 487 if (!gctx->iio[gctx->io_mode & 0xFF]) { 488 pr_info("Undefined indirect IO write method %d\n", 489 gctx->io_mode & 0x7F); 490 return; 491 } 492 atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], 493 idx, val); 494 } 495 break; 496 case ATOM_ARG_PS: 497 idx = U8(*ptr); 498 (*ptr)++; 499 DEBUG("PS[0x%02X]", idx); 500 ctx->ps[idx] = cpu_to_le32(val); 501 break; 502 case ATOM_ARG_WS: 503 idx = U8(*ptr); 504 (*ptr)++; 505 DEBUG("WS[0x%02X]", idx); 506 switch (idx) { 507 case ATOM_WS_QUOTIENT: 508 gctx->divmul[0] = val; 509 break; 510 case ATOM_WS_REMAINDER: 511 gctx->divmul[1] = val; 512 break; 513 case ATOM_WS_DATAPTR: 514 gctx->data_block = val; 515 break; 516 case ATOM_WS_SHIFT: 517 gctx->shift = val; 518 break; 519 case ATOM_WS_OR_MASK: 520 case ATOM_WS_AND_MASK: 521 break; 522 case ATOM_WS_FB_WINDOW: 523 gctx->fb_base = val; 524 break; 525 case ATOM_WS_ATTRIBUTES: 526 gctx->io_attr = val; 527 break; 528 case ATOM_WS_REGPTR: 529 gctx->reg_block = val; 530 break; 531 default: 532 ctx->ws[idx] = val; 533 } 534 break; 535 case ATOM_ARG_FB: 536 idx = U8(*ptr); 537 (*ptr)++; 538 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 539 DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n", 540 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 541 } else 542 gctx->scratch[(gctx->fb_base / 4) + idx] = val; 543 DEBUG("FB[0x%02X]", idx); 544 break; 545 case ATOM_ARG_PLL: 546 idx = U8(*ptr); 547 (*ptr)++; 548 DEBUG("PLL[0x%02X]", idx); 549 gctx->card->pll_write(gctx->card, idx, val); 550 break; 551 case ATOM_ARG_MC: 552 idx = U8(*ptr); 553 (*ptr)++; 554 DEBUG("MC[0x%02X]", idx); 555 gctx->card->mc_write(gctx->card, idx, val); 556 return; 557 } 558 switch (align) { 559 case ATOM_SRC_DWORD: 560 DEBUG(".[31:0] <- 0x%08X\n", old_val); 561 break; 562 case ATOM_SRC_WORD0: 563 DEBUG(".[15:0] <- 0x%04X\n", old_val); 564 break; 565 case ATOM_SRC_WORD8: 566 DEBUG(".[23:8] <- 0x%04X\n", old_val); 567 break; 568 case ATOM_SRC_WORD16: 569 DEBUG(".[31:16] <- 0x%04X\n", old_val); 570 break; 571 case ATOM_SRC_BYTE0: 572 DEBUG(".[7:0] <- 0x%02X\n", old_val); 573 break; 574 case ATOM_SRC_BYTE8: 575 DEBUG(".[15:8] <- 0x%02X\n", old_val); 576 break; 577 case ATOM_SRC_BYTE16: 578 DEBUG(".[23:16] <- 0x%02X\n", old_val); 579 break; 580 case ATOM_SRC_BYTE24: 581 DEBUG(".[31:24] <- 0x%02X\n", old_val); 582 break; 583 } 584} 585 586static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg) 587{ 588 uint8_t attr = U8((*ptr)++); 589 uint32_t dst, src, saved; 590 int dptr = *ptr; 591 SDEBUG(" dst: "); 592 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 593 SDEBUG(" src: "); 594 src = atom_get_src(ctx, attr, ptr); 595 dst += src; 596 SDEBUG(" dst: "); 597 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 598} 599 600static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg) 601{ 602 uint8_t attr = U8((*ptr)++); 603 uint32_t dst, src, saved; 604 int dptr = *ptr; 605 SDEBUG(" dst: "); 606 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 607 SDEBUG(" src: "); 608 src = atom_get_src(ctx, attr, ptr); 609 dst &= src; 610 SDEBUG(" dst: "); 611 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 612} 613 614static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg) 615{ 616 printk("ATOM BIOS beeped!\n"); 617} 618 619static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg) 620{ 621 int idx = U8((*ptr)++); 622 int r = 0; 623 624 if (idx < ATOM_TABLE_NAMES_CNT) 625 SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]); 626 else 627 SDEBUG(" table: %d\n", idx); 628 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) 629 r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); 630 if (r) { 631 ctx->abort = true; 632 } 633} 634 635static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) 636{ 637 uint8_t attr = U8((*ptr)++); 638 uint32_t saved; 639 int dptr = *ptr; 640 attr &= 0x38; 641 attr |= atom_def_dst[attr >> 3] << 6; 642 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 643 SDEBUG(" dst: "); 644 atom_put_dst(ctx, arg, attr, &dptr, 0, saved); 645} 646 647static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg) 648{ 649 uint8_t attr = U8((*ptr)++); 650 uint32_t dst, src; 651 SDEBUG(" src1: "); 652 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 653 SDEBUG(" src2: "); 654 src = atom_get_src(ctx, attr, ptr); 655 ctx->ctx->cs_equal = (dst == src); 656 ctx->ctx->cs_above = (dst > src); 657 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE", 658 ctx->ctx->cs_above ? "GT" : "LE"); 659} 660 661static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) 662{ 663 unsigned count = U8((*ptr)++); 664 SDEBUG(" count: %d\n", count); 665 if (arg == ATOM_UNIT_MICROSEC) 666 udelay(count); 667 else if (!drm_can_sleep()) 668 mdelay(count); 669 else 670 drm_msleep(count); 671} 672 673static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg) 674{ 675 uint8_t attr = U8((*ptr)++); 676 uint32_t dst, src; 677 SDEBUG(" src1: "); 678 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 679 SDEBUG(" src2: "); 680 src = atom_get_src(ctx, attr, ptr); 681 if (src != 0) { 682 ctx->ctx->divmul[0] = dst / src; 683 ctx->ctx->divmul[1] = dst % src; 684 } else { 685 ctx->ctx->divmul[0] = 0; 686 ctx->ctx->divmul[1] = 0; 687 } 688} 689 690static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg) 691{ 692 uint64_t val64; 693 uint8_t attr = U8((*ptr)++); 694 uint32_t dst, src; 695 SDEBUG(" src1: "); 696 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 697 SDEBUG(" src2: "); 698 src = atom_get_src(ctx, attr, ptr); 699 if (src != 0) { 700 val64 = dst; 701 val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32; 702 do_div(val64, src); 703 ctx->ctx->divmul[0] = lower_32_bits(val64); 704 ctx->ctx->divmul[1] = upper_32_bits(val64); 705 } else { 706 ctx->ctx->divmul[0] = 0; 707 ctx->ctx->divmul[1] = 0; 708 } 709} 710 711static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg) 712{ 713 /* functionally, a nop */ 714} 715 716static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) 717{ 718 int execute = 0, target = U16(*ptr); 719 unsigned long cjiffies; 720 721 (*ptr) += 2; 722 switch (arg) { 723 case ATOM_COND_ABOVE: 724 execute = ctx->ctx->cs_above; 725 break; 726 case ATOM_COND_ABOVEOREQUAL: 727 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal; 728 break; 729 case ATOM_COND_ALWAYS: 730 execute = 1; 731 break; 732 case ATOM_COND_BELOW: 733 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal); 734 break; 735 case ATOM_COND_BELOWOREQUAL: 736 execute = !ctx->ctx->cs_above; 737 break; 738 case ATOM_COND_EQUAL: 739 execute = ctx->ctx->cs_equal; 740 break; 741 case ATOM_COND_NOTEQUAL: 742 execute = !ctx->ctx->cs_equal; 743 break; 744 } 745 if (arg != ATOM_COND_ALWAYS) 746 SDEBUG(" taken: %s\n", execute ? "yes" : "no"); 747 SDEBUG(" target: 0x%04X\n", target); 748 if (execute) { 749 if (ctx->last_jump == (ctx->start + target)) { 750 cjiffies = jiffies; 751 if (time_after(cjiffies, ctx->last_jump_jiffies)) { 752 cjiffies -= ctx->last_jump_jiffies; 753 if ((jiffies_to_msecs(cjiffies) > ATOM_CMD_TIMEOUT_SEC*1000)) { 754 DRM_ERROR("atombios stuck in loop for more than %dsecs aborting\n", 755 ATOM_CMD_TIMEOUT_SEC); 756 ctx->abort = true; 757 } 758 } else { 759 /* jiffies wrap around we will just wait a little longer */ 760 ctx->last_jump_jiffies = jiffies; 761 } 762 } else { 763 ctx->last_jump = ctx->start + target; 764 ctx->last_jump_jiffies = jiffies; 765 } 766 *ptr = ctx->start + target; 767 } 768} 769 770static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg) 771{ 772 uint8_t attr = U8((*ptr)++); 773 uint32_t dst, mask, src, saved; 774 int dptr = *ptr; 775 SDEBUG(" dst: "); 776 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 777 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr); 778 SDEBUG(" mask: 0x%08x", mask); 779 SDEBUG(" src: "); 780 src = atom_get_src(ctx, attr, ptr); 781 dst &= mask; 782 dst |= src; 783 SDEBUG(" dst: "); 784 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 785} 786 787static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg) 788{ 789 uint8_t attr = U8((*ptr)++); 790 uint32_t src, saved; 791 int dptr = *ptr; 792 if (((attr >> 3) & 7) != ATOM_SRC_DWORD) 793 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 794 else { 795 atom_skip_dst(ctx, arg, attr, ptr); 796 saved = 0xCDCDCDCD; 797 } 798 SDEBUG(" src: "); 799 src = atom_get_src(ctx, attr, ptr); 800 SDEBUG(" dst: "); 801 atom_put_dst(ctx, arg, attr, &dptr, src, saved); 802} 803 804static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg) 805{ 806 uint8_t attr = U8((*ptr)++); 807 uint32_t dst, src; 808 SDEBUG(" src1: "); 809 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 810 SDEBUG(" src2: "); 811 src = atom_get_src(ctx, attr, ptr); 812 ctx->ctx->divmul[0] = dst * src; 813} 814 815static void atom_op_mul32(atom_exec_context *ctx, int *ptr, int arg) 816{ 817 uint64_t val64; 818 uint8_t attr = U8((*ptr)++); 819 uint32_t dst, src; 820 SDEBUG(" src1: "); 821 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 822 SDEBUG(" src2: "); 823 src = atom_get_src(ctx, attr, ptr); 824 val64 = (uint64_t)dst * (uint64_t)src; 825 ctx->ctx->divmul[0] = lower_32_bits(val64); 826 ctx->ctx->divmul[1] = upper_32_bits(val64); 827} 828 829static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg) 830{ 831 /* nothing */ 832} 833 834static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg) 835{ 836 uint8_t attr = U8((*ptr)++); 837 uint32_t dst, src, saved; 838 int dptr = *ptr; 839 SDEBUG(" dst: "); 840 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 841 SDEBUG(" src: "); 842 src = atom_get_src(ctx, attr, ptr); 843 dst |= src; 844 SDEBUG(" dst: "); 845 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 846} 847 848static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg) 849{ 850 uint8_t val = U8((*ptr)++); 851 SDEBUG("POST card output: 0x%02X\n", val); 852} 853 854static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg) 855{ 856 pr_info("unimplemented!\n"); 857} 858 859static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg) 860{ 861 pr_info("unimplemented!\n"); 862} 863 864static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg) 865{ 866 pr_info("unimplemented!\n"); 867} 868 869static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg) 870{ 871 int idx = U8(*ptr); 872 (*ptr)++; 873 SDEBUG(" block: %d\n", idx); 874 if (!idx) 875 ctx->ctx->data_block = 0; 876 else if (idx == 255) 877 ctx->ctx->data_block = ctx->start; 878 else 879 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx); 880 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block); 881} 882 883static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg) 884{ 885 uint8_t attr = U8((*ptr)++); 886 SDEBUG(" fb_base: "); 887 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr); 888} 889 890static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg) 891{ 892 int port; 893 switch (arg) { 894 case ATOM_PORT_ATI: 895 port = U16(*ptr); 896 if (port < ATOM_IO_NAMES_CNT) 897 SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]); 898 else 899 SDEBUG(" port: %d\n", port); 900 if (!port) 901 ctx->ctx->io_mode = ATOM_IO_MM; 902 else 903 ctx->ctx->io_mode = ATOM_IO_IIO | port; 904 (*ptr) += 2; 905 break; 906 case ATOM_PORT_PCI: 907 ctx->ctx->io_mode = ATOM_IO_PCI; 908 (*ptr)++; 909 break; 910 case ATOM_PORT_SYSIO: 911 ctx->ctx->io_mode = ATOM_IO_SYSIO; 912 (*ptr)++; 913 break; 914 } 915} 916 917static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg) 918{ 919 ctx->ctx->reg_block = U16(*ptr); 920 (*ptr) += 2; 921 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); 922} 923 924static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg) 925{ 926 uint8_t attr = U8((*ptr)++), shift; 927 uint32_t saved, dst; 928 int dptr = *ptr; 929 attr &= 0x38; 930 attr |= atom_def_dst[attr >> 3] << 6; 931 SDEBUG(" dst: "); 932 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 933 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 934 SDEBUG(" shift: %d\n", shift); 935 dst <<= shift; 936 SDEBUG(" dst: "); 937 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 938} 939 940static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg) 941{ 942 uint8_t attr = U8((*ptr)++), shift; 943 uint32_t saved, dst; 944 int dptr = *ptr; 945 attr &= 0x38; 946 attr |= atom_def_dst[attr >> 3] << 6; 947 SDEBUG(" dst: "); 948 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 949 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 950 SDEBUG(" shift: %d\n", shift); 951 dst >>= shift; 952 SDEBUG(" dst: "); 953 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 954} 955 956static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) 957{ 958 uint8_t attr = U8((*ptr)++), shift; 959 uint32_t saved, dst; 960 int dptr = *ptr; 961 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 962 SDEBUG(" dst: "); 963 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 964 /* op needs to full dst value */ 965 dst = saved; 966 shift = atom_get_src(ctx, attr, ptr); 967 SDEBUG(" shift: %d\n", shift); 968 dst <<= shift; 969 dst &= atom_arg_mask[dst_align]; 970 dst >>= atom_arg_shift[dst_align]; 971 SDEBUG(" dst: "); 972 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 973} 974 975static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg) 976{ 977 uint8_t attr = U8((*ptr)++), shift; 978 uint32_t saved, dst; 979 int dptr = *ptr; 980 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 981 SDEBUG(" dst: "); 982 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 983 /* op needs to full dst value */ 984 dst = saved; 985 shift = atom_get_src(ctx, attr, ptr); 986 SDEBUG(" shift: %d\n", shift); 987 dst >>= shift; 988 dst &= atom_arg_mask[dst_align]; 989 dst >>= atom_arg_shift[dst_align]; 990 SDEBUG(" dst: "); 991 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 992} 993 994static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg) 995{ 996 uint8_t attr = U8((*ptr)++); 997 uint32_t dst, src, saved; 998 int dptr = *ptr; 999 SDEBUG(" dst: "); 1000 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 1001 SDEBUG(" src: "); 1002 src = atom_get_src(ctx, attr, ptr); 1003 dst -= src; 1004 SDEBUG(" dst: "); 1005 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 1006} 1007 1008static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg) 1009{ 1010 uint8_t attr = U8((*ptr)++); 1011 uint32_t src, val, target; 1012 SDEBUG(" switch: "); 1013 src = atom_get_src(ctx, attr, ptr); 1014 while (U16(*ptr) != ATOM_CASE_END) 1015 if (U8(*ptr) == ATOM_CASE_MAGIC) { 1016 (*ptr)++; 1017 SDEBUG(" case: "); 1018 val = 1019 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM, 1020 ptr); 1021 target = U16(*ptr); 1022 if (val == src) { 1023 SDEBUG(" target: %04X\n", target); 1024 *ptr = ctx->start + target; 1025 return; 1026 } 1027 (*ptr) += 2; 1028 } else { 1029 pr_info("Bad case\n"); 1030 return; 1031 } 1032 (*ptr) += 2; 1033} 1034 1035static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg) 1036{ 1037 uint8_t attr = U8((*ptr)++); 1038 uint32_t dst, src; 1039 SDEBUG(" src1: "); 1040 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 1041 SDEBUG(" src2: "); 1042 src = atom_get_src(ctx, attr, ptr); 1043 ctx->ctx->cs_equal = ((dst & src) == 0); 1044 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE"); 1045} 1046 1047static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg) 1048{ 1049 uint8_t attr = U8((*ptr)++); 1050 uint32_t dst, src, saved; 1051 int dptr = *ptr; 1052 SDEBUG(" dst: "); 1053 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 1054 SDEBUG(" src: "); 1055 src = atom_get_src(ctx, attr, ptr); 1056 dst ^= src; 1057 SDEBUG(" dst: "); 1058 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 1059} 1060 1061static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg) 1062{ 1063 uint8_t val = U8((*ptr)++); 1064 SDEBUG("DEBUG output: 0x%02X\n", val); 1065} 1066 1067static void atom_op_processds(atom_exec_context *ctx, int *ptr, int arg) 1068{ 1069 uint16_t val = U16(*ptr); 1070 (*ptr) += val + 2; 1071 SDEBUG("PROCESSDS output: 0x%02X\n", val); 1072} 1073 1074static struct { 1075 void (*func) (atom_exec_context *, int *, int); 1076 int arg; 1077} opcode_table[ATOM_OP_CNT] = { 1078 { 1079 NULL, 0}, { 1080 atom_op_move, ATOM_ARG_REG}, { 1081 atom_op_move, ATOM_ARG_PS}, { 1082 atom_op_move, ATOM_ARG_WS}, { 1083 atom_op_move, ATOM_ARG_FB}, { 1084 atom_op_move, ATOM_ARG_PLL}, { 1085 atom_op_move, ATOM_ARG_MC}, { 1086 atom_op_and, ATOM_ARG_REG}, { 1087 atom_op_and, ATOM_ARG_PS}, { 1088 atom_op_and, ATOM_ARG_WS}, { 1089 atom_op_and, ATOM_ARG_FB}, { 1090 atom_op_and, ATOM_ARG_PLL}, { 1091 atom_op_and, ATOM_ARG_MC}, { 1092 atom_op_or, ATOM_ARG_REG}, { 1093 atom_op_or, ATOM_ARG_PS}, { 1094 atom_op_or, ATOM_ARG_WS}, { 1095 atom_op_or, ATOM_ARG_FB}, { 1096 atom_op_or, ATOM_ARG_PLL}, { 1097 atom_op_or, ATOM_ARG_MC}, { 1098 atom_op_shift_left, ATOM_ARG_REG}, { 1099 atom_op_shift_left, ATOM_ARG_PS}, { 1100 atom_op_shift_left, ATOM_ARG_WS}, { 1101 atom_op_shift_left, ATOM_ARG_FB}, { 1102 atom_op_shift_left, ATOM_ARG_PLL}, { 1103 atom_op_shift_left, ATOM_ARG_MC}, { 1104 atom_op_shift_right, ATOM_ARG_REG}, { 1105 atom_op_shift_right, ATOM_ARG_PS}, { 1106 atom_op_shift_right, ATOM_ARG_WS}, { 1107 atom_op_shift_right, ATOM_ARG_FB}, { 1108 atom_op_shift_right, ATOM_ARG_PLL}, { 1109 atom_op_shift_right, ATOM_ARG_MC}, { 1110 atom_op_mul, ATOM_ARG_REG}, { 1111 atom_op_mul, ATOM_ARG_PS}, { 1112 atom_op_mul, ATOM_ARG_WS}, { 1113 atom_op_mul, ATOM_ARG_FB}, { 1114 atom_op_mul, ATOM_ARG_PLL}, { 1115 atom_op_mul, ATOM_ARG_MC}, { 1116 atom_op_div, ATOM_ARG_REG}, { 1117 atom_op_div, ATOM_ARG_PS}, { 1118 atom_op_div, ATOM_ARG_WS}, { 1119 atom_op_div, ATOM_ARG_FB}, { 1120 atom_op_div, ATOM_ARG_PLL}, { 1121 atom_op_div, ATOM_ARG_MC}, { 1122 atom_op_add, ATOM_ARG_REG}, { 1123 atom_op_add, ATOM_ARG_PS}, { 1124 atom_op_add, ATOM_ARG_WS}, { 1125 atom_op_add, ATOM_ARG_FB}, { 1126 atom_op_add, ATOM_ARG_PLL}, { 1127 atom_op_add, ATOM_ARG_MC}, { 1128 atom_op_sub, ATOM_ARG_REG}, { 1129 atom_op_sub, ATOM_ARG_PS}, { 1130 atom_op_sub, ATOM_ARG_WS}, { 1131 atom_op_sub, ATOM_ARG_FB}, { 1132 atom_op_sub, ATOM_ARG_PLL}, { 1133 atom_op_sub, ATOM_ARG_MC}, { 1134 atom_op_setport, ATOM_PORT_ATI}, { 1135 atom_op_setport, ATOM_PORT_PCI}, { 1136 atom_op_setport, ATOM_PORT_SYSIO}, { 1137 atom_op_setregblock, 0}, { 1138 atom_op_setfbbase, 0}, { 1139 atom_op_compare, ATOM_ARG_REG}, { 1140 atom_op_compare, ATOM_ARG_PS}, { 1141 atom_op_compare, ATOM_ARG_WS}, { 1142 atom_op_compare, ATOM_ARG_FB}, { 1143 atom_op_compare, ATOM_ARG_PLL}, { 1144 atom_op_compare, ATOM_ARG_MC}, { 1145 atom_op_switch, 0}, { 1146 atom_op_jump, ATOM_COND_ALWAYS}, { 1147 atom_op_jump, ATOM_COND_EQUAL}, { 1148 atom_op_jump, ATOM_COND_BELOW}, { 1149 atom_op_jump, ATOM_COND_ABOVE}, { 1150 atom_op_jump, ATOM_COND_BELOWOREQUAL}, { 1151 atom_op_jump, ATOM_COND_ABOVEOREQUAL}, { 1152 atom_op_jump, ATOM_COND_NOTEQUAL}, { 1153 atom_op_test, ATOM_ARG_REG}, { 1154 atom_op_test, ATOM_ARG_PS}, { 1155 atom_op_test, ATOM_ARG_WS}, { 1156 atom_op_test, ATOM_ARG_FB}, { 1157 atom_op_test, ATOM_ARG_PLL}, { 1158 atom_op_test, ATOM_ARG_MC}, { 1159 atom_op_delay, ATOM_UNIT_MILLISEC}, { 1160 atom_op_delay, ATOM_UNIT_MICROSEC}, { 1161 atom_op_calltable, 0}, { 1162 atom_op_repeat, 0}, { 1163 atom_op_clear, ATOM_ARG_REG}, { 1164 atom_op_clear, ATOM_ARG_PS}, { 1165 atom_op_clear, ATOM_ARG_WS}, { 1166 atom_op_clear, ATOM_ARG_FB}, { 1167 atom_op_clear, ATOM_ARG_PLL}, { 1168 atom_op_clear, ATOM_ARG_MC}, { 1169 atom_op_nop, 0}, { 1170 atom_op_eot, 0}, { 1171 atom_op_mask, ATOM_ARG_REG}, { 1172 atom_op_mask, ATOM_ARG_PS}, { 1173 atom_op_mask, ATOM_ARG_WS}, { 1174 atom_op_mask, ATOM_ARG_FB}, { 1175 atom_op_mask, ATOM_ARG_PLL}, { 1176 atom_op_mask, ATOM_ARG_MC}, { 1177 atom_op_postcard, 0}, { 1178 atom_op_beep, 0}, { 1179 atom_op_savereg, 0}, { 1180 atom_op_restorereg, 0}, { 1181 atom_op_setdatablock, 0}, { 1182 atom_op_xor, ATOM_ARG_REG}, { 1183 atom_op_xor, ATOM_ARG_PS}, { 1184 atom_op_xor, ATOM_ARG_WS}, { 1185 atom_op_xor, ATOM_ARG_FB}, { 1186 atom_op_xor, ATOM_ARG_PLL}, { 1187 atom_op_xor, ATOM_ARG_MC}, { 1188 atom_op_shl, ATOM_ARG_REG}, { 1189 atom_op_shl, ATOM_ARG_PS}, { 1190 atom_op_shl, ATOM_ARG_WS}, { 1191 atom_op_shl, ATOM_ARG_FB}, { 1192 atom_op_shl, ATOM_ARG_PLL}, { 1193 atom_op_shl, ATOM_ARG_MC}, { 1194 atom_op_shr, ATOM_ARG_REG}, { 1195 atom_op_shr, ATOM_ARG_PS}, { 1196 atom_op_shr, ATOM_ARG_WS}, { 1197 atom_op_shr, ATOM_ARG_FB}, { 1198 atom_op_shr, ATOM_ARG_PLL}, { 1199 atom_op_shr, ATOM_ARG_MC}, { 1200 atom_op_debug, 0}, { 1201 atom_op_processds, 0}, { 1202 atom_op_mul32, ATOM_ARG_PS}, { 1203 atom_op_mul32, ATOM_ARG_WS}, { 1204 atom_op_div32, ATOM_ARG_PS}, { 1205 atom_op_div32, ATOM_ARG_WS}, 1206}; 1207 1208static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) 1209{ 1210 int base = CU16(ctx->cmd_table + 4 + 2 * index); 1211 int len, ws, ps, ptr; 1212 unsigned char op; 1213 atom_exec_context ectx; 1214 int ret = 0; 1215 1216 if (!base) 1217 return -EINVAL; 1218 1219 len = CU16(base + ATOM_CT_SIZE_PTR); 1220 ws = CU8(base + ATOM_CT_WS_PTR); 1221 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; 1222 ptr = base + ATOM_CT_CODE_PTR; 1223 1224 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); 1225 1226 ectx.ctx = ctx; 1227 ectx.ps_shift = ps / 4; 1228 ectx.start = base; 1229 ectx.ps = params; 1230 ectx.abort = false; 1231 ectx.last_jump = 0; 1232 if (ws) 1233 ectx.ws = kcalloc(4, ws, GFP_KERNEL); 1234 else 1235 ectx.ws = NULL; 1236 1237 debug_depth++; 1238 while (1) { 1239 op = CU8(ptr++); 1240 if (op < ATOM_OP_NAMES_CNT) 1241 SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1); 1242 else 1243 SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1); 1244 if (ectx.abort) { 1245 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n", 1246 base, len, ws, ps, ptr - 1); 1247 ret = -EINVAL; 1248 goto free; 1249 } 1250 1251 if (op < ATOM_OP_CNT && op > 0) 1252 opcode_table[op].func(&ectx, &ptr, 1253 opcode_table[op].arg); 1254 else 1255 break; 1256 1257 if (op == ATOM_OP_EOT) 1258 break; 1259 } 1260 debug_depth--; 1261 SDEBUG("<<\n"); 1262 1263free: 1264 if (ws) 1265 kfree(ectx.ws); 1266 return ret; 1267} 1268 1269int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1270{ 1271 int r; 1272 1273 mutex_lock(&ctx->mutex); 1274 /* reset data block */ 1275 ctx->data_block = 0; 1276 /* reset reg block */ 1277 ctx->reg_block = 0; 1278 /* reset fb window */ 1279 ctx->fb_base = 0; 1280 /* reset io mode */ 1281 ctx->io_mode = ATOM_IO_MM; 1282 /* reset divmul */ 1283 ctx->divmul[0] = 0; 1284 ctx->divmul[1] = 0; 1285 r = amdgpu_atom_execute_table_locked(ctx, index, params); 1286 mutex_unlock(&ctx->mutex); 1287 return r; 1288} 1289 1290static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 }; 1291 1292static void atom_index_iio(struct atom_context *ctx, int base) 1293{ 1294 ctx->iio = kzalloc(2 * 256, GFP_KERNEL); 1295 if (!ctx->iio) 1296 return; 1297 while (CU8(base) == ATOM_IIO_START) { 1298 ctx->iio[CU8(base + 1)] = base + 2; 1299 base += 2; 1300 while (CU8(base) != ATOM_IIO_END) 1301 base += atom_iio_len[CU8(base)]; 1302 base += 3; 1303 } 1304} 1305 1306struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) 1307{ 1308 int base; 1309 struct atom_context *ctx = 1310 kzalloc(sizeof(struct atom_context), GFP_KERNEL); 1311 char *str; 1312 u16 idx; 1313 1314 if (!ctx) 1315 return NULL; 1316 1317 ctx->card = card; 1318 ctx->bios = bios; 1319 1320 if (CU16(0) != ATOM_BIOS_MAGIC) { 1321 pr_info("Invalid BIOS magic\n"); 1322 kfree(ctx); 1323 return NULL; 1324 } 1325 if (strncmp 1326 (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC, 1327 strlen(ATOM_ATI_MAGIC))) { 1328 pr_info("Invalid ATI magic\n"); 1329 kfree(ctx); 1330 return NULL; 1331 } 1332 1333 base = CU16(ATOM_ROM_TABLE_PTR); 1334 if (strncmp 1335 (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, 1336 strlen(ATOM_ROM_MAGIC))) { 1337 pr_info("Invalid ATOM magic\n"); 1338 kfree(ctx); 1339 return NULL; 1340 } 1341 1342 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR); 1343 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR); 1344 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4); 1345 if (!ctx->iio) { 1346 amdgpu_atom_destroy(ctx); 1347 return NULL; 1348 } 1349 1350 idx = CU16(ATOM_ROM_PART_NUMBER_PTR); 1351 if (idx == 0) 1352 idx = 0x80; 1353 1354 str = CSTR(idx); 1355 if (*str != '\0') { 1356 pr_info("ATOM BIOS: %s\n", str); 1357 strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version)); 1358 } 1359 1360 1361 return ctx; 1362} 1363 1364int amdgpu_atom_asic_init(struct atom_context *ctx) 1365{ 1366 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR); 1367 uint32_t ps[16]; 1368 int ret; 1369 1370 memset(ps, 0, 64); 1371 1372 ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR)); 1373 ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR)); 1374 if (!ps[0] || !ps[1]) 1375 return 1; 1376 1377 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT)) 1378 return 1; 1379 ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps); 1380 if (ret) 1381 return ret; 1382 1383 memset(ps, 0, 64); 1384 1385 return ret; 1386} 1387 1388void amdgpu_atom_destroy(struct atom_context *ctx) 1389{ 1390 kfree(ctx->iio); 1391 kfree(ctx); 1392} 1393 1394bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index, 1395 uint16_t * size, uint8_t * frev, uint8_t * crev, 1396 uint16_t * data_start) 1397{ 1398 int offset = index * 2 + 4; 1399 int idx = CU16(ctx->data_table + offset); 1400 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4); 1401 1402 if (!mdt[index]) 1403 return false; 1404 1405 if (size) 1406 *size = CU16(idx); 1407 if (frev) 1408 *frev = CU8(idx + 2); 1409 if (crev) 1410 *crev = CU8(idx + 3); 1411 *data_start = idx; 1412 return true; 1413} 1414 1415bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev, 1416 uint8_t * crev) 1417{ 1418 int offset = index * 2 + 4; 1419 int idx = CU16(ctx->cmd_table + offset); 1420 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4); 1421 1422 if (!mct[index]) 1423 return false; 1424 1425 if (frev) 1426 *frev = CU8(idx + 2); 1427 if (crev) 1428 *crev = CU8(idx + 3); 1429 return true; 1430} 1431 1432