amdgpu_atom.c revision 1.3
10SN/A/* 29330SN/A * Copyright 2008 Advanced Micro Devices, Inc. 30SN/A * 40SN/A * Permission is hereby granted, free of charge, to any person obtaining a 50SN/A * copy of this software and associated documentation files (the "Software"), 60SN/A * to deal in the Software without restriction, including without limitation 72362SN/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80SN/A * and/or sell copies of the Software, and to permit persons to whom the 92362SN/A * Software is furnished to do so, subject to the following conditions: 100SN/A * 110SN/A * The above copyright notice and this permission notice shall be included in 120SN/A * all copies or substantial portions of the Software. 130SN/A * 140SN/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 150SN/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 160SN/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 170SN/A * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 180SN/A * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 190SN/A * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 200SN/A * OTHER DEALINGS IN THE SOFTWARE. 212362SN/A * 222362SN/A * Author: Stanislaw Skowronek 232362SN/A */ 240SN/A 250SN/A#include <linux/module.h> 260SN/A#include <linux/sched.h> 270SN/A#include <linux/slab.h> 280SN/A#include <asm/unaligned.h> 290SN/A 300SN/A#include <drm/drm_util.h> 310SN/A 320SN/A#define ATOM_DEBUG 330SN/A 340SN/A#include "atom.h" 350SN/A#include "atom-names.h" 360SN/A#include "atom-bits.h" 370SN/A#include "amdgpu.h" 380SN/A 390SN/A#define ATOM_COND_ABOVE 0 400SN/A#define ATOM_COND_ABOVEOREQUAL 1 410SN/A#define ATOM_COND_ALWAYS 2 420SN/A#define ATOM_COND_BELOW 3 430SN/A#define ATOM_COND_BELOWOREQUAL 4 440SN/A#define ATOM_COND_EQUAL 5 450SN/A#define ATOM_COND_NOTEQUAL 6 460SN/A 470SN/A#define ATOM_PORT_ATI 0 480SN/A#define ATOM_PORT_PCI 1 490SN/A#define ATOM_PORT_SYSIO 2 508630SN/A 510SN/A#define ATOM_UNIT_MICROSEC 0 520SN/A#define ATOM_UNIT_MILLISEC 1 530SN/A 540SN/A#define PLL_INDEX 2 550SN/A#define PLL_DATA 3 560SN/A 570SN/Atypedef struct { 580SN/A struct atom_context *ctx; 590SN/A uint32_t *ps, *ws; 600SN/A int ps_shift; 610SN/A uint16_t start; 620SN/A unsigned last_jump; 630SN/A unsigned long last_jump_jiffies; 640SN/A bool abort; 650SN/A} atom_exec_context; 660SN/A 670SN/Aint amdgpu_atom_debug = 0; 680SN/Astatic int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); 690SN/Aint amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); 700SN/A 710SN/Astatic uint32_t atom_arg_mask[8] = 720SN/A { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, 730SN/A0xFF000000 }; 740SN/Astatic int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; 750SN/A 760SN/Astatic int atom_dst_to_src[8][4] = { 770SN/A /* translate destination alignment field to the source alignment encoding */ 780SN/A {0, 0, 0, 0}, 790SN/A {1, 2, 3, 0}, 800SN/A {1, 2, 3, 0}, 810SN/A {1, 2, 3, 0}, 820SN/A {4, 5, 6, 7}, 830SN/A {4, 5, 6, 7}, 840SN/A {4, 5, 6, 7}, 850SN/A {4, 5, 6, 7}, 860SN/A}; 870SN/Astatic int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 }; 880SN/A 890SN/Astatic int debug_depth = 0; 900SN/A#ifdef ATOM_DEBUG 910SN/Astatic void debug_print_spaces(int n) 920SN/A{ 930SN/A while (n--) 940SN/A printk(" "); 950SN/A} 960SN/A 970SN/A#define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0) 980SN/A#define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0) 990SN/A#else 1000SN/A#define DEBUG(...) do { } while (0) 1010SN/A#define SDEBUG(...) do { } while (0) 1020SN/A#endif 1030SN/A 1040SN/Astatic uint32_t atom_iio_execute(struct atom_context *ctx, int base, 1050SN/A uint32_t index, uint32_t data) 1060SN/A{ 1070SN/A uint32_t temp = 0xCDCDCDCD; 1080SN/A 1090SN/A while (1) 1100SN/A switch (CU8(base)) { 1110SN/A case ATOM_IIO_NOP: 1120SN/A base++; 1130SN/A break; 1140SN/A case ATOM_IIO_READ: 1150SN/A temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1)); 1160SN/A base += 3; 1170SN/A break; 1180SN/A case ATOM_IIO_WRITE: 1190SN/A ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp); 1200SN/A base += 3; 1210SN/A break; 1220SN/A case ATOM_IIO_CLEAR: 1230SN/A temp &= 1240SN/A ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 1250SN/A CU8(base + 2)); 1260SN/A base += 3; 1270SN/A break; 1280SN/A case ATOM_IIO_SET: 1290SN/A temp |= 1300SN/A (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 1310SN/A 2); 1320SN/A base += 3; 1330SN/A break; 1340SN/A case ATOM_IIO_MOVE_INDEX: 1350SN/A temp &= 1360SN/A ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 1370SN/A CU8(base + 3)); 1380SN/A temp |= 1390SN/A ((index >> CU8(base + 2)) & 1400SN/A (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 1410SN/A 3); 142 base += 4; 143 break; 144 case ATOM_IIO_MOVE_DATA: 145 temp &= 146 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 147 CU8(base + 3)); 148 temp |= 149 ((data >> CU8(base + 2)) & 150 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 151 3); 152 base += 4; 153 break; 154 case ATOM_IIO_MOVE_ATTR: 155 temp &= 156 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 157 CU8(base + 3)); 158 temp |= 159 ((ctx-> 160 io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - 161 CU8 162 (base 163 + 164 1)))) 165 << CU8(base + 3); 166 base += 4; 167 break; 168 case ATOM_IIO_END: 169 return temp; 170 default: 171 pr_info("Unknown IIO opcode\n"); 172 return 0; 173 } 174} 175 176static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, 177 int *ptr, uint32_t *saved, int print) 178{ 179 uint32_t idx, val = 0xCDCDCDCD, align, arg; 180 struct atom_context *gctx = ctx->ctx; 181 arg = attr & 7; 182 align = (attr >> 3) & 7; 183 switch (arg) { 184 case ATOM_ARG_REG: 185 idx = U16(*ptr); 186 (*ptr) += 2; 187 if (print) 188 DEBUG("REG[0x%04X]", idx); 189 idx += gctx->reg_block; 190 switch (gctx->io_mode) { 191 case ATOM_IO_MM: 192 val = gctx->card->reg_read(gctx->card, idx); 193 break; 194 case ATOM_IO_PCI: 195 pr_info("PCI registers are not implemented\n"); 196 return 0; 197 case ATOM_IO_SYSIO: 198 pr_info("SYSIO registers are not implemented\n"); 199 return 0; 200 default: 201 if (!(gctx->io_mode & 0x80)) { 202 pr_info("Bad IO mode\n"); 203 return 0; 204 } 205 if (!gctx->iio[gctx->io_mode & 0x7F]) { 206 pr_info("Undefined indirect IO read method %d\n", 207 gctx->io_mode & 0x7F); 208 return 0; 209 } 210 val = 211 atom_iio_execute(gctx, 212 gctx->iio[gctx->io_mode & 0x7F], 213 idx, 0); 214 } 215 break; 216 case ATOM_ARG_PS: 217 idx = U8(*ptr); 218 (*ptr)++; 219 /* get_unaligned_le32 avoids unaligned accesses from atombios 220 * tables, noticed on a DEC Alpha. */ 221 val = get_unaligned_le32((u32 *)&ctx->ps[idx]); 222 if (print) 223 DEBUG("PS[0x%02X,0x%04X]", idx, val); 224 break; 225 case ATOM_ARG_WS: 226 idx = U8(*ptr); 227 (*ptr)++; 228 if (print) 229 DEBUG("WS[0x%02X]", idx); 230 switch (idx) { 231 case ATOM_WS_QUOTIENT: 232 val = gctx->divmul[0]; 233 break; 234 case ATOM_WS_REMAINDER: 235 val = gctx->divmul[1]; 236 break; 237 case ATOM_WS_DATAPTR: 238 val = gctx->data_block; 239 break; 240 case ATOM_WS_SHIFT: 241 val = gctx->shift; 242 break; 243 case ATOM_WS_OR_MASK: 244 val = 1 << gctx->shift; 245 break; 246 case ATOM_WS_AND_MASK: 247 val = ~(1 << gctx->shift); 248 break; 249 case ATOM_WS_FB_WINDOW: 250 val = gctx->fb_base; 251 break; 252 case ATOM_WS_ATTRIBUTES: 253 val = gctx->io_attr; 254 break; 255 case ATOM_WS_REGPTR: 256 val = gctx->reg_block; 257 break; 258 default: 259 val = ctx->ws[idx]; 260 } 261 break; 262 case ATOM_ARG_ID: 263 idx = U16(*ptr); 264 (*ptr) += 2; 265 if (print) { 266 if (gctx->data_block) 267 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block); 268 else 269 DEBUG("ID[0x%04X]", idx); 270 } 271 val = U32(idx + gctx->data_block); 272 break; 273 case ATOM_ARG_FB: 274 idx = U8(*ptr); 275 (*ptr)++; 276 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 277 DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n", 278 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 279 val = 0; 280 } else 281 val = gctx->scratch[(gctx->fb_base / 4) + idx]; 282 if (print) 283 DEBUG("FB[0x%02X]", idx); 284 break; 285 case ATOM_ARG_IMM: 286 switch (align) { 287 case ATOM_SRC_DWORD: 288 val = U32(*ptr); 289 (*ptr) += 4; 290 if (print) 291 DEBUG("IMM 0x%08X\n", val); 292 return val; 293 case ATOM_SRC_WORD0: 294 case ATOM_SRC_WORD8: 295 case ATOM_SRC_WORD16: 296 val = U16(*ptr); 297 (*ptr) += 2; 298 if (print) 299 DEBUG("IMM 0x%04X\n", val); 300 return val; 301 case ATOM_SRC_BYTE0: 302 case ATOM_SRC_BYTE8: 303 case ATOM_SRC_BYTE16: 304 case ATOM_SRC_BYTE24: 305 val = U8(*ptr); 306 (*ptr)++; 307 if (print) 308 DEBUG("IMM 0x%02X\n", val); 309 return val; 310 } 311 return 0; 312 case ATOM_ARG_PLL: 313 idx = U8(*ptr); 314 (*ptr)++; 315 if (print) 316 DEBUG("PLL[0x%02X]", idx); 317 val = gctx->card->pll_read(gctx->card, idx); 318 break; 319 case ATOM_ARG_MC: 320 idx = U8(*ptr); 321 (*ptr)++; 322 if (print) 323 DEBUG("MC[0x%02X]", idx); 324 val = gctx->card->mc_read(gctx->card, idx); 325 break; 326 } 327 if (saved) 328 *saved = val; 329 val &= atom_arg_mask[align]; 330 val >>= atom_arg_shift[align]; 331 if (print) 332 switch (align) { 333 case ATOM_SRC_DWORD: 334 DEBUG(".[31:0] -> 0x%08X\n", val); 335 break; 336 case ATOM_SRC_WORD0: 337 DEBUG(".[15:0] -> 0x%04X\n", val); 338 break; 339 case ATOM_SRC_WORD8: 340 DEBUG(".[23:8] -> 0x%04X\n", val); 341 break; 342 case ATOM_SRC_WORD16: 343 DEBUG(".[31:16] -> 0x%04X\n", val); 344 break; 345 case ATOM_SRC_BYTE0: 346 DEBUG(".[7:0] -> 0x%02X\n", val); 347 break; 348 case ATOM_SRC_BYTE8: 349 DEBUG(".[15:8] -> 0x%02X\n", val); 350 break; 351 case ATOM_SRC_BYTE16: 352 DEBUG(".[23:16] -> 0x%02X\n", val); 353 break; 354 case ATOM_SRC_BYTE24: 355 DEBUG(".[31:24] -> 0x%02X\n", val); 356 break; 357 } 358 return val; 359} 360 361static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr) 362{ 363 uint32_t align = (attr >> 3) & 7, arg = attr & 7; 364 switch (arg) { 365 case ATOM_ARG_REG: 366 case ATOM_ARG_ID: 367 (*ptr) += 2; 368 break; 369 case ATOM_ARG_PLL: 370 case ATOM_ARG_MC: 371 case ATOM_ARG_PS: 372 case ATOM_ARG_WS: 373 case ATOM_ARG_FB: 374 (*ptr)++; 375 break; 376 case ATOM_ARG_IMM: 377 switch (align) { 378 case ATOM_SRC_DWORD: 379 (*ptr) += 4; 380 return; 381 case ATOM_SRC_WORD0: 382 case ATOM_SRC_WORD8: 383 case ATOM_SRC_WORD16: 384 (*ptr) += 2; 385 return; 386 case ATOM_SRC_BYTE0: 387 case ATOM_SRC_BYTE8: 388 case ATOM_SRC_BYTE16: 389 case ATOM_SRC_BYTE24: 390 (*ptr)++; 391 return; 392 } 393 return; 394 } 395} 396 397static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr) 398{ 399 return atom_get_src_int(ctx, attr, ptr, NULL, 1); 400} 401 402static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr) 403{ 404 uint32_t val = 0xCDCDCDCD; 405 406 switch (align) { 407 case ATOM_SRC_DWORD: 408 val = U32(*ptr); 409 (*ptr) += 4; 410 break; 411 case ATOM_SRC_WORD0: 412 case ATOM_SRC_WORD8: 413 case ATOM_SRC_WORD16: 414 val = U16(*ptr); 415 (*ptr) += 2; 416 break; 417 case ATOM_SRC_BYTE0: 418 case ATOM_SRC_BYTE8: 419 case ATOM_SRC_BYTE16: 420 case ATOM_SRC_BYTE24: 421 val = U8(*ptr); 422 (*ptr)++; 423 break; 424 } 425 return val; 426} 427 428static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, 429 int *ptr, uint32_t *saved, int print) 430{ 431 return atom_get_src_int(ctx, 432 arg | atom_dst_to_src[(attr >> 3) & 433 7][(attr >> 6) & 3] << 3, 434 ptr, saved, print); 435} 436 437static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr) 438{ 439 atom_skip_src_int(ctx, 440 arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 441 3] << 3, ptr); 442} 443 444static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, 445 int *ptr, uint32_t val, uint32_t saved) 446{ 447 uint32_t align = 448 atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val = 449 val, idx; 450 struct atom_context *gctx = ctx->ctx; 451 old_val &= atom_arg_mask[align] >> atom_arg_shift[align]; 452 val <<= atom_arg_shift[align]; 453 val &= atom_arg_mask[align]; 454 saved &= ~atom_arg_mask[align]; 455 val |= saved; 456 switch (arg) { 457 case ATOM_ARG_REG: 458 idx = U16(*ptr); 459 (*ptr) += 2; 460 DEBUG("REG[0x%04X]", idx); 461 idx += gctx->reg_block; 462 switch (gctx->io_mode) { 463 case ATOM_IO_MM: 464 if (idx == 0) 465 gctx->card->reg_write(gctx->card, idx, 466 val << 2); 467 else 468 gctx->card->reg_write(gctx->card, idx, val); 469 break; 470 case ATOM_IO_PCI: 471 pr_info("PCI registers are not implemented\n"); 472 return; 473 case ATOM_IO_SYSIO: 474 pr_info("SYSIO registers are not implemented\n"); 475 return; 476 default: 477 if (!(gctx->io_mode & 0x80)) { 478 pr_info("Bad IO mode\n"); 479 return; 480 } 481 if (!gctx->iio[gctx->io_mode & 0xFF]) { 482 pr_info("Undefined indirect IO write method %d\n", 483 gctx->io_mode & 0x7F); 484 return; 485 } 486 atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], 487 idx, val); 488 } 489 break; 490 case ATOM_ARG_PS: 491 idx = U8(*ptr); 492 (*ptr)++; 493 DEBUG("PS[0x%02X]", idx); 494 ctx->ps[idx] = cpu_to_le32(val); 495 break; 496 case ATOM_ARG_WS: 497 idx = U8(*ptr); 498 (*ptr)++; 499 DEBUG("WS[0x%02X]", idx); 500 switch (idx) { 501 case ATOM_WS_QUOTIENT: 502 gctx->divmul[0] = val; 503 break; 504 case ATOM_WS_REMAINDER: 505 gctx->divmul[1] = val; 506 break; 507 case ATOM_WS_DATAPTR: 508 gctx->data_block = val; 509 break; 510 case ATOM_WS_SHIFT: 511 gctx->shift = val; 512 break; 513 case ATOM_WS_OR_MASK: 514 case ATOM_WS_AND_MASK: 515 break; 516 case ATOM_WS_FB_WINDOW: 517 gctx->fb_base = val; 518 break; 519 case ATOM_WS_ATTRIBUTES: 520 gctx->io_attr = val; 521 break; 522 case ATOM_WS_REGPTR: 523 gctx->reg_block = val; 524 break; 525 default: 526 ctx->ws[idx] = val; 527 } 528 break; 529 case ATOM_ARG_FB: 530 idx = U8(*ptr); 531 (*ptr)++; 532 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 533 DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n", 534 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 535 } else 536 gctx->scratch[(gctx->fb_base / 4) + idx] = val; 537 DEBUG("FB[0x%02X]", idx); 538 break; 539 case ATOM_ARG_PLL: 540 idx = U8(*ptr); 541 (*ptr)++; 542 DEBUG("PLL[0x%02X]", idx); 543 gctx->card->pll_write(gctx->card, idx, val); 544 break; 545 case ATOM_ARG_MC: 546 idx = U8(*ptr); 547 (*ptr)++; 548 DEBUG("MC[0x%02X]", idx); 549 gctx->card->mc_write(gctx->card, idx, val); 550 return; 551 } 552 switch (align) { 553 case ATOM_SRC_DWORD: 554 DEBUG(".[31:0] <- 0x%08X\n", old_val); 555 break; 556 case ATOM_SRC_WORD0: 557 DEBUG(".[15:0] <- 0x%04X\n", old_val); 558 break; 559 case ATOM_SRC_WORD8: 560 DEBUG(".[23:8] <- 0x%04X\n", old_val); 561 break; 562 case ATOM_SRC_WORD16: 563 DEBUG(".[31:16] <- 0x%04X\n", old_val); 564 break; 565 case ATOM_SRC_BYTE0: 566 DEBUG(".[7:0] <- 0x%02X\n", old_val); 567 break; 568 case ATOM_SRC_BYTE8: 569 DEBUG(".[15:8] <- 0x%02X\n", old_val); 570 break; 571 case ATOM_SRC_BYTE16: 572 DEBUG(".[23:16] <- 0x%02X\n", old_val); 573 break; 574 case ATOM_SRC_BYTE24: 575 DEBUG(".[31:24] <- 0x%02X\n", old_val); 576 break; 577 } 578} 579 580static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg) 581{ 582 uint8_t attr = U8((*ptr)++); 583 uint32_t dst, src, saved; 584 int dptr = *ptr; 585 SDEBUG(" dst: "); 586 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 587 SDEBUG(" src: "); 588 src = atom_get_src(ctx, attr, ptr); 589 dst += src; 590 SDEBUG(" dst: "); 591 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 592} 593 594static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg) 595{ 596 uint8_t attr = U8((*ptr)++); 597 uint32_t dst, src, saved; 598 int dptr = *ptr; 599 SDEBUG(" dst: "); 600 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 601 SDEBUG(" src: "); 602 src = atom_get_src(ctx, attr, ptr); 603 dst &= src; 604 SDEBUG(" dst: "); 605 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 606} 607 608static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg) 609{ 610 printk("ATOM BIOS beeped!\n"); 611} 612 613static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg) 614{ 615 int idx = U8((*ptr)++); 616 int r = 0; 617 618 if (idx < ATOM_TABLE_NAMES_CNT) 619 SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]); 620 else 621 SDEBUG(" table: %d\n", idx); 622 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) 623 r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); 624 if (r) { 625 ctx->abort = true; 626 } 627} 628 629static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) 630{ 631 uint8_t attr = U8((*ptr)++); 632 uint32_t saved; 633 int dptr = *ptr; 634 attr &= 0x38; 635 attr |= atom_def_dst[attr >> 3] << 6; 636 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 637 SDEBUG(" dst: "); 638 atom_put_dst(ctx, arg, attr, &dptr, 0, saved); 639} 640 641static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg) 642{ 643 uint8_t attr = U8((*ptr)++); 644 uint32_t dst, src; 645 SDEBUG(" src1: "); 646 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 647 SDEBUG(" src2: "); 648 src = atom_get_src(ctx, attr, ptr); 649 ctx->ctx->cs_equal = (dst == src); 650 ctx->ctx->cs_above = (dst > src); 651 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE", 652 ctx->ctx->cs_above ? "GT" : "LE"); 653} 654 655static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) 656{ 657 unsigned count = U8((*ptr)++); 658 SDEBUG(" count: %d\n", count); 659 if (arg == ATOM_UNIT_MICROSEC) 660 udelay(count); 661 else if (!drm_can_sleep()) 662 mdelay(count); 663 else 664 drm_msleep(count); 665} 666 667static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg) 668{ 669 uint8_t attr = U8((*ptr)++); 670 uint32_t dst, src; 671 SDEBUG(" src1: "); 672 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 673 SDEBUG(" src2: "); 674 src = atom_get_src(ctx, attr, ptr); 675 if (src != 0) { 676 ctx->ctx->divmul[0] = dst / src; 677 ctx->ctx->divmul[1] = dst % src; 678 } else { 679 ctx->ctx->divmul[0] = 0; 680 ctx->ctx->divmul[1] = 0; 681 } 682} 683 684static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg) 685{ 686 uint64_t val64; 687 uint8_t attr = U8((*ptr)++); 688 uint32_t dst, src; 689 SDEBUG(" src1: "); 690 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 691 SDEBUG(" src2: "); 692 src = atom_get_src(ctx, attr, ptr); 693 if (src != 0) { 694 val64 = dst; 695 val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32; 696 do_div(val64, src); 697 ctx->ctx->divmul[0] = lower_32_bits(val64); 698 ctx->ctx->divmul[1] = upper_32_bits(val64); 699 } else { 700 ctx->ctx->divmul[0] = 0; 701 ctx->ctx->divmul[1] = 0; 702 } 703} 704 705static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg) 706{ 707 /* functionally, a nop */ 708} 709 710static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) 711{ 712 int execute = 0, target = U16(*ptr); 713 unsigned long cjiffies; 714 715 (*ptr) += 2; 716 switch (arg) { 717 case ATOM_COND_ABOVE: 718 execute = ctx->ctx->cs_above; 719 break; 720 case ATOM_COND_ABOVEOREQUAL: 721 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal; 722 break; 723 case ATOM_COND_ALWAYS: 724 execute = 1; 725 break; 726 case ATOM_COND_BELOW: 727 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal); 728 break; 729 case ATOM_COND_BELOWOREQUAL: 730 execute = !ctx->ctx->cs_above; 731 break; 732 case ATOM_COND_EQUAL: 733 execute = ctx->ctx->cs_equal; 734 break; 735 case ATOM_COND_NOTEQUAL: 736 execute = !ctx->ctx->cs_equal; 737 break; 738 } 739 if (arg != ATOM_COND_ALWAYS) 740 SDEBUG(" taken: %s\n", execute ? "yes" : "no"); 741 SDEBUG(" target: 0x%04X\n", target); 742 if (execute) { 743 if (ctx->last_jump == (ctx->start + target)) { 744 cjiffies = jiffies; 745 if (time_after(cjiffies, ctx->last_jump_jiffies)) { 746 cjiffies -= ctx->last_jump_jiffies; 747 if ((jiffies_to_msecs(cjiffies) > 10000)) { 748 DRM_ERROR("atombios stuck in loop for more than 10secs aborting\n"); 749 ctx->abort = true; 750 } 751 } else { 752 /* jiffies wrap around we will just wait a little longer */ 753 ctx->last_jump_jiffies = jiffies; 754 } 755 } else { 756 ctx->last_jump = ctx->start + target; 757 ctx->last_jump_jiffies = jiffies; 758 } 759 *ptr = ctx->start + target; 760 } 761} 762 763static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg) 764{ 765 uint8_t attr = U8((*ptr)++); 766 uint32_t dst, mask, src, saved; 767 int dptr = *ptr; 768 SDEBUG(" dst: "); 769 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 770 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr); 771 SDEBUG(" mask: 0x%08x", mask); 772 SDEBUG(" src: "); 773 src = atom_get_src(ctx, attr, ptr); 774 dst &= mask; 775 dst |= src; 776 SDEBUG(" dst: "); 777 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 778} 779 780static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg) 781{ 782 uint8_t attr = U8((*ptr)++); 783 uint32_t src, saved; 784 int dptr = *ptr; 785 if (((attr >> 3) & 7) != ATOM_SRC_DWORD) 786 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 787 else { 788 atom_skip_dst(ctx, arg, attr, ptr); 789 saved = 0xCDCDCDCD; 790 } 791 SDEBUG(" src: "); 792 src = atom_get_src(ctx, attr, ptr); 793 SDEBUG(" dst: "); 794 atom_put_dst(ctx, arg, attr, &dptr, src, saved); 795} 796 797static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg) 798{ 799 uint8_t attr = U8((*ptr)++); 800 uint32_t dst, src; 801 SDEBUG(" src1: "); 802 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 803 SDEBUG(" src2: "); 804 src = atom_get_src(ctx, attr, ptr); 805 ctx->ctx->divmul[0] = dst * src; 806} 807 808static void atom_op_mul32(atom_exec_context *ctx, int *ptr, int arg) 809{ 810 uint64_t val64; 811 uint8_t attr = U8((*ptr)++); 812 uint32_t dst, src; 813 SDEBUG(" src1: "); 814 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 815 SDEBUG(" src2: "); 816 src = atom_get_src(ctx, attr, ptr); 817 val64 = (uint64_t)dst * (uint64_t)src; 818 ctx->ctx->divmul[0] = lower_32_bits(val64); 819 ctx->ctx->divmul[1] = upper_32_bits(val64); 820} 821 822static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg) 823{ 824 /* nothing */ 825} 826 827static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg) 828{ 829 uint8_t attr = U8((*ptr)++); 830 uint32_t dst, src, saved; 831 int dptr = *ptr; 832 SDEBUG(" dst: "); 833 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 834 SDEBUG(" src: "); 835 src = atom_get_src(ctx, attr, ptr); 836 dst |= src; 837 SDEBUG(" dst: "); 838 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 839} 840 841static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg) 842{ 843 uint8_t val = U8((*ptr)++); 844 SDEBUG("POST card output: 0x%02X\n", val); 845} 846 847static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg) 848{ 849 pr_info("unimplemented!\n"); 850} 851 852static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg) 853{ 854 pr_info("unimplemented!\n"); 855} 856 857static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg) 858{ 859 pr_info("unimplemented!\n"); 860} 861 862static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg) 863{ 864 int idx = U8(*ptr); 865 (*ptr)++; 866 SDEBUG(" block: %d\n", idx); 867 if (!idx) 868 ctx->ctx->data_block = 0; 869 else if (idx == 255) 870 ctx->ctx->data_block = ctx->start; 871 else 872 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx); 873 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block); 874} 875 876static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg) 877{ 878 uint8_t attr = U8((*ptr)++); 879 SDEBUG(" fb_base: "); 880 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr); 881} 882 883static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg) 884{ 885 int port; 886 switch (arg) { 887 case ATOM_PORT_ATI: 888 port = U16(*ptr); 889 if (port < ATOM_IO_NAMES_CNT) 890 SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]); 891 else 892 SDEBUG(" port: %d\n", port); 893 if (!port) 894 ctx->ctx->io_mode = ATOM_IO_MM; 895 else 896 ctx->ctx->io_mode = ATOM_IO_IIO | port; 897 (*ptr) += 2; 898 break; 899 case ATOM_PORT_PCI: 900 ctx->ctx->io_mode = ATOM_IO_PCI; 901 (*ptr)++; 902 break; 903 case ATOM_PORT_SYSIO: 904 ctx->ctx->io_mode = ATOM_IO_SYSIO; 905 (*ptr)++; 906 break; 907 } 908} 909 910static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg) 911{ 912 ctx->ctx->reg_block = U16(*ptr); 913 (*ptr) += 2; 914 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); 915} 916 917static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg) 918{ 919 uint8_t attr = U8((*ptr)++), shift; 920 uint32_t saved, dst; 921 int dptr = *ptr; 922 attr &= 0x38; 923 attr |= atom_def_dst[attr >> 3] << 6; 924 SDEBUG(" dst: "); 925 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 926 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 927 SDEBUG(" shift: %d\n", shift); 928 dst <<= shift; 929 SDEBUG(" dst: "); 930 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 931} 932 933static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg) 934{ 935 uint8_t attr = U8((*ptr)++), shift; 936 uint32_t saved, dst; 937 int dptr = *ptr; 938 attr &= 0x38; 939 attr |= atom_def_dst[attr >> 3] << 6; 940 SDEBUG(" dst: "); 941 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 942 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 943 SDEBUG(" shift: %d\n", shift); 944 dst >>= shift; 945 SDEBUG(" dst: "); 946 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 947} 948 949static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) 950{ 951 uint8_t attr = U8((*ptr)++), shift; 952 uint32_t saved, dst; 953 int dptr = *ptr; 954 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 955 SDEBUG(" dst: "); 956 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 957 /* op needs to full dst value */ 958 dst = saved; 959 shift = atom_get_src(ctx, attr, ptr); 960 SDEBUG(" shift: %d\n", shift); 961 dst <<= shift; 962 dst &= atom_arg_mask[dst_align]; 963 dst >>= atom_arg_shift[dst_align]; 964 SDEBUG(" dst: "); 965 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 966} 967 968static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg) 969{ 970 uint8_t attr = U8((*ptr)++), shift; 971 uint32_t saved, dst; 972 int dptr = *ptr; 973 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 974 SDEBUG(" dst: "); 975 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 976 /* op needs to full dst value */ 977 dst = saved; 978 shift = atom_get_src(ctx, attr, ptr); 979 SDEBUG(" shift: %d\n", shift); 980 dst >>= shift; 981 dst &= atom_arg_mask[dst_align]; 982 dst >>= atom_arg_shift[dst_align]; 983 SDEBUG(" dst: "); 984 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 985} 986 987static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg) 988{ 989 uint8_t attr = U8((*ptr)++); 990 uint32_t dst, src, saved; 991 int dptr = *ptr; 992 SDEBUG(" dst: "); 993 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 994 SDEBUG(" src: "); 995 src = atom_get_src(ctx, attr, ptr); 996 dst -= src; 997 SDEBUG(" dst: "); 998 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 999} 1000 1001static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg) 1002{ 1003 uint8_t attr = U8((*ptr)++); 1004 uint32_t src, val, target; 1005 SDEBUG(" switch: "); 1006 src = atom_get_src(ctx, attr, ptr); 1007 while (U16(*ptr) != ATOM_CASE_END) 1008 if (U8(*ptr) == ATOM_CASE_MAGIC) { 1009 (*ptr)++; 1010 SDEBUG(" case: "); 1011 val = 1012 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM, 1013 ptr); 1014 target = U16(*ptr); 1015 if (val == src) { 1016 SDEBUG(" target: %04X\n", target); 1017 *ptr = ctx->start + target; 1018 return; 1019 } 1020 (*ptr) += 2; 1021 } else { 1022 pr_info("Bad case\n"); 1023 return; 1024 } 1025 (*ptr) += 2; 1026} 1027 1028static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg) 1029{ 1030 uint8_t attr = U8((*ptr)++); 1031 uint32_t dst, src; 1032 SDEBUG(" src1: "); 1033 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 1034 SDEBUG(" src2: "); 1035 src = atom_get_src(ctx, attr, ptr); 1036 ctx->ctx->cs_equal = ((dst & src) == 0); 1037 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE"); 1038} 1039 1040static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg) 1041{ 1042 uint8_t attr = U8((*ptr)++); 1043 uint32_t dst, src, saved; 1044 int dptr = *ptr; 1045 SDEBUG(" dst: "); 1046 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 1047 SDEBUG(" src: "); 1048 src = atom_get_src(ctx, attr, ptr); 1049 dst ^= src; 1050 SDEBUG(" dst: "); 1051 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 1052} 1053 1054static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg) 1055{ 1056 uint8_t val = U8((*ptr)++); 1057 SDEBUG("DEBUG output: 0x%02X\n", val); 1058} 1059 1060static void atom_op_processds(atom_exec_context *ctx, int *ptr, int arg) 1061{ 1062 uint16_t val = U16(*ptr); 1063 (*ptr) += val + 2; 1064 SDEBUG("PROCESSDS output: 0x%02X\n", val); 1065} 1066 1067static struct { 1068 void (*func) (atom_exec_context *, int *, int); 1069 int arg; 1070} opcode_table[ATOM_OP_CNT] = { 1071 { 1072 NULL, 0}, { 1073 atom_op_move, ATOM_ARG_REG}, { 1074 atom_op_move, ATOM_ARG_PS}, { 1075 atom_op_move, ATOM_ARG_WS}, { 1076 atom_op_move, ATOM_ARG_FB}, { 1077 atom_op_move, ATOM_ARG_PLL}, { 1078 atom_op_move, ATOM_ARG_MC}, { 1079 atom_op_and, ATOM_ARG_REG}, { 1080 atom_op_and, ATOM_ARG_PS}, { 1081 atom_op_and, ATOM_ARG_WS}, { 1082 atom_op_and, ATOM_ARG_FB}, { 1083 atom_op_and, ATOM_ARG_PLL}, { 1084 atom_op_and, ATOM_ARG_MC}, { 1085 atom_op_or, ATOM_ARG_REG}, { 1086 atom_op_or, ATOM_ARG_PS}, { 1087 atom_op_or, ATOM_ARG_WS}, { 1088 atom_op_or, ATOM_ARG_FB}, { 1089 atom_op_or, ATOM_ARG_PLL}, { 1090 atom_op_or, ATOM_ARG_MC}, { 1091 atom_op_shift_left, ATOM_ARG_REG}, { 1092 atom_op_shift_left, ATOM_ARG_PS}, { 1093 atom_op_shift_left, ATOM_ARG_WS}, { 1094 atom_op_shift_left, ATOM_ARG_FB}, { 1095 atom_op_shift_left, ATOM_ARG_PLL}, { 1096 atom_op_shift_left, ATOM_ARG_MC}, { 1097 atom_op_shift_right, ATOM_ARG_REG}, { 1098 atom_op_shift_right, ATOM_ARG_PS}, { 1099 atom_op_shift_right, ATOM_ARG_WS}, { 1100 atom_op_shift_right, ATOM_ARG_FB}, { 1101 atom_op_shift_right, ATOM_ARG_PLL}, { 1102 atom_op_shift_right, ATOM_ARG_MC}, { 1103 atom_op_mul, ATOM_ARG_REG}, { 1104 atom_op_mul, ATOM_ARG_PS}, { 1105 atom_op_mul, ATOM_ARG_WS}, { 1106 atom_op_mul, ATOM_ARG_FB}, { 1107 atom_op_mul, ATOM_ARG_PLL}, { 1108 atom_op_mul, ATOM_ARG_MC}, { 1109 atom_op_div, ATOM_ARG_REG}, { 1110 atom_op_div, ATOM_ARG_PS}, { 1111 atom_op_div, ATOM_ARG_WS}, { 1112 atom_op_div, ATOM_ARG_FB}, { 1113 atom_op_div, ATOM_ARG_PLL}, { 1114 atom_op_div, ATOM_ARG_MC}, { 1115 atom_op_add, ATOM_ARG_REG}, { 1116 atom_op_add, ATOM_ARG_PS}, { 1117 atom_op_add, ATOM_ARG_WS}, { 1118 atom_op_add, ATOM_ARG_FB}, { 1119 atom_op_add, ATOM_ARG_PLL}, { 1120 atom_op_add, ATOM_ARG_MC}, { 1121 atom_op_sub, ATOM_ARG_REG}, { 1122 atom_op_sub, ATOM_ARG_PS}, { 1123 atom_op_sub, ATOM_ARG_WS}, { 1124 atom_op_sub, ATOM_ARG_FB}, { 1125 atom_op_sub, ATOM_ARG_PLL}, { 1126 atom_op_sub, ATOM_ARG_MC}, { 1127 atom_op_setport, ATOM_PORT_ATI}, { 1128 atom_op_setport, ATOM_PORT_PCI}, { 1129 atom_op_setport, ATOM_PORT_SYSIO}, { 1130 atom_op_setregblock, 0}, { 1131 atom_op_setfbbase, 0}, { 1132 atom_op_compare, ATOM_ARG_REG}, { 1133 atom_op_compare, ATOM_ARG_PS}, { 1134 atom_op_compare, ATOM_ARG_WS}, { 1135 atom_op_compare, ATOM_ARG_FB}, { 1136 atom_op_compare, ATOM_ARG_PLL}, { 1137 atom_op_compare, ATOM_ARG_MC}, { 1138 atom_op_switch, 0}, { 1139 atom_op_jump, ATOM_COND_ALWAYS}, { 1140 atom_op_jump, ATOM_COND_EQUAL}, { 1141 atom_op_jump, ATOM_COND_BELOW}, { 1142 atom_op_jump, ATOM_COND_ABOVE}, { 1143 atom_op_jump, ATOM_COND_BELOWOREQUAL}, { 1144 atom_op_jump, ATOM_COND_ABOVEOREQUAL}, { 1145 atom_op_jump, ATOM_COND_NOTEQUAL}, { 1146 atom_op_test, ATOM_ARG_REG}, { 1147 atom_op_test, ATOM_ARG_PS}, { 1148 atom_op_test, ATOM_ARG_WS}, { 1149 atom_op_test, ATOM_ARG_FB}, { 1150 atom_op_test, ATOM_ARG_PLL}, { 1151 atom_op_test, ATOM_ARG_MC}, { 1152 atom_op_delay, ATOM_UNIT_MILLISEC}, { 1153 atom_op_delay, ATOM_UNIT_MICROSEC}, { 1154 atom_op_calltable, 0}, { 1155 atom_op_repeat, 0}, { 1156 atom_op_clear, ATOM_ARG_REG}, { 1157 atom_op_clear, ATOM_ARG_PS}, { 1158 atom_op_clear, ATOM_ARG_WS}, { 1159 atom_op_clear, ATOM_ARG_FB}, { 1160 atom_op_clear, ATOM_ARG_PLL}, { 1161 atom_op_clear, ATOM_ARG_MC}, { 1162 atom_op_nop, 0}, { 1163 atom_op_eot, 0}, { 1164 atom_op_mask, ATOM_ARG_REG}, { 1165 atom_op_mask, ATOM_ARG_PS}, { 1166 atom_op_mask, ATOM_ARG_WS}, { 1167 atom_op_mask, ATOM_ARG_FB}, { 1168 atom_op_mask, ATOM_ARG_PLL}, { 1169 atom_op_mask, ATOM_ARG_MC}, { 1170 atom_op_postcard, 0}, { 1171 atom_op_beep, 0}, { 1172 atom_op_savereg, 0}, { 1173 atom_op_restorereg, 0}, { 1174 atom_op_setdatablock, 0}, { 1175 atom_op_xor, ATOM_ARG_REG}, { 1176 atom_op_xor, ATOM_ARG_PS}, { 1177 atom_op_xor, ATOM_ARG_WS}, { 1178 atom_op_xor, ATOM_ARG_FB}, { 1179 atom_op_xor, ATOM_ARG_PLL}, { 1180 atom_op_xor, ATOM_ARG_MC}, { 1181 atom_op_shl, ATOM_ARG_REG}, { 1182 atom_op_shl, ATOM_ARG_PS}, { 1183 atom_op_shl, ATOM_ARG_WS}, { 1184 atom_op_shl, ATOM_ARG_FB}, { 1185 atom_op_shl, ATOM_ARG_PLL}, { 1186 atom_op_shl, ATOM_ARG_MC}, { 1187 atom_op_shr, ATOM_ARG_REG}, { 1188 atom_op_shr, ATOM_ARG_PS}, { 1189 atom_op_shr, ATOM_ARG_WS}, { 1190 atom_op_shr, ATOM_ARG_FB}, { 1191 atom_op_shr, ATOM_ARG_PLL}, { 1192 atom_op_shr, ATOM_ARG_MC}, { 1193 atom_op_debug, 0}, { 1194 atom_op_processds, 0}, { 1195 atom_op_mul32, ATOM_ARG_PS}, { 1196 atom_op_mul32, ATOM_ARG_WS}, { 1197 atom_op_div32, ATOM_ARG_PS}, { 1198 atom_op_div32, ATOM_ARG_WS}, 1199}; 1200 1201static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) 1202{ 1203 int base = CU16(ctx->cmd_table + 4 + 2 * index); 1204 int len, ws, ps, ptr; 1205 unsigned char op; 1206 atom_exec_context ectx; 1207 int ret = 0; 1208 1209 if (!base) 1210 return -EINVAL; 1211 1212 len = CU16(base + ATOM_CT_SIZE_PTR); 1213 ws = CU8(base + ATOM_CT_WS_PTR); 1214 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; 1215 ptr = base + ATOM_CT_CODE_PTR; 1216 1217 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); 1218 1219 ectx.ctx = ctx; 1220 ectx.ps_shift = ps / 4; 1221 ectx.start = base; 1222 ectx.ps = params; 1223 ectx.abort = false; 1224 ectx.last_jump = 0; 1225 if (ws) 1226 ectx.ws = kcalloc(4, ws, GFP_KERNEL); 1227 else 1228 ectx.ws = NULL; 1229 1230 debug_depth++; 1231 while (1) { 1232 op = CU8(ptr++); 1233 if (op < ATOM_OP_NAMES_CNT) 1234 SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1); 1235 else 1236 SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1); 1237 if (ectx.abort) { 1238 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n", 1239 base, len, ws, ps, ptr - 1); 1240 ret = -EINVAL; 1241 goto free; 1242 } 1243 1244 if (op < ATOM_OP_CNT && op > 0) 1245 opcode_table[op].func(&ectx, &ptr, 1246 opcode_table[op].arg); 1247 else 1248 break; 1249 1250 if (op == ATOM_OP_EOT) 1251 break; 1252 } 1253 debug_depth--; 1254 SDEBUG("<<\n"); 1255 1256free: 1257 if (ws) 1258 kfree(ectx.ws); 1259 return ret; 1260} 1261 1262int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1263{ 1264 int r; 1265 1266 mutex_lock(&ctx->mutex); 1267 /* reset data block */ 1268 ctx->data_block = 0; 1269 /* reset reg block */ 1270 ctx->reg_block = 0; 1271 /* reset fb window */ 1272 ctx->fb_base = 0; 1273 /* reset io mode */ 1274 ctx->io_mode = ATOM_IO_MM; 1275 /* reset divmul */ 1276 ctx->divmul[0] = 0; 1277 ctx->divmul[1] = 0; 1278 r = amdgpu_atom_execute_table_locked(ctx, index, params); 1279 mutex_unlock(&ctx->mutex); 1280 return r; 1281} 1282 1283static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 }; 1284 1285static void atom_index_iio(struct atom_context *ctx, int base) 1286{ 1287 ctx->iio = kzalloc(2 * 256, GFP_KERNEL); 1288 if (!ctx->iio) 1289 return; 1290 while (CU8(base) == ATOM_IIO_START) { 1291 ctx->iio[CU8(base + 1)] = base + 2; 1292 base += 2; 1293 while (CU8(base) != ATOM_IIO_END) 1294 base += atom_iio_len[CU8(base)]; 1295 base += 3; 1296 } 1297} 1298 1299struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) 1300{ 1301 int base; 1302 struct atom_context *ctx = 1303 kzalloc(sizeof(struct atom_context), GFP_KERNEL); 1304 char *str; 1305 u16 idx; 1306 1307 if (!ctx) 1308 return NULL; 1309 1310 ctx->card = card; 1311 ctx->bios = bios; 1312 1313 if (CU16(0) != ATOM_BIOS_MAGIC) { 1314 pr_info("Invalid BIOS magic\n"); 1315 kfree(ctx); 1316 return NULL; 1317 } 1318 if (strncmp 1319 (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC, 1320 strlen(ATOM_ATI_MAGIC))) { 1321 pr_info("Invalid ATI magic\n"); 1322 kfree(ctx); 1323 return NULL; 1324 } 1325 1326 base = CU16(ATOM_ROM_TABLE_PTR); 1327 if (strncmp 1328 (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, 1329 strlen(ATOM_ROM_MAGIC))) { 1330 pr_info("Invalid ATOM magic\n"); 1331 kfree(ctx); 1332 return NULL; 1333 } 1334 1335 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR); 1336 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR); 1337 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4); 1338 if (!ctx->iio) { 1339 amdgpu_atom_destroy(ctx); 1340 return NULL; 1341 } 1342 1343 idx = CU16(ATOM_ROM_PART_NUMBER_PTR); 1344 if (idx == 0) 1345 idx = 0x80; 1346 1347 str = CSTR(idx); 1348 if (*str != '\0') { 1349 pr_info("ATOM BIOS: %s\n", str); 1350 strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version)); 1351 } 1352 1353 1354 return ctx; 1355} 1356 1357int amdgpu_atom_asic_init(struct atom_context *ctx) 1358{ 1359 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR); 1360 uint32_t ps[16]; 1361 int ret; 1362 1363 memset(ps, 0, 64); 1364 1365 ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR)); 1366 ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR)); 1367 if (!ps[0] || !ps[1]) 1368 return 1; 1369 1370 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT)) 1371 return 1; 1372 ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps); 1373 if (ret) 1374 return ret; 1375 1376 memset(ps, 0, 64); 1377 1378 return ret; 1379} 1380 1381void amdgpu_atom_destroy(struct atom_context *ctx) 1382{ 1383 kfree(ctx->iio); 1384 kfree(ctx); 1385} 1386 1387bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index, 1388 uint16_t * size, uint8_t * frev, uint8_t * crev, 1389 uint16_t * data_start) 1390{ 1391 int offset = index * 2 + 4; 1392 int idx = CU16(ctx->data_table + offset); 1393 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4); 1394 1395 if (!mdt[index]) 1396 return false; 1397 1398 if (size) 1399 *size = CU16(idx); 1400 if (frev) 1401 *frev = CU8(idx + 2); 1402 if (crev) 1403 *crev = CU8(idx + 3); 1404 *data_start = idx; 1405 return true; 1406} 1407 1408bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev, 1409 uint8_t * crev) 1410{ 1411 int offset = index * 2 + 4; 1412 int idx = CU16(ctx->cmd_table + offset); 1413 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4); 1414 1415 if (!mct[index]) 1416 return false; 1417 1418 if (frev) 1419 *frev = CU8(idx + 2); 1420 if (crev) 1421 *crev = CU8(idx + 3); 1422 return true; 1423} 1424 1425