1206917Smarius/* 2206917Smarius * Copyright 2020 Advanced Micro Devices, Inc. 3206917Smarius * 4206917Smarius * Permission is hereby granted, free of charge, to any person obtaining a 5206917Smarius * copy of this software and associated documentation files (the "Software"), 6206917Smarius * to deal in the Software without restriction, including without limitation 7206917Smarius * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8206917Smarius * and/or sell copies of the Software, and to permit persons to whom the 9206917Smarius * Software is furnished to do so, subject to the following conditions: 10206917Smarius * 11206917Smarius * The above copyright notice and this permission notice shall be included in 12206917Smarius * all copies or substantial portions of the Software. 13206917Smarius * 14206917Smarius * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15206917Smarius * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16206917Smarius * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17206917Smarius * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18206917Smarius * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19206917Smarius * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20206917Smarius * OTHER DEALINGS IN THE SOFTWARE. 21206917Smarius * 22206917Smarius */ 23206917Smarius#include "amdgpu.h" 24206917Smarius#include "soc15.h" 25206917Smarius 26206917Smarius#include "soc15_common.h" 27206917Smarius#include "aldebaran_ip_offset.h" 28206917Smarius 29206917Smariusint aldebaran_reg_base_init(struct amdgpu_device *adev) 30206917Smarius{ 31206917Smarius /* HW has more IP blocks, only initialized the block needed by our driver */ 32206917Smarius uint32_t i; 33206917Smarius for (i = 0 ; i < MAX_INSTANCE ; ++i) { 34206917Smarius adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); 35206917Smarius adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); 36206917Smarius adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); 37206917Smarius adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); 38206917Smarius adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); 39206917Smarius adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); 40206917Smarius adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); 41206917Smarius adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); 42206917Smarius adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); 43206917Smarius adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); 44206917Smarius adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); 45206917Smarius adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i])); 46206917Smarius adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i])); 47206917Smarius adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i])); 48206917Smarius adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); 49206917Smarius adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); 50206917Smarius adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i])); 51206917Smarius adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); 52206917Smarius } 53206917Smarius return 0; 54206917Smarius} 55206917Smarius