cmpcireg.h revision 1.2
1/* $OpenBSD: cmpcireg.h,v 1.2 2006/07/27 00:45:59 brad Exp $ */ 2/* $NetBSD: cmpcireg.h,v 1.7 2005/12/11 12:22:48 christos Exp $ */ 3 4/* 5 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Takuya SHIOZAKI <tshiozak@NetBSD.org> . 10 * 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by ITOH Yasufumi. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37/* C-Media CMI8x38 Audio Chip Support */ 38 39#ifndef _DEV_PCI_CMPCIREG_H_ 40#define _DEV_PCI_CMPCIREG_H_ 41 42/* 43 * PCI Configuration Registers 44 */ 45 46#define CMPCI_PCI_IOBASEREG (PCI_MAPREG_START) 47 48 49/* 50 * I/O Space 51 */ 52 53#define CMPCI_REG_FUNC_0 0x00 54# define CMPCI_REG_CH0_DIR 0x00000001 55# define CMPCI_REG_CH1_DIR 0x00000002 56# define CMPCI_REG_CH0_PAUSE 0x00000004 57# define CMPCI_REG_CH1_PAUSE 0x00000008 58# define CMPCI_REG_CH0_ENABLE 0x00010000 59# define CMPCI_REG_CH1_ENABLE 0x00020000 60# define CMPCI_REG_CH0_RESET 0x00040000 61# define CMPCI_REG_CH1_RESET 0x00080000 62 63#define CMPCI_REG_FUNC_1 0x04 64# define CMPCI_REG_JOY_ENABLE 0x00000002 65# define CMPCI_REG_UART_ENABLE 0x00000004 66# define CMPCI_REG_LEGACY_ENABLE 0x00000008 67# define CMPCI_REG_BREQ 0x00000010 68# define CMPCI_REG_MCBINTR_ENABLE 0x00000020 69# define CMPCI_REG_SPDIFOUT_DAC 0x00000040 70# define CMPCI_REG_SPDIF_LOOP 0x00000080 71# define CMPCI_REG_SPDIF0_ENABLE 0x00000100 72# define CMPCI_REG_SPDIF1_ENABLE 0x00000200 73# define CMPCI_REG_DAC_FS_SHIFT 10 74# define CMPCI_REG_DAC_FS_MASK 0x00000007 75# define CMPCI_REG_ADC_FS_SHIFT 13 76# define CMPCI_REG_ADC_FS_MASK 0x00000007 77 78#define CMPCI_REG_CHANNEL_FORMAT 0x08 79# define CMPCI_REG_SPDIN_PHASE 0x80 80# define CMPCI_REG_CH0_FORMAT_SHIFT 0 81# define CMPCI_REG_CH0_FORMAT_MASK 0x00000003 82# define CMPCI_REG_CH1_FORMAT_SHIFT 2 83# define CMPCI_REG_CH1_FORMAT_MASK 0x00000003 84# define CMPCI_REG_FORMAT_MONO 0x00000000 85# define CMPCI_REG_FORMAT_STEREO 0x00000001 86# define CMPCI_REG_FORMAT_8BIT 0x00000000 87# define CMPCI_REG_FORMAT_16BIT 0x00000002 88 89#define CMPCI_REG_INTR_CTRL 0x0c 90# define CMPCI_REG_CH0_INTR_ENABLE 0x00010000 91# define CMPCI_REG_CH1_INTR_ENABLE 0x00020000 92# define CMPCI_REG_TDMA_INTR_ENABLE 0x00040000 93 94#define CMPCI_REG_INTR_STATUS 0x10 95# define CMPCI_REG_CH0_INTR 0x00000001 96# define CMPCI_REG_CH1_INTR 0x00000002 97# define CMPCI_REG_CH0_BUSY 0x00000004 98# define CMPCI_REG_CH1_BUSY 0x00000008 99# define CMPCI_REG_LEGACY_STEREO 0x00000010 100# define CMPCI_REG_LEGACY_HDMA 0x00000020 101# define CMPCI_REG_DMASTAT 0x00000040 102# define CMPCI_REG_XDO46 0x00000080 103# define CMPCI_REG_HTDMA_INTR 0x00004000 104# define CMPCI_REG_LTDMA_INTR 0x00008000 105# define CMPCI_REG_UART_INTR 0x00010000 106# define CMPCI_REG_MCB_INTR 0x04000000 107# define CMPCI_REG_VCO 0x08000000 108# define CMPCI_REG_ANY_INTR 0x80000000 109 110#define CMPCI_REG_LEGACY_CTRL 0x14 111# define CMPCI_REG_LEGACY_SPDIF_ENABLE 0x00200000 112# define CMPCI_REG_SPDIF_COPYRIGHT 0x00400000 113# define CMPCI_REG_XSPDIF_ENABLE 0x00800000 114# define CMPCI_REG_FMSEL_SHIFT 24 115# define CMPCI_REG_FMSEL_MASK 0x00000003 116# define CMPCI_REG_VSBSEL_SHIFT 26 117# define CMPCI_REG_VSBSEL_MASK 0x00000003 118# define CMPCI_REG_VMPUSEL_SHIFT 29 119# define CMPCI_REG_VMPUSEL_MASK 0x00000003 120 121#define CMPCI_REG_MISC 0x18 122# define CMPCI_REG_2ND_SPDIFIN 0x00000100 123# define CMPCI_REG_SPDIFOUT_48K 0x00008000 124# define CMPCI_REG_FM_ENABLE 0x00080000 125# define CMPCI_REG_SPDFLOOPI 0x00100000 126# define CMPCI_REG_SPDIF48K 0x01000000 127# define CMPCI_REG_5V 0x02000000 128# define CMPCI_REG_N4SPK3D 0x04000000 129 130 131#define CMPCI_REG_SBDATA 0x22 132#define CMPCI_REG_SBADDR 0x23 133# define CMPCI_SB16_MIXER_RESET 0x00 134# define CMPCI_SB16_MIXER_MASTER_L 0x30 135# define CMPCI_SB16_MIXER_MASTER_R 0x31 136# define CMPCI_SB16_MIXER_VOICE_L 0x32 137# define CMPCI_SB16_MIXER_VOICE_R 0x33 138# define CMPCI_SB16_MIXER_FM_L 0x34 139# define CMPCI_SB16_MIXER_FM_R 0x35 140# define CMPCI_SB16_MIXER_CDDA_L 0x36 141# define CMPCI_SB16_MIXER_CDDA_R 0x37 142# define CMPCI_SB16_MIXER_LINE_L 0x38 143# define CMPCI_SB16_MIXER_LINE_R 0x39 144# define CMPCI_SB16_MIXER_MIC 0x3A 145# define CMPCI_SB16_MIXER_VALBITS 5 146# define CMPCI_SB16_MIXER_SPEAKER 0x3B 147# define CMPCI_SB16_MIXER_SPEAKER_VALBITS 2 148# define CMPCI_SB16_MIXER_OUTMIX 0x3C 149# define CMPCI_SB16_SW_MIC 0x01 150# define CMPCI_SB16_SW_CD_R 0x02 151# define CMPCI_SB16_SW_CD_L 0x04 152# define CMPCI_SB16_SW_CD (CMPCI_SB16_SW_CD_L|CMPCI_SB16_SW_CD_R) 153# define CMPCI_SB16_SW_LINE_R 0x08 154# define CMPCI_SB16_SW_LINE_L 0x10 155# define CMPCI_SB16_SW_LINE (CMPCI_SB16_SW_LINE_L|CMPCI_SB16_SW_LINE_R) 156# define CMPCI_SB16_SW_FM_R 0x20 157# define CMPCI_SB16_SW_FM_L 0x40 158# define CMPCI_SB16_SW_FM (CMPCI_SB16_SW_FM_L|CMPCI_SB16_SW_FM_R) 159# define CMPCI_SB16_MIXER_ADCMIX_L 0x3D 160# define CMPCI_SB16_MIXER_ADCMIX_R 0x3E 161# define CMPCI_SB16_MIXER_FM_SRC_R 0x20 162# define CMPCI_SB16_MIXER_LINE_SRC_R 0x08 163# define CMPCI_SB16_MIXER_CD_SRC_R 0x02 164# define CMPCI_SB16_MIXER_MIC_SRC 0x01 165# define CMPCI_SB16_MIXER_SRC_R_TO_L(v) ((v) << 1) 166 167# define CMPCI_SB16_MIXER_L_TO_R(addr) ((addr)+1) 168 169# define CMPCI_ADJUST_MIC_GAIN(sc, x) cmpci_adjust((x), 0xf8) 170# define CMPCI_ADJUST_GAIN(sc, x) cmpci_adjust((x), 0xf8) 171# define CMPCI_ADJUST_2_GAIN(sc, x) cmpci_adjust((x), 0xc0) 172 173#define CMPCI_REG_MIXER24 0x24 174# define CMPCI_REG_SPDIN_MONITOR 0x01 175# define CMPCI_REG_SURROUND 0x02 176# define CMPCI_REG_INDIVIDUAL 0x20 177# define CMPCI_REG_REVERSE_FR 0x10 178# define CMPCI_REG_FMMUTE 0x80 179# define CMPCI_REG_WSMUTE 0x40 180# define CMPCI_REG_WAVEINL 0x08 181# define CMPCI_REG_WAVEINR 0x04 182 183#define CMPCI_REG_MIXER25 0x25 184# define CMPCI_REG_RAUXREN 0x80 185# define CMPCI_REG_RAUXLEN 0x40 186# define CMPCI_REG_VAUXRM 0x20 /* 0: mute, 1: unmute */ 187# define CMPCI_REG_VAUXLM 0x10 188# define CMPCI_REG_VADMIC 0x0E 189# define CMPCI_REG_MICGAINZ 0x01 /* 1: disable preamp */ 190 191# define CMPCI_ADJUST_ADMIC_GAIN(sc, x) (cmpci_adjust((x), 0xe0) >> 5) 192# define CMPCI_REG_ADMIC_VALBITS 3 193# define CMPCI_REG_ADMIC_MASK 0x07 194# define CMPCI_REG_ADMIC_SHIFT 0x01 195 196/* Note that the doc tells a lie */ 197#define CMPCI_REG_MIXER_AUX 0x26 198# define CMPCI_ADJUST_AUX_GAIN(sc, l, r) \ 199 (cmpci_adjust((l), 0xc0) >> 4 | cmpci_adjust((r), 0xc0)) 200# define CMPCI_REG_AUX_VALBITS 4 201 202#define CMPCI_REG_MPU_BASE 0x40 203#define CMPCI_REG_MPU_SIZE 0x10 204#define CMPCI_REG_FM_BASE 0x50 205#define CMPCI_REG_FM_SIZE 0x10 206 207#define CMPCI_REG_DMA0_BASE 0x80 208#define CMPCI_REG_DMA0_BYTES 0x84 209#define CMPCI_REG_DMA0_SAMPLES 0x86 210#define CMPCI_REG_DMA1_BASE 0x88 211#define CMPCI_REG_DMA1_BYTES 0x8C 212#define CMPCI_REG_DMA1_SAMPLES 0x8E 213 214 215/* sample rate */ 216#define CMPCI_REG_RATE_5512 0 217#define CMPCI_REG_RATE_11025 1 218#define CMPCI_REG_RATE_22050 2 219#define CMPCI_REG_RATE_44100 3 220#define CMPCI_REG_RATE_8000 4 221#define CMPCI_REG_RATE_16000 5 222#define CMPCI_REG_RATE_32000 6 223#define CMPCI_REG_RATE_48000 7 224#define CMPCI_REG_NUMRATE 8 225 226#endif /* _DEV_PCI_CMPCIREG_H_ */ 227 228/* end of file */ 229