miidevs.h revision 1.78
1/* $OpenBSD: miidevs.h,v 1.78 2006/04/15 01:39:13 brad Exp $ */ 2 3/* 4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. 5 * 6 * generated from: 7 * OpenBSD: miidevs,v 1.75 2006/04/15 01:38:52 brad Exp 8 */ 9/* $NetBSD: miidevs,v 1.3 1998/11/05 03:43:43 thorpej Exp $ */ 10 11/*- 12 * Copyright (c) 1998 The NetBSD Foundation, Inc. 13 * All rights reserved. 14 * 15 * This code is derived from software contributed to The NetBSD Foundation 16 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 17 * NASA Ames Research Center. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgement: 29 * This product includes software developed by the NetBSD 30 * Foundation, Inc. and its contributors. 31 * 4. Neither the name of The NetBSD Foundation nor the names of its 32 * contributors may be used to endorse or promote products derived 33 * from this software without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 36 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 37 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 38 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 39 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 40 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 41 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 42 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 43 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 44 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 45 * POSSIBILITY OF SUCH DAMAGE. 46 */ 47 48/* 49 * List of known MII OUIs 50 */ 51 52#define MII_OUI_3COM 0x00105a /* 3com */ 53#define MII_OUI_LUCENT 0x00601d /* Lucent Technologies */ 54#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */ 55#define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */ 56#define MII_OUI_ASIX 0x000ec6 /* ASIX Electronics */ 57#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */ 58#define MII_OUI_CENIX 0x000749 /* CENiX Inc. */ 59#define MII_OUI_CICADA 0x0003F1 /* Cicada Semiconductor */ 60#define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */ 61#define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */ 62#define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */ 63#define MII_OUI_ICPLUS 0x0090c3 /* IC Plus Corp. */ 64#define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */ 65#define MII_OUI_INTEL 0x00aa00 /* Intel */ 66#define MII_OUI_JATO 0x00e083 /* Jato Technologies */ 67#define MII_OUI_LEVEL1 0x00207b /* Level 1 */ 68#define MII_OUI_MYSON 0x00c0b4 /* Myson Technology */ 69#define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */ 70#define MII_OUI_PLESSEY 0x046b40 /* Plessey Semiconductor */ 71#define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */ 72#define MII_OUI_REALTEK 0x000020 /* Realtek Semiconductor */ 73#define MII_OUI_REALTEK2 0x00e04c /* Realtek Semiconductor */ 74#define MII_OUI_SEEQ 0x00a07d /* Seeq */ 75#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */ 76#define MII_OUI_SMSC 0x00800f /* Standard Microsystems */ 77#define MII_OUI_TI 0x080028 /* Texas Instruments */ 78#define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */ 79#define MII_OUI_VIA 0x004063 /* VIA Networking Technologies */ 80#define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */ 81 82/* in the 79c873, AMD uses another OUI (which matches Davicom!) */ 83#define MII_OUI_xxALTIMA 0x000895 /* Altima Communications */ 84#define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */ 85#define MII_OUI_xxINTEL 0x00f800 /* Intel (alt) */ 86#define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor (alt) */ 87 88/* some vendors have the bits swapped within bytes 89 (ie, ordered as on the wire) */ 90#define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */ 91#define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */ 92#define MII_OUI_xxSEEQ 0x0005be /* Seeq */ 93#define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */ 94#define MII_OUI_xxTI 0x100014 /* Texas Instruments */ 95#define MII_OUI_xxXAQTI 0x350700 /* XaQti Corp. */ 96 97/* Level 1 is completely different - from right to left. 98 (Two bits get lost in the third OUI byte.) */ 99#define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */ 100#define MII_OUI_xxLEVEL1a 0x0004de /* Level 1 */ 101 102/* Don't know what's going on here. */ 103#define MII_OUI_xxDAVICOM 0x006040 /* Davicom Semiconductor */ 104 105/* This is the OUI of the gigE PHY in the RealTek 8169S/8110S chips */ 106#define MII_OUI_xxREALTEK 0x000732 /* Realtek Semiconductor */ 107 108/* Contrived vendor for dcphy */ 109#define MII_OUI_xxDEC 0x040440 /* Digital Clone */ 110 111#define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */ 112 113/* 114 * List of known models. Grouped by oui. 115 */ 116 117/* Advanced Micro Devices PHYs */ 118#define MII_MODEL_xxAMD_79C873 0x0000 119#define MII_STR_xxAMD_79C873 "Am79C873 10/100 PHY" 120#define MII_MODEL_AMD_79C873phy 0x0036 121#define MII_STR_AMD_79C873phy "Am79C873 internal PHY" 122#define MII_MODEL_AMD_79C875phy 0x0014 123#define MII_STR_AMD_79C875phy "Am79C875 quad PHY" 124 125/* Altima Communications PHYs */ 126#define MII_MODEL_xxALTIMA_AC_UNKNOWN 0x0001 127#define MII_STR_xxALTIMA_AC_UNKNOWN "AC_UNKNOWN 10/100 PHY" 128#define MII_MODEL_xxALTIMA_AC101 0x0021 129#define MII_STR_xxALTIMA_AC101 "AC101 10/100 PHY" 130#define MII_MODEL_xxALTIMA_AC101L 0x0012 131#define MII_STR_xxALTIMA_AC101L "AC101L 10/100 PHY" 132 133/* Broadcom Corp. PHYs */ 134#define MII_MODEL_xxBROADCOM_BCM5400 0x0004 135#define MII_STR_xxBROADCOM_BCM5400 "BCM5400 1000baseT PHY" 136#define MII_MODEL_xxBROADCOM_BCM5401 0x0005 137#define MII_STR_xxBROADCOM_BCM5401 "BCM5401 10/100/1000baseT PHY" 138#define MII_MODEL_xxBROADCOM_BCM5411 0x0007 139#define MII_STR_xxBROADCOM_BCM5411 "BCM5411 10/100/1000baseT PHY" 140#define MII_MODEL_xxBROADCOM_BCM5462 0x000d 141#define MII_STR_xxBROADCOM_BCM5462 "BCM5462 10/100/1000baseT PHY" 142#define MII_MODEL_xxBROADCOM_BCM5421 0x000e 143#define MII_STR_xxBROADCOM_BCM5421 "BCM5421 10/100/1000baseT PHY" 144#define MII_MODEL_xxBROADCOM_BCM5752 0x0010 145#define MII_STR_xxBROADCOM_BCM5752 "BCM5752 10/100/1000baseT PHY" 146#define MII_MODEL_xxBROADCOM_BCM5701 0x0011 147#define MII_STR_xxBROADCOM_BCM5701 "BCM5701 10/100/1000baseT PHY" 148#define MII_MODEL_xxBROADCOM_BCM5706C 0x0015 149#define MII_STR_xxBROADCOM_BCM5706C "BCM5706C 10/100/1000baseT PHY" 150#define MII_MODEL_xxBROADCOM_BCM5703 0x0016 151#define MII_STR_xxBROADCOM_BCM5703 "BCM5703 10/100/1000baseT PHY" 152#define MII_MODEL_xxBROADCOM_BCM5704 0x0019 153#define MII_STR_xxBROADCOM_BCM5704 "BCM5704 10/100/1000baseT PHY" 154#define MII_MODEL_xxBROADCOM_BCM5705 0x001a 155#define MII_STR_xxBROADCOM_BCM5705 "BCM5705 10/100/1000baseT PHY" 156#define MII_MODEL_xxBROADCOM_BCM5750 0x0018 157#define MII_STR_xxBROADCOM_BCM5750 "BCM5750 10/100/1000baseT PHY" 158#define MII_MODEL_xxBROADCOM_BCM54K2 0x002e 159#define MII_STR_xxBROADCOM_BCM54K2 "BCM54K2 10/100/1000baseT PHY" 160#define MII_MODEL_xxBROADCOM_BCM5714 0x0034 161#define MII_STR_xxBROADCOM_BCM5714 "BCM5714 10/100/1000baseT PHY" 162#define MII_MODEL_xxBROADCOM_BCM5780 0x0035 163#define MII_STR_xxBROADCOM_BCM5780 "BCM5780 10/100/1000baseT PHY" 164#define MII_MODEL_xxBROADCOM_BCM5708C 0x0036 165#define MII_STR_xxBROADCOM_BCM5708C "BCM5708C 10/100/1000baseT PHY" 166#define MII_MODEL_BROADCOM_BCM5400 0x0004 167#define MII_STR_BROADCOM_BCM5400 "BCM5400 1000baseT PHY" 168#define MII_MODEL_BROADCOM_BCM5401 0x0005 169#define MII_STR_BROADCOM_BCM5401 "BCM5401 1000baseT PHY" 170#define MII_MODEL_BROADCOM_BCM5411 0x0007 171#define MII_STR_BROADCOM_BCM5411 "BCM5411 1000baseT PHY" 172#define MII_MODEL_BROADCOM_3C905B 0x0012 173#define MII_STR_BROADCOM_3C905B "Broadcom 3C905B internal PHY" 174#define MII_MODEL_BROADCOM_3C905C 0x0017 175#define MII_STR_BROADCOM_3C905C "Broadcom 3C905C internal PHY" 176#define MII_MODEL_BROADCOM_BCM5221 0x001e 177#define MII_STR_BROADCOM_BCM5221 "BCM5221 100baseTX PHY" 178#define MII_MODEL_BROADCOM_BCM5201 0x0021 179#define MII_STR_BROADCOM_BCM5201 "BCM5201 10/100 PHY" 180#define MII_MODEL_BROADCOM_BCM5214 0x0028 181#define MII_STR_BROADCOM_BCM5214 "BCM5214 Quad 10/100 PHY" 182#define MII_MODEL_BROADCOM_BCM5222 0x0032 183#define MII_STR_BROADCOM_BCM5222 "BCM5222 Dual 10/100 PHY" 184#define MII_MODEL_BROADCOM_BCM5220 0x0033 185#define MII_STR_BROADCOM_BCM5220 "BCM5220 10/100 PHY" 186#define MII_MODEL_BROADCOM_BCM4401 0x0036 187#define MII_STR_BROADCOM_BCM4401 "BCM4401 10/100baseTX PHY" 188 189/* Cicada Semiconductor PHYs (now owned by Vitesse?) */ 190#define MII_MODEL_CICADA_CS8201 0x0001 191#define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000TX PHY" 192#define MII_MODEL_CICADA_CS8201A 0x0020 193#define MII_STR_CICADA_CS8201A "Cicada CS8201 10/100/1000TX PHY" 194#define MII_MODEL_CICADA_CS8201B 0x0021 195#define MII_STR_CICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY" 196#define MII_MODEL_xxCICADA_CS8201B 0x0021 197#define MII_STR_xxCICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY" 198 199/* Davicom Semiconductor PHYs */ 200#define MII_MODEL_xxDAVICOM_DM9101 0x0000 201#define MII_STR_xxDAVICOM_DM9101 "DM9101 10/100 PHY" 202#define MII_MODEL_DAVICOM_DM9102 0x0004 203#define MII_STR_DAVICOM_DM9102 "DM9102 10/100 PHY" 204#define MII_MODEL_DAVICOM_DM9601 0x000c 205#define MII_STR_DAVICOM_DM9601 "DM9601 10/100 PHY" 206 207/* Enable Semiconductor PHYs (Agere) */ 208#define MII_MODEL_ENABLESEMI_LU3X31FT 0x0001 209#define MII_STR_ENABLESEMI_LU3X31FT "Enable LU3X31FT" 210#define MII_MODEL_ENABLESEMI_88E1000S 0x0004 211#define MII_STR_ENABLESEMI_88E1000S "Enable 88E1000S" 212#define MII_MODEL_ENABLESEMI_88E1000 0x0005 213#define MII_STR_ENABLESEMI_88E1000 "Enable 88E1000" 214 215/* Marvell Semiconductor PHYs */ 216#define MII_MODEL_MARVELL_E1000 0x0000 217#define MII_STR_MARVELL_E1000 "Marvell 88E1000* Gigabit PHY" 218#define MII_MODEL_MARVELL_E1011 0x0002 219#define MII_STR_MARVELL_E1011 "Marvell 88E1011 Gigabit PHY" 220#define MII_MODEL_MARVELL_E1000_3 0x0003 221#define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY" 222#define MII_MODEL_MARVELL_E1000_4 0x0004 223#define MII_STR_MARVELL_E1000_4 "Marvell 88E1000S Gigabit PHY" 224#define MII_MODEL_MARVELL_E1000_5 0x0005 225#define MII_STR_MARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY" 226#define MII_MODEL_MARVELL_E1000_6 0x0006 227#define MII_STR_MARVELL_E1000_6 "Marvell 88E1000 Gigabit PHY" 228#define MII_MODEL_MARVELL_E1111 0x000c 229#define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY" 230#define MII_MODEL_xxMARVELL_E1000_2 0x0002 231#define MII_STR_xxMARVELL_E1000_2 "Marvell 88E1000 Gigabit PHY" 232#define MII_MODEL_xxMARVELL_E1000_3 0x0003 233#define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY" 234#define MII_MODEL_xxMARVELL_E1000_5 0x0005 235#define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY" 236#define MII_MODEL_xxMARVELL_E1111 0x000c 237#define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY" 238 239/* Contrived vendor/model for dcphy */ 240#define MII_MODEL_xxDEC_xxDC 0x0001 241#define MII_STR_xxDEC_xxDC "DC" 242 243/* IC Plus Corp. PHYs */ 244#define MII_MODEL_ICPLUS_IP101 0x0005 245#define MII_STR_ICPLUS_IP101 "IP101 10/100 PHY" 246 247/* Integrated Circuit Systems PHYs */ 248#define MII_MODEL_xxICS_1890 0x0002 249#define MII_STR_xxICS_1890 "ICS1890 10/100 PHY" 250#define MII_MODEL_xxICS_1892 0x0003 251#define MII_STR_xxICS_1892 "ICS1892 10/100 PHY" 252#define MII_MODEL_xxICS_1893 0x0004 253#define MII_STR_xxICS_1893 "ICS1893 10/100 PHY" 254 255/* Intel PHYs */ 256#define MII_MODEL_xxINTEL_I82553 0x0000 257#define MII_STR_xxINTEL_I82553 "i82553 10/100 PHY" 258#define MII_MODEL_INTEL_I82555 0x0015 259#define MII_STR_INTEL_I82555 "i82555 10/100 PHY" 260#define MII_MODEL_INTEL_I82562EM 0x0032 261#define MII_STR_INTEL_I82562EM "i82562EM 10/100 PHY" 262#define MII_MODEL_INTEL_I82562ET 0x0033 263#define MII_STR_INTEL_I82562ET "i82562ET 10/100 PHY" 264#define MII_MODEL_INTEL_I82553 0x0035 265#define MII_STR_INTEL_I82553 "i82553 10/100 PHY" 266 267/* Jato Technologies PHYs */ 268#define MII_MODEL_JATO_BASEX 0x0000 269#define MII_STR_JATO_BASEX "Jato 1000baseX PHY" 270 271/* Level 1 PHYs */ 272#define MII_MODEL_xxLEVEL1_LXT970 0x0000 273#define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 PHY" 274#define MII_MODEL_xxLEVEL1a_LXT971 0x000e 275#define MII_STR_xxLEVEL1a_LXT971 "LXT971 10/100 PHY" 276 277/* Lucent Technologies PHYs */ 278#define MII_MODEL_LUCENT_LU6612 0x000c 279#define MII_STR_LUCENT_LU6612 "LU6612 10/100 PHY" 280#define MII_MODEL_LUCENT_LU3X51FT 0x0033 281#define MII_STR_LUCENT_LU3X51FT "LU3X51FT 10/100 PHY" 282#define MII_MODEL_LUCENT_LU3X54FT 0x0036 283#define MII_STR_LUCENT_LU3X54FT "LU3X54FT 10/100 PHY" 284 285/* Myson Technology PHYs */ 286#define MII_MODEL_MYSON_MTD972 0x0000 287#define MII_STR_MYSON_MTD972 "MTD972 10/100 PHY" 288 289/* National Semiconductor PHYs */ 290#define MII_MODEL_NATSEMI_DP83840 0x0000 291#define MII_STR_NATSEMI_DP83840 "DP83840 10/100 PHY" 292#define MII_MODEL_NATSEMI_DP83843 0x0001 293#define MII_STR_NATSEMI_DP83843 "DP83843 10/100 PHY" 294#define MII_MODEL_NATSEMI_DP83815 0x0002 295#define MII_STR_NATSEMI_DP83815 "DP83815 10/100 PHY" 296#define MII_MODEL_NATSEMI_DP83847 0x0003 297#define MII_STR_NATSEMI_DP83847 "DP83847 10/100 PHY" 298#define MII_MODEL_NATSEMI_DP83891 0x0005 299#define MII_STR_NATSEMI_DP83891 "DP83891 10/100/1000 PHY" 300#define MII_MODEL_NATSEMI_DP83861 0x0006 301#define MII_STR_NATSEMI_DP83861 "DP83861 10/100/1000 PHY" 302 303/* Plessey Semiconductor PHYs */ 304#define MII_MODEL_PLESSEY_NWK914 0x0000 305#define MII_STR_PLESSEY_NWK914 "NWK914 10/100 PHY" 306 307/* Quality Semiconductor PHYs */ 308#define MII_MODEL_QUALSEMI_QS6612 0x0000 309#define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 PHY" 310 311/* Realtek Semiconductor PHYs */ 312#define MII_MODEL_REALTEK_RTL8201L 0x0020 313#define MII_STR_REALTEK_RTL8201L "RTL8201L 10/100 PHY" 314#define MII_MODEL_xxREALTEK_RTL8169S 0x0011 315#define MII_STR_xxREALTEK_RTL8169S "RTL8169S/8110S PHY" 316 317/* Seeq PHYs */ 318#define MII_MODEL_xxSEEQ_80220 0x0003 319#define MII_STR_xxSEEQ_80220 "Seeq 80220 10/100 PHY" 320#define MII_MODEL_xxSEEQ_84220 0x0004 321#define MII_STR_xxSEEQ_84220 "Seeq 84220 10/100 PHY" 322#define MII_MODEL_xxSEEQ_80225 0x0008 323#define MII_STR_xxSEEQ_80225 "Seeq 80225 10/100 PHY" 324 325/* Silicon Integrated Systems PHYs */ 326#define MII_MODEL_xxSIS_900 0x0000 327#define MII_STR_xxSIS_900 "SiS 900 10/100 PHY" 328 329/* Standard Microsystems PHYs */ 330#define MII_MODEL_SMSC_LAN83C185 0x000a 331#define MII_STR_SMSC_LAN83C185 "LAN83C185 10/100 PHY" 332 333/* Texas Instruments PHYs */ 334#define MII_MODEL_xxTI_TLAN10T 0x0001 335#define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT PHY" 336#define MII_MODEL_xxTI_100VGPMI 0x0002 337#define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan PHY" 338#define MII_MODEL_xxTI_TNETE2101 0x0003 339#define MII_STR_xxTI_TNETE2101 "TNETE2101 PHY" 340 341/* TDK Semiconductor PHYs */ 342#define MII_MODEL_TSC_78Q2120 0x0014 343#define MII_STR_TSC_78Q2120 "78Q2120 10/100 PHY" 344#define MII_MODEL_TSC_78Q2121 0x0015 345#define MII_STR_TSC_78Q2121 "78Q2121 100baseTX PHY" 346 347/* VIA Networking Technologies PHYs */ 348#define MII_MODEL_VIA_VT6103 0x0032 349#define MII_STR_VIA_VT6103 "VT6103 10/100 PHY" 350#define MII_MODEL_VIA_VT6103_2 0x0034 351#define MII_STR_VIA_VT6103_2 "VT6103 10/100 PHY" 352 353/* XaQti Corp. PHYs */ 354#define MII_MODEL_XAQTI_XMACII 0x0000 355#define MII_STR_XAQTI_XMACII "XaQti Corp. XMAC II Gigabit PHY" 356