miidevs.h revision 1.68
1/* $OpenBSD: miidevs.h,v 1.68 2005/10/01 17:20:34 brad Exp $ */ 2 3/* 4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. 5 * 6 * generated from: 7 * OpenBSD: miidevs,v 1.65 2005/10/01 17:17:53 brad Exp 8 */ 9/* $NetBSD: miidevs,v 1.3 1998/11/05 03:43:43 thorpej Exp $ */ 10 11/*- 12 * Copyright (c) 1998 The NetBSD Foundation, Inc. 13 * All rights reserved. 14 * 15 * This code is derived from software contributed to The NetBSD Foundation 16 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 17 * NASA Ames Research Center. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgement: 29 * This product includes software developed by the NetBSD 30 * Foundation, Inc. and its contributors. 31 * 4. Neither the name of The NetBSD Foundation nor the names of its 32 * contributors may be used to endorse or promote products derived 33 * from this software without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 36 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 37 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 38 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 39 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 40 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 41 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 42 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 43 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 44 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 45 * POSSIBILITY OF SUCH DAMAGE. 46 */ 47 48/* 49 * List of known MII OUIs 50 */ 51 52#define MII_OUI_3COM 0x00105a /* 3com */ 53#define MII_OUI_LUCENT 0x00601d /* Lucent Technologies */ 54#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */ 55#define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */ 56#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */ 57#define MII_OUI_CICADA 0x0003F1 /* Cicada Semiconductor */ 58#define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */ 59#define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */ 60#define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */ 61#define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */ 62#define MII_OUI_INTEL 0x00aa00 /* Intel */ 63#define MII_OUI_JATO 0x00e083 /* Jato Technologies */ 64#define MII_OUI_LEVEL1 0x00207b /* Level 1 */ 65#define MII_OUI_MYSON 0x00c0b4 /* Myson Technology */ 66#define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */ 67#define MII_OUI_PLESSEY 0x046b40 /* Plessey Semiconductor */ 68#define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */ 69#define MII_OUI_REALTEK 0x000020 /* Realtek Semiconductor */ 70#define MII_OUI_REALTEK2 0x00e04c /* Realtek Semiconductor */ 71#define MII_OUI_SEEQ 0x00a07d /* Seeq */ 72#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */ 73#define MII_OUI_TI 0x080028 /* Texas Instruments */ 74#define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */ 75#define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */ 76 77/* in the 79c873, AMD uses another OUI (which matches Davicom!) */ 78#define MII_OUI_xxALTIMA 0x000895 /* Altima Communications */ 79#define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */ 80#define MII_OUI_xxINTEL 0x00f800 /* Intel (alt) */ 81#define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor (alt) */ 82 83/* some vendors have the bits swapped within bytes 84 (ie, ordered as on the wire) */ 85#define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */ 86#define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */ 87#define MII_OUI_xxSEEQ 0x0005be /* Seeq */ 88#define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */ 89#define MII_OUI_xxTI 0x100014 /* Texas Instruments */ 90#define MII_OUI_xxXAQTI 0x350700 /* XaQti Corp. */ 91 92/* Level 1 is completely different - from right to left. 93 (Two bits get lost in the third OUI byte.) */ 94#define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */ 95#define MII_OUI_xxLEVEL1a 0x0004de /* Level 1 */ 96 97/* Don't know what's going on here. */ 98#define MII_OUI_xxDAVICOM 0x006040 /* Davicom Semiconductor */ 99 100/* This is the OUI of the gigE PHY in the RealTek 8169S/8110S chips */ 101#define MII_OUI_xxREALTEK 0x000732 /* Realtek Semiconductor */ 102 103/* Contrived vendor for dcphy */ 104#define MII_OUI_xxDEC 0x040440 /* Digital Clone */ 105 106#define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */ 107 108/* 109 * List of known models. Grouped by oui. 110 */ 111 112/* Advanced Micro Devices PHYs */ 113#define MII_MODEL_xxAMD_79C873 0x0000 114#define MII_STR_xxAMD_79C873 "Am79C873 10/100 PHY" 115#define MII_MODEL_AMD_79C873phy 0x0036 116#define MII_STR_AMD_79C873phy "Am79C873 internal PHY" 117#define MII_MODEL_AMD_79C875phy 0x0014 118#define MII_STR_AMD_79C875phy "Am79C875 quad PHY" 119 120/* Altima Communications PHYs */ 121#define MII_MODEL_xxALTIMA_AC_UNKNOWN 0x0001 122#define MII_STR_xxALTIMA_AC_UNKNOWN "AC_UNKNOWN 10/100 PHY" 123#define MII_MODEL_xxALTIMA_AC101 0x0021 124#define MII_STR_xxALTIMA_AC101 "AC101 10/100 PHY" 125#define MII_MODEL_xxALTIMA_AC101L 0x0012 126#define MII_STR_xxALTIMA_AC101L "AC101L 10/100 PHY" 127 128/* Broadcom Corp. PHYs */ 129#define MII_MODEL_xxBROADCOM_BCM5400 0x0004 130#define MII_STR_xxBROADCOM_BCM5400 "BCM5400 1000baseT PHY" 131#define MII_MODEL_xxBROADCOM_BCM5401 0x0005 132#define MII_STR_xxBROADCOM_BCM5401 "BCM5401 10/100/1000baseT PHY" 133#define MII_MODEL_xxBROADCOM_BCM5411 0x0007 134#define MII_STR_xxBROADCOM_BCM5411 "BCM5411 10/100/1000baseT PHY" 135#define MII_MODEL_xxBROADCOM_BCM5462 0x000d 136#define MII_STR_xxBROADCOM_BCM5462 "BCM5462 10/100/1000baseT PHY" 137#define MII_MODEL_xxBROADCOM_BCM5421 0x000e 138#define MII_STR_xxBROADCOM_BCM5421 "BCM5421 10/100/1000baseT PHY" 139#define MII_MODEL_xxBROADCOM_BCM5752 0x0010 140#define MII_STR_xxBROADCOM_BCM5752 "BCM5752 10/100/1000baseT PHY" 141#define MII_MODEL_xxBROADCOM_BCM5701 0x0011 142#define MII_STR_xxBROADCOM_BCM5701 "BCM5701 10/100/1000baseT PHY" 143#define MII_MODEL_xxBROADCOM_BCM5703 0x0016 144#define MII_STR_xxBROADCOM_BCM5703 "BCM5703 10/100/1000baseT PHY" 145#define MII_MODEL_xxBROADCOM_BCM5704 0x0019 146#define MII_STR_xxBROADCOM_BCM5704 "BCM5704 10/100/1000baseT PHY" 147#define MII_MODEL_xxBROADCOM_BCM5705 0x001a 148#define MII_STR_xxBROADCOM_BCM5705 "BCM5705 10/100/1000baseT PHY" 149#define MII_MODEL_xxBROADCOM_BCM5750 0x0018 150#define MII_STR_xxBROADCOM_BCM5750 "BCM5750 10/100/1000baseT PHY" 151#define MII_MODEL_xxBROADCOM_BCM5421K2 0x002e 152#define MII_STR_xxBROADCOM_BCM5421K2 "BCM5421K2 10/100/1000baseT PHY" 153#define MII_MODEL_xxBROADCOM_BCM5714 0x0034 154#define MII_STR_xxBROADCOM_BCM5714 "BCM5714 10/100/1000baseT PHY" 155#define MII_MODEL_BROADCOM_BCM5400 0x0004 156#define MII_STR_BROADCOM_BCM5400 "BCM5400 1000baseT PHY" 157#define MII_MODEL_BROADCOM_BCM5401 0x0005 158#define MII_STR_BROADCOM_BCM5401 "BCM5401 1000baseT PHY" 159#define MII_MODEL_BROADCOM_BCM5411 0x0007 160#define MII_STR_BROADCOM_BCM5411 "BCM5411 1000baseT PHY" 161#define MII_MODEL_BROADCOM_3C905B 0x0012 162#define MII_STR_BROADCOM_3C905B "Broadcom 3C905B internal PHY" 163#define MII_MODEL_BROADCOM_3C905C 0x0017 164#define MII_STR_BROADCOM_3C905C "Broadcom 3C905C internal PHY" 165#define MII_MODEL_BROADCOM_BCM5221 0x001e 166#define MII_STR_BROADCOM_BCM5221 "BCM5221 100baseTX PHY" 167#define MII_MODEL_BROADCOM_BCM5201 0x0021 168#define MII_STR_BROADCOM_BCM5201 "BCM5201 10/100 PHY" 169#define MII_MODEL_BROADCOM_BCM5214 0x0028 170#define MII_STR_BROADCOM_BCM5214 "BCM5214 Quad 10/100 PHY" 171#define MII_MODEL_BROADCOM_BCM5222 0x0032 172#define MII_STR_BROADCOM_BCM5222 "BCM5222 Dual 10/100 PHY" 173#define MII_MODEL_BROADCOM_BCM5220 0x0033 174#define MII_STR_BROADCOM_BCM5220 "BCM5220 10/100 PHY" 175#define MII_MODEL_BROADCOM_BCM4401 0x0036 176#define MII_STR_BROADCOM_BCM4401 "BCM4401 10/100baseTX PHY" 177 178/* Cicada Semiconductor PHYs (now owned by Vitesse?) */ 179#define MII_MODEL_CICADA_CS8201 0x0001 180#define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000TX PHY" 181#define MII_MODEL_CICADA_CS8201A 0x0020 182#define MII_STR_CICADA_CS8201A "Cicada CS8201 10/100/1000TX PHY" 183#define MII_MODEL_CICADA_CS8201B 0x0021 184#define MII_STR_CICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY" 185#define MII_MODEL_xxCICADA_CS8201B 0x0021 186#define MII_STR_xxCICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY" 187 188/* Davicom Semiconductor PHYs */ 189#define MII_MODEL_xxDAVICOM_DM9101 0x0000 190#define MII_STR_xxDAVICOM_DM9101 "DM9101 10/100 PHY" 191#define MII_MODEL_DAVICOM_DM9102 0x0004 192#define MII_STR_DAVICOM_DM9102 "DM9102 10/100 PHY" 193#define MII_MODEL_DAVICOM_DM9601 0x000c 194#define MII_STR_DAVICOM_DM9601 "DM9601 10/100 PHY" 195 196/* Enable Semiconductor PHYs (Agere) */ 197#define MII_MODEL_ENABLESEMI_LU3X31FT 0x0001 198#define MII_STR_ENABLESEMI_LU3X31FT "Enable LU3X31FT" 199#define MII_MODEL_ENABLESEMI_88E1000S 0x0004 200#define MII_STR_ENABLESEMI_88E1000S "Enable 88E1000S" 201#define MII_MODEL_ENABLESEMI_88E1000 0x0005 202#define MII_STR_ENABLESEMI_88E1000 "Enable 88E1000" 203 204/* Marvell Semiconductor PHYs */ 205#define MII_MODEL_MARVELL_E1000 0x0000 206#define MII_STR_MARVELL_E1000 "Marvell 88E1000* Gigabit PHY" 207#define MII_MODEL_MARVELL_E1011 0x0002 208#define MII_STR_MARVELL_E1011 "Marvell 88E1011 Gigabit PHY" 209#define MII_MODEL_MARVELL_E1000_3 0x0003 210#define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY" 211#define MII_MODEL_MARVELL_E1000_4 0x0004 212#define MII_STR_MARVELL_E1000_4 "Marvell 88E1000S Gigabit PHY" 213#define MII_MODEL_MARVELL_E1000_5 0x0005 214#define MII_STR_MARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY" 215#define MII_MODEL_MARVELL_E1000_6 0x0006 216#define MII_STR_MARVELL_E1000_6 "Marvell 88E1000 Gigabit PHY" 217#define MII_MODEL_MARVELL_E1111RCJ 0x000c 218#define MII_STR_MARVELL_E1111RCJ "Marvell 88E1111-RCJ Gigabit PHY" 219#define MII_MODEL_xxMARVELL_E1000_2 0x0002 220#define MII_STR_xxMARVELL_E1000_2 "Marvell 88E1000 Gigabit PHY" 221#define MII_MODEL_xxMARVELL_E1000_3 0x0003 222#define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY" 223#define MII_MODEL_xxMARVELL_E1000_5 0x0005 224#define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY" 225#define MII_MODEL_xxMARVELL_E1111 0x000c 226#define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY" 227 228/* Contrived vendor/model for dcphy */ 229#define MII_MODEL_xxDEC_xxDC 0x0001 230#define MII_STR_xxDEC_xxDC "DC" 231 232/* Integrated Circuit Systems PHYs */ 233#define MII_MODEL_xxICS_1890 0x0002 234#define MII_STR_xxICS_1890 "ICS1890 10/100 PHY" 235#define MII_MODEL_xxICS_1892 0x0003 236#define MII_STR_xxICS_1892 "ICS1892 10/100 PHY" 237#define MII_MODEL_xxICS_1893 0x0004 238#define MII_STR_xxICS_1893 "ICS1893 10/100 PHY" 239 240/* Intel PHYs */ 241#define MII_MODEL_xxINTEL_I82553 0x0000 242#define MII_STR_xxINTEL_I82553 "i82553 10/100 PHY" 243#define MII_MODEL_INTEL_I82555 0x0015 244#define MII_STR_INTEL_I82555 "i82555 10/100 PHY" 245#define MII_MODEL_INTEL_I82562EM 0x0032 246#define MII_STR_INTEL_I82562EM "i82562EM 10/100 PHY" 247#define MII_MODEL_INTEL_I82562ET 0x0033 248#define MII_STR_INTEL_I82562ET "i82562ET 10/100 PHY" 249#define MII_MODEL_INTEL_I82553 0x0035 250#define MII_STR_INTEL_I82553 "i82553 10/100 PHY" 251 252/* Jato Technologies PHYs */ 253#define MII_MODEL_JATO_BASEX 0x0000 254#define MII_STR_JATO_BASEX "Jato 1000baseX PHY" 255 256/* Level 1 PHYs */ 257#define MII_MODEL_xxLEVEL1_LXT970 0x0000 258#define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 PHY" 259#define MII_MODEL_xxLEVEL1a_LXT971 0x000e 260#define MII_STR_xxLEVEL1a_LXT971 "LXT971 10/100 PHY" 261 262/* Lucent Technologies PHYs */ 263#define MII_MODEL_LUCENT_LU6612 0x000c 264#define MII_STR_LUCENT_LU6612 "LU6612 10/100 PHY" 265#define MII_MODEL_LUCENT_LU3X51FT 0x0033 266#define MII_STR_LUCENT_LU3X51FT "LU3X51FT 10/100 PHY" 267#define MII_MODEL_LUCENT_LU3X54FT 0x0036 268#define MII_STR_LUCENT_LU3X54FT "LU3X54FT 10/100 PHY" 269 270/* Myson Technology PHYs */ 271#define MII_MODEL_MYSON_MTD972 0x0000 272#define MII_STR_MYSON_MTD972 "MTD972 10/100 PHY" 273 274/* National Semiconductor PHYs */ 275#define MII_MODEL_NATSEMI_DP83840 0x0000 276#define MII_STR_NATSEMI_DP83840 "DP83840 10/100 PHY" 277#define MII_MODEL_NATSEMI_DP83843 0x0001 278#define MII_STR_NATSEMI_DP83843 "DP83843 10/100 PHY" 279#define MII_MODEL_NATSEMI_DP83815 0x0002 280#define MII_STR_NATSEMI_DP83815 "DP83815 10/100 PHY" 281#define MII_MODEL_NATSEMI_DP83891 0x0005 282#define MII_STR_NATSEMI_DP83891 "DP83891 10/100/1000 PHY" 283#define MII_MODEL_NATSEMI_DP83861 0x0006 284#define MII_STR_NATSEMI_DP83861 "DP83861 10/100/1000 PHY" 285 286/* Plessey Semiconductor PHYs */ 287#define MII_MODEL_PLESSEY_NWK914 0x0000 288#define MII_STR_PLESSEY_NWK914 "NWK914 10/100 PHY" 289 290/* Quality Semiconductor PHYs */ 291#define MII_MODEL_QUALSEMI_QS6612 0x0000 292#define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 PHY" 293 294/* Realtek Semiconductor PHYs */ 295#define MII_MODEL_REALTEK_RTL8201L 0x0020 296#define MII_STR_REALTEK_RTL8201L "RTL8201L 10/100 PHY" 297#define MII_MODEL_xxREALTEK_RTL8169S 0x0011 298#define MII_STR_xxREALTEK_RTL8169S "RTL8169S/8110S PHY" 299 300/* Seeq PHYs */ 301#define MII_MODEL_xxSEEQ_80220 0x0003 302#define MII_STR_xxSEEQ_80220 "Seeq 80220 10/100 PHY" 303#define MII_MODEL_xxSEEQ_84220 0x0004 304#define MII_STR_xxSEEQ_84220 "Seeq 84220 10/100 PHY" 305#define MII_MODEL_xxSEEQ_80225 0x0008 306#define MII_STR_xxSEEQ_80225 "Seeq 80225 10/100 PHY" 307 308/* Silicon Integrated Systems PHYs */ 309#define MII_MODEL_xxSIS_900 0x0000 310#define MII_STR_xxSIS_900 "SiS 900 10/100 PHY" 311 312/* Texas Instruments PHYs */ 313#define MII_MODEL_xxTI_TLAN10T 0x0001 314#define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT PHY" 315#define MII_MODEL_xxTI_100VGPMI 0x0002 316#define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan PHY" 317#define MII_MODEL_xxTI_TNETE2101 0x0003 318#define MII_STR_xxTI_TNETE2101 "TNETE2101 PHY" 319 320/* TDK Semiconductor PHYs */ 321#define MII_MODEL_TSC_78Q2120 0x0014 322#define MII_STR_TSC_78Q2120 "78Q2120 10/100 PHY" 323#define MII_MODEL_TSC_78Q2121 0x0015 324#define MII_STR_TSC_78Q2121 "78Q2121 100baseTX PHY" 325 326/* XaQti Corp. PHYs */ 327#define MII_MODEL_XAQTI_XMACII 0x0000 328#define MII_STR_XAQTI_XMACII "XaQti Corp. XMAC II Gigabit PHY" 329