miidevs.h revision 1.42 
1/*	$OpenBSD: miidevs.h,v 1.42 2003/10/05 03:28:34 krw Exp $	*/
2
3/*
4 * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
5 *
6 * generated from:
7 *	OpenBSD: miidevs,v 1.39 2003/10/05 03:24:24 krw Exp
8 */
9/* $NetBSD: miidevs,v 1.3 1998/11/05 03:43:43 thorpej Exp $ */
10
11/*-
12 * Copyright (c) 1998 The NetBSD Foundation, Inc.
13 * All rights reserved.
14 *
15 * This code is derived from software contributed to The NetBSD Foundation
16 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
17 * NASA Ames Research Center.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
21 * are met:
22 * 1. Redistributions of source code must retain the above copyright
23 *    notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 *    notice, this list of conditions and the following disclaimer in the
26 *    documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 *    must display the following acknowledgement:
29 *	This product includes software developed by the NetBSD
30 *	Foundation, Inc. and its contributors.
31 * 4. Neither the name of The NetBSD Foundation nor the names of its
32 *    contributors may be used to endorse or promote products derived
33 *    from this software without specific prior written permission.
34 *
35 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
36 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
37 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
38 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
39 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
40 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
41 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
42 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
43 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
44 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
45 * POSSIBILITY OF SUCH DAMAGE.
46 */
47
48/*
49 * List of known MII OUIs
50 */
51
52#define	MII_OUI_3COM	0x00105a	/* 3com */
53#define	MII_OUI_ALTIMA	0x0010a9	/* Altima Communications */
54#define	MII_OUI_AMD	0x00001a	/* Advanced Micro Devices */
55#define	MII_OUI_BROADCOM	0x001018	/* Broadcom Corporation */
56#define	MII_OUI_ENABLESEMI	0x0010dd	/* Enable Semiconductor */
57#define	MII_OUI_DAVICOM	0x00606e	/* Davicom Semiconductor */
58#define	MII_OUI_MARVELL	0x005043	/* Marvell Semiconductor */
59#define	MII_OUI_ICS	0x00a0be	/* Integrated Circuit Systems */
60#define	MII_OUI_INTEL	0x00aa00	/* Intel */
61#define	MII_OUI_LEVEL1	0x00207b	/* Level 1 */
62#define	MII_OUI_MYSON	0x00c0b4	/* Myson Technology */
63#define	MII_OUI_NATSEMI	0x080017	/* National Semiconductor */
64#define	MII_OUI_QUALSEMI	0x006051	/* Quality Semiconductor */
65#define	MII_OUI_SEEQ	0x00a07d	/* Seeq */
66#define	MII_OUI_SIS	0x00e006	/* Silicon Integrated Systems */
67#define	MII_OUI_TI	0x080028	/* Texas Instruments */
68#define	MII_OUI_TSC	0x00c039	/* TDK Semiconductor */
69#define	MII_OUI_XAQTI	0x00e0ae	/* XaQti Corp. */
70
71/* in the 79c873, AMD uses another OUI (which matches Davicom!) */
72#define	MII_OUI_xxALTIMA	0x000895	/* Altima Communications */
73#define	MII_OUI_xxAMD	0x00606e	/* Advanced Micro Devices */
74
75#define	MII_OUI_xxINTEL	0x00f800	/* Intel (alt) */
76
77/* some vendors have the bits swapped within bytes
78	(ie, ordered as on the wire) */
79#define	MII_OUI_xxBROADCOM	0x000818	/* Broadcom Corporation */
80#define	MII_OUI_xxICS	0x00057d	/* Integrated Circuit Systems */
81#define	MII_OUI_xxSEEQ	0x0005be	/* Seeq */
82#define	MII_OUI_xxSIS	0x000760	/* Silicon Integrated Systems */
83#define	MII_OUI_xxTI	0x100014	/* Texas Instruments */
84#define	MII_OUI_xxXAQTI	0x350700	/* XaQti Corp. */
85
86/* Level 1 is completely different - from right to left.
87	(Two bits get lost in the third OUI byte.) */
88#define	MII_OUI_xxLEVEL1	0x1e0400	/* Level 1 */
89#define	MII_OUI_xxLEVEL1a	0x0004de	/* Level 1 */
90
91/* Don't know what's going on here. */
92#define	MII_OUI_xxDAVICOM	0x006040	/* Davicom Semiconductor */
93
94/* Contrived vendor for dcphy */
95#define	MII_OUI_xxDEC	0x040440	/* Digital Clone */
96
97#define	MII_OUI_xxMARVELL	0x000ac2	/* Marvell Semiconductor */
98
99/*
100 * List of known models.  Grouped by oui.
101 */
102
103/* Advanced Micro Devices PHYs */
104#define	MII_MODEL_xxAMD_79C873	0x0000
105#define	MII_STR_xxAMD_79C873	"Am79C873 10/100 media interface"
106#define	MII_MODEL_AMD_79C873phy	0x0036
107#define	MII_STR_AMD_79C873phy	"Am79C873 internal PHY"
108
109/* Altima Communications PHYs */
110#define	MII_MODEL_xxALTIMA_AC101	0x0021
111#define	MII_STR_xxALTIMA_AC101	"AC101 10/100 media interface"
112#define	MII_MODEL_xxALTIMA_AC101L	0x0012
113#define	MII_STR_xxALTIMA_AC101L	"AC101L 10/100 media interface"
114
115/* Broadcom Corp. PHYs */
116#define	MII_MODEL_xxBROADCOM_BCM5400	0x0004
117#define	MII_STR_xxBROADCOM_BCM5400	"BCM5400 1000baseTX PHY"
118#define	MII_MODEL_xxBROADCOM_BCM5401	0x0005
119#define	MII_STR_xxBROADCOM_BCM5401	"BCM5401 10/100/1000baseTX PHY"
120#define	MII_MODEL_xxBROADCOM_BCM5411	0x0007
121#define	MII_STR_xxBROADCOM_BCM5411	"BCM5411 10/100/1000baseTX PHY"
122#define	MII_MODEL_xxBROADCOM_BCM5421S	0x000e
123#define	MII_STR_xxBROADCOM_BCM5421S	"BCM5421S 10/100/1000baseTX PHY"
124#define	MII_MODEL_xxBROADCOM_BCM5701	0x0011
125#define	MII_STR_xxBROADCOM_BCM5701	"BCM5701 10/100/1000baseTX PHY"
126#define	MII_MODEL_xxBROADCOM_BCM5703	0x0016
127#define	MII_STR_xxBROADCOM_BCM5703	"BCM5703 10/100/1000baseTX PHY"
128#define	MII_MODEL_xxBROADCOM_BCM5704	0x0019
129#define	MII_STR_xxBROADCOM_BCM5704	"BCM5704 10/100/1000baseTX PHY"
130#define	MII_MODEL_xxBROADCOM_BCM5705	0x001a
131#define	MII_STR_xxBROADCOM_BCM5705	"BCM5705 10/100/1000baseTX PHY"
132#define	MII_MODEL_BROADCOM_BCM5400	0x0004
133#define	MII_STR_BROADCOM_BCM5400	"BCM5400 1000baseTX PHY"
134#define	MII_MODEL_BROADCOM_BCM5401	0x0005
135#define	MII_STR_BROADCOM_BCM5401	"BCM5401 1000baseTX PHY"
136#define	MII_MODEL_BROADCOM_BCM5411	0x0007
137#define	MII_STR_BROADCOM_BCM5411	"BCM5411 1000baseTX PHY"
138#define	MII_MODEL_BROADCOM_3C905B	0x0012
139#define	MII_STR_BROADCOM_3C905B	"Broadcom 3C905B internal PHY"
140#define	MII_MODEL_BROADCOM_3C905C	0x0017
141#define	MII_STR_BROADCOM_3C905C	"Broadcom 3C905C internal PHY"
142#define	MII_MODEL_BROADCOM_BCM5221	0x001e
143#define	MII_STR_BROADCOM_BCM5221	"BCM5221 100baseTX PHY"
144#define	MII_MODEL_BROADCOM_BCM5201	0x0021
145#define	MII_STR_BROADCOM_BCM5201	"BCM5201 10/100 media interface"
146#define	MII_MODEL_BROADCOM_BCM4401_0x0036	BCM4401
147#define	MII_STR_BROADCOM_BCM4401_0x0036	"10/100baseTX PHY"
148
149/* Davicom Semiconductor PHYs */
150#define	MII_MODEL_DAVICOM_DM9102	0x0004
151#define	MII_STR_DAVICOM_DM9102	"DM9102 10/100 media interface"
152#define	MII_MODEL_xxDAVICOM_DM9101	0x0000
153#define	MII_STR_xxDAVICOM_DM9101	"DM9101 10/100 media interface"
154
155/* Enable Semiconductor PHYs */
156#define	MII_MODEL_ENABLESEMI_88E1000	0x0005
157#define	MII_STR_ENABLESEMI_88E1000	"Enable 88E1000"
158#define	MII_MODEL_ENABLESEMI_88E1000S	0x0004
159#define	MII_STR_ENABLESEMI_88E1000S	"Enable 88E1000S"
160
161/* Marvell Semiconductor PHYs */
162#define	MII_MODEL_MARVELL_E1000	0x0000
163#define	MII_STR_MARVELL_E1000	"Marvell 88E1000* Gigabit PHY"
164#define	MII_MODEL_MARVELL_E1011	0x0002
165#define	MII_STR_MARVELL_E1011	"Marvell 88E1011 Gigabit PHY"
166#define	MII_MODEL_MARVELL_E1000_3	0x0003
167#define	MII_STR_MARVELL_E1000_3	"Marvell 88E1000 Gigabit PHY"
168#define	MII_MODEL_MARVELL_E1000_4	0x0004
169#define	MII_STR_MARVELL_E1000_4	"Marvell 88E1000S Gigabit PHY"
170#define	MII_MODEL_MARVELL_E1000_5	0x0005
171#define	MII_STR_MARVELL_E1000_5	"Marvell 88E1000 Gigabit PHY"
172#define	MII_MODEL_MARVELL_E1000_6	0x0006
173#define	MII_STR_MARVELL_E1000_6	"Marvell 88E1000 Gigabit PHY"
174#define	MII_MODEL_xxMARVELL_E1000_3	0x0003
175#define	MII_STR_xxMARVELL_E1000_3	"Marvell 88E1000 Gigabit PHY"
176#define	MII_MODEL_xxMARVELL_E1000_5	0x0005
177#define	MII_STR_xxMARVELL_E1000_5	"Marvell 88E1000 Gigabit PHY"
178
179/* Contrived vendor/model for dcphy */
180#define	MII_MODEL_xxDEC_xxDC	0x0001
181#define	MII_STR_xxDEC_xxDC	"DC"
182
183/* Integrated Circuit Systems PHYs */
184#define	MII_MODEL_xxICS_1890	0x0002
185#define	MII_STR_xxICS_1890	"ICS1890 10/100 media interface"
186#define	MII_MODEL_xxICS_1892	0x0003
187#define	MII_STR_xxICS_1892	"ICS1892 10/100 media interface"
188#define	MII_MODEL_xxICS_1893	0x0004
189#define	MII_STR_xxICS_1893	"ICS1893 10/100 media interface"
190
191/* Intel PHYs */
192#define	MII_MODEL_xxINTEL_I82553	0x0000
193#define	MII_STR_xxINTEL_I82553	"i82553 10/100 media interface"
194#define	MII_MODEL_INTEL_I82555	0x0015
195#define	MII_STR_INTEL_I82555	"i82555 10/100 media interface"
196#define	MII_MODEL_INTEL_I82562EM	0x0032
197#define	MII_STR_INTEL_I82562EM	"i82562EM 10/100 media interface"
198#define	MII_MODEL_INTEL_I82562ET	0x0033
199#define	MII_STR_INTEL_I82562ET	"i82562ET 10/100 media interface"
200#define	MII_MODEL_INTEL_I82553	0x0035
201#define	MII_STR_INTEL_I82553	"i82553 10/100 media interface"
202
203/* Level 1 PHYs */
204#define	MII_MODEL_xxLEVEL1_LXT970	0x0000
205#define	MII_STR_xxLEVEL1_LXT970	"LXT970 10/100 media interface"
206#define	MII_MODEL_xxLEVEL1a_LXT971	0x000e
207#define	MII_STR_xxLEVEL1a_LXT971	"LXT971 10/100 media interface"
208
209/* Myson Technology PHYs */
210#define	MII_MODEL_MYSON_MTD972	0x0000
211#define	MII_STR_MYSON_MTD972	"MTD972 10/100 media interface"
212
213/* National Semiconductor PHYs */
214#define	MII_MODEL_NATSEMI_DP83840	0x0000
215#define	MII_STR_NATSEMI_DP83840	"DP83840 10/100 media interface"
216#define	MII_MODEL_NATSEMI_DP83843	0x0001
217#define	MII_STR_NATSEMI_DP83843	"DP83843 10/100 media interface"
218#define	MII_MODEL_NATSEMI_DP83815	0x0002
219#define	MII_STR_NATSEMI_DP83815	"DP83815 10/100 integrated"
220#define	MII_MODEL_NATSEMI_DP83891	0x0005
221#define	MII_STR_NATSEMI_DP83891	"DP83891 10/100/1000 media interface"
222#define	MII_MODEL_NATSEMI_DP83861	0x0006
223#define	MII_STR_NATSEMI_DP83861	"DP83861 10/100/1000 media interface"
224
225/* Quality Semiconductor PHYs */
226#define	MII_MODEL_QUALSEMI_QS6612	0x0000
227#define	MII_STR_QUALSEMI_QS6612	"QS6612 10/100 media interface"
228
229/* Seeq PHYs */
230#define	MII_MODEL_xxSEEQ_80220	0x0003
231#define	MII_STR_xxSEEQ_80220	"Seeq 80220 10/100 media interface"
232#define	MII_MODEL_xxSEEQ_84220	0x0004
233#define	MII_STR_xxSEEQ_84220	"Seeq 84220 10/100 media interface"
234
235/* Silicon Integrated Systems PHYs */
236#define	MII_MODEL_xxSIS_900	0x0000
237#define	MII_STR_xxSIS_900	"SiS 900 10/100 media interface"
238
239/* Texas Instruments PHYs */
240#define	MII_MODEL_xxTI_TLAN10T	0x0001
241#define	MII_STR_xxTI_TLAN10T	"ThunderLAN 10baseT media interface"
242#define	MII_MODEL_xxTI_100VGPMI	0x0002
243#define	MII_STR_xxTI_100VGPMI	"ThunderLAN 100VG-AnyLan media interface"
244#define	MII_MODEL_xxTI_TNETE2101	0x0003
245#define	MII_STR_xxTI_TNETE2101	"TNETE2101 media interface"
246
247/* TDK Semiconductor PHYs */
248#define	MII_MODEL_TSC_78Q2120	0x0014
249#define	MII_STR_TSC_78Q2120	"78Q2120 10/100 media interface"
250#define	MII_MODEL_TSC_78Q2121	0x0015
251#define	MII_STR_TSC_78Q2121	"78Q2121 100baseTX media interface"
252
253/* XaQti Corp. PHYs */
254#define	MII_MODEL_XAQTI_XMACII	0x0000
255#define	MII_STR_XAQTI_XMACII	"XaQti Corp. XMAC II gigabit interface"
256