miidevs.h revision 1.24
1/* $OpenBSD: miidevs.h,v 1.24 2001/06/01 19:47:20 deraadt Exp $ */ 2 3/* 4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. 5 * 6 * generated from: 7 * OpenBSD: miidevs,v 1.21 2001/06/01 19:47:13 deraadt Exp 8 */ 9/* $NetBSD: miidevs,v 1.3 1998/11/05 03:43:43 thorpej Exp $ */ 10 11/*- 12 * Copyright (c) 1998 The NetBSD Foundation, Inc. 13 * All rights reserved. 14 * 15 * This code is derived from software contributed to The NetBSD Foundation 16 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 17 * NASA Ames Research Center. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgement: 29 * This product includes software developed by the NetBSD 30 * Foundation, Inc. and its contributors. 31 * 4. Neither the name of The NetBSD Foundation nor the names of its 32 * contributors may be used to endorse or promote products derived 33 * from this software without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 36 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 37 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 38 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 39 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 40 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 41 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 42 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 43 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 44 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 45 * POSSIBILITY OF SUCH DAMAGE. 46 */ 47 48/* 49 * List of known MII OUIs 50 */ 51 52#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */ 53#define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */ 54#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */ 55#define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */ 56#define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */ 57#define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */ 58#define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */ 59#define MII_OUI_INTEL 0x00aa00 /* Intel */ 60#define MII_OUI_LEVEL1 0x00207b /* Level 1 */ 61#define MII_OUI_MYSON 0x00c0b4 /* Myson Technology */ 62#define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */ 63#define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */ 64#define MII_OUI_SEEQ 0x00a07d /* Seeq */ 65#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */ 66#define MII_OUI_TI 0x080028 /* Texas Instruments */ 67#define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */ 68#define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */ 69 70/* in the 79c873, AMD uses another OUI (which matches Davicom!) */ 71#define MII_OUI_xxALTIMA 0x000895 /* Altima Communications */ 72#define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */ 73 74#define MII_OUI_xxINTEL 0x00f800 /* Intel (alt) */ 75 76/* some vendors have the bits swapped within bytes 77 (ie, ordered as on the wire) */ 78#define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */ 79#define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */ 80#define MII_OUI_xxSEEQ 0x0005be /* Seeq */ 81#define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */ 82#define MII_OUI_xxTI 0x100014 /* Texas Instruments */ 83#define MII_OUI_xxXAQTI 0x350700 /* XaQti Corp. */ 84 85/* Level 1 is completely different - from right to left. 86 (Two bits get lost in the third OUI byte.) */ 87#define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */ 88 89/* Don't know what's going on here. */ 90#define MII_OUI_xxDAVICOM 0x006040 /* Davicom Semiconductor */ 91 92/* Contrived vendor for dcphy */ 93#define MII_OUI_xxDEC 0x040440 /* Digital Clone */ 94 95/* 96 * List of known models. Grouped by oui. 97 */ 98 99/* Advanced Micro Devices PHYs */ 100#define MII_MODEL_xxAMD_79C873 0x0000 101#define MII_STR_xxAMD_79C873 "Am79C873 10/100 media interface" 102#define MII_MODEL_AMD_79C873phy 0x0036 103#define MII_STR_AMD_79C873phy "Am79C873 internal PHY" 104 105/* Altima Communications PHYs */ 106#define MII_MODEL_xxALTIMA_AC101 0x0021 107#define MII_STR_xxALTIMA_AC101 "AC101 10/100 media interface" 108 109/* Broadcom Corp. PHYs */ 110#define MII_MODEL_BROADCOM_3C905C 0x0017 111#define MII_STR_BROADCOM_3C905C "Broadcom 3C905C internal PHY" 112#define MII_MODEL_BROADCOM_BCM5201 0x0021 113#define MII_STR_BROADCOM_BCM5201 "BCM5201 10/100 media interface" 114#define MII_MODEL_xxBROADCOM_BCM5400 0x0004 115#define MII_STR_xxBROADCOM_BCM5400 "BCM5400 1000baseTX PHY" 116#define MII_MODEL_BROADCOM_BCM5400 0x0004 117#define MII_STR_BROADCOM_BCM5400 "BCM5400 1000baseTX PHY" 118#define MII_MODEL_BROADCOM_BCM5401 0x0005 119#define MII_STR_BROADCOM_BCM5401 "BCM5401 1000baseTX PHY" 120#define MII_MODEL_BROADCOM_BCM5411 0x0007 121#define MII_STR_BROADCOM_BCM5411 "BCM5411 1000baseTX PHY" 122#define MII_MODEL_BROADCOM_BCM5221 0x001e 123#define MII_STR_BROADCOM_BCM5221 "BCM5221 100baseTX PHY" 124 125/* Davicom Semiconductor PHYs */ 126#define MII_MODEL_xxDAVICOM_DM9101 0x0000 127#define MII_STR_xxDAVICOM_DM9101 "DM9101 10/100 media interface" 128 129/* Marvell Semiconductor PHYs */ 130#define MII_MODEL_MARVELL_E1000 0x0000 131#define MII_STR_MARVELL_E1000 "Marvell Semiconductor 88E1000* Gigabit" 132 133/* Contrived vendor/model for dcphy */ 134#define MII_MODEL_xxDEC_xxDC 0x0001 135#define MII_STR_xxDEC_xxDC "DC" 136 137/* Integrated Circuit Systems PHYs */ 138#define MII_MODEL_xxICS_1890 0x0002 139#define MII_STR_xxICS_1890 "ICS1890 10/100 media interface" 140#define MII_MODEL_xxICS_1892 0x0003 141#define MII_STR_xxICS_1892 "ICS1892 10/100 media interface" 142 143/* Intel PHYs */ 144#define MII_MODEL_xxINTEL_I82553 0x0000 145#define MII_STR_xxINTEL_I82553 "i82553 10/100 media interface" 146#define MII_MODEL_INTEL_I82555 0x0015 147#define MII_STR_INTEL_I82555 "i82555 10/100 media interface" 148#define MII_MODEL_INTEL_I82562EM 0x0032 149#define MII_STR_INTEL_I82562EM "i82562EM 10/100 media interface" 150#define MII_MODEL_INTEL_I82562ET 0x0033 151#define MII_STR_INTEL_I82562ET "i82562ET 10/100 media interface" 152#define MII_MODEL_INTEL_I82553 0x0035 153#define MII_STR_INTEL_I82553 "i82553 10/100 media interface" 154 155/* Level 1 PHYs */ 156#define MII_MODEL_xxLEVEL1_LXT970 0x0000 157#define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface" 158 159/* Myson Technology PHYs */ 160#define MII_MODEL_MYSON_MTD972 0x0000 161#define MII_STR_MYSON_MTD972 "MTD972 10/100 media interface" 162 163/* National Semiconductor PHYs */ 164#define MII_MODEL_NATSEMI_DP83840 0x0000 165#define MII_STR_NATSEMI_DP83840 "DP83840 10/100 media interface" 166#define MII_MODEL_NATSEMI_DP83843 0x0001 167#define MII_STR_NATSEMI_DP83843 "DP83843 10/100 media interface" 168#define MII_MODEL_NATSEMI_DP83815 0x0002 169#define MII_STR_NATSEMI_DP83815 "DP83815 10/100 integrated" 170#define MII_MODEL_NATSEMI_DP83891 0x0005 171#define MII_STR_NATSEMI_DP83891 "DP83891 10/100/1000 media interface" 172#define MII_MODEL_NATSEMI_DP83861 0x0006 173#define MII_STR_NATSEMI_DP83861 "DP83861 10/100/1000 media interface" 174 175/* Quality Semiconductor PHYs */ 176#define MII_MODEL_QUALSEMI_QS6612 0x0000 177#define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 media interface" 178 179/* Seeq PHYs */ 180#define MII_MODEL_xxSEEQ_80220 0x0003 181#define MII_STR_xxSEEQ_80220 "Seeq 80220 10/100 media interface" 182#define MII_MODEL_xxSEEQ_84220 0x0004 183#define MII_STR_xxSEEQ_84220 "Seeq 84220 10/100 media interface" 184 185/* Silicon Integrated Systems PHYs */ 186#define MII_MODEL_xxSIS_900 0x0000 187#define MII_STR_xxSIS_900 "SiS 900 10/100 media interface" 188 189/* Texas Instruments PHYs */ 190#define MII_MODEL_xxTI_TLAN10T 0x0001 191#define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT media interface" 192#define MII_MODEL_xxTI_100VGPMI 0x0002 193#define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan media interface" 194#define MII_MODEL_xxTI_TNETE2101 0x0003 195#define MII_STR_xxTI_TNETE2101 "TNETE2101 media interface" 196 197/* TDK Semiconductor PHYs */ 198#define MII_MODEL_TSC_78Q2120 0x0014 199#define MII_STR_TSC_78Q2120 "78Q2120 10/100 media interface" 200#define MII_MODEL_TSC_78Q2121 0x0015 201#define MII_STR_TSC_78Q2121 "78Q2121 100baseTX media interface" 202 203/* XaQti Corp. PHYs */ 204#define MII_MODEL_XAQTI_XMACII 0x0000 205#define MII_STR_XAQTI_XMACII "XaQti Corp. XMAC II gigabit interface" 206