miidevs.h revision 1.108
1/* $OpenBSD: miidevs.h,v 1.108 2008/10/25 00:23:24 brad Exp $ */ 2 3/* 4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. 5 * 6 * generated from: 7 * OpenBSD: miidevs,v 1.105 2008/10/25 00:23:11 brad Exp 8 */ 9/* $NetBSD: miidevs,v 1.3 1998/11/05 03:43:43 thorpej Exp $ */ 10 11/*- 12 * Copyright (c) 1998 The NetBSD Foundation, Inc. 13 * All rights reserved. 14 * 15 * This code is derived from software contributed to The NetBSD Foundation 16 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 17 * NASA Ames Research Center. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41/* 42 * List of known MII OUIs 43 */ 44#define MII_OUI_AMD 0x00001a /* AMD */ 45#define MII_OUI_REALTEK 0x000020 /* Realtek */ 46#define MII_OUI_VITESSE 0x0001c1 /* Vitesse */ 47#define MII_OUI_CICADA 0x0003f1 /* Cicada */ 48#define MII_OUI_CENIX 0x000749 /* CENiX */ 49#define MII_OUI_BROADCOM2 0x000af7 /* Broadcom */ 50#define MII_OUI_ASIX 0x000ec6 /* ASIX */ 51#define MII_OUI_BROADCOM 0x001018 /* Broadcom */ 52#define MII_OUI_3COM 0x00105a /* 3com */ 53#define MII_OUI_ALTIMA 0x0010a9 /* Altima */ 54#define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semi. */ 55#define MII_OUI_ATHEROS 0x001374 /* Atheros */ 56#define MII_OUI_JMICRON 0x001b8c /* JMicron */ 57#define MII_OUI_LEVEL1 0x00207b /* Level 1 */ 58#define MII_OUI_VIA 0x004063 /* VIA Networking */ 59#define MII_OUI_MARVELL 0x005043 /* Marvell */ 60#define MII_OUI_LUCENT 0x00601d /* Lucent */ 61#define MII_OUI_QUALITYSEMI 0x006051 /* Quality Semi. */ 62#define MII_OUI_DAVICOM 0x00606e /* Davicom */ 63#define MII_OUI_SMSC 0x00800f /* Standard Microsystems */ 64#define MII_OUI_ICPLUS 0x0090c3 /* IC Plus */ 65#define MII_OUI_TOPICSEMI 0x0090c3 /* Topic Semi. */ 66#define MII_OUI_AGERE 0x00a0bc /* Agere */ 67#define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */ 68#define MII_OUI_SEEQ 0x00a07d /* Seeq */ 69#define MII_OUI_INTEL 0x00aa00 /* Intel */ 70#define MII_OUI_TDK 0x00c039 /* TDK */ 71#define MII_OUI_MYSON 0x00c0b4 /* Myson */ 72#define MII_OUI_PMCSIERRA 0x00e004 /* PMC-Sierra */ 73#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */ 74#define MII_OUI_REALTEK2 0x00e04c /* Realtek */ 75#define MII_OUI_JATO 0x00e083 /* Jato Technologies */ 76#define MII_OUI_XAQTI 0x00e0ae /* XaQti */ 77#define MII_OUI_PLESSEYSEMI 0x046b40 /* Plessey Semi. */ 78#define MII_OUI_NATSEMI 0x080017 /* National Semi. */ 79#define MII_OUI_TI 0x080028 /* Texas Instruments */ 80 81/* in the 79c873, AMD uses another OUI (which matches Davicom!) */ 82#define MII_OUI_xxALTIMA 0x000895 /* Altima */ 83#define MII_OUI_xxAMD 0x00606e /* AMD */ 84#define MII_OUI_xxCICADA 0x00c08f /* Cicada (alt) */ 85#define MII_OUI_xxINTEL 0x00f800 /* Intel (alt) */ 86 87/* some vendors have the bits swapped within bytes 88 (ie, ordered as on the wire) */ 89#define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */ 90#define MII_OUI_xxSEEQ 0x0005be /* Seeq */ 91#define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */ 92#define MII_OUI_xxBROADCOM 0x000818 /* Broadcom */ 93#define MII_OUI_xxTI 0x100014 /* Texas Instruments */ 94#define MII_OUI_xxXAQTI 0x350700 /* XaQti */ 95 96/* Level 1 is completely different - from right to left. 97 (Two bits get lost in the third OUI byte.) */ 98#define MII_OUI_xxLEVEL1a 0x0004de /* Level 1 */ 99#define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */ 100 101/* Don't know what's going on here. */ 102#define MII_OUI_xxBROADCOM2 0x0050ef /* Broadcom */ 103#define MII_OUI_xxDAVICOM 0x006040 /* Davicom */ 104 105/* This is the OUI of the gigE PHY in the RealTek 8169S/8110S chips */ 106#define MII_OUI_xxREALTEK 0x000732 /* Realtek */ 107 108/* Contrived vendor for dcphy */ 109#define MII_OUI_xxDEC 0x040440 /* Digital Clone */ 110 111#define MII_OUI_xxMARVELL 0x000ac2 /* Marvell */ 112 113/* 114 * List of known models. Grouped by oui. 115 */ 116 117/* AMD PHYs */ 118#define MII_MODEL_xxAMD_79C873 0x0000 119#define MII_STR_xxAMD_79C873 "Am79C873 10/100 PHY" 120#define MII_MODEL_AMD_79C875phy 0x0014 121#define MII_STR_AMD_79C875phy "Am79C875 quad PHY" 122#define MII_MODEL_AMD_79C873phy 0x0036 123#define MII_STR_AMD_79C873phy "Am79C873 internal PHY" 124 125/* Agere PHYs */ 126#define MII_MODEL_AGERE_ET1011 0x0004 127#define MII_STR_AGERE_ET1011 "ET1011 10/100/1000baseT PHY" 128 129/* Atheros PHYs */ 130#define MII_MODEL_ATHEROS_F1 0x0001 131#define MII_STR_ATHEROS_F1 "F1 10/100/1000 PHY" 132#define MII_MODEL_ATHEROS_F2 0x0002 133#define MII_STR_ATHEROS_F2 "F2 10/100 PHY" 134 135/* Altima PHYs */ 136#define MII_MODEL_xxALTIMA_AC_UNKNOWN 0x0001 137#define MII_STR_xxALTIMA_AC_UNKNOWN "AC_UNKNOWN 10/100 PHY" 138#define MII_MODEL_xxALTIMA_AC101L 0x0012 139#define MII_STR_xxALTIMA_AC101L "AC101L 10/100 PHY" 140#define MII_MODEL_xxALTIMA_AC101 0x0021 141#define MII_STR_xxALTIMA_AC101 "AC101 10/100 PHY" 142 143/* Broadcom PHYs */ 144#define MII_MODEL_xxBROADCOM_BCM5400 0x0004 145#define MII_STR_xxBROADCOM_BCM5400 "BCM5400 1000baseT PHY" 146#define MII_MODEL_xxBROADCOM_BCM5401 0x0005 147#define MII_STR_xxBROADCOM_BCM5401 "BCM5401 10/100/1000baseT PHY" 148#define MII_MODEL_xxBROADCOM_BCM5411 0x0007 149#define MII_STR_xxBROADCOM_BCM5411 "BCM5411 10/100/1000baseT PHY" 150#define MII_MODEL_xxBROADCOM_BCM5462 0x000d 151#define MII_STR_xxBROADCOM_BCM5462 "BCM5462 10/100/1000baseT PHY" 152#define MII_MODEL_xxBROADCOM_BCM5421 0x000e 153#define MII_STR_xxBROADCOM_BCM5421 "BCM5421 10/100/1000baseT PHY" 154#define MII_MODEL_xxBROADCOM_BCM5752 0x0010 155#define MII_STR_xxBROADCOM_BCM5752 "BCM5752 10/100/1000baseT PHY" 156#define MII_MODEL_xxBROADCOM_BCM5701 0x0011 157#define MII_STR_xxBROADCOM_BCM5701 "BCM5701 10/100/1000baseT PHY" 158#define MII_MODEL_xxBROADCOM_BCM5706 0x0015 159#define MII_STR_xxBROADCOM_BCM5706 "BCM5706 10/100/1000baseT/SX PHY" 160#define MII_MODEL_xxBROADCOM_BCM5703 0x0016 161#define MII_STR_xxBROADCOM_BCM5703 "BCM5703 10/100/1000baseT PHY" 162#define MII_MODEL_xxBROADCOM_BCM5750 0x0018 163#define MII_STR_xxBROADCOM_BCM5750 "BCM5750 10/100/1000baseT PHY" 164#define MII_MODEL_xxBROADCOM_BCM5704 0x0019 165#define MII_STR_xxBROADCOM_BCM5704 "BCM5704 10/100/1000baseT PHY" 166#define MII_MODEL_xxBROADCOM_BCM5705 0x001a 167#define MII_STR_xxBROADCOM_BCM5705 "BCM5705 10/100/1000baseT PHY" 168#define MII_MODEL_xxBROADCOM_BCM54K2 0x002e 169#define MII_STR_xxBROADCOM_BCM54K2 "BCM54K2 10/100/1000baseT PHY" 170#define MII_MODEL_xxBROADCOM_BCM5714 0x0034 171#define MII_STR_xxBROADCOM_BCM5714 "BCM5714 10/100/1000baseT/SX PHY" 172#define MII_MODEL_xxBROADCOM_BCM5780 0x0035 173#define MII_STR_xxBROADCOM_BCM5780 "BCM5780 10/100/1000baseT/SX PHY" 174#define MII_MODEL_xxBROADCOM_BCM5708C 0x0036 175#define MII_STR_xxBROADCOM_BCM5708C "BCM5708C 10/100/1000baseT PHY" 176#define MII_MODEL_xxBROADCOM2_BCM5755 0x000c 177#define MII_STR_xxBROADCOM2_BCM5755 "BCM5755 10/100/1000baseT PHY" 178#define MII_MODEL_xxBROADCOM2_BCM5787 0x000e 179#define MII_STR_xxBROADCOM2_BCM5787 "BCM5787 10/100/1000baseT PHY" 180#define MII_MODEL_xxBROADCOM2_BCM5708S 0x0015 181#define MII_STR_xxBROADCOM2_BCM5708S "BCM5708S 1000/2500baseSX PHY" 182#define MII_MODEL_xxBROADCOM2_BCM5722 0x002d 183#define MII_STR_xxBROADCOM2_BCM5722 "BCM5722 10/100/1000baseT PHY" 184#define MII_MODEL_BROADCOM_BCM5400 0x0004 185#define MII_STR_BROADCOM_BCM5400 "BCM5400 1000baseT PHY" 186#define MII_MODEL_BROADCOM_BCM5401 0x0005 187#define MII_STR_BROADCOM_BCM5401 "BCM5401 1000baseT PHY" 188#define MII_MODEL_BROADCOM_BCM5411 0x0007 189#define MII_STR_BROADCOM_BCM5411 "BCM5411 1000baseT PHY" 190#define MII_MODEL_BROADCOM_3C905B 0x0012 191#define MII_STR_BROADCOM_3C905B "3C905B internal PHY" 192#define MII_MODEL_BROADCOM_3C905C 0x0017 193#define MII_STR_BROADCOM_3C905C "3C905C internal PHY" 194#define MII_MODEL_BROADCOM_BCM5221 0x001e 195#define MII_STR_BROADCOM_BCM5221 "BCM5221 100baseTX PHY" 196#define MII_MODEL_BROADCOM_BCM5201 0x0021 197#define MII_STR_BROADCOM_BCM5201 "BCM5201 10/100 PHY" 198#define MII_MODEL_BROADCOM_BCM5214 0x0028 199#define MII_STR_BROADCOM_BCM5214 "BCM5214 Quad 10/100 PHY" 200#define MII_MODEL_BROADCOM_BCM5222 0x0032 201#define MII_STR_BROADCOM_BCM5222 "BCM5222 Dual 10/100 PHY" 202#define MII_MODEL_BROADCOM_BCM5220 0x0033 203#define MII_STR_BROADCOM_BCM5220 "BCM5220 10/100 PHY" 204#define MII_MODEL_BROADCOM_BCM4401 0x0036 205#define MII_STR_BROADCOM_BCM4401 "BCM4401 10/100baseTX PHY" 206#define MII_MODEL_BROADCOM2_BCM5906 0x0004 207#define MII_STR_BROADCOM2_BCM5906 "BCM5906 10/100baseTX PHY" 208 209/* Cicada PHYs (now owned by Vitesse) */ 210#define MII_MODEL_xxCICADA_CS8201B 0x0021 211#define MII_STR_xxCICADA_CS8201B "CS8201 10/100/1000TX PHY" 212#define MII_MODEL_CICADA_CS8201 0x0001 213#define MII_STR_CICADA_CS8201 "CS8201 10/100/1000TX PHY" 214#define MII_MODEL_CICADA_CS8204 0x0004 215#define MII_STR_CICADA_CS8204 "CS8204 10/100/1000TX PHY" 216#define MII_MODEL_CICADA_VSC8211 0x000b 217#define MII_STR_CICADA_VSC8211 "VSC8211 10/100/1000 PHY" 218#define MII_MODEL_CICADA_CS8201A 0x0020 219#define MII_STR_CICADA_CS8201A "CS8201 10/100/1000TX PHY" 220#define MII_MODEL_CICADA_CS8201B 0x0021 221#define MII_STR_CICADA_CS8201B "CS8201 10/100/1000TX PHY" 222 223/* Davicom PHYs */ 224#define MII_MODEL_xxDAVICOM_DM9101 0x0000 225#define MII_STR_xxDAVICOM_DM9101 "DM9101 10/100 PHY" 226#define MII_MODEL_DAVICOM_DM9102 0x0004 227#define MII_STR_DAVICOM_DM9102 "DM9102 10/100 PHY" 228#define MII_MODEL_DAVICOM_DM9601 0x000c 229#define MII_STR_DAVICOM_DM9601 "DM9601 10/100 PHY" 230 231/* Contrived vendor/model for dcphy */ 232#define MII_MODEL_xxDEC_xxDC 0x0001 233#define MII_STR_xxDEC_xxDC "DC" 234 235/* Enable Semi. PHYs (Agere) */ 236#define MII_MODEL_ENABLESEMI_LU3X31FT 0x0001 237#define MII_STR_ENABLESEMI_LU3X31FT "LU3X31FT" 238#define MII_MODEL_ENABLESEMI_LU3X31T2 0x0002 239#define MII_STR_ENABLESEMI_LU3X31T2 "LU3X31T2" 240#define MII_MODEL_ENABLESEMI_88E1000S 0x0004 241#define MII_STR_ENABLESEMI_88E1000S "88E1000S" 242#define MII_MODEL_ENABLESEMI_88E1000 0x0005 243#define MII_STR_ENABLESEMI_88E1000 "88E1000" 244 245/* IC Plus PHYs */ 246#define MII_MODEL_ICPLUS_IP100 0x0004 247#define MII_STR_ICPLUS_IP100 "IP100 10/100 PHY" 248#define MII_MODEL_ICPLUS_IP101 0x0005 249#define MII_STR_ICPLUS_IP101 "IP101 10/100 PHY" 250#define MII_MODEL_ICPLUS_IP1000A 0x0008 251#define MII_STR_ICPLUS_IP1000A "IP1000A 10/100/1000 PHY" 252#define MII_MODEL_ICPLUS_IP1001 0x0025 253#define MII_STR_ICPLUS_IP1001 "IP1001 10/100/1000 PHY" 254 255/* Integrated Circuit Systems PHYs */ 256#define MII_MODEL_xxICS_1890 0x0002 257#define MII_STR_xxICS_1890 "ICS1890 10/100 PHY" 258#define MII_MODEL_xxICS_1892 0x0003 259#define MII_STR_xxICS_1892 "ICS1892 10/100 PHY" 260#define MII_MODEL_xxICS_1893 0x0004 261#define MII_STR_xxICS_1893 "ICS1893 10/100 PHY" 262 263/* Intel PHYs */ 264#define MII_MODEL_xxINTEL_I82553 0x0000 265#define MII_STR_xxINTEL_I82553 "i82553 10/100 PHY" 266#define MII_MODEL_INTEL_I82555 0x0015 267#define MII_STR_INTEL_I82555 "i82555 10/100 PHY" 268#define MII_MODEL_INTEL_I82562G 0x0031 269#define MII_STR_INTEL_I82562G "i82562G 10/100 PHY" 270#define MII_MODEL_INTEL_I82562EM 0x0032 271#define MII_STR_INTEL_I82562EM "i82562EM 10/100 PHY" 272#define MII_MODEL_INTEL_I82562ET 0x0033 273#define MII_STR_INTEL_I82562ET "i82562ET 10/100 PHY" 274#define MII_MODEL_INTEL_I82553 0x0035 275#define MII_STR_INTEL_I82553 "i82553 10/100 PHY" 276 277/* Jato Technologies PHYs */ 278#define MII_MODEL_JATO_BASEX 0x0000 279#define MII_STR_JATO_BASEX "Jato 1000baseX PHY" 280 281/* JMicron PHYs */ 282#define MII_MODEL_JMICRON_JMP211 0x0021 283#define MII_STR_JMICRON_JMP211 "JMP211 10/100/1000 PHY" 284#define MII_MODEL_JMICRON_JMP202 0x0022 285#define MII_STR_JMICRON_JMP202 "JMP202 10/100 PHY" 286 287/* Level 1 PHYs */ 288#define MII_MODEL_xxLEVEL1_LXT970 0x0000 289#define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 PHY" 290#define MII_MODEL_xxLEVEL1a_LXT971 0x000e 291#define MII_STR_xxLEVEL1a_LXT971 "LXT971 10/100 PHY" 292#define MII_MODEL_LEVEL1_LXT1000_OLD 0x0003 293#define MII_STR_LEVEL1_LXT1000_OLD "LXT1000 10/100/1000 PHY" 294#define MII_MODEL_LEVEL1_LXT1000 0x000c 295#define MII_STR_LEVEL1_LXT1000 "LXT1000 10/100/1000 PHY" 296 297/* Lucent PHYs */ 298#define MII_MODEL_LUCENT_LU6612 0x000c 299#define MII_STR_LUCENT_LU6612 "LU6612 10/100 PHY" 300#define MII_MODEL_LUCENT_LU3X51FT 0x0033 301#define MII_STR_LUCENT_LU3X51FT "LU3X51FT 10/100 PHY" 302#define MII_MODEL_LUCENT_LU3X54FT 0x0036 303#define MII_STR_LUCENT_LU3X54FT "LU3X54FT 10/100 PHY" 304 305/* Marvell PHYs */ 306#define MII_MODEL_xxMARVELL_E1000_5 0x0002 307#define MII_STR_xxMARVELL_E1000_5 "88E1000 5 Gigabit PHY" 308#define MII_MODEL_xxMARVELL_E1000_6 0x0003 309#define MII_STR_xxMARVELL_E1000_6 "88E1000 6 Gigabit PHY" 310#define MII_MODEL_xxMARVELL_E1000_7 0x0005 311#define MII_STR_xxMARVELL_E1000_7 "88E1000 7 Gigabit PHY" 312#define MII_MODEL_xxMARVELL_E1111 0x000c 313#define MII_STR_xxMARVELL_E1111 "88E1111 Gigabit PHY" 314#define MII_MODEL_MARVELL_E1000_1 0x0000 315#define MII_STR_MARVELL_E1000_1 "88E1000 1 Gigabit PHY" 316#define MII_MODEL_MARVELL_E1011 0x0002 317#define MII_STR_MARVELL_E1011 "88E1011 Gigabit PHY" 318#define MII_MODEL_MARVELL_E1000_2 0x0003 319#define MII_STR_MARVELL_E1000_2 "88E1000 2 Gigabit PHY" 320#define MII_MODEL_MARVELL_E1000S 0x0004 321#define MII_STR_MARVELL_E1000S "88E1000S Gigabit PHY" 322#define MII_MODEL_MARVELL_E1000_3 0x0005 323#define MII_STR_MARVELL_E1000_3 "88E1000 3 Gigabit PHY" 324#define MII_MODEL_MARVELL_E1000_4 0x0006 325#define MII_STR_MARVELL_E1000_4 "88E1000 4 Gigabit PHY" 326#define MII_MODEL_MARVELL_E3082 0x0008 327#define MII_STR_MARVELL_E3082 "88E3082 10/100 PHY" 328#define MII_MODEL_MARVELL_E1112 0x0009 329#define MII_STR_MARVELL_E1112 "88E1112 Gigabit PHY" 330#define MII_MODEL_MARVELL_E1149 0x000b 331#define MII_STR_MARVELL_E1149 "88E1149 Gigabit PHY" 332#define MII_MODEL_MARVELL_E1111 0x000c 333#define MII_STR_MARVELL_E1111 "88E1111 Gigabit PHY" 334#define MII_MODEL_MARVELL_E1116 0x0021 335#define MII_STR_MARVELL_E1116 "88E1116 Gigabit PHY" 336#define MII_MODEL_MARVELL_E1118 0x0022 337#define MII_STR_MARVELL_E1118 "88E1118 Gigabit PHY" 338#define MII_MODEL_MARVELL_E1116R 0x0024 339#define MII_STR_MARVELL_E1116R "88E1116R Gigabit PHY" 340#define MII_MODEL_MARVELL_E3016 0x0026 341#define MII_STR_MARVELL_E3016 "88E3016 10/100 PHY" 342 343/* Myson PHYs */ 344#define MII_MODEL_MYSON_MTD972 0x0000 345#define MII_STR_MYSON_MTD972 "MTD972 10/100 PHY" 346 347/* National Semi. PHYs */ 348#define MII_MODEL_NATSEMI_DP83840 0x0000 349#define MII_STR_NATSEMI_DP83840 "DP83840 10/100 PHY" 350#define MII_MODEL_NATSEMI_DP83843 0x0001 351#define MII_STR_NATSEMI_DP83843 "DP83843 10/100 PHY" 352#define MII_MODEL_NATSEMI_DP83815 0x0002 353#define MII_STR_NATSEMI_DP83815 "DP83815 10/100 PHY" 354#define MII_MODEL_NATSEMI_DP83847 0x0003 355#define MII_STR_NATSEMI_DP83847 "DP83847 10/100 PHY" 356#define MII_MODEL_NATSEMI_DP83891 0x0005 357#define MII_STR_NATSEMI_DP83891 "DP83891 10/100/1000 PHY" 358#define MII_MODEL_NATSEMI_DP83861 0x0006 359#define MII_STR_NATSEMI_DP83861 "DP83861 10/100/1000 PHY" 360#define MII_MODEL_NATSEMI_DP83865 0x0007 361#define MII_STR_NATSEMI_DP83865 "DP83865 10/100/1000 PHY" 362 363/* Plessey Semi. PHYs */ 364#define MII_MODEL_PLESSEY_NWK914 0x0000 365#define MII_STR_PLESSEY_NWK914 "NWK914 10/100 PHY" 366 367/* Quality Semi. PHYs */ 368#define MII_MODEL_QUALITYSEMI_QS6612 0x0000 369#define MII_STR_QUALITYSEMI_QS6612 "QS6612 10/100 PHY" 370 371/* Realtek PHYs */ 372#define MII_MODEL_xxREALTEK_RTL8169S 0x0011 373#define MII_STR_xxREALTEK_RTL8169S "RTL8169S/8110S PHY" 374#define MII_MODEL_REALTEK_RTL8201L 0x0020 375#define MII_STR_REALTEK_RTL8201L "RTL8201L 10/100 PHY" 376 377/* Seeq PHYs */ 378#define MII_MODEL_xxSEEQ_80220 0x0003 379#define MII_STR_xxSEEQ_80220 "80220 10/100 PHY" 380#define MII_MODEL_xxSEEQ_84220 0x0004 381#define MII_STR_xxSEEQ_84220 "84220 10/100 PHY" 382#define MII_MODEL_xxSEEQ_80225 0x0008 383#define MII_STR_xxSEEQ_80225 "80225 10/100 PHY" 384 385/* Silicon Integrated Systems PHYs */ 386#define MII_MODEL_xxSIS_900 0x0000 387#define MII_STR_xxSIS_900 "900 10/100 PHY" 388 389/* Standard Microsystems PHYs */ 390#define MII_MODEL_SMSC_LAN83C185 0x000a 391#define MII_STR_SMSC_LAN83C185 "LAN83C185 10/100 PHY" 392 393/* Texas Instruments PHYs */ 394#define MII_MODEL_xxTI_TLAN10T 0x0001 395#define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT PHY" 396#define MII_MODEL_xxTI_100VGPMI 0x0002 397#define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan PHY" 398#define MII_MODEL_xxTI_TNETE2101 0x0003 399#define MII_STR_xxTI_TNETE2101 "TNETE2101 PHY" 400 401/* TDK PHYs */ 402#define MII_MODEL_TDK_78Q2120 0x0014 403#define MII_STR_TDK_78Q2120 "78Q2120 10/100 PHY" 404#define MII_MODEL_TDK_78Q2121 0x0015 405#define MII_STR_TDK_78Q2121 "78Q2121 100baseTX PHY" 406 407/* VIA Networking PHYs */ 408#define MII_MODEL_VIA_VT6103 0x0032 409#define MII_STR_VIA_VT6103 "VT6103 10/100 PHY" 410#define MII_MODEL_VIA_VT6103_2 0x0034 411#define MII_STR_VIA_VT6103_2 "VT6103 10/100 PHY" 412 413/* Vitesse PHYs */ 414#define MII_MODEL_VITESSE_VSC8601 0x0002 415#define MII_STR_VITESSE_VSC8601 "VSC8601 10/100/1000 PHY" 416 417/* XaQti PHYs */ 418#define MII_MODEL_XAQTI_XMACII 0x0000 419#define MII_STR_XAQTI_XMACII "XMAC II Gigabit PHY" 420