wdcvar.h revision 1.8
1/* $OpenBSD: wdcvar.h,v 1.8 2000/04/10 07:06:15 csapuntz Exp $ */ 2/* $NetBSD: wdcvar.h,v 1.17 1999/04/11 20:50:29 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40#define WAITTIME (10 * hz) /* time to wait for a completion */ 41 /* this is a lot for hard drives, but not for cdroms */ 42 43struct channel_queue { /* per channel queue (may be shared) */ 44 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 45}; 46 47struct channel_softc_vtbl; 48 49struct channel_softc { /* Per channel data */ 50 struct channel_softc_vtbl *_vtbl; 51 52 /* Our location */ 53 int channel; 54 /* Our controller's softc */ 55 struct wdc_softc *wdc; 56 /* Our registers */ 57 bus_space_tag_t cmd_iot; 58 bus_space_handle_t cmd_ioh; 59 bus_space_tag_t ctl_iot; 60 bus_space_handle_t ctl_ioh; 61 /* data32{iot,ioh} are only used for 32 bit xfers */ 62 bus_space_tag_t data32iot; 63 bus_space_handle_t data32ioh; 64 /* Our state */ 65 int ch_flags; 66#define WDCF_ACTIVE 0x01 /* channel is active */ 67#define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 68#define WDCF_ONESLAVE 0x20 /* slave-only channel */ 69 u_int8_t ch_status; /* copy of status register */ 70 u_int8_t ch_error; /* copy of error register */ 71 /* per-drive infos */ 72 struct ata_drive_datas ch_drive[2]; 73 74 /* 75 * channel queues. May be the same for all channels, if hw channels 76 * are not independants 77 */ 78 struct channel_queue *ch_queue; 79}; 80 81/* 82 * Disk Controller register definitions. 83 */ 84#define _WDC_REGMASK 7 85#define _WDC_AUX 8 86#define _WDC_RDONLY 16 87#define _WDC_WRONLY 32 88enum wdc_regs { 89 wdr_error = _WDC_RDONLY | 1, 90 wdr_precomp = _WDC_WRONLY | 1, 91 wdr_features = _WDC_WRONLY | 1, 92 wdr_seccnt = 2, 93 wdr_ireason = 2, 94 wdr_sector = 3, 95 wdr_cyl_lo = 4, 96 wdr_cyl_hi = 5, 97 wdr_sdh = 6, 98 wdr_status = _WDC_RDONLY | 7, 99 wdr_command = _WDC_WRONLY | 7, 100 wdr_altsts = _WDC_RDONLY | _WDC_AUX, 101 wdr_ctlr = _WDC_WRONLY | _WDC_AUX 102}; 103 104struct channel_softc_vtbl { 105 u_int8_t (*read_reg)(struct channel_softc *, enum wdc_regs reg); 106 void (*write_reg)(struct channel_softc *, enum wdc_regs reg, 107 u_int8_t var); 108 109 void (*read_raw_multi_2)(struct channel_softc *, 110 void *data, unsigned int nbytes); 111 void (*write_raw_multi_2)(struct channel_softc *, 112 void *data, unsigned int nbytes); 113 114 void (*read_raw_multi_4)(struct channel_softc *, 115 void *data, unsigned int nbytes); 116 void (*write_raw_multi_4)(struct channel_softc *, 117 void *data, unsigned int nbytes); 118}; 119 120 121#define CHP_READ_REG(chp, a) ((chp)->_vtbl->read_reg)(chp, a) 122#define CHP_WRITE_REG(chp, a, b) ((chp)->_vtbl->write_reg)(chp, a, b) 123#define CHP_READ_RAW_MULTI_2(chp, a, b) \ 124 ((chp)->_vtbl->read_raw_multi_2)(chp, a, b) 125#define CHP_WRITE_RAW_MULTI_2(chp, a, b) \ 126 ((chp)->_vtbl->write_raw_multi_2)(chp, a, b) 127#define CHP_READ_RAW_MULTI_4(chp, a, b) \ 128 ((chp)->_vtbl->read_raw_multi_4)(chp, a, b) 129#define CHP_WRITE_RAW_MULTI_4(chp, a, b) \ 130 ((chp)->_vtbl->write_raw_multi_4)(chp, a, b) 131 132struct wdc_softc { /* Per controller state */ 133 struct device sc_dev; 134 /* mandatory fields */ 135 int cap; 136/* Capabilities supported by the controller */ 137#define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 138#define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 139#define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 140#define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 141#define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 142#define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 143#define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 144#define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 145#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 146#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 147 u_int8_t PIO_cap; /* highest PIO mode supported */ 148 u_int8_t DMA_cap; /* highest DMA mode supported */ 149 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 150 int nchannels; /* Number of channels on this controller */ 151 struct channel_softc **channels; /* channels-specific datas (array) */ 152 153#if 0 154 /* 155 * The reference count here is used for both IDE and ATAPI devices. 156 */ 157 struct scsipi_adapter sc_atapi_adapter; 158#endif 159 160 /* if WDC_CAPABILITY_DMA set in 'cap' */ 161 void *dma_arg; 162 int (*dma_init) __P((void *, int, int, void *, size_t, 163 int)); 164 void (*dma_start) __P((void *, int, int, int)); 165 int (*dma_finish) __P((void *, int, int, int)); 166/* flags passed to DMA functions */ 167#define WDC_DMA_READ 0x01 168#define WDC_DMA_POLL 0x02 169 170 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 171 int (*claim_hw) __P((void *, int)); 172 void (*free_hw) __P((void *)); 173 174 /* if WDC_CAPABILITY_MODE set in 'cap' */ 175 void (*set_modes) __P((struct channel_softc *)); 176}; 177 178 /* 179 * Description of a command to be handled by a controller. 180 * These commands are queued in a list. 181 */ 182struct wdc_xfer { 183 volatile u_int c_flags; 184#define C_INUSE 0x0001 /* xfer struct is in use */ 185#define C_ATAPI 0x0002 /* xfer is ATAPI request */ 186#define C_TIMEOU 0x0004 /* xfer processing timed out */ 187#define C_NEEDDONE 0x0010 /* need to call upper-level done */ 188#define C_POLL 0x0020 /* cmd is polled */ 189#define C_DMA 0x0040 /* cmd uses DMA */ 190#define C_SENSE 0x0080 /* cmd is a internal command */ 191#define C_MEDIA_ACCESS 0x0100 /* is a media access command */ 192#define C_POLL_MACHINE 0x0200 /* machine has a poll hander */ 193 194 /* Informations about our location */ 195 struct channel_softc *chp; 196 u_int8_t drive; 197 198 /* Information about the current transfer */ 199 void *cmd; /* wdc, ata or scsipi command structure */ 200 void *databuf; 201 int c_bcount; /* byte count left */ 202 int c_skip; /* bytes already transferred */ 203 TAILQ_ENTRY(wdc_xfer) c_xferchain; 204 LIST_ENTRY(wdc_xfer) free_list; 205 void (*c_start) __P((struct channel_softc *, struct wdc_xfer *)); 206 int (*c_intr) __P((struct channel_softc *, struct wdc_xfer *, int)); 207 int (*c_done) __P((struct channel_softc *, struct wdc_xfer *, int)); 208 void (*c_kill_xfer) __P((struct channel_softc *, struct wdc_xfer *)); 209 210 /* Used by ATAPISCSI */ 211 int timeout; 212 int endticks; 213 int delay; 214 unsigned int expect_irq:1; 215 unsigned int claim_irq:1; 216 217 int (*next) __P((struct channel_softc *, struct wdc_xfer *, int)); 218 219 /* Used for tape devices */ 220 int transfer_len; 221}; 222 223/* 224 * Public functions which can be called by ATA or ATAPI specific parts, 225 * or bus-specific backends. 226 */ 227 228int wdcprobe __P((struct channel_softc *)); 229void wdcattach __P((struct channel_softc *)); 230int wdcdetach __P((struct channel_softc *, int)); 231int wdcactivate __P((struct device *, enum devact)); 232int wdcintr __P((void *)); 233void wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *)); 234struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */ 235#define WDC_CANSLEEP 0x00 236#define WDC_NOSLEEP 0x01 237void wdc_free_xfer __P((struct channel_softc *, struct wdc_xfer *)); 238void wdcstart __P((struct channel_softc *)); 239void wdcrestart __P((void*)); 240int wdcreset __P((struct channel_softc *, int)); 241#define VERBOSE 1 242#define SILENT 0 /* wdcreset will not print errors */ 243int wdcwait __P((struct channel_softc *, int, int, int)); 244void wdcbit_bucket __P((struct channel_softc *, int)); 245 246void wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 247 u_int8_t, u_int8_t, u_int8_t, u_int8_t)); 248void wdccommandshort __P((struct channel_softc *, int, int)); 249void wdctimeout __P((void *arg)); 250 251int wdc_addref __P((struct channel_softc *)); 252void wdc_delref __P((struct channel_softc *)); 253 254/* 255 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 256 * command is aborted. 257 */ 258#define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout)) 259#define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout)) 260#define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \ 261 WDCS_DRDY, (timeout)) 262/* ATA/ATAPI specs says a device can take 31s to reset */ 263#define WDC_RESET_WAIT 31000 264 265void wdc_atapibus_attach __P((struct channel_softc *)); 266int atapi_print __P((void *, const char *)); 267 268void wdc_disable_intr __P((struct channel_softc *)); 269void wdc_enable_intr __P((struct channel_softc *)); 270int wdc_select_drive __P((struct channel_softc *, int, int)); 271 272void wdc_output_bytes __P((struct ata_drive_datas *drvp, void *, unsigned int)); 273void wdc_input_bytes __P((struct ata_drive_datas *drvp, void *, unsigned int)); 274 275