wdcvar.h revision 1.35
1/* $OpenBSD: wdcvar.h,v 1.35 2004/10/17 08:42:41 grange Exp $ */ 2/* $NetBSD: wdcvar.h,v 1.17 1999/04/11 20:50:29 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40#ifndef _DEV_IC_WDCVAR_H_ 41#define _DEV_IC_WDCVAR_H_ 42 43#include <sys/timeout.h> 44 45struct channel_queue { /* per channel queue (may be shared) */ 46 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 47}; 48 49struct channel_softc_vtbl; 50 51 52#define WDC_OPTION_PROBE_VERBOSE 0x10000 53 54struct channel_softc { /* Per channel data */ 55 struct channel_softc_vtbl *_vtbl; 56 57 /* Our location */ 58 int channel; 59 /* Our controller's softc */ 60 struct wdc_softc *wdc; 61 /* Our registers */ 62 bus_space_tag_t cmd_iot; 63 bus_space_handle_t cmd_ioh; 64 bus_space_tag_t ctl_iot; 65 bus_space_handle_t ctl_ioh; 66 /* data32{iot,ioh} are only used for 32 bit xfers */ 67 bus_space_tag_t data32iot; 68 bus_space_handle_t data32ioh; 69 /* Our state */ 70 int ch_flags; 71#define WDCF_ACTIVE 0x01 /* channel is active */ 72#define WDCF_ONESLAVE 0x02 /* slave-only channel */ 73#define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 74#define WDCF_DMA_WAIT 0x20 /* controller is waiting for DMA */ 75#define WDCF_VERBOSE_PROBE 0x40 /* verbose probe */ 76 u_int8_t ch_status; /* copy of status register */ 77 u_int8_t ch_prev_log_status; /* previous logged value of status reg */ 78 u_int8_t ch_log_idx; 79 u_int8_t ch_error; /* copy of error register */ 80 /* per-drive infos */ 81 struct ata_drive_datas ch_drive[2]; 82 83 /* 84 * channel queues. May be the same for all channels, if hw channels 85 * are not independent. 86 */ 87 struct channel_queue *ch_queue; 88 struct timeout ch_timo; 89}; 90 91/* 92 * Disk Controller register definitions. 93 */ 94#define _WDC_REGMASK 7 95#define _WDC_AUX 8 96#define _WDC_RDONLY 16 97#define _WDC_WRONLY 32 98enum wdc_regs { 99 wdr_error = _WDC_RDONLY | 1, 100 wdr_precomp = _WDC_WRONLY | 1, 101 wdr_features = _WDC_WRONLY | 1, 102 wdr_seccnt = 2, 103 wdr_ireason = 2, 104 wdr_sector = 3, 105 wdr_lba_lo = 3, 106 wdr_cyl_lo = 4, 107 wdr_lba_mi = 4, 108 wdr_cyl_hi = 5, 109 wdr_lba_hi = 5, 110 wdr_sdh = 6, 111 wdr_status = _WDC_RDONLY | 7, 112 wdr_command = _WDC_WRONLY | 7, 113 wdr_altsts = _WDC_RDONLY | _WDC_AUX, 114 wdr_ctlr = _WDC_WRONLY | _WDC_AUX 115}; 116 117#define WDC_NREG 8 /* number of command registers */ 118#define WDC_NSHADOWREG 2 /* number of command "shadow" registers */ 119 120struct channel_softc_vtbl { 121 u_int8_t (*read_reg)(struct channel_softc *, enum wdc_regs reg); 122 void (*write_reg)(struct channel_softc *, enum wdc_regs reg, 123 u_int8_t var); 124 125 void (*read_raw_multi_2)(struct channel_softc *, 126 void *data, unsigned int nbytes); 127 void (*write_raw_multi_2)(struct channel_softc *, 128 void *data, unsigned int nbytes); 129 130 void (*read_raw_multi_4)(struct channel_softc *, 131 void *data, unsigned int nbytes); 132 void (*write_raw_multi_4)(struct channel_softc *, 133 void *data, unsigned int nbytes); 134}; 135 136 137#define CHP_READ_REG(chp, a) ((chp)->_vtbl->read_reg)(chp, a) 138#define CHP_WRITE_REG(chp, a, b) ((chp)->_vtbl->write_reg)(chp, a, b) 139#define CHP_READ_RAW_MULTI_2(chp, a, b) \ 140 ((chp)->_vtbl->read_raw_multi_2)(chp, a, b) 141#define CHP_WRITE_RAW_MULTI_2(chp, a, b) \ 142 ((chp)->_vtbl->write_raw_multi_2)(chp, a, b) 143#define CHP_READ_RAW_MULTI_4(chp, a, b) \ 144 ((chp)->_vtbl->read_raw_multi_4)(chp, a, b) 145#define CHP_WRITE_RAW_MULTI_4(chp, a, b) \ 146 ((chp)->_vtbl->write_raw_multi_4)(chp, a, b) 147 148struct wdc_softc { /* Per controller state */ 149 struct device sc_dev; 150 /* mandatory fields */ 151 int cap; 152/* Capabilities supported by the controller */ 153#define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 154#define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 155#define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 156#define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 157#define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 158#define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 159#define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 160#define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 161#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 162#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 163#define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */ 164#define WDC_CAPABILITY_SINGLE_DRIVE 0x800 /* Don't proble second drive */ 165#define WDC_CAPABILITY_NO_ATAPI_DMA 0x1000 /* Don't do DMA with ATAPI */ 166#define WDC_CAPABILITY_SATA 0x2000 /* SATA controller */ 167 u_int8_t PIO_cap; /* highest PIO mode supported */ 168 u_int8_t DMA_cap; /* highest DMA mode supported */ 169 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 170 int nchannels; /* Number of channels on this controller */ 171 struct channel_softc **channels; /* channels-specific datas (array) */ 172 u_int16_t quirks; /* per-device oddities */ 173#define WDC_QUIRK_NOSHORTDMA 0x0001 /* can't do short DMA transfers */ 174 175#if 0 176 /* 177 * The reference count here is used for both IDE and ATAPI devices. 178 */ 179 struct scsipi_adapter sc_atapi_adapter; 180#endif 181 182 /* if WDC_CAPABILITY_DMA set in 'cap' */ 183 void *dma_arg; 184 int (*dma_init)(void *, int, int, void *, size_t, 185 int); 186 void (*dma_start)(void *, int, int); 187 int (*dma_finish)(void *, int, int, int); 188/* flags passed to DMA functions */ 189#define WDC_DMA_READ 0x01 190#define WDC_DMA_IRQW 0x02 191#define WDC_DMA_LBA48 0x04 192 int dma_status; /* status return from dma_finish() */ 193#define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */ 194#define WDC_DMAST_ERR 0x02 /* DMA error */ 195#define WDC_DMAST_UNDER 0x04 /* DMA underrun */ 196 197 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 198 int (*claim_hw)(void *, int); 199 void (*free_hw)(void *); 200 201 /* if WDC_CAPABILITY_MODE set in 'cap' */ 202 void (*set_modes)(struct channel_softc *); 203 204 /* if WDC_CAPABILITY_IRQACK set in 'cap' */ 205 void (*irqack)(struct channel_softc *); 206}; 207 208 /* 209 * Description of a command to be handled by a controller. 210 * These commands are queued in a list. 211 */ 212struct atapi_return_args; 213 214struct wdc_xfer { 215 volatile u_int c_flags; 216#define C_ATAPI 0x0002 /* xfer is ATAPI request */ 217#define C_TIMEOU 0x0004 /* xfer processing timed out */ 218#define C_NEEDDONE 0x0010 /* need to call upper-level done */ 219#define C_POLL 0x0020 /* cmd is polled */ 220#define C_DMA 0x0040 /* cmd uses DMA */ 221#define C_SENSE 0x0080 /* cmd is a internal command */ 222#define C_MEDIA_ACCESS 0x0100 /* is a media access command */ 223#define C_POLL_MACHINE 0x0200 /* machine has a poll hander */ 224 225 /* Informations about our location */ 226 struct channel_softc *chp; 227 u_int8_t drive; 228 229 /* Information about the current transfer */ 230 void *cmd; /* wdc, ata or scsipi command structure */ 231 void *databuf; 232 int c_bcount; /* byte count left */ 233 int c_skip; /* bytes already transferred */ 234 TAILQ_ENTRY(wdc_xfer) c_xferchain; 235 LIST_ENTRY(wdc_xfer) free_list; 236 void (*c_start)(struct channel_softc *, struct wdc_xfer *); 237 int (*c_intr)(struct channel_softc *, struct wdc_xfer *, int); 238 void (*c_kill_xfer)(struct channel_softc *, struct wdc_xfer *); 239 240 /* Used by ATAPISCSI */ 241 volatile int endticks; 242 struct timeout atapi_poll_to; 243 void (*next)(struct channel_softc *, struct wdc_xfer *, int, 244 struct atapi_return_args *); 245 void (*c_done)(struct channel_softc *, struct wdc_xfer *, int, 246 struct atapi_return_args *); 247 248 /* Used for tape devices */ 249 int transfer_len; 250}; 251 252/* 253 * Public functions which can be called by ATA or ATAPI specific parts, 254 * or bus-specific backends. 255 */ 256 257int wdcprobe(struct channel_softc *); 258void wdcattach(struct channel_softc *); 259int wdcdetach(struct channel_softc *, int); 260int wdcactivate(struct device *, enum devact); 261int wdcintr(void *); 262void wdc_exec_xfer(struct channel_softc *, struct wdc_xfer *); 263struct wdc_xfer *wdc_get_xfer(int); /* int = WDC_NOSLEEP/CANSLEEP */ 264#define WDC_CANSLEEP 0x00 265#define WDC_NOSLEEP 0x01 266void wdc_free_xfer(struct channel_softc *, struct wdc_xfer *); 267void wdcstart(struct channel_softc *); 268void wdcrestart(void *); 269int wdcreset(struct channel_softc *, int); 270#define VERBOSE 1 271#define SILENT 0 /* wdcreset will not print errors */ 272int wdc_wait_for_status(struct channel_softc *, int, int, int); 273int wdc_dmawait(struct channel_softc *, struct wdc_xfer *, int); 274void wdcbit_bucket(struct channel_softc *, int); 275 276void wdccommand(struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 277 u_int8_t, u_int8_t, u_int8_t, u_int8_t); 278void wdccommandext(struct channel_softc *, u_int8_t, u_int8_t, u_int64_t, 279 u_int16_t); 280void wdccommandshort(struct channel_softc *, int, int); 281void wdctimeout(void *arg); 282 283int wdc_addref(struct channel_softc *); 284void wdc_delref(struct channel_softc *); 285 286/* 287 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 288 * command is aborted. 289 */ 290#define wdcwait(chp, status, mask, timeout) ((wdc_wait_for_status((chp), (status), (mask), (timeout)) >= 0) ? 0 : -1) 291#define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout)) 292#define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout)) 293#define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \ 294 WDCS_DRDY, (timeout)) 295 296/* ATA/ATAPI specs says a device can take 31s to reset */ 297#define WDC_RESET_WAIT 31000 298 299int atapi_print(void *, const char *); 300 301void wdc_disable_intr(struct channel_softc *); 302void wdc_enable_intr(struct channel_softc *); 303int wdc_select_drive(struct channel_softc *, int, int); 304void wdc_set_drive(struct channel_softc *, int drive); 305void wdc_output_bytes(struct ata_drive_datas *drvp, void *, unsigned int); 306void wdc_input_bytes(struct ata_drive_datas *drvp, void *, unsigned int); 307 308void wdc_print_current_modes(struct channel_softc *); 309 310int wdc_ioctl(struct ata_drive_datas *, u_long, caddr_t, int, struct proc *); 311 312#endif /* !_DEV_IC_WDCVAR_H_ */ 313