wdcvar.h revision 1.32
1/* $OpenBSD: wdcvar.h,v 1.32 2003/10/21 18:58:50 jmc Exp $ */ 2/* $NetBSD: wdcvar.h,v 1.17 1999/04/11 20:50:29 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40#include <sys/timeout.h> 41 42struct channel_queue { /* per channel queue (may be shared) */ 43 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 44}; 45 46struct channel_softc_vtbl; 47 48 49#define WDC_OPTION_PROBE_VERBOSE 0x10000 50 51struct channel_softc { /* Per channel data */ 52 struct channel_softc_vtbl *_vtbl; 53 54 /* Our location */ 55 int channel; 56 /* Our controller's softc */ 57 struct wdc_softc *wdc; 58 /* Our registers */ 59 bus_space_tag_t cmd_iot; 60 bus_space_handle_t cmd_ioh; 61 bus_space_tag_t ctl_iot; 62 bus_space_handle_t ctl_ioh; 63 /* data32{iot,ioh} are only used for 32 bit xfers */ 64 bus_space_tag_t data32iot; 65 bus_space_handle_t data32ioh; 66 /* Our state */ 67 int ch_flags; 68#define WDCF_ACTIVE 0x01 /* channel is active */ 69#define WDCF_ONESLAVE 0x02 /* slave-only channel */ 70#define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 71#define WDCF_DMA_WAIT 0x20 /* controller is waiting for DMA */ 72#define WDCF_VERBOSE_PROBE 0x40 /* verbose probe */ 73 u_int8_t ch_status; /* copy of status register */ 74 u_int8_t ch_prev_log_status; /* previous logged value of status reg */ 75 u_int8_t ch_log_idx; 76 u_int8_t ch_error; /* copy of error register */ 77 /* per-drive infos */ 78 struct ata_drive_datas ch_drive[2]; 79 80 /* 81 * channel queues. May be the same for all channels, if hw channels 82 * are not independent. 83 */ 84 struct channel_queue *ch_queue; 85 struct timeout ch_timo; 86}; 87 88/* 89 * Disk Controller register definitions. 90 */ 91#define _WDC_REGMASK 7 92#define _WDC_AUX 8 93#define _WDC_RDONLY 16 94#define _WDC_WRONLY 32 95enum wdc_regs { 96 wdr_error = _WDC_RDONLY | 1, 97 wdr_precomp = _WDC_WRONLY | 1, 98 wdr_features = _WDC_WRONLY | 1, 99 wdr_seccnt = 2, 100 wdr_ireason = 2, 101 wdr_sector = 3, 102 wdr_lba_lo = 3, 103 wdr_cyl_lo = 4, 104 wdr_lba_mi = 4, 105 wdr_cyl_hi = 5, 106 wdr_lba_hi = 5, 107 wdr_sdh = 6, 108 wdr_status = _WDC_RDONLY | 7, 109 wdr_command = _WDC_WRONLY | 7, 110 wdr_altsts = _WDC_RDONLY | _WDC_AUX, 111 wdr_ctlr = _WDC_WRONLY | _WDC_AUX 112}; 113 114struct channel_softc_vtbl { 115 u_int8_t (*read_reg)(struct channel_softc *, enum wdc_regs reg); 116 void (*write_reg)(struct channel_softc *, enum wdc_regs reg, 117 u_int8_t var); 118 119 void (*read_raw_multi_2)(struct channel_softc *, 120 void *data, unsigned int nbytes); 121 void (*write_raw_multi_2)(struct channel_softc *, 122 void *data, unsigned int nbytes); 123 124 void (*read_raw_multi_4)(struct channel_softc *, 125 void *data, unsigned int nbytes); 126 void (*write_raw_multi_4)(struct channel_softc *, 127 void *data, unsigned int nbytes); 128}; 129 130 131#define CHP_READ_REG(chp, a) ((chp)->_vtbl->read_reg)(chp, a) 132#define CHP_WRITE_REG(chp, a, b) ((chp)->_vtbl->write_reg)(chp, a, b) 133#define CHP_READ_RAW_MULTI_2(chp, a, b) \ 134 ((chp)->_vtbl->read_raw_multi_2)(chp, a, b) 135#define CHP_WRITE_RAW_MULTI_2(chp, a, b) \ 136 ((chp)->_vtbl->write_raw_multi_2)(chp, a, b) 137#define CHP_READ_RAW_MULTI_4(chp, a, b) \ 138 ((chp)->_vtbl->read_raw_multi_4)(chp, a, b) 139#define CHP_WRITE_RAW_MULTI_4(chp, a, b) \ 140 ((chp)->_vtbl->write_raw_multi_4)(chp, a, b) 141 142struct wdc_softc { /* Per controller state */ 143 struct device sc_dev; 144 /* mandatory fields */ 145 int cap; 146/* Capabilities supported by the controller */ 147#define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 148#define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 149#define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 150#define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 151#define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 152#define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 153#define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 154#define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 155#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 156#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 157#define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */ 158#define WDC_CAPABILITY_SINGLE_DRIVE 0x800 /* Don't proble second drive */ 159#define WDC_CAPABILITY_NO_ATAPI_DMA 0x1000 /* Don't do DMA with ATAPI */ 160#define WDC_CAPABILITY_SATA 0x2000 /* SATA controller */ 161 u_int8_t PIO_cap; /* highest PIO mode supported */ 162 u_int8_t DMA_cap; /* highest DMA mode supported */ 163 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 164 int nchannels; /* Number of channels on this controller */ 165 struct channel_softc **channels; /* channels-specific datas (array) */ 166 167#if 0 168 /* 169 * The reference count here is used for both IDE and ATAPI devices. 170 */ 171 struct scsipi_adapter sc_atapi_adapter; 172#endif 173 174 /* if WDC_CAPABILITY_DMA set in 'cap' */ 175 void *dma_arg; 176 int (*dma_init)(void *, int, int, void *, size_t, 177 int); 178 void (*dma_start)(void *, int, int); 179 int (*dma_finish)(void *, int, int, int); 180/* flags passed to DMA functions */ 181#define WDC_DMA_READ 0x01 182#define WDC_DMA_IRQW 0x02 183#define WDC_DMA_LBA48 0x04 184 int dma_status; /* status return from dma_finish() */ 185#define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */ 186#define WDC_DMAST_ERR 0x02 /* DMA error */ 187#define WDC_DMAST_UNDER 0x04 /* DMA underrun */ 188 189 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 190 int (*claim_hw)(void *, int); 191 void (*free_hw)(void *); 192 193 /* if WDC_CAPABILITY_MODE set in 'cap' */ 194 void (*set_modes)(struct channel_softc *); 195 196 /* if WDC_CAPABILITY_IRQACK set in 'cap' */ 197 void (*irqack)(struct channel_softc *); 198}; 199 200 /* 201 * Description of a command to be handled by a controller. 202 * These commands are queued in a list. 203 */ 204struct atapi_return_args; 205 206struct wdc_xfer { 207 volatile u_int c_flags; 208#define C_ATAPI 0x0002 /* xfer is ATAPI request */ 209#define C_TIMEOU 0x0004 /* xfer processing timed out */ 210#define C_NEEDDONE 0x0010 /* need to call upper-level done */ 211#define C_POLL 0x0020 /* cmd is polled */ 212#define C_DMA 0x0040 /* cmd uses DMA */ 213#define C_SENSE 0x0080 /* cmd is a internal command */ 214#define C_MEDIA_ACCESS 0x0100 /* is a media access command */ 215#define C_POLL_MACHINE 0x0200 /* machine has a poll hander */ 216 217 /* Informations about our location */ 218 struct channel_softc *chp; 219 u_int8_t drive; 220 221 /* Information about the current transfer */ 222 void *cmd; /* wdc, ata or scsipi command structure */ 223 void *databuf; 224 int c_bcount; /* byte count left */ 225 int c_skip; /* bytes already transferred */ 226 TAILQ_ENTRY(wdc_xfer) c_xferchain; 227 LIST_ENTRY(wdc_xfer) free_list; 228 void (*c_start)(struct channel_softc *, struct wdc_xfer *); 229 int (*c_intr)(struct channel_softc *, struct wdc_xfer *, int); 230 void (*c_kill_xfer)(struct channel_softc *, struct wdc_xfer *); 231 232 /* Used by ATAPISCSI */ 233 volatile int endticks; 234 struct timeout atapi_poll_to; 235 void (*next)(struct channel_softc *, struct wdc_xfer *, int, 236 struct atapi_return_args *); 237 void (*c_done)(struct channel_softc *, struct wdc_xfer *, int, 238 struct atapi_return_args *); 239 240 /* Used for tape devices */ 241 int transfer_len; 242}; 243 244/* 245 * Public functions which can be called by ATA or ATAPI specific parts, 246 * or bus-specific backends. 247 */ 248 249int wdcprobe(struct channel_softc *); 250void wdcattach(struct channel_softc *); 251int wdcdetach(struct channel_softc *, int); 252int wdcactivate(struct device *, enum devact); 253int wdcintr(void *); 254void wdc_exec_xfer(struct channel_softc *, struct wdc_xfer *); 255struct wdc_xfer *wdc_get_xfer(int); /* int = WDC_NOSLEEP/CANSLEEP */ 256#define WDC_CANSLEEP 0x00 257#define WDC_NOSLEEP 0x01 258void wdc_free_xfer(struct channel_softc *, struct wdc_xfer *); 259void wdcstart(struct channel_softc *); 260void wdcrestart(void *); 261int wdcreset(struct channel_softc *, int); 262#define VERBOSE 1 263#define SILENT 0 /* wdcreset will not print errors */ 264int wdc_wait_for_status(struct channel_softc *, int, int, int); 265int wdc_dmawait(struct channel_softc *, struct wdc_xfer *, int); 266void wdcbit_bucket(struct channel_softc *, int); 267 268void wdccommand(struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 269 u_int8_t, u_int8_t, u_int8_t, u_int8_t); 270void wdccommandext(struct channel_softc *, u_int8_t, u_int8_t, u_int64_t, 271 u_int16_t); 272void wdccommandshort(struct channel_softc *, int, int); 273void wdctimeout(void *arg); 274 275int wdc_addref(struct channel_softc *); 276void wdc_delref(struct channel_softc *); 277 278/* 279 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 280 * command is aborted. 281 */ 282#define wdcwait(chp, status, mask, timeout) ((wdc_wait_for_status((chp), (status), (mask), (timeout)) >= 0) ? 0 : -1) 283#define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout)) 284#define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout)) 285#define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \ 286 WDCS_DRDY, (timeout)) 287 288/* ATA/ATAPI specs says a device can take 31s to reset */ 289#define WDC_RESET_WAIT 31000 290 291int atapi_print(void *, const char *); 292 293void wdc_disable_intr(struct channel_softc *); 294void wdc_enable_intr(struct channel_softc *); 295int wdc_select_drive(struct channel_softc *, int, int); 296void wdc_set_drive(struct channel_softc *, int drive); 297void wdc_output_bytes(struct ata_drive_datas *drvp, void *, unsigned int); 298void wdc_input_bytes(struct ata_drive_datas *drvp, void *, unsigned int); 299 300void wdc_print_current_modes(struct channel_softc *); 301 302int wdc_ioctl(struct ata_drive_datas *, u_long, caddr_t, int, struct proc *); 303