wdcvar.h revision 1.3
1/*      $OpenBSD: wdcvar.h,v 1.3 1999/10/09 03:42:04 csapuntz Exp $     */
2/*	$NetBSD: wdcvar.h,v 1.17 1999/04/11 20:50:29 bouyer Exp $	*/
3
4/*-
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 *	notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 *	notice, this list of conditions and the following disclaimer in the
18 *	documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 *    must display the following acknowledgement:
21 *        This product includes software developed by the NetBSD
22 *        Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 *    contributors may be used to endorse or promote products derived
25 *    from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#define	WAITTIME    (10 * hz)    /* time to wait for a completion */
41	/* this is a lot for hard drives, but not for cdroms */
42
43struct channel_queue {  /* per channel queue (may be shared) */
44	TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer;
45};
46
47struct channel_softc { /* Per channel data */
48	/* Our location */
49	int channel;
50	/* Our controller's softc */
51	struct wdc_softc *wdc;
52	/* Our registers */
53	bus_space_tag_t       cmd_iot;
54	bus_space_handle_t    cmd_ioh;
55	bus_space_tag_t       ctl_iot;
56	bus_space_handle_t    ctl_ioh;
57	/* data32{iot,ioh} are only used for 32 bit xfers */
58	bus_space_tag_t         data32iot;
59	bus_space_handle_t      data32ioh;
60	/* Our state */
61	int ch_flags;
62#define WDCF_ACTIVE   0x01	/* channel is active */
63#define WDCF_IRQ_WAIT 0x10	/* controller is waiting for irq */
64#define WDCF_ONESLAVE 0x20      /* slave-only channel */
65	u_int8_t ch_status;         /* copy of status register */
66	u_int8_t ch_error;          /* copy of error register */
67	/* per-drive infos */
68	struct ata_drive_datas ch_drive[2];
69
70	/*
71	 * channel queues. May be the same for all channels, if hw channels
72	 * are not independants
73	 */
74	struct channel_queue *ch_queue;
75};
76
77struct wdc_softc { /* Per controller state */
78	struct device sc_dev;
79	/* mandatory fields */
80	int           cap;
81/* Capabilities supported by the controller */
82#define	WDC_CAPABILITY_DATA16 0x0001    /* can do  16-bit data access */
83#define	WDC_CAPABILITY_DATA32 0x0002    /* can do 32-bit data access */
84#define WDC_CAPABILITY_MODE   0x0004	/* controller knows its PIO/DMA modes */
85#define	WDC_CAPABILITY_DMA    0x0008	/* DMA */
86#define	WDC_CAPABILITY_UDMA   0x0010	/* Ultra-DMA/33 */
87#define	WDC_CAPABILITY_HWLOCK 0x0020	/* Needs to lock HW */
88#define	WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */
89#define	WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */
90#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
91#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */
92	u_int8_t      PIO_cap; /* highest PIO mode supported */
93	u_int8_t      DMA_cap; /* highest DMA mode supported */
94	u_int8_t      UDMA_cap; /* highest UDMA mode supported */
95	int nchannels;	/* Number of channels on this controller */
96	struct channel_softc **channels;  /* channels-specific datas (array) */
97
98#if 0
99	/*
100	 * The reference count here is used for both IDE and ATAPI devices.
101	 */
102	struct scsipi_adapter sc_atapi_adapter;
103#endif
104
105	/* if WDC_CAPABILITY_DMA set in 'cap' */
106	void            *dma_arg;
107	int            (*dma_init) __P((void *, int, int, void *, size_t,
108	                int));
109	void           (*dma_start) __P((void *, int, int, int));
110	int            (*dma_finish) __P((void *, int, int, int));
111/* flags passed to DMA functions */
112#define WDC_DMA_READ 0x01
113#define WDC_DMA_POLL 0x02
114
115	/* if WDC_CAPABILITY_HWLOCK set in 'cap' */
116	int            (*claim_hw) __P((void *, int));
117	void            (*free_hw) __P((void *));
118
119	/* if WDC_CAPABILITY_MODE set in 'cap' */
120	void 		(*set_modes) __P((struct channel_softc *));
121};
122
123 /*
124  * Description of a command to be handled by a controller.
125  * These commands are queued in a list.
126  */
127struct wdc_xfer {
128	volatile u_int c_flags;
129#define C_INUSE  	0x0001 /* xfer struct is in use */
130#define C_ATAPI  	0x0002 /* xfer is ATAPI request */
131#define C_TIMEOU  	0x0004 /* xfer processing timed out */
132#define C_NEEDDONE  	0x0010 /* need to call upper-level done */
133#define C_POLL		0x0020 /* cmd is polled */
134#define C_DMA		0x0040 /* cmd uses DMA */
135#define C_SENSE		0x0080 /* cmd is a internal command */
136
137	/* Informations about our location */
138	struct channel_softc *chp;
139	u_int8_t drive;
140
141	/* Information about the current transfer  */
142	void *cmd; /* wdc, ata or scsipi command structure */
143	void *databuf;
144	int c_bcount;      /* byte count left */
145	int c_skip;        /* bytes already transferred */
146	TAILQ_ENTRY(wdc_xfer) c_xferchain;
147	LIST_ENTRY(wdc_xfer) free_list;
148	void (*c_start) __P((struct channel_softc *, struct wdc_xfer *));
149	int  (*c_intr)  __P((struct channel_softc *, struct wdc_xfer *, int));
150};
151
152/*
153 * Public functions which can be called by ATA or ATAPI specific parts,
154 * or bus-specific backends.
155 */
156
157int   wdcprobe __P((struct channel_softc *));
158void  wdcattach __P((struct channel_softc *));
159int   wdcintr __P((void *));
160void  wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *));
161struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */
162#define WDC_CANSLEEP 0x00
163#define WDC_NOSLEEP 0x01
164void   wdc_free_xfer  __P((struct channel_softc *, struct wdc_xfer *));
165void  wdcstart __P((struct channel_softc *));
166void  wdcrestart __P((void*));
167int   wdcreset	__P((struct channel_softc *, int));
168#define VERBOSE 1
169#define SILENT 0 /* wdcreset will not print errors */
170int   wdcwait __P((struct channel_softc *, int, int, int));
171void  wdcbit_bucket __P(( struct channel_softc *, int));
172void  wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t,
173	                  u_int8_t, u_int8_t, u_int8_t, u_int8_t));
174void   wdccommandshort __P((struct channel_softc *, int, int));
175void  wdctimeout	__P((void *arg));
176
177int	wdc_addref __P((struct channel_softc *));
178void	wdc_delref __P((struct channel_softc *));
179
180/*
181 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
182 * command is aborted.
183 */
184#define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout))
185#define wait_for_unbusy(chp, timeout)	wdcwait((chp), 0, 0, (timeout))
186#define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \
187	WDCS_DRDY, (timeout))
188/* ATA/ATAPI specs says a device can take 31s to reset */
189#define WDC_RESET_WAIT 31000
190
191void wdc_atapibus_attach __P((struct channel_softc *));
192int   atapi_print       __P((void *, const char *));
193
194void wdc_disable_intr __P((struct channel_softc *));
195void wdc_enable_intr __P((struct channel_softc *));
196int wdc_select_drive __P((struct channel_softc *, int, int));
197