wdcvar.h revision 1.23
1/* $OpenBSD: wdcvar.h,v 1.23 2002/03/14 03:16:05 millert Exp $ */ 2/* $NetBSD: wdcvar.h,v 1.17 1999/04/11 20:50:29 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40#include <sys/timeout.h> 41 42struct channel_queue { /* per channel queue (may be shared) */ 43 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 44}; 45 46struct channel_softc_vtbl; 47 48 49#define WDC_OPTION_PROBE_VERBOSE 0x10000 50 51struct channel_softc { /* Per channel data */ 52 struct channel_softc_vtbl *_vtbl; 53 54 /* Our location */ 55 int channel; 56 /* Our controller's softc */ 57 struct wdc_softc *wdc; 58 /* Our registers */ 59 bus_space_tag_t cmd_iot; 60 bus_space_handle_t cmd_ioh; 61 bus_space_tag_t ctl_iot; 62 bus_space_handle_t ctl_ioh; 63 /* data32{iot,ioh} are only used for 32 bit xfers */ 64 bus_space_tag_t data32iot; 65 bus_space_handle_t data32ioh; 66 /* Our state */ 67 int ch_flags; 68#define WDCF_ACTIVE 0x01 /* channel is active */ 69#define WDCF_ONESLAVE 0x02 /* slave-only channel */ 70#define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 71#define WDCF_VERBOSE_PROBE 0x40 /* verbose probe */ 72 u_int8_t ch_status; /* copy of status register */ 73 u_int8_t ch_error; /* copy of error register */ 74 /* per-drive infos */ 75 struct ata_drive_datas ch_drive[2]; 76 77 /* 78 * channel queues. May be the same for all channels, if hw channels 79 * are not independants 80 */ 81 struct channel_queue *ch_queue; 82 struct timeout ch_timo; 83}; 84 85/* 86 * Disk Controller register definitions. 87 */ 88#define _WDC_REGMASK 7 89#define _WDC_AUX 8 90#define _WDC_RDONLY 16 91#define _WDC_WRONLY 32 92enum wdc_regs { 93 wdr_error = _WDC_RDONLY | 1, 94 wdr_precomp = _WDC_WRONLY | 1, 95 wdr_features = _WDC_WRONLY | 1, 96 wdr_seccnt = 2, 97 wdr_ireason = 2, 98 wdr_sector = 3, 99 wdr_cyl_lo = 4, 100 wdr_cyl_hi = 5, 101 wdr_sdh = 6, 102 wdr_status = _WDC_RDONLY | 7, 103 wdr_command = _WDC_WRONLY | 7, 104 wdr_altsts = _WDC_RDONLY | _WDC_AUX, 105 wdr_ctlr = _WDC_WRONLY | _WDC_AUX 106}; 107 108struct channel_softc_vtbl { 109 u_int8_t (*read_reg)(struct channel_softc *, enum wdc_regs reg); 110 void (*write_reg)(struct channel_softc *, enum wdc_regs reg, 111 u_int8_t var); 112 113 void (*read_raw_multi_2)(struct channel_softc *, 114 void *data, unsigned int nbytes); 115 void (*write_raw_multi_2)(struct channel_softc *, 116 void *data, unsigned int nbytes); 117 118 void (*read_raw_multi_4)(struct channel_softc *, 119 void *data, unsigned int nbytes); 120 void (*write_raw_multi_4)(struct channel_softc *, 121 void *data, unsigned int nbytes); 122}; 123 124 125#define CHP_READ_REG(chp, a) ((chp)->_vtbl->read_reg)(chp, a) 126#define CHP_WRITE_REG(chp, a, b) ((chp)->_vtbl->write_reg)(chp, a, b) 127#define CHP_READ_RAW_MULTI_2(chp, a, b) \ 128 ((chp)->_vtbl->read_raw_multi_2)(chp, a, b) 129#define CHP_WRITE_RAW_MULTI_2(chp, a, b) \ 130 ((chp)->_vtbl->write_raw_multi_2)(chp, a, b) 131#define CHP_READ_RAW_MULTI_4(chp, a, b) \ 132 ((chp)->_vtbl->read_raw_multi_4)(chp, a, b) 133#define CHP_WRITE_RAW_MULTI_4(chp, a, b) \ 134 ((chp)->_vtbl->write_raw_multi_4)(chp, a, b) 135 136struct wdc_softc { /* Per controller state */ 137 struct device sc_dev; 138 /* mandatory fields */ 139 int cap; 140/* Capabilities supported by the controller */ 141#define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 142#define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 143#define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 144#define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 145#define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 146#define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 147#define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 148#define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 149#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 150#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 151#define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */ 152#define WDC_CAPABILITY_SINGLE_DRIVE 0x800 /* Don't proble second drive */ 153#define WDC_CAPABILITY_NO_ATAPI_DMA 0x1000 /* Don't do DMA with ATAPI */ 154 u_int8_t PIO_cap; /* highest PIO mode supported */ 155 u_int8_t DMA_cap; /* highest DMA mode supported */ 156 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 157 int nchannels; /* Number of channels on this controller */ 158 struct channel_softc **channels; /* channels-specific datas (array) */ 159 160#if 0 161 /* 162 * The reference count here is used for both IDE and ATAPI devices. 163 */ 164 struct scsipi_adapter sc_atapi_adapter; 165#endif 166 167 /* if WDC_CAPABILITY_DMA set in 'cap' */ 168 void *dma_arg; 169 int (*dma_init)(void *, int, int, void *, size_t, 170 int); 171 void (*dma_start)(void *, int, int); 172 int (*dma_finish)(void *, int, int); 173/* flags passed to DMA functions */ 174#define WDC_DMA_READ 0x01 175#define WDC_DMA_IRQW 0x02 176 int dma_status; /* status return from dma_finish() */ 177#define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */ 178#define WDC_DMAST_ERR 0x02 /* DMA error */ 179#define WDC_DMAST_UNDER 0x04 /* DMA underrun */ 180 181 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 182 int (*claim_hw)(void *, int); 183 void (*free_hw)(void *); 184 185 /* if WDC_CAPABILITY_MODE set in 'cap' */ 186 void (*set_modes)(struct channel_softc *); 187 188 /* if WDC_CAPABILITY_IRQACK set in 'cap' */ 189 void (*irqack)(struct channel_softc *); 190}; 191 192 /* 193 * Description of a command to be handled by a controller. 194 * These commands are queued in a list. 195 */ 196struct atapi_return_args; 197 198struct wdc_xfer { 199 volatile u_int c_flags; 200#define C_ATAPI 0x0002 /* xfer is ATAPI request */ 201#define C_TIMEOU 0x0004 /* xfer processing timed out */ 202#define C_NEEDDONE 0x0010 /* need to call upper-level done */ 203#define C_POLL 0x0020 /* cmd is polled */ 204#define C_DMA 0x0040 /* cmd uses DMA */ 205#define C_SENSE 0x0080 /* cmd is a internal command */ 206#define C_MEDIA_ACCESS 0x0100 /* is a media access command */ 207#define C_POLL_MACHINE 0x0200 /* machine has a poll hander */ 208 209 /* Informations about our location */ 210 struct channel_softc *chp; 211 u_int8_t drive; 212 213 /* Information about the current transfer */ 214 void *cmd; /* wdc, ata or scsipi command structure */ 215 void *databuf; 216 int c_bcount; /* byte count left */ 217 int c_skip; /* bytes already transferred */ 218 TAILQ_ENTRY(wdc_xfer) c_xferchain; 219 LIST_ENTRY(wdc_xfer) free_list; 220 void (*c_start)(struct channel_softc *, struct wdc_xfer *); 221 int (*c_intr)(struct channel_softc *, struct wdc_xfer *, int); 222 void (*c_kill_xfer)(struct channel_softc *, struct wdc_xfer *); 223 224 /* Used by ATAPISCSI */ 225 volatile int endticks; 226 struct timeout atapi_poll_to; 227 void (*next)(struct channel_softc *, struct wdc_xfer *, int, 228 struct atapi_return_args *); 229 void (*c_done)(struct channel_softc *, struct wdc_xfer *, int, 230 struct atapi_return_args *); 231 232 /* Used for tape devices */ 233 int transfer_len; 234}; 235 236/* 237 * Public functions which can be called by ATA or ATAPI specific parts, 238 * or bus-specific backends. 239 */ 240 241int wdcprobe(struct channel_softc *); 242void wdcattach(struct channel_softc *); 243int wdcdetach(struct channel_softc *, int); 244int wdcactivate(struct device *, enum devact); 245int wdcintr(void *); 246void wdc_exec_xfer(struct channel_softc *, struct wdc_xfer *); 247struct wdc_xfer *wdc_get_xfer(int); /* int = WDC_NOSLEEP/CANSLEEP */ 248#define WDC_CANSLEEP 0x00 249#define WDC_NOSLEEP 0x01 250void wdc_free_xfer(struct channel_softc *, struct wdc_xfer *); 251void wdcstart(struct channel_softc *); 252void wdcrestart(void *); 253int wdcreset(struct channel_softc *, int); 254#define VERBOSE 1 255#define SILENT 0 /* wdcreset will not print errors */ 256int wdc_wait_for_status(struct channel_softc *, int, int, int); 257int wdc_dmawait(struct channel_softc *, struct wdc_xfer *, int); 258void wdcbit_bucket(struct channel_softc *, int); 259 260void wdccommand(struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 261 u_int8_t, u_int8_t, u_int8_t, u_int8_t); 262void wdccommandshort(struct channel_softc *, int, int); 263void wdctimeout(void *arg); 264 265int wdc_addref(struct channel_softc *); 266void wdc_delref(struct channel_softc *); 267 268/* 269 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 270 * command is aborted. 271 */ 272#define wdcwait(chp, status, mask, timeout) ((wdc_wait_for_status((chp), (status), (mask), (timeout)) >= 0) ? 0 : -1) 273#define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout)) 274#define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout)) 275#define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \ 276 WDCS_DRDY, (timeout)) 277 278/* ATA/ATAPI specs says a device can take 31s to reset */ 279#define WDC_RESET_WAIT 31000 280 281int atapi_print(void *, const char *); 282 283void wdc_disable_intr(struct channel_softc *); 284void wdc_enable_intr(struct channel_softc *); 285int wdc_select_drive(struct channel_softc *, int, int); 286 287void wdc_output_bytes(struct ata_drive_datas *drvp, void *, unsigned int); 288void wdc_input_bytes(struct ata_drive_datas *drvp, void *, unsigned int); 289 290void wdc_print_current_modes(struct channel_softc *); 291 292int wdc_ioctl(struct ata_drive_datas *, u_long, caddr_t, int, struct proc *); 293