wdcvar.h revision 1.12
1/* $OpenBSD: wdcvar.h,v 1.12 2000/10/27 20:29:28 csapuntz Exp $ */ 2/* $NetBSD: wdcvar.h,v 1.17 1999/04/11 20:50:29 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40#include <sys/timeout.h> 41 42#define WAITTIME (10 * hz) /* time to wait for a completion */ 43 /* this is a lot for hard drives, but not for cdroms */ 44 45struct channel_queue { /* per channel queue (may be shared) */ 46 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 47}; 48 49struct channel_softc_vtbl; 50 51 52#define WDC_OPTION_PROBE_VERBOSE 0x10000 53 54struct channel_softc { /* Per channel data */ 55 struct channel_softc_vtbl *_vtbl; 56 57 /* Our location */ 58 int channel; 59 /* Our controller's softc */ 60 struct wdc_softc *wdc; 61 /* Our registers */ 62 bus_space_tag_t cmd_iot; 63 bus_space_handle_t cmd_ioh; 64 bus_space_tag_t ctl_iot; 65 bus_space_handle_t ctl_ioh; 66 /* data32{iot,ioh} are only used for 32 bit xfers */ 67 bus_space_tag_t data32iot; 68 bus_space_handle_t data32ioh; 69 /* Our state */ 70 int ch_flags; 71#define WDCF_ACTIVE 0x01 /* channel is active */ 72#define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 73#define WDCF_ONESLAVE 0x20 /* slave-only channel */ 74#define WDCF_VERBOSE_PROBE 0x40 /* verbose probe */ 75 u_int8_t ch_status; /* copy of status register */ 76 u_int8_t ch_error; /* copy of error register */ 77 /* per-drive infos */ 78 struct ata_drive_datas ch_drive[2]; 79 80 /* 81 * channel queues. May be the same for all channels, if hw channels 82 * are not independants 83 */ 84 struct channel_queue *ch_queue; 85 struct timeout ch_timo; 86}; 87 88/* 89 * Disk Controller register definitions. 90 */ 91#define _WDC_REGMASK 7 92#define _WDC_AUX 8 93#define _WDC_RDONLY 16 94#define _WDC_WRONLY 32 95enum wdc_regs { 96 wdr_error = _WDC_RDONLY | 1, 97 wdr_precomp = _WDC_WRONLY | 1, 98 wdr_features = _WDC_WRONLY | 1, 99 wdr_seccnt = 2, 100 wdr_ireason = 2, 101 wdr_sector = 3, 102 wdr_cyl_lo = 4, 103 wdr_cyl_hi = 5, 104 wdr_sdh = 6, 105 wdr_status = _WDC_RDONLY | 7, 106 wdr_command = _WDC_WRONLY | 7, 107 wdr_altsts = _WDC_RDONLY | _WDC_AUX, 108 wdr_ctlr = _WDC_WRONLY | _WDC_AUX 109}; 110 111struct channel_softc_vtbl { 112 u_int8_t (*read_reg)(struct channel_softc *, enum wdc_regs reg); 113 void (*write_reg)(struct channel_softc *, enum wdc_regs reg, 114 u_int8_t var); 115 116 void (*read_raw_multi_2)(struct channel_softc *, 117 void *data, unsigned int nbytes); 118 void (*write_raw_multi_2)(struct channel_softc *, 119 void *data, unsigned int nbytes); 120 121 void (*read_raw_multi_4)(struct channel_softc *, 122 void *data, unsigned int nbytes); 123 void (*write_raw_multi_4)(struct channel_softc *, 124 void *data, unsigned int nbytes); 125}; 126 127 128#define CHP_READ_REG(chp, a) ((chp)->_vtbl->read_reg)(chp, a) 129#define CHP_WRITE_REG(chp, a, b) ((chp)->_vtbl->write_reg)(chp, a, b) 130#define CHP_READ_RAW_MULTI_2(chp, a, b) \ 131 ((chp)->_vtbl->read_raw_multi_2)(chp, a, b) 132#define CHP_WRITE_RAW_MULTI_2(chp, a, b) \ 133 ((chp)->_vtbl->write_raw_multi_2)(chp, a, b) 134#define CHP_READ_RAW_MULTI_4(chp, a, b) \ 135 ((chp)->_vtbl->read_raw_multi_4)(chp, a, b) 136#define CHP_WRITE_RAW_MULTI_4(chp, a, b) \ 137 ((chp)->_vtbl->write_raw_multi_4)(chp, a, b) 138 139struct wdc_softc { /* Per controller state */ 140 struct device sc_dev; 141 /* mandatory fields */ 142 int cap; 143/* Capabilities supported by the controller */ 144#define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 145#define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 146#define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 147#define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 148#define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 149#define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 150#define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 151#define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 152#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 153#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 154 u_int8_t PIO_cap; /* highest PIO mode supported */ 155 u_int8_t DMA_cap; /* highest DMA mode supported */ 156 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 157 int nchannels; /* Number of channels on this controller */ 158 struct channel_softc **channels; /* channels-specific datas (array) */ 159 160#if 0 161 /* 162 * The reference count here is used for both IDE and ATAPI devices. 163 */ 164 struct scsipi_adapter sc_atapi_adapter; 165#endif 166 167 /* if WDC_CAPABILITY_DMA set in 'cap' */ 168 void *dma_arg; 169 int (*dma_init) __P((void *, int, int, void *, size_t, 170 int)); 171 void (*dma_start) __P((void *, int, int, int)); 172 int (*dma_finish) __P((void *, int, int, int)); 173/* flags passed to DMA functions */ 174#define WDC_DMA_READ 0x01 175#define WDC_DMA_POLL 0x02 176 177 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 178 int (*claim_hw) __P((void *, int)); 179 void (*free_hw) __P((void *)); 180 181 /* if WDC_CAPABILITY_MODE set in 'cap' */ 182 void (*set_modes) __P((struct channel_softc *)); 183}; 184 185 /* 186 * Description of a command to be handled by a controller. 187 * These commands are queued in a list. 188 */ 189struct wdc_xfer { 190 volatile u_int c_flags; 191#define C_INUSE 0x0001 /* xfer struct is in use */ 192#define C_ATAPI 0x0002 /* xfer is ATAPI request */ 193#define C_TIMEOU 0x0004 /* xfer processing timed out */ 194#define C_NEEDDONE 0x0010 /* need to call upper-level done */ 195#define C_POLL 0x0020 /* cmd is polled */ 196#define C_DMA 0x0040 /* cmd uses DMA */ 197#define C_SENSE 0x0080 /* cmd is a internal command */ 198#define C_MEDIA_ACCESS 0x0100 /* is a media access command */ 199#define C_POLL_MACHINE 0x0200 /* machine has a poll hander */ 200 201 /* Informations about our location */ 202 struct channel_softc *chp; 203 u_int8_t drive; 204 205 /* Information about the current transfer */ 206 void *cmd; /* wdc, ata or scsipi command structure */ 207 void *databuf; 208 int c_bcount; /* byte count left */ 209 int c_skip; /* bytes already transferred */ 210 TAILQ_ENTRY(wdc_xfer) c_xferchain; 211 LIST_ENTRY(wdc_xfer) free_list; 212 void (*c_start) __P((struct channel_softc *, struct wdc_xfer *)); 213 int (*c_intr) __P((struct channel_softc *, struct wdc_xfer *, int)); 214 int (*c_done) __P((struct channel_softc *, struct wdc_xfer *, int)); 215 void (*c_kill_xfer) __P((struct channel_softc *, struct wdc_xfer *)); 216 217 /* Used by ATAPISCSI */ 218 int timeout; 219 int endticks; 220 int delay; 221 unsigned int expect_irq:1; 222 unsigned int claim_irq:1; 223 224 int (*next) __P((struct channel_softc *, struct wdc_xfer *, int)); 225 226 /* Used for tape devices */ 227 int transfer_len; 228}; 229 230/* 231 * Public functions which can be called by ATA or ATAPI specific parts, 232 * or bus-specific backends. 233 */ 234 235int wdcprobe __P((struct channel_softc *)); 236void wdcattach __P((struct channel_softc *)); 237int wdcdetach __P((struct channel_softc *, int)); 238int wdcactivate __P((struct device *, enum devact)); 239int wdcintr __P((void *)); 240void wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *)); 241struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */ 242#define WDC_CANSLEEP 0x00 243#define WDC_NOSLEEP 0x01 244void wdc_free_xfer __P((struct channel_softc *, struct wdc_xfer *)); 245void wdcstart __P((struct channel_softc *)); 246void wdcrestart __P((void*)); 247int wdcreset __P((struct channel_softc *, int)); 248#define VERBOSE 1 249#define SILENT 0 /* wdcreset will not print errors */ 250int wdc_wait_for_status __P((struct channel_softc *, int, int, int)); 251void wdcbit_bucket __P((struct channel_softc *, int)); 252 253void wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 254 u_int8_t, u_int8_t, u_int8_t, u_int8_t)); 255void wdccommandshort __P((struct channel_softc *, int, int)); 256void wdctimeout __P((void *arg)); 257 258int wdc_addref __P((struct channel_softc *)); 259void wdc_delref __P((struct channel_softc *)); 260 261/* 262 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 263 * command is aborted. 264 */ 265#define wdcwait(chp, status, mask, timeout) ((wdc_wait_for_status((chp), (status), (mask), (timeout)) >= 0) ? 0 : -1) 266#define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout)) 267#define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout)) 268#define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \ 269 WDCS_DRDY, (timeout)) 270 271/* ATA/ATAPI specs says a device can take 31s to reset */ 272#define WDC_RESET_WAIT 31000 273 274void wdc_atapibus_attach __P((struct channel_softc *)); 275int atapi_print __P((void *, const char *)); 276 277void wdc_disable_intr __P((struct channel_softc *)); 278void wdc_enable_intr __P((struct channel_softc *)); 279int wdc_select_drive __P((struct channel_softc *, int, int)); 280 281void wdc_output_bytes __P((struct ata_drive_datas *drvp, void *, unsigned int)); 282void wdc_input_bytes __P((struct ata_drive_datas *drvp, void *, unsigned int)); 283 284