wdcvar.h revision 1.10
1/* $OpenBSD: wdcvar.h,v 1.10 2000/07/20 07:40:32 csapuntz Exp $ */ 2/* $NetBSD: wdcvar.h,v 1.17 1999/04/11 20:50:29 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40#include <sys/timeout.h> 41 42#define WAITTIME (10 * hz) /* time to wait for a completion */ 43 /* this is a lot for hard drives, but not for cdroms */ 44 45struct channel_queue { /* per channel queue (may be shared) */ 46 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 47}; 48 49struct channel_softc_vtbl; 50 51 52#define WDC_OPTION_PROBE_VERBOSE 0x10000 53 54struct channel_softc { /* Per channel data */ 55 struct channel_softc_vtbl *_vtbl; 56 57 /* Our location */ 58 int channel; 59 /* Our controller's softc */ 60 struct wdc_softc *wdc; 61 /* Our registers */ 62 bus_space_tag_t cmd_iot; 63 bus_space_handle_t cmd_ioh; 64 bus_space_tag_t ctl_iot; 65 bus_space_handle_t ctl_ioh; 66 /* data32{iot,ioh} are only used for 32 bit xfers */ 67 bus_space_tag_t data32iot; 68 bus_space_handle_t data32ioh; 69 /* Our state */ 70 int ch_flags; 71#define WDCF_ACTIVE 0x01 /* channel is active */ 72#define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 73#define WDCF_ONESLAVE 0x20 /* slave-only channel */ 74 u_int8_t ch_status; /* copy of status register */ 75 u_int8_t ch_error; /* copy of error register */ 76 /* per-drive infos */ 77 struct ata_drive_datas ch_drive[2]; 78 79 /* 80 * channel queues. May be the same for all channels, if hw channels 81 * are not independants 82 */ 83 struct channel_queue *ch_queue; 84 struct timeout ch_timo; 85}; 86 87/* 88 * Disk Controller register definitions. 89 */ 90#define _WDC_REGMASK 7 91#define _WDC_AUX 8 92#define _WDC_RDONLY 16 93#define _WDC_WRONLY 32 94enum wdc_regs { 95 wdr_error = _WDC_RDONLY | 1, 96 wdr_precomp = _WDC_WRONLY | 1, 97 wdr_features = _WDC_WRONLY | 1, 98 wdr_seccnt = 2, 99 wdr_ireason = 2, 100 wdr_sector = 3, 101 wdr_cyl_lo = 4, 102 wdr_cyl_hi = 5, 103 wdr_sdh = 6, 104 wdr_status = _WDC_RDONLY | 7, 105 wdr_command = _WDC_WRONLY | 7, 106 wdr_altsts = _WDC_RDONLY | _WDC_AUX, 107 wdr_ctlr = _WDC_WRONLY | _WDC_AUX 108}; 109 110struct channel_softc_vtbl { 111 u_int8_t (*read_reg)(struct channel_softc *, enum wdc_regs reg); 112 void (*write_reg)(struct channel_softc *, enum wdc_regs reg, 113 u_int8_t var); 114 115 void (*read_raw_multi_2)(struct channel_softc *, 116 void *data, unsigned int nbytes); 117 void (*write_raw_multi_2)(struct channel_softc *, 118 void *data, unsigned int nbytes); 119 120 void (*read_raw_multi_4)(struct channel_softc *, 121 void *data, unsigned int nbytes); 122 void (*write_raw_multi_4)(struct channel_softc *, 123 void *data, unsigned int nbytes); 124}; 125 126 127#define CHP_READ_REG(chp, a) ((chp)->_vtbl->read_reg)(chp, a) 128#define CHP_WRITE_REG(chp, a, b) ((chp)->_vtbl->write_reg)(chp, a, b) 129#define CHP_READ_RAW_MULTI_2(chp, a, b) \ 130 ((chp)->_vtbl->read_raw_multi_2)(chp, a, b) 131#define CHP_WRITE_RAW_MULTI_2(chp, a, b) \ 132 ((chp)->_vtbl->write_raw_multi_2)(chp, a, b) 133#define CHP_READ_RAW_MULTI_4(chp, a, b) \ 134 ((chp)->_vtbl->read_raw_multi_4)(chp, a, b) 135#define CHP_WRITE_RAW_MULTI_4(chp, a, b) \ 136 ((chp)->_vtbl->write_raw_multi_4)(chp, a, b) 137 138struct wdc_softc { /* Per controller state */ 139 struct device sc_dev; 140 /* mandatory fields */ 141 int cap; 142/* Capabilities supported by the controller */ 143#define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 144#define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 145#define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 146#define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 147#define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 148#define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 149#define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 150#define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 151#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 152#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 153 u_int8_t PIO_cap; /* highest PIO mode supported */ 154 u_int8_t DMA_cap; /* highest DMA mode supported */ 155 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 156 int nchannels; /* Number of channels on this controller */ 157 struct channel_softc **channels; /* channels-specific datas (array) */ 158 159#if 0 160 /* 161 * The reference count here is used for both IDE and ATAPI devices. 162 */ 163 struct scsipi_adapter sc_atapi_adapter; 164#endif 165 166 /* if WDC_CAPABILITY_DMA set in 'cap' */ 167 void *dma_arg; 168 int (*dma_init) __P((void *, int, int, void *, size_t, 169 int)); 170 void (*dma_start) __P((void *, int, int, int)); 171 int (*dma_finish) __P((void *, int, int, int)); 172/* flags passed to DMA functions */ 173#define WDC_DMA_READ 0x01 174#define WDC_DMA_POLL 0x02 175 176 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 177 int (*claim_hw) __P((void *, int)); 178 void (*free_hw) __P((void *)); 179 180 /* if WDC_CAPABILITY_MODE set in 'cap' */ 181 void (*set_modes) __P((struct channel_softc *)); 182}; 183 184 /* 185 * Description of a command to be handled by a controller. 186 * These commands are queued in a list. 187 */ 188struct wdc_xfer { 189 volatile u_int c_flags; 190#define C_INUSE 0x0001 /* xfer struct is in use */ 191#define C_ATAPI 0x0002 /* xfer is ATAPI request */ 192#define C_TIMEOU 0x0004 /* xfer processing timed out */ 193#define C_NEEDDONE 0x0010 /* need to call upper-level done */ 194#define C_POLL 0x0020 /* cmd is polled */ 195#define C_DMA 0x0040 /* cmd uses DMA */ 196#define C_SENSE 0x0080 /* cmd is a internal command */ 197#define C_MEDIA_ACCESS 0x0100 /* is a media access command */ 198#define C_POLL_MACHINE 0x0200 /* machine has a poll hander */ 199 200 /* Informations about our location */ 201 struct channel_softc *chp; 202 u_int8_t drive; 203 204 /* Information about the current transfer */ 205 void *cmd; /* wdc, ata or scsipi command structure */ 206 void *databuf; 207 int c_bcount; /* byte count left */ 208 int c_skip; /* bytes already transferred */ 209 TAILQ_ENTRY(wdc_xfer) c_xferchain; 210 LIST_ENTRY(wdc_xfer) free_list; 211 void (*c_start) __P((struct channel_softc *, struct wdc_xfer *)); 212 int (*c_intr) __P((struct channel_softc *, struct wdc_xfer *, int)); 213 int (*c_done) __P((struct channel_softc *, struct wdc_xfer *, int)); 214 void (*c_kill_xfer) __P((struct channel_softc *, struct wdc_xfer *)); 215 216 /* Used by ATAPISCSI */ 217 int timeout; 218 int endticks; 219 int delay; 220 unsigned int expect_irq:1; 221 unsigned int claim_irq:1; 222 223 int (*next) __P((struct channel_softc *, struct wdc_xfer *, int)); 224 225 /* Used for tape devices */ 226 int transfer_len; 227}; 228 229/* 230 * Public functions which can be called by ATA or ATAPI specific parts, 231 * or bus-specific backends. 232 */ 233 234int wdcprobe __P((struct channel_softc *)); 235void wdcattach __P((struct channel_softc *)); 236int wdcdetach __P((struct channel_softc *, int)); 237int wdcactivate __P((struct device *, enum devact)); 238int wdcintr __P((void *)); 239void wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *)); 240struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */ 241#define WDC_CANSLEEP 0x00 242#define WDC_NOSLEEP 0x01 243void wdc_free_xfer __P((struct channel_softc *, struct wdc_xfer *)); 244void wdcstart __P((struct channel_softc *)); 245void wdcrestart __P((void*)); 246int wdcreset __P((struct channel_softc *, int)); 247#define VERBOSE 1 248#define SILENT 0 /* wdcreset will not print errors */ 249int wdcwait __P((struct channel_softc *, int, int, int)); 250void wdcbit_bucket __P((struct channel_softc *, int)); 251 252void wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 253 u_int8_t, u_int8_t, u_int8_t, u_int8_t)); 254void wdccommandshort __P((struct channel_softc *, int, int)); 255void wdctimeout __P((void *arg)); 256 257int wdc_addref __P((struct channel_softc *)); 258void wdc_delref __P((struct channel_softc *)); 259 260/* 261 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 262 * command is aborted. 263 */ 264#define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout)) 265#define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout)) 266#define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \ 267 WDCS_DRDY, (timeout)) 268/* ATA/ATAPI specs says a device can take 31s to reset */ 269#define WDC_RESET_WAIT 31000 270 271void wdc_atapibus_attach __P((struct channel_softc *)); 272int atapi_print __P((void *, const char *)); 273 274void wdc_disable_intr __P((struct channel_softc *)); 275void wdc_enable_intr __P((struct channel_softc *)); 276int wdc_select_drive __P((struct channel_softc *, int, int)); 277 278void wdc_output_bytes __P((struct ata_drive_datas *drvp, void *, unsigned int)); 279void wdc_input_bytes __P((struct ata_drive_datas *drvp, void *, unsigned int)); 280 281