wdcvar.h revision 1.1
1/*      $OpenBSD: wdcvar.h,v 1.1 1999/07/18 21:25:16 csapuntz Exp $     */
2/*	$NetBSD: wdcvar.h,v 1.17 1999/04/11 20:50:29 bouyer Exp $	*/
3
4/*-
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 *	notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 *	notice, this list of conditions and the following disclaimer in the
18 *	documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 *    must display the following acknowledgement:
21 *        This product includes software developed by the NetBSD
22 *        Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 *    contributors may be used to endorse or promote products derived
25 *    from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#if 0
41/* XXX for scsipi_adapter */
42#include <dev/scsipi/scsipi_all.h>
43#include <dev/scsipi/scsipiconf.h>
44#endif
45
46struct atapiscsi_softc;
47
48#define	WAITTIME    (10 * hz)    /* time to wait for a completion */
49	/* this is a lot for hard drives, but not for cdroms */
50
51struct channel_queue {  /* per channel queue (may be shared) */
52	TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer;
53};
54
55struct channel_softc { /* Per channel data */
56	/* Our location */
57	int channel;
58	/* Our controller's softc */
59	struct wdc_softc *wdc;
60	/* Our registers */
61	bus_space_tag_t       cmd_iot;
62	bus_space_handle_t    cmd_ioh;
63	bus_space_tag_t       ctl_iot;
64	bus_space_handle_t    ctl_ioh;
65	/* data32{iot,ioh} are only used for 32 bit xfers */
66	bus_space_tag_t         data32iot;
67	bus_space_handle_t      data32ioh;
68	/* Our state */
69	int ch_flags;
70#define WDCF_ACTIVE   0x01	/* channel is active */
71#define WDCF_IRQ_WAIT 0x10	/* controller is waiting for irq */
72	u_int8_t ch_status;         /* copy of status register */
73	u_int8_t ch_error;          /* copy of error register */
74	/* per-drive infos */
75	struct ata_drive_datas ch_drive[2];
76
77	struct atapiscsi_softc *ch_as;
78
79	/*
80	 * channel queues. May be the same for all channels, if hw channels
81	 * are not independants
82	 */
83	struct channel_queue *ch_queue;
84};
85
86struct wdc_softc { /* Per controller state */
87	struct device sc_dev;
88	/* mandatory fields */
89	int           cap;
90/* Capabilities supported by the controller */
91#define	WDC_CAPABILITY_DATA16 0x0001    /* can do  16-bit data access */
92#define	WDC_CAPABILITY_DATA32 0x0002    /* can do 32-bit data access */
93#define WDC_CAPABILITY_MODE   0x0004	/* controller knows its PIO/DMA modes */
94#define	WDC_CAPABILITY_DMA    0x0008	/* DMA */
95#define	WDC_CAPABILITY_UDMA   0x0010	/* Ultra-DMA/33 */
96#define	WDC_CAPABILITY_HWLOCK 0x0020	/* Needs to lock HW */
97#define	WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */
98#define	WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */
99#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
100#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */
101	u_int8_t      PIO_cap; /* highest PIO mode supported */
102	u_int8_t      DMA_cap; /* highest DMA mode supported */
103	u_int8_t      UDMA_cap; /* highest UDMA mode supported */
104	int nchannels;	/* Number of channels on this controller */
105	struct channel_softc **channels;  /* channels-specific datas (array) */
106
107#if 0
108	/*
109	 * The reference count here is used for both IDE and ATAPI devices.
110	 */
111	struct scsipi_adapter sc_atapi_adapter;
112#endif
113
114	/* if WDC_CAPABILITY_DMA set in 'cap' */
115	void            *dma_arg;
116	int            (*dma_init) __P((void *, int, int, void *, size_t,
117	                int));
118	void           (*dma_start) __P((void *, int, int, int));
119	int            (*dma_finish) __P((void *, int, int, int));
120/* flags passed to DMA functions */
121#define WDC_DMA_READ 0x01
122#define WDC_DMA_POLL 0x02
123
124	/* if WDC_CAPABILITY_HWLOCK set in 'cap' */
125	int            (*claim_hw) __P((void *, int));
126	void            (*free_hw) __P((void *));
127
128	/* if WDC_CAPABILITY_MODE set in 'cap' */
129	void 		(*set_modes) __P((struct channel_softc *));
130};
131
132 /*
133  * Description of a command to be handled by a controller.
134  * These commands are queued in a list.
135  */
136struct wdc_xfer {
137	volatile u_int c_flags;
138#define C_INUSE  	0x0001 /* xfer struct is in use */
139#define C_ATAPI  	0x0002 /* xfer is ATAPI request */
140#define C_TIMEOU  	0x0004 /* xfer processing timed out */
141#define C_NEEDDONE  	0x0010 /* need to call upper-level done */
142#define C_POLL		0x0020 /* cmd is polled */
143#define C_DMA		0x0040 /* cmd uses DMA */
144#define C_SENSE		0x0080 /* cmd is a internal command */
145
146	/* Informations about our location */
147	struct channel_softc *chp;
148	u_int8_t drive;
149
150	/* Information about the current transfer  */
151	void *cmd; /* wdc, ata or scsipi command structure */
152	void *databuf;
153	int c_bcount;      /* byte count left */
154	int c_skip;        /* bytes already transferred */
155	TAILQ_ENTRY(wdc_xfer) c_xferchain;
156	LIST_ENTRY(wdc_xfer) free_list;
157	void (*c_start) __P((struct channel_softc *, struct wdc_xfer *));
158	int  (*c_intr)  __P((struct channel_softc *, struct wdc_xfer *, int));
159};
160
161/*
162 * Public functions which can be called by ATA or ATAPI specific parts,
163 * or bus-specific backends.
164 */
165
166int   wdcprobe __P((struct channel_softc *));
167void  wdcattach __P((struct channel_softc *));
168void  wdc_final_attach __P((struct channel_softc *));
169int   wdcintr __P((void *));
170void  wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *));
171struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */
172#define WDC_CANSLEEP 0x00
173#define WDC_NOSLEEP 0x01
174void   wdc_free_xfer  __P((struct channel_softc *, struct wdc_xfer *));
175void  wdcstart __P((struct channel_softc *));
176void  wdcrestart __P((void*));
177int   wdcreset	__P((struct channel_softc *, int));
178#define VERBOSE 1
179#define SILENT 0 /* wdcreset will not print errors */
180int   wdcwait __P((struct channel_softc *, int, int, int));
181void  wdcbit_bucket __P(( struct channel_softc *, int));
182void  wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t,
183	                  u_int8_t, u_int8_t, u_int8_t, u_int8_t));
184void   wdccommandshort __P((struct channel_softc *, int, int));
185void  wdctimeout	__P((void *arg));
186
187int	wdc_addref __P((struct channel_softc *));
188void	wdc_delref __P((struct channel_softc *));
189
190/*
191 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
192 * command is aborted.
193 */
194#define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout))
195#define wait_for_unbusy(chp, timeout)	wdcwait((chp), 0, 0, (timeout))
196#define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \
197	WDCS_DRDY, (timeout))
198/* ATA/ATAPI specs says a device can take 31s to reset */
199#define WDC_RESET_WAIT 31000
200
201void wdc_atapibus_attach __P((struct channel_softc *));
202void wdc_atapibus_final_attach __P((struct channel_softc *));
203
204int   atapi_print       __P((void *, const char *));
205