wdcreg.h revision 1.1
1/* $OpenBSD: wdcreg.h,v 1.1 1999/07/18 21:25:16 csapuntz Exp $ */ 2/* $NetBSD: wdcreg.h,v 1.22 1999/03/07 14:02:54 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)wdreg.h 7.1 (Berkeley) 5/9/91 40 */ 41 42/* 43 * Disk Controller register definitions. 44 */ 45 46/* offsets of registers in the 'regular' register region */ 47#define wd_data 0 /* data register (R/W - 16 bits) */ 48#define wd_error 1 /* error register (R) */ 49#define wd_precomp 1 /* write precompensation (W) */ 50#define wd_features 1 /* features (W), same as wd_precomp */ 51#define wd_seccnt 2 /* sector count (R/W) */ 52#define wd_ireason 2 /* interrupt reason (R/W) (for atapi) */ 53#define wd_sector 3 /* first sector number (R/W) */ 54#define wd_cyl_lo 4 /* cylinder address, low byte (R/W) */ 55#define wd_cyl_hi 5 /* cylinder address, high byte (R/W) */ 56#define wd_sdh 6 /* sector size/drive/head (R/W) */ 57#define wd_command 7 /* command register (W) */ 58#define wd_status 7 /* immediate status (R) */ 59 60/* offsets of registers in the auxiliary register region */ 61#define wd_aux_altsts 0 /* alternate fixed disk status (R) */ 62#define wd_aux_ctlr 0 /* fixed disk controller control (W) */ 63#define WDCTL_4BIT 0x08 /* use four head bits (wd1003) */ 64#define WDCTL_RST 0x04 /* reset the controller */ 65#define WDCTL_IDS 0x02 /* disable controller interrupts */ 66#if 0 /* NOT MAPPED; fd uses this register on PCs */ 67#define wd_digin 1 /* disk controller input (R) */ 68#endif 69 70/* 71 * Status bits. 72 */ 73#define WDCS_BSY 0x80 /* busy */ 74#define WDCS_DRDY 0x40 /* drive ready */ 75#define WDCS_DWF 0x20 /* drive write fault */ 76#define WDCS_DSC 0x10 /* drive seek complete */ 77#define WDCS_DRQ 0x08 /* data request */ 78#define WDCS_CORR 0x04 /* corrected data */ 79#define WDCS_IDX 0x02 /* index */ 80#define WDCS_ERR 0x01 /* error */ 81#define WDCS_BITS "\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err" 82 83/* 84 * Error bits. 85 */ 86#define WDCE_BBK 0x80 /* bad block detected */ 87#define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ 88#define WDCE_UNC 0x40 /* uncorrectable data error */ 89#define WDCE_MC 0x20 /* media changed */ 90#define WDCE_IDNF 0x10 /* id not found */ 91#define WDCE_MCR 0x08 /* media change requested */ 92#define WDCE_ABRT 0x04 /* aborted command */ 93#define WDCE_TK0NF 0x02 /* track 0 not found */ 94#define WDCE_AMNF 0x01 /* address mark not found */ 95 96/* 97 * Commands for Disk Controller. 98 */ 99#define WDCC_NOP 0x00 /* NOP - Always fail with "aborted command" */ 100#define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ 101 102#define WDCC_READ 0x20 /* disk read code */ 103#define WDCC_WRITE 0x30 /* disk write code */ 104#define WDCC__LONG 0x02 /* modifier -- access ecc bytes */ 105#define WDCC__NORETRY 0x01 /* modifier -- no retrys */ 106 107#define WDCC_FORMAT 0x50 /* disk format code */ 108#define WDCC_DIAGNOSE 0x90 /* controller diagnostic */ 109#define WDCC_IDP 0x91 /* initialize drive parameters */ 110 111#define WDCC_READMULTI 0xc4 /* read multiple */ 112#define WDCC_WRITEMULTI 0xc5 /* write multiple */ 113#define WDCC_SETMULTI 0xc6 /* set multiple mode */ 114 115#define WDCC_READDMA 0xc8 /* read with DMA */ 116#define WDCC_WRITEDMA 0xca /* write with DMA */ 117 118#define WDCC_ACKMC 0xdb /* acknowledge media change */ 119#define WDCC_LOCK 0xde /* lock drawer */ 120#define WDCC_UNLOCK 0xdf /* unlock drawer */ 121 122#define WDCC_FLUSHCACHE 0xe7 /* Flush cache */ 123#define WDCC_IDENTIFY 0xec /* read parameters from controller */ 124#define SET_FEATURES 0xef /* set features */ 125 126#define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ 127#define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ 128#define WDCC_SLEEP 0xe6 /* enter sleep mode */ 129#define WDCC_STANDBY 0xe2 /* set standby timer & enter standby mode */ 130#define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ 131#define WDCC_CHECK_PWR 0xe5 /* check power mode */ 132 133/* Subcommands for SET_FEATURES (features register ) */ 134#define WDSF_EN_WR_CACHE 0x02 135#define WDSF_SET_MODE 0x03 136#define WDSF_REASSIGN_EN 0x04 137#define WDSF_RETRY_DS 0x33 138#define WDSF_SET_CACHE_SGMT 0x54 139#define WDSF_READAHEAD_DS 0x55 140#define WDSF_POD_DS 0x66 141#define WDSF_ECC_DS 0x77 142#define WDSF_WRITE_CACHE_DS 0x82 143#define WDSF_REASSIGN_DS 0x84 144#define WDSF_ECC_EN 0x88 145#define WDSF_RETRY_EN 0x99 146#define WDSF_SET_CURRENT 0x9A 147#define WDSF_READAHEAD_EN 0xAA 148#define WDSF_PREFETCH_SET 0xAB 149#define WDSF_POD_EN 0xCC 150 151/* parameters uploaded to device/heads register */ 152#define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ 153#define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ 154#define WDSD_LBA 0x40 /* logical block addressing */ 155 156/* Commands for ATAPI devices */ 157#define ATAPI_CHECK_POWER_MODE 0xe5 158#define ATAPI_EXEC_DRIVE_DIAGS 0x90 159#define ATAPI_IDLE_IMMEDIATE 0xe1 160#define ATAPI_NOP 0x00 161#define ATAPI_PKT_CMD 0xa0 162#define ATAPI_IDENTIFY_DEVICE 0xa1 163#define ATAPI_SOFT_RESET 0x08 164#define ATAPI_SLEEP 0xe6 165#define ATAPI_STANDBY_IMMEDIATE 0xe0 166 167/* Bytes used by ATAPI_PACKET_COMMAND ( feature register) */ 168#define ATAPI_PKT_CMD_FTRE_DMA 0x01 169#define ATAPI_PKT_CMD_FTRE_OVL 0x02 170 171/* ireason */ 172#define WDCI_CMD 0x01 /* command(1) or data(0) */ 173#define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ 174#define WDCI_RELEASE 0x04 /* bus released until completion */ 175 176#define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) 177#define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) 178#define PHASE_DATAOUT WDCS_DRQ 179#define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) 180#define PHASE_ABORTED 0 181 182