ti.c revision 1.12
1/* $OpenBSD: ti.c,v 1.12 2014/12/22 02:28:51 tedu Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25 2000/01/18 00:26:29 wpaul Exp $ 35 */ 36 37/* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for OpenBSD. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The following people deserve special thanks: 65 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 66 * for testing 67 * - Raymond Lee of Netgear, for providing a pair of Netgear 68 * GA620 Tigon 2 boards for testing 69 * - Ulf Zimmermann, for bringing the GA260 to my attention and 70 * convincing me to write this driver. 71 * - Andrew Gallatin for providing FreeBSD/Alpha support. 72 */ 73 74#include "bpfilter.h" 75#include "vlan.h" 76 77#include <sys/param.h> 78#include <sys/systm.h> 79#include <sys/sockio.h> 80#include <sys/mbuf.h> 81#include <sys/malloc.h> 82#include <sys/kernel.h> 83#include <sys/socket.h> 84#include <sys/device.h> 85#include <sys/queue.h> 86 87#include <net/if.h> 88#include <net/if_dl.h> 89#include <net/if_types.h> 90 91#include <netinet/in.h> 92#include <netinet/if_ether.h> 93 94#include <net/if_media.h> 95 96#if NBPFILTER > 0 97#include <net/bpf.h> 98#endif 99 100#if NVLAN > 0 101#include <net/if_vlan_var.h> 102#endif 103 104#include <machine/bus.h> 105 106#include <dev/ic/tireg.h> 107#include <dev/ic/tivar.h> 108#include <dev/pci/pcireg.h> 109 110struct cfdriver ti_cd = { 111 NULL, "ti", DV_IFNET 112}; 113 114void ti_txeof_tigon1(struct ti_softc *); 115void ti_txeof_tigon2(struct ti_softc *); 116void ti_rxeof(struct ti_softc *); 117 118void ti_stats_update(struct ti_softc *); 119int ti_encap_tigon1(struct ti_softc *, struct mbuf *, u_int32_t *); 120int ti_encap_tigon2(struct ti_softc *, struct mbuf *, u_int32_t *); 121 122int ti_intr(void *); 123void ti_start(struct ifnet *); 124int ti_ioctl(struct ifnet *, u_long, caddr_t); 125void ti_init(void *); 126void ti_init2(struct ti_softc *); 127void ti_stop(struct ti_softc *); 128void ti_watchdog(struct ifnet *); 129int ti_ifmedia_upd(struct ifnet *); 130void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 131 132u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 133u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 134int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 135 136void ti_add_mcast(struct ti_softc *, struct ether_addr *); 137void ti_del_mcast(struct ti_softc *, struct ether_addr *); 138void ti_iff(struct ti_softc *); 139 140void ti_mem_read(struct ti_softc *, u_int32_t, u_int32_t, void *); 141void ti_mem_write(struct ti_softc *, u_int32_t, u_int32_t, const void*); 142void ti_mem_set(struct ti_softc *, u_int32_t, u_int32_t); 143void ti_loadfw(struct ti_softc *); 144void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 145void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, 146 caddr_t, int); 147void ti_handle_events(struct ti_softc *); 148int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 149int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 150int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 151int ti_init_rx_ring_std(struct ti_softc *); 152void ti_free_rx_ring_std(struct ti_softc *); 153int ti_init_rx_ring_jumbo(struct ti_softc *); 154void ti_free_rx_ring_jumbo(struct ti_softc *); 155int ti_init_rx_ring_mini(struct ti_softc *); 156void ti_free_rx_ring_mini(struct ti_softc *); 157void ti_free_tx_ring(struct ti_softc *); 158int ti_init_tx_ring(struct ti_softc *); 159 160int ti_64bitslot_war(struct ti_softc *); 161int ti_chipinit(struct ti_softc *); 162void ti_chipinit_pci(struct ti_softc *); 163void ti_chipinit_sbus(struct ti_softc *); 164int ti_gibinit(struct ti_softc *); 165 166/* 167 * Send an instruction or address to the EEPROM, check for ACK. 168 */ 169u_int32_t 170ti_eeprom_putbyte(struct ti_softc *sc, int byte) 171{ 172 int i, ack = 0; 173 174 /* 175 * Make sure we're in TX mode. 176 */ 177 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 178 179 /* 180 * Feed in each bit and strobe the clock. 181 */ 182 for (i = 0x80; i; i >>= 1) { 183 if (byte & i) 184 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 185 else 186 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 187 DELAY(1); 188 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 189 DELAY(1); 190 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 191 } 192 193 /* 194 * Turn off TX mode. 195 */ 196 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 197 198 /* 199 * Check for ack. 200 */ 201 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 202 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 203 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 204 205 return (ack); 206} 207 208/* 209 * Read a byte of data stored in the EEPROM at address 'addr.' 210 * We have to send two address bytes since the EEPROM can hold 211 * more than 256 bytes of data. 212 */ 213u_int8_t 214ti_eeprom_getbyte(struct ti_softc *sc, int addr, u_int8_t *dest) 215{ 216 int i; 217 u_int8_t byte = 0; 218 219 EEPROM_START; 220 221 /* 222 * Send write control code to EEPROM. 223 */ 224 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 225 printf("%s: failed to send write command, status: %x\n", 226 sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 227 return (1); 228 } 229 230 /* 231 * Send first byte of address of byte we want to read. 232 */ 233 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 234 printf("%s: failed to send address, status: %x\n", 235 sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 236 return (1); 237 } 238 /* 239 * Send second byte address of byte we want to read. 240 */ 241 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 242 printf("%s: failed to send address, status: %x\n", 243 sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 244 return (1); 245 } 246 247 EEPROM_STOP; 248 EEPROM_START; 249 /* 250 * Send read control code to EEPROM. 251 */ 252 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 253 printf("%s: failed to send read command, status: %x\n", 254 sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 255 return (1); 256 } 257 258 /* 259 * Start reading bits from EEPROM. 260 */ 261 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 262 for (i = 0x80; i; i >>= 1) { 263 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 264 DELAY(1); 265 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 266 byte |= i; 267 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 268 DELAY(1); 269 } 270 271 EEPROM_STOP; 272 273 /* 274 * No ACK generated for read, so just return byte. 275 */ 276 277 *dest = byte; 278 279 return (0); 280} 281 282/* 283 * Read a sequence of bytes from the EEPROM. 284 */ 285int 286ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 287{ 288 int err = 0, i; 289 u_int8_t byte = 0; 290 291 for (i = 0; i < cnt; i++) { 292 err = ti_eeprom_getbyte(sc, off + i, &byte); 293 if (err) 294 break; 295 *(dest + i) = byte; 296 } 297 298 return (err ? 1 : 0); 299} 300 301/* 302 * NIC memory read function. 303 * Can be used to copy data from NIC local memory. 304 */ 305void 306ti_mem_read(struct ti_softc *sc, u_int32_t addr, u_int32_t len, void *buf) 307{ 308 int segptr, segsize, cnt; 309 caddr_t ptr; 310 311 segptr = addr; 312 cnt = len; 313 ptr = buf; 314 315 while(cnt) { 316 if (cnt < TI_WINLEN) 317 segsize = cnt; 318 else 319 segsize = TI_WINLEN - (segptr % TI_WINLEN); 320 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 321 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 322 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 323 segsize / 4); 324 ptr += segsize; 325 segptr += segsize; 326 cnt -= segsize; 327 } 328} 329 330/* 331 * NIC memory write function. 332 * Can be used to copy data into NIC local memory. 333 */ 334void 335ti_mem_write(struct ti_softc *sc, u_int32_t addr, u_int32_t len, 336 const void *buf) 337{ 338 int segptr, segsize, cnt; 339 const char *ptr; 340 341 segptr = addr; 342 cnt = len; 343 ptr = buf; 344 345 while(cnt) { 346 if (cnt < TI_WINLEN) 347 segsize = cnt; 348 else 349 segsize = TI_WINLEN - (segptr % TI_WINLEN); 350 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 351 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 352 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 353 segsize / 4); 354 ptr += segsize; 355 segptr += segsize; 356 cnt -= segsize; 357 } 358} 359 360/* 361 * NIC memory write function. 362 * Can be used to clear a section of NIC local memory. 363 */ 364void 365ti_mem_set(struct ti_softc *sc, u_int32_t addr, u_int32_t len) 366{ 367 int segptr, segsize, cnt; 368 369 segptr = addr; 370 cnt = len; 371 372 while(cnt) { 373 if (cnt < TI_WINLEN) 374 segsize = cnt; 375 else 376 segsize = TI_WINLEN - (segptr % TI_WINLEN); 377 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 378 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 379 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 380 segptr += segsize; 381 cnt -= segsize; 382 } 383} 384 385/* 386 * Load firmware image into the NIC. Check that the firmware revision 387 * is acceptable and see if we want the firmware for the Tigon 1 or 388 * Tigon 2. 389 */ 390void 391ti_loadfw(struct ti_softc *sc) 392{ 393 struct tigon_firmware *tf; 394 u_char *buf = NULL; 395 u_int32_t *b; 396 size_t buflen, i, cnt; 397 char *name; 398 int error; 399 400 switch(sc->ti_hwrev) { 401 case TI_HWREV_TIGON: 402 name = "tigon1"; 403 break; 404 case TI_HWREV_TIGON_II: 405 name = "tigon2"; 406 break; 407 default: 408 printf("%s: can't load firmware: unknown hardware rev\n", 409 sc->sc_dv.dv_xname); 410 return; 411 } 412 413 error = loadfirmware(name, &buf, &buflen); 414 if (error) 415 return; 416 /* convert firmware to host byte order */ 417 b = (u_int32_t *)buf; 418 cnt = buflen / sizeof(u_int32_t); 419 for (i = 0; i < cnt; i++) 420 b[i] = letoh32(b[i]); 421 422 tf = (struct tigon_firmware *)buf; 423 if (tf->FwReleaseMajor != TI_FIRMWARE_MAJOR || 424 tf->FwReleaseMinor != TI_FIRMWARE_MINOR || 425 tf->FwReleaseFix != TI_FIRMWARE_FIX) { 426 printf("%s: firmware revision mismatch; want " 427 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dv.dv_xname, 428 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 429 TI_FIRMWARE_FIX, tf->FwReleaseMajor, 430 tf->FwReleaseMinor, tf->FwReleaseFix); 431 free(buf, M_DEVBUF, 0); 432 return; 433 } 434 ti_mem_write(sc, tf->FwTextAddr, tf->FwTextLen, 435 (caddr_t)&tf->data[tf->FwTextOffset]); 436 ti_mem_write(sc, tf->FwRodataAddr, tf->FwRodataLen, 437 (caddr_t)&tf->data[tf->FwRodataOffset]); 438 ti_mem_write(sc, tf->FwDataAddr, tf->FwDataLen, 439 (caddr_t)&tf->data[tf->FwDataOffset]); 440 ti_mem_set(sc, tf->FwBssAddr, tf->FwBssLen); 441 ti_mem_set(sc, tf->FwSbssAddr, tf->FwSbssLen); 442 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tf->FwStartAddr); 443 free(buf, M_DEVBUF, 0); 444} 445 446/* 447 * Send the NIC a command via the command ring. 448 */ 449void 450ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 451{ 452 u_int32_t index; 453 454 index = sc->ti_cmd_saved_prodidx; 455 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 456 TI_INC(index, TI_CMD_RING_CNT); 457 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 458 sc->ti_cmd_saved_prodidx = index; 459} 460 461/* 462 * Send the NIC an extended command. The 'len' parameter specifies the 463 * number of command slots to include after the initial command. 464 */ 465void 466ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, 467 int len) 468{ 469 u_int32_t index; 470 int i; 471 472 index = sc->ti_cmd_saved_prodidx; 473 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 474 TI_INC(index, TI_CMD_RING_CNT); 475 for (i = 0; i < len; i++) { 476 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 477 *(u_int32_t *)(&arg[i * 4])); 478 TI_INC(index, TI_CMD_RING_CNT); 479 } 480 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 481 sc->ti_cmd_saved_prodidx = index; 482} 483 484/* 485 * Handle events that have triggered interrupts. 486 */ 487void 488ti_handle_events(struct ti_softc *sc) 489{ 490 struct ti_event_desc *e; 491 struct ifnet *ifp = &sc->arpcom.ac_if; 492 493 if (sc->ti_rdata->ti_event_ring == NULL) 494 return; 495 496 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 497 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 498 switch (TI_EVENT_EVENT(e)) { 499 case TI_EV_LINKSTAT_CHANGED: 500 sc->ti_linkstat = TI_EVENT_CODE(e); 501 switch (sc->ti_linkstat) { 502 case TI_EV_CODE_LINK_UP: 503 case TI_EV_CODE_GIG_LINK_UP: 504 { 505 struct ifmediareq ifmr; 506 507 bzero(&ifmr, sizeof(ifmr)); 508 ti_ifmedia_sts(ifp, &ifmr); 509 if (ifmr.ifm_active & IFM_FDX) { 510 ifp->if_link_state = 511 LINK_STATE_FULL_DUPLEX; 512 } else { 513 ifp->if_link_state = 514 LINK_STATE_HALF_DUPLEX; 515 } 516 if_link_state_change(ifp); 517 ifp->if_baudrate = 518 ifmedia_baudrate(ifmr.ifm_active); 519 break; 520 } 521 case TI_EV_CODE_LINK_DOWN: 522 ifp->if_link_state = LINK_STATE_DOWN; 523 if_link_state_change(ifp); 524 ifp->if_baudrate = 0; 525 break; 526 default: 527 printf("%s: unknown link state code %d\n", 528 sc->sc_dv.dv_xname, sc->ti_linkstat); 529 } 530 break; 531 case TI_EV_ERROR: 532 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 533 printf("%s: invalid command\n", 534 sc->sc_dv.dv_xname); 535 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 536 printf("%s: unknown command\n", 537 sc->sc_dv.dv_xname); 538 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 539 printf("%s: bad config data\n", 540 sc->sc_dv.dv_xname); 541 break; 542 case TI_EV_FIRMWARE_UP: 543 ti_init2(sc); 544 break; 545 case TI_EV_STATS_UPDATED: 546 ti_stats_update(sc); 547 break; 548 case TI_EV_RESET_JUMBO_RING: 549 case TI_EV_MCAST_UPDATED: 550 /* Who cares. */ 551 break; 552 default: 553 printf("%s: unknown event: %d\n", sc->sc_dv.dv_xname, 554 TI_EVENT_EVENT(e)); 555 break; 556 } 557 /* Advance the consumer index. */ 558 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 559 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 560 } 561} 562 563/* 564 * Intialize a standard receive ring descriptor. 565 */ 566int 567ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, 568 bus_dmamap_t dmamap) 569{ 570 struct mbuf *m_new = NULL; 571 struct ti_rx_desc *r; 572 573 if (dmamap == NULL) { 574 /* if (m) panic() */ 575 576 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 577 0, BUS_DMA_NOWAIT, &dmamap)) { 578 printf("%s: can't create recv map\n", 579 sc->sc_dv.dv_xname); 580 return (ENOMEM); 581 } 582 } else if (m == NULL) 583 bus_dmamap_unload(sc->sc_dmatag, dmamap); 584 585 sc->ti_cdata.ti_rx_std_map[i] = dmamap; 586 587 if (m == NULL) { 588 m_new = MCLGETI(NULL, MCLBYTES, NULL, M_DONTWAIT); 589 if (m_new == NULL) 590 return (ENOBUFS); 591 592 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 593 m_adj(m_new, ETHER_ALIGN); 594 595 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 596 BUS_DMA_NOWAIT)) { 597 m_freem(m_new); 598 return (ENOBUFS); 599 } 600 } else { 601 /* 602 * We're re-using a previously allocated mbuf; 603 * be sure to re-init pointers and lengths to 604 * default values. 605 */ 606 m_new = m; 607 m_new->m_data = m_new->m_ext.ext_buf; 608 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 609 m_adj(m_new, ETHER_ALIGN); 610 } 611 612 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 613 r = &sc->ti_rdata->ti_rx_std_ring[i]; 614 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 615 r->ti_type = TI_BDTYPE_RECV_BD; 616 r->ti_flags = TI_BDFLAG_IP_CKSUM; 617 r->ti_len = dmamap->dm_segs[0].ds_len; 618 r->ti_idx = i; 619 620 return (0); 621} 622 623/* 624 * Intialize a mini receive ring descriptor. This only applies to 625 * the Tigon 2. 626 */ 627int 628ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, 629 bus_dmamap_t dmamap) 630{ 631 struct mbuf *m_new = NULL; 632 struct ti_rx_desc *r; 633 634 if (dmamap == NULL) { 635 /* if (m) panic() */ 636 637 if (bus_dmamap_create(sc->sc_dmatag, MHLEN, 1, MHLEN, 638 0, BUS_DMA_NOWAIT, &dmamap)) { 639 printf("%s: can't create recv map\n", 640 sc->sc_dv.dv_xname); 641 return (ENOMEM); 642 } 643 } else if (m == NULL) 644 bus_dmamap_unload(sc->sc_dmatag, dmamap); 645 646 sc->ti_cdata.ti_rx_mini_map[i] = dmamap; 647 648 if (m == NULL) { 649 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 650 if (m_new == NULL) 651 return (ENOBUFS); 652 653 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 654 m_adj(m_new, ETHER_ALIGN); 655 656 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 657 BUS_DMA_NOWAIT)) { 658 m_freem(m); 659 return (ENOBUFS); 660 } 661 } else { 662 /* 663 * We're re-using a previously allocated mbuf; 664 * be sure to re-init pointers and lengths to 665 * default values. 666 */ 667 m_new = m; 668 m_new->m_data = m_new->m_pktdat; 669 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 670 } 671 672 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 673 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 674 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 675 r->ti_type = TI_BDTYPE_RECV_BD; 676 r->ti_flags = TI_BDFLAG_MINI_RING | TI_BDFLAG_IP_CKSUM; 677 r->ti_len = dmamap->dm_segs[0].ds_len; 678 r->ti_idx = i; 679 680 return (0); 681} 682 683/* 684 * Initialize a jumbo receive ring descriptor. This allocates 685 * a jumbo buffer from the pool managed internally by the driver. 686 */ 687int 688ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m, 689 bus_dmamap_t dmamap) 690{ 691 struct mbuf *m_new = NULL; 692 struct ti_rx_desc *r; 693 694 if (dmamap == NULL) { 695 /* if (m) panic() */ 696 697 if (bus_dmamap_create(sc->sc_dmatag, TI_JUMBO_FRAMELEN, 1, 698 TI_JUMBO_FRAMELEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 699 printf("%s: can't create recv map\n", 700 sc->sc_dv.dv_xname); 701 return (ENOMEM); 702 } 703 } else if (m == NULL) 704 bus_dmamap_unload(sc->sc_dmatag, dmamap); 705 706 if (m == NULL) { 707 m_new = MCLGETI(NULL, TI_JUMBO_FRAMELEN, NULL, M_DONTWAIT); 708 if (m_new == NULL) 709 return (ENOBUFS); 710 711 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 712 m_adj(m_new, ETHER_ALIGN); 713 714 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 715 BUS_DMA_NOWAIT)) { 716 m_freem(m); 717 return (ENOBUFS); 718 } 719 } else { 720 /* 721 * We're re-using a previously allocated mbuf; 722 * be sure to re-init pointers and lengths to 723 * default values. 724 */ 725 m_new = m; 726 m_new->m_data = m_new->m_ext.ext_buf; 727 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 728 m_adj(m_new, ETHER_ALIGN); 729 } 730 731 /* Set up the descriptor. */ 732 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 733 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 734 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 735 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 736 r->ti_flags = TI_BDFLAG_JUMBO_RING | TI_BDFLAG_IP_CKSUM; 737 r->ti_len = m_new->m_len; 738 r->ti_idx = i; 739 740 return (0); 741} 742 743/* 744 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 745 * that's 1MB of memory, which is a lot. For now, we fill only the first 746 * 256 ring entries and hope that our CPU is fast enough to keep up with 747 * the NIC. 748 */ 749int 750ti_init_rx_ring_std(struct ti_softc *sc) 751{ 752 int i; 753 struct ti_cmd_desc cmd; 754 755 for (i = 0; i < TI_SSLOTS; i++) { 756 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 757 return (ENOBUFS); 758 } 759 760 TI_UPDATE_STDPROD(sc, i - 1); 761 sc->ti_std = i - 1; 762 763 return (0); 764} 765 766void 767ti_free_rx_ring_std(struct ti_softc *sc) 768{ 769 int i; 770 771 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 772 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 773 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 774 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 775 bus_dmamap_destroy(sc->sc_dmatag, 776 sc->ti_cdata.ti_rx_std_map[i]); 777 sc->ti_cdata.ti_rx_std_map[i] = 0; 778 } 779 bzero(&sc->ti_rdata->ti_rx_std_ring[i], 780 sizeof(struct ti_rx_desc)); 781 } 782} 783 784int 785ti_init_rx_ring_jumbo(struct ti_softc *sc) 786{ 787 int i; 788 struct ti_cmd_desc cmd; 789 790 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 791 if (ti_newbuf_jumbo(sc, i, NULL, 0) == ENOBUFS) 792 return (ENOBUFS); 793 }; 794 795 TI_UPDATE_JUMBOPROD(sc, i - 1); 796 sc->ti_jumbo = i - 1; 797 798 return (0); 799} 800 801void 802ti_free_rx_ring_jumbo(struct ti_softc *sc) 803{ 804 int i; 805 806 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 807 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 808 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 809 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 810 } 811 bzero(&sc->ti_rdata->ti_rx_jumbo_ring[i], 812 sizeof(struct ti_rx_desc)); 813 } 814} 815 816int 817ti_init_rx_ring_mini(struct ti_softc *sc) 818{ 819 int i; 820 821 for (i = 0; i < TI_MSLOTS; i++) { 822 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 823 return (ENOBUFS); 824 }; 825 826 TI_UPDATE_MINIPROD(sc, i - 1); 827 sc->ti_mini = i - 1; 828 829 return (0); 830} 831 832void 833ti_free_rx_ring_mini(struct ti_softc *sc) 834{ 835 int i; 836 837 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 838 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 839 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 840 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 841 bus_dmamap_destroy(sc->sc_dmatag, 842 sc->ti_cdata.ti_rx_mini_map[i]); 843 sc->ti_cdata.ti_rx_mini_map[i] = 0; 844 } 845 bzero(&sc->ti_rdata->ti_rx_mini_ring[i], 846 sizeof(struct ti_rx_desc)); 847 } 848} 849 850void 851ti_free_tx_ring(struct ti_softc *sc) 852{ 853 int i; 854 struct ti_txmap_entry *entry; 855 856 if (sc->ti_rdata->ti_tx_ring == NULL) 857 return; 858 859 for (i = 0; i < TI_TX_RING_CNT; i++) { 860 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 861 m_freem(sc->ti_cdata.ti_tx_chain[i]); 862 sc->ti_cdata.ti_tx_chain[i] = NULL; 863 SLIST_INSERT_HEAD(&sc->ti_tx_map_listhead, 864 sc->ti_cdata.ti_tx_map[i], link); 865 sc->ti_cdata.ti_tx_map[i] = 0; 866 } 867 bzero(&sc->ti_rdata->ti_tx_ring[i], 868 sizeof(struct ti_tx_desc)); 869 } 870 871 while ((entry = SLIST_FIRST(&sc->ti_tx_map_listhead))) { 872 SLIST_REMOVE_HEAD(&sc->ti_tx_map_listhead, link); 873 bus_dmamap_destroy(sc->sc_dmatag, entry->dmamap); 874 free(entry, M_DEVBUF, 0); 875 } 876} 877 878int 879ti_init_tx_ring(struct ti_softc *sc) 880{ 881 int i; 882 bus_dmamap_t dmamap; 883 struct ti_txmap_entry *entry; 884 885 sc->ti_txcnt = 0; 886 sc->ti_tx_saved_considx = 0; 887 sc->ti_tx_saved_prodidx = 0; 888 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 889 890 SLIST_INIT(&sc->ti_tx_map_listhead); 891 for (i = 0; i < TI_TX_RING_CNT; i++) { 892 if (bus_dmamap_create(sc->sc_dmatag, TI_JUMBO_FRAMELEN, 893 TI_NTXSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) 894 return (ENOBUFS); 895 896 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 897 if (!entry) { 898 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 899 return (ENOBUFS); 900 } 901 entry->dmamap = dmamap; 902 SLIST_INSERT_HEAD(&sc->ti_tx_map_listhead, entry, link); 903 } 904 905 return (0); 906} 907 908/* 909 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 910 * but we have to support the old way too so that Tigon 1 cards will 911 * work. 912 */ 913void 914ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 915{ 916 struct ti_cmd_desc cmd; 917 u_int16_t *m; 918 u_int32_t ext[2] = {0, 0}; 919 920 m = (u_int16_t *)&addr->ether_addr_octet[0]; 921 922 switch(sc->ti_hwrev) { 923 case TI_HWREV_TIGON: 924 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 925 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 926 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 927 break; 928 case TI_HWREV_TIGON_II: 929 ext[0] = htons(m[0]); 930 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 931 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 932 break; 933 default: 934 printf("%s: unknown hwrev\n", sc->sc_dv.dv_xname); 935 break; 936 } 937} 938 939void 940ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 941{ 942 struct ti_cmd_desc cmd; 943 u_int16_t *m; 944 u_int32_t ext[2] = {0, 0}; 945 946 m = (u_int16_t *)&addr->ether_addr_octet[0]; 947 948 switch(sc->ti_hwrev) { 949 case TI_HWREV_TIGON: 950 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 951 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 952 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 953 break; 954 case TI_HWREV_TIGON_II: 955 ext[0] = htons(m[0]); 956 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 957 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 958 break; 959 default: 960 printf("%s: unknown hwrev\n", sc->sc_dv.dv_xname); 961 break; 962 } 963} 964 965/* 966 * Configure the Tigon's multicast address filter. 967 * 968 * The actual multicast table management is a bit of a pain, thanks to 969 * slight brain damage on the part of both Alteon and us. With our 970 * multicast code, we are only alerted when the multicast address table 971 * changes and at that point we only have the current list of addresses: 972 * we only know the current state, not the previous state, so we don't 973 * actually know what addresses were removed or added. The firmware has 974 * state, but we can't get our grubby mits on it, and there is no 'delete 975 * all multicast addresses' command. Hence, we have to maintain our own 976 * state so we know what addresses have been programmed into the NIC at 977 * any given time. 978 */ 979void 980ti_iff(struct ti_softc *sc) 981{ 982 struct ifnet *ifp = &sc->arpcom.ac_if; 983 struct arpcom *ac = &sc->arpcom; 984 struct ether_multi *enm; 985 struct ether_multistep step; 986 struct ti_cmd_desc cmd; 987 struct ti_mc_entry *mc; 988 u_int32_t intrs; 989 990 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 991 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 992 ifp->if_flags &= ~IFF_ALLMULTI; 993 994 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 995 ifp->if_flags |= IFF_ALLMULTI; 996 if (ifp->if_flags & IFF_PROMISC) { 997 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 998 TI_CMD_CODE_PROMISC_ENB, 0); 999 } else { 1000 TI_DO_CMD(TI_CMD_SET_ALLMULTI, 1001 TI_CMD_CODE_ALLMULTI_ENB, 0); 1002 } 1003 } else { 1004 /* Disable interrupts. */ 1005 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1006 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1007 1008 /* First, zot all the existing filters. */ 1009 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1010 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1011 ti_del_mcast(sc, &mc->mc_addr); 1012 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1013 free(mc, M_DEVBUF, 0); 1014 } 1015 1016 /* Now program new ones. */ 1017 ETHER_FIRST_MULTI(step, ac, enm); 1018 while (enm != NULL) { 1019 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1020 M_NOWAIT); 1021 if (mc == NULL) 1022 panic("ti_iff"); 1023 1024 bcopy(enm->enm_addrlo, &mc->mc_addr, 1025 ETHER_ADDR_LEN); 1026 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, 1027 mc_entries); 1028 ti_add_mcast(sc, &mc->mc_addr); 1029 1030 ETHER_NEXT_MULTI(step, enm); 1031 } 1032 1033 /* Re-enable interrupts. */ 1034 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1035 } 1036} 1037 1038/* 1039 * Check to see if the BIOS has configured us for a 64 bit slot when 1040 * we aren't actually in one. If we detect this condition, we can work 1041 * around it on the Tigon 2 by setting a bit in the PCI state register, 1042 * but for the Tigon 1 we must give up and abort the interface attach. 1043 */ 1044int 1045ti_64bitslot_war(struct ti_softc *sc) 1046{ 1047 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1048 CSR_WRITE_4(sc, 0x600, 0); 1049 CSR_WRITE_4(sc, 0x604, 0); 1050 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1051 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1052 if (sc->ti_hwrev == TI_HWREV_TIGON) 1053 return (EINVAL); 1054 else { 1055 TI_SETBIT(sc, TI_PCI_STATE, 1056 TI_PCISTATE_32BIT_BUS); 1057 return (0); 1058 } 1059 } 1060 } 1061 1062 return (0); 1063} 1064 1065/* 1066 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1067 * self-test results. 1068 */ 1069int 1070ti_chipinit(struct ti_softc *sc) 1071{ 1072 u_int32_t chip_rev; 1073 1074 /* Initialize link to down state. */ 1075 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1076 1077 /* Set endianness before we access any non-PCI registers. */ 1078 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1079 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1080 1081 /* Check the ROM failed bit to see if self-tests passed. */ 1082 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1083 printf("%s: board self-diagnostics failed!\n", 1084 sc->sc_dv.dv_xname); 1085 return (ENODEV); 1086 } 1087 1088 /* Halt the CPU. */ 1089 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1090 1091 /* Figure out the hardware revision. */ 1092 chip_rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1093 switch(chip_rev) { 1094 case TI_REV_TIGON_I: 1095 sc->ti_hwrev = TI_HWREV_TIGON; 1096 break; 1097 case TI_REV_TIGON_II: 1098 sc->ti_hwrev = TI_HWREV_TIGON_II; 1099 break; 1100 default: 1101 printf("\n"); 1102 printf("%s: unsupported chip revision: %x\n", 1103 sc->sc_dv.dv_xname, chip_rev); 1104 return (ENODEV); 1105 } 1106 1107 /* Do special setup for Tigon 2. */ 1108 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1109 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1110 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1111 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1112 } 1113 1114 if (sc->ti_sbus) 1115 ti_chipinit_sbus(sc); 1116 else 1117 ti_chipinit_pci(sc); 1118 1119 /* Recommended settings from Tigon manual. */ 1120 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1121 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1122 1123 if (ti_64bitslot_war(sc)) { 1124 printf("%s: bios thinks we're in a 64 bit slot, " 1125 "but we aren't", sc->sc_dv.dv_xname); 1126 return (EINVAL); 1127 } 1128 1129 return (0); 1130} 1131 1132void 1133ti_chipinit_pci(struct ti_softc *sc) 1134{ 1135 u_int32_t cacheline; 1136 u_int32_t pci_writemax = 0; 1137 1138 /* Set up the PCI state register. */ 1139 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD | TI_PCI_WRITE_CMD); 1140 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 1141 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1142 1143 /* Clear the read/write max DMA parameters. */ 1144 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1145 TI_PCISTATE_READ_MAXDMA)); 1146 1147 /* Get cache line size. */ 1148 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1149 1150 /* 1151 * If the system has set enabled the PCI memory write 1152 * and invalidate command in the command register, set 1153 * the write max parameter accordingly. This is necessary 1154 * to use MWI with the Tigon 2. 1155 */ 1156 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCI_COMMAND_INVALIDATE_ENABLE) { 1157 switch(cacheline) { 1158 case 1: 1159 case 4: 1160 case 8: 1161 case 16: 1162 case 32: 1163 case 64: 1164 break; 1165 default: 1166 /* Disable PCI memory write and invalidate. */ 1167 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1168 TI_PCI_CMDSTAT) & ~PCI_COMMAND_INVALIDATE_ENABLE); 1169 break; 1170 } 1171 } 1172 1173#ifdef __brokenalpha__ 1174 /* 1175 * From the Alteon sample driver: 1176 * Must insure that we do not cross an 8K (bytes) boundary 1177 * for DMA reads. Our highest limit is 1K bytes. This is a 1178 * restriction on some ALPHA platforms with early revision 1179 * 21174 PCI chipsets, such as the AlphaPC 164lx 1180 */ 1181 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1182#else 1183 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1184#endif 1185 1186 /* This sets the min dma param all the way up (0xff). */ 1187 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1188 1189 /* Configure DMA variables. */ 1190 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_DMA_SWAP_OPTIONS | 1191 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1192 TI_OPMODE_DONT_FRAG_JUMBO); 1193} 1194 1195void 1196ti_chipinit_sbus(struct ti_softc *sc) 1197{ 1198 /* Set up the PCI state register. */ 1199 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD | TI_PCI_WRITE_CMD | 1200 TI_PCISTATE_NO_SWAP_READ_DMA | TI_PCISTATE_NO_SWAP_WRITE_DMA | 1201 TI_PCI_WRITEMAX_64 | TI_PCI_READMAX_64 | 1202 TI_PCISTATE_PROVIDE_LEN); 1203 1204 /* Configure DMA variables. */ 1205 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_WORDSWAP_BD | 1206 TI_OPMODE_1_DMA_ACTIVE | TI_OPMODE_SBUS | 1207 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1208 TI_OPMODE_DONT_FRAG_JUMBO); 1209} 1210 1211/* 1212 * Initialize the general information block and firmware, and 1213 * start the CPU(s) running. 1214 */ 1215int 1216ti_gibinit(struct ti_softc *sc) 1217{ 1218 struct ti_rcb *rcb; 1219 int i; 1220 struct ifnet *ifp; 1221 1222 ifp = &sc->arpcom.ac_if; 1223 1224 /* Disable interrupts for now. */ 1225 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1226 1227 /* 1228 * Tell the chip where to find the general information block. 1229 * While this struct could go into >4GB memory, we allocate it in a 1230 * single slab with the other descriptors, and those don't seem to 1231 * support being located in a 64-bit region. 1232 */ 1233 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1234 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, 1235 TI_RING_DMA_ADDR(sc, ti_info) & 0xffffffff); 1236 1237 /* Load the firmware into SRAM. */ 1238 ti_loadfw(sc); 1239 1240 /* Set up the contents of the general info and ring control blocks. */ 1241 1242 /* Set up the event ring and producer pointer. */ 1243 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1244 1245 TI_HOSTADDR(rcb->ti_hostaddr) = TI_RING_DMA_ADDR(sc, ti_event_ring); 1246 rcb->ti_flags = 0; 1247 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1248 TI_RING_DMA_ADDR(sc, ti_ev_prodidx_r); 1249 sc->ti_ev_prodidx.ti_idx = 0; 1250 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1251 sc->ti_ev_saved_considx = 0; 1252 1253 /* Set up the command ring and producer mailbox. */ 1254 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1255 1256 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1257 rcb->ti_flags = 0; 1258 rcb->ti_max_len = 0; 1259 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1260 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1261 } 1262 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1263 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1264 sc->ti_cmd_saved_prodidx = 0; 1265 1266 /* 1267 * Assign the address of the stats refresh buffer. 1268 * We re-use the current stats buffer for this to 1269 * conserve memory. 1270 */ 1271 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1272 TI_RING_DMA_ADDR(sc, ti_info.ti_stats); 1273 1274 /* Set up the standard receive ring. */ 1275 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1276 TI_HOSTADDR(rcb->ti_hostaddr) = 1277 TI_RING_DMA_ADDR(sc, ti_rx_std_ring); 1278 rcb->ti_max_len = ETHER_MAX_LEN; 1279 rcb->ti_flags = 0; 1280 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1281#if NVLAN > 0 1282 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1283 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1284#endif 1285 1286 /* Set up the jumbo receive ring. */ 1287 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1288 TI_HOSTADDR(rcb->ti_hostaddr) = TI_RING_DMA_ADDR(sc, ti_rx_jumbo_ring); 1289 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1290 rcb->ti_flags = 0; 1291 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1292#if NVLAN > 0 1293 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1294 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1295#endif 1296 1297 /* 1298 * Set up the mini ring. Only activated on the 1299 * Tigon 2 but the slot in the config block is 1300 * still there on the Tigon 1. 1301 */ 1302 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1303 TI_HOSTADDR(rcb->ti_hostaddr) = TI_RING_DMA_ADDR(sc, ti_rx_mini_ring); 1304 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1305 if (sc->ti_hwrev == TI_HWREV_TIGON) 1306 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1307 else 1308 rcb->ti_flags = 0; 1309 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1310#if NVLAN > 0 1311 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1312 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1313#endif 1314 1315 /* 1316 * Set up the receive return ring. 1317 */ 1318 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1319 TI_HOSTADDR(rcb->ti_hostaddr) = TI_RING_DMA_ADDR(sc,ti_rx_return_ring); 1320 rcb->ti_flags = 0; 1321 rcb->ti_max_len = TI_RETURN_RING_CNT; 1322 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1323 TI_RING_DMA_ADDR(sc, ti_return_prodidx_r); 1324 1325 /* 1326 * Set up the tx ring. Note: for the Tigon 2, we have the option 1327 * of putting the transmit ring in the host's address space and 1328 * letting the chip DMA it instead of leaving the ring in the NIC's 1329 * memory and accessing it through the shared memory region. We 1330 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1331 * so we have to revert to the shared memory scheme if we detect 1332 * a Tigon 1 chip. 1333 */ 1334 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1335 bzero(sc->ti_rdata->ti_tx_ring, 1336 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1337 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1338 if (sc->ti_hwrev == TI_HWREV_TIGON) 1339 rcb->ti_flags = 0; 1340 else 1341 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1342 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1343#if NVLAN > 0 1344 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1345 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1346#endif 1347 rcb->ti_max_len = TI_TX_RING_CNT; 1348 if (sc->ti_hwrev == TI_HWREV_TIGON) 1349 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1350 else 1351 TI_HOSTADDR(rcb->ti_hostaddr) = 1352 TI_RING_DMA_ADDR(sc, ti_tx_ring); 1353 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1354 TI_RING_DMA_ADDR(sc, ti_tx_considx_r); 1355 1356 TI_RING_DMASYNC(sc, ti_info, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1357 1358 /* Set up tuneables */ 1359 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, (sc->ti_rx_coal_ticks / 10)); 1360 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1361 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1362 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1363 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1364 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1365 1366 /* Turn interrupts on. */ 1367 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1368 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1369 1370 /* Start CPU. */ 1371 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1372 1373 return (0); 1374} 1375 1376int 1377ti_attach(struct ti_softc *sc) 1378{ 1379 bus_dma_segment_t seg; 1380 int rseg; 1381 struct ifnet *ifp; 1382 caddr_t kva; 1383 1384 if (ti_chipinit(sc)) { 1385 printf("%s: chip initialization failed\n", sc->sc_dv.dv_xname); 1386 return (1); 1387 } 1388 1389 /* Zero out the NIC's on-board SRAM. */ 1390 ti_mem_set(sc, 0x2000, 0x100000 - 0x2000); 1391 1392 /* Init again -- zeroing memory may have clobbered some registers. */ 1393 if (ti_chipinit(sc)) { 1394 printf("%s: chip initialization failed\n", sc->sc_dv.dv_xname); 1395 return (1); 1396 } 1397 1398 /* 1399 * Get station address from the EEPROM. Note: the manual states 1400 * that the MAC address is at offset 0x8c, however the data is 1401 * stored as two longwords (since that's how it's loaded into 1402 * the NIC). This means the MAC address is actually preceded 1403 * by two zero bytes. We need to skip over those. 1404 */ 1405 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1406 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1407 printf("%s: failed to read station address\n", 1408 sc->sc_dv.dv_xname); 1409 return (1); 1410 } 1411 1412 /* 1413 * A Tigon chip was detected. Inform the world. 1414 */ 1415 printf(", address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 1416 1417 /* Allocate the general information block and ring buffers. */ 1418 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct ti_ring_data), 1419 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1420 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 1421 return (1); 1422 } 1423 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1424 sizeof(struct ti_ring_data), &kva, BUS_DMA_NOWAIT)) { 1425 printf("%s: can't map dma buffers (%zu bytes)\n", 1426 sc->sc_dv.dv_xname, sizeof(struct ti_ring_data)); 1427 goto fail_1; 1428 } 1429 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct ti_ring_data), 1, 1430 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1431 &sc->ti_ring_map)) { 1432 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 1433 goto fail_2; 1434 } 1435 if (bus_dmamap_load(sc->sc_dmatag, sc->ti_ring_map, kva, 1436 sizeof(struct ti_ring_data), NULL, BUS_DMA_NOWAIT)) { 1437 goto fail_3; 1438 } 1439 sc->ti_rdata = (struct ti_ring_data *)kva; 1440 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1441 1442 /* Set default tuneable values. */ 1443 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1444 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1445 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1446 sc->ti_rx_max_coal_bds = 64; 1447 sc->ti_tx_max_coal_bds = 128; 1448 sc->ti_tx_buf_ratio = 21; 1449 1450 /* Set up ifnet structure */ 1451 ifp = &sc->arpcom.ac_if; 1452 ifp->if_softc = sc; 1453 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1454 ifp->if_ioctl = ti_ioctl; 1455 ifp->if_start = ti_start; 1456 ifp->if_watchdog = ti_watchdog; 1457 ifp->if_hardmtu = TI_JUMBO_FRAMELEN - ETHER_HDR_LEN; 1458 IFQ_SET_MAXLEN(&ifp->if_snd, TI_TX_RING_CNT - 1); 1459 IFQ_SET_READY(&ifp->if_snd); 1460 bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ); 1461 1462 ifp->if_capabilities = IFCAP_VLAN_MTU; 1463 1464#if NVLAN > 0 1465 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1466#endif 1467 1468 /* Set up ifmedia support. */ 1469 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1470 if (sc->ti_copper) { 1471 /* 1472 * Copper cards allow manual 10/100 mode selection, 1473 * but not manual 1000baseTX mode selection. Why? 1474 * Because currently there's no way to specify the 1475 * master/slave setting through the firmware interface, 1476 * so Alteon decided to just bag it and handle it 1477 * via autonegotiation. 1478 */ 1479 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1480 ifmedia_add(&sc->ifmedia, 1481 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1482 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1483 ifmedia_add(&sc->ifmedia, 1484 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1485 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1486 ifmedia_add(&sc->ifmedia, 1487 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1488 } else { 1489 /* Fiber cards don't support 10/100 modes. */ 1490 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1491 ifmedia_add(&sc->ifmedia, 1492 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1493 } 1494 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1495 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1496 1497 /* 1498 * Call MI attach routines. 1499 */ 1500 if_attach(ifp); 1501 ether_ifattach(ifp); 1502 1503 return (0); 1504 1505fail_3: 1506 bus_dmamap_destroy(sc->sc_dmatag, sc->ti_ring_map); 1507 1508fail_2: 1509 bus_dmamem_unmap(sc->sc_dmatag, kva, 1510 sizeof(struct ti_ring_data)); 1511 1512fail_1: 1513 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1514 1515 return (1); 1516} 1517 1518/* 1519 * Frame reception handling. This is called if there's a frame 1520 * on the receive return list. 1521 * 1522 * Note: we have to be able to handle three possibilities here: 1523 * 1) the frame is from the mini receive ring (can only happen) 1524 * on Tigon 2 boards) 1525 * 2) the frame is from the jumbo receive ring 1526 * 3) the frame is from the standard receive ring 1527 */ 1528 1529void 1530ti_rxeof(struct ti_softc *sc) 1531{ 1532 struct ifnet *ifp; 1533 struct ti_cmd_desc cmd; 1534 1535 ifp = &sc->arpcom.ac_if; 1536 1537 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1538 struct ti_rx_desc *cur_rx; 1539 u_int32_t rxidx; 1540 struct mbuf *m = NULL; 1541 bus_dmamap_t dmamap; 1542 1543 cur_rx = 1544 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1545 rxidx = cur_rx->ti_idx; 1546 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1547 1548 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1549 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1550 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1551 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1552 dmamap = sc->ti_cdata.ti_rx_jumbo_map[rxidx]; 1553 sc->ti_cdata.ti_rx_jumbo_map[rxidx] = 0; 1554 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1555 ifp->if_ierrors++; 1556 ti_newbuf_jumbo(sc, sc->ti_jumbo, m, dmamap); 1557 continue; 1558 } 1559 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL, dmamap) 1560 == ENOBUFS) { 1561 ifp->if_ierrors++; 1562 ti_newbuf_jumbo(sc, sc->ti_jumbo, m, dmamap); 1563 continue; 1564 } 1565 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1566 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1567 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1568 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1569 dmamap = sc->ti_cdata.ti_rx_mini_map[rxidx]; 1570 sc->ti_cdata.ti_rx_mini_map[rxidx] = 0; 1571 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1572 ifp->if_ierrors++; 1573 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1574 continue; 1575 } 1576 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1577 == ENOBUFS) { 1578 ifp->if_ierrors++; 1579 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1580 continue; 1581 } 1582 } else { 1583 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1584 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1585 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1586 dmamap = sc->ti_cdata.ti_rx_std_map[rxidx]; 1587 sc->ti_cdata.ti_rx_std_map[rxidx] = 0; 1588 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1589 ifp->if_ierrors++; 1590 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1591 continue; 1592 } 1593 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 1594 == ENOBUFS) { 1595 ifp->if_ierrors++; 1596 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1597 continue; 1598 } 1599 } 1600 1601 if (m == NULL) 1602 panic("%s: couldn't get mbuf", sc->sc_dv.dv_xname); 1603 1604 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1605 ifp->if_ipackets++; 1606 m->m_pkthdr.rcvif = ifp; 1607 1608#if NVLAN > 0 1609 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1610 m->m_pkthdr.ether_vtag = cur_rx->ti_vlan_tag; 1611 m->m_flags |= M_VLANTAG; 1612 } 1613#endif 1614 1615#if NBPFILTER > 0 1616 /* 1617 * Handle BPF listeners. Let the BPF user see the packet. 1618 */ 1619 if (ifp->if_bpf) 1620 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1621#endif 1622 1623 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1624 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1625 1626 ether_input_mbuf(ifp, m); 1627 } 1628 1629 /* Only necessary on the Tigon 1. */ 1630 if (sc->ti_hwrev == TI_HWREV_TIGON) 1631 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1632 sc->ti_rx_saved_considx); 1633 1634 TI_UPDATE_STDPROD(sc, sc->ti_std); 1635 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1636 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1637} 1638 1639void 1640ti_txeof_tigon1(struct ti_softc *sc) 1641{ 1642 struct ifnet *ifp; 1643 struct ti_txmap_entry *entry; 1644 int active = 1; 1645 1646 ifp = &sc->arpcom.ac_if; 1647 1648 /* 1649 * Go through our tx ring and free mbufs for those 1650 * frames that have been sent. 1651 */ 1652 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1653 u_int32_t idx = 0; 1654 struct ti_tx_desc txdesc; 1655 1656 idx = sc->ti_tx_saved_considx; 1657 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 1658 sizeof(txdesc), (caddr_t)&txdesc); 1659 1660 if (txdesc.ti_flags & TI_BDFLAG_END) 1661 ifp->if_opackets++; 1662 1663 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1664 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1665 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1666 1667 entry = sc->ti_cdata.ti_tx_map[idx]; 1668 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1669 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1670 1671 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1672 SLIST_INSERT_HEAD(&sc->ti_tx_map_listhead, entry, 1673 link); 1674 sc->ti_cdata.ti_tx_map[idx] = NULL; 1675 1676 } 1677 sc->ti_txcnt--; 1678 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1679 ifp->if_timer = 0; 1680 1681 active = 0; 1682 } 1683 1684 if (!active) 1685 ifp->if_flags &= ~IFF_OACTIVE; 1686} 1687 1688void 1689ti_txeof_tigon2(struct ti_softc *sc) 1690{ 1691 struct ti_tx_desc *cur_tx = NULL; 1692 struct ifnet *ifp; 1693 struct ti_txmap_entry *entry; 1694 1695 ifp = &sc->arpcom.ac_if; 1696 1697 /* 1698 * Go through our tx ring and free mbufs for those 1699 * frames that have been sent. 1700 */ 1701 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1702 u_int32_t idx = 0; 1703 1704 idx = sc->ti_tx_saved_considx; 1705 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1706 1707 if (cur_tx->ti_flags & TI_BDFLAG_END) 1708 ifp->if_opackets++; 1709 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1710 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1711 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1712 1713 entry = sc->ti_cdata.ti_tx_map[idx]; 1714 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1715 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1716 1717 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1718 SLIST_INSERT_HEAD(&sc->ti_tx_map_listhead, entry, 1719 link); 1720 sc->ti_cdata.ti_tx_map[idx] = NULL; 1721 1722 } 1723 sc->ti_txcnt--; 1724 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1725 ifp->if_timer = 0; 1726 } 1727 1728 if (cur_tx != NULL) 1729 ifp->if_flags &= ~IFF_OACTIVE; 1730} 1731 1732int 1733ti_intr(void *xsc) 1734{ 1735 struct ti_softc *sc; 1736 struct ifnet *ifp; 1737 1738 sc = xsc; 1739 ifp = &sc->arpcom.ac_if; 1740 1741 /* XXX checking this register is expensive. */ 1742 /* Make sure this is really our interrupt. */ 1743 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1744 return (0); 1745 1746 /* Ack interrupt and stop others from occurring. */ 1747 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1748 1749 if (ifp->if_flags & IFF_RUNNING) { 1750 /* Check RX return ring producer/consumer */ 1751 ti_rxeof(sc); 1752 1753 /* Check TX ring producer/consumer */ 1754 if (sc->ti_hwrev == TI_HWREV_TIGON) 1755 ti_txeof_tigon1(sc); 1756 else 1757 ti_txeof_tigon2(sc); 1758 } 1759 1760 ti_handle_events(sc); 1761 1762 /* Re-enable interrupts. */ 1763 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1764 1765 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 1766 ti_start(ifp); 1767 1768 return (1); 1769} 1770 1771void 1772ti_stats_update(struct ti_softc *sc) 1773{ 1774 struct ifnet *ifp; 1775 struct ti_stats *stats = &sc->ti_rdata->ti_info.ti_stats; 1776 1777 ifp = &sc->arpcom.ac_if; 1778 1779 TI_RING_DMASYNC(sc, ti_info.ti_stats, BUS_DMASYNC_POSTREAD); 1780 1781 ifp->if_collisions += stats->dot3StatsSingleCollisionFrames + 1782 stats->dot3StatsMultipleCollisionFrames + 1783 stats->dot3StatsExcessiveCollisions + 1784 stats->dot3StatsLateCollisions - 1785 ifp->if_collisions; 1786 1787 TI_RING_DMASYNC(sc, ti_info.ti_stats, BUS_DMASYNC_PREREAD); 1788} 1789 1790/* 1791 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1792 * pointers to descriptors. 1793 */ 1794int 1795ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1796{ 1797 u_int32_t frag, cur; 1798 struct ti_txmap_entry *entry; 1799 bus_dmamap_t txmap; 1800 struct ti_tx_desc txdesc; 1801 int i = 0; 1802 1803 entry = SLIST_FIRST(&sc->ti_tx_map_listhead); 1804 if (entry == NULL) 1805 return (ENOBUFS); 1806 txmap = entry->dmamap; 1807 1808 cur = frag = *txidx; 1809 1810 /* 1811 * Start packing the mbufs in this chain into 1812 * the fragment pointers. Stop when we run out 1813 * of fragments or hit the end of the mbuf chain. 1814 */ 1815 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1816 BUS_DMA_NOWAIT)) 1817 return (ENOBUFS); 1818 1819 /* 1820 * Sanity check: avoid coming within 16 descriptors 1821 * of the end of the ring. 1822 */ 1823 if (txmap->dm_nsegs > (TI_TX_RING_CNT - sc->ti_txcnt - 16)) 1824 goto fail_unload; 1825 1826 for (i = 0; i < txmap->dm_nsegs; i++) { 1827 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 1828 break; 1829 1830 memset(&txdesc, 0, sizeof(txdesc)); 1831 1832 TI_HOSTADDR(txdesc.ti_addr) = txmap->dm_segs[i].ds_addr; 1833 txdesc.ti_len = txmap->dm_segs[i].ds_len & 0xffff; 1834 txdesc.ti_flags = 0; 1835 txdesc.ti_vlan_tag = 0; 1836 1837#if NVLAN > 0 1838 if (m_head->m_flags & M_VLANTAG) { 1839 txdesc.ti_flags |= TI_BDFLAG_VLAN_TAG; 1840 txdesc.ti_vlan_tag = m_head->m_pkthdr.ether_vtag; 1841 } 1842#endif 1843 1844 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 1845 sizeof(txdesc), (caddr_t)&txdesc); 1846 1847 cur = frag; 1848 TI_INC(frag, TI_TX_RING_CNT); 1849 } 1850 1851 if (frag == sc->ti_tx_saved_considx) 1852 goto fail_unload; 1853 1854 txdesc.ti_flags |= TI_BDFLAG_END; 1855 ti_mem_write(sc, TI_TX_RING_BASE + cur * sizeof(txdesc), 1856 sizeof(txdesc), (caddr_t)&txdesc); 1857 1858 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1859 BUS_DMASYNC_PREWRITE); 1860 1861 sc->ti_cdata.ti_tx_chain[cur] = m_head; 1862 SLIST_REMOVE_HEAD(&sc->ti_tx_map_listhead, link); 1863 sc->ti_cdata.ti_tx_map[cur] = entry; 1864 sc->ti_txcnt += txmap->dm_nsegs; 1865 1866 *txidx = frag; 1867 1868 return (0); 1869 1870fail_unload: 1871 bus_dmamap_unload(sc->sc_dmatag, txmap); 1872 1873 return (ENOBUFS); 1874} 1875 1876/* 1877 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1878 * pointers to descriptors. 1879 */ 1880int 1881ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1882{ 1883 struct ti_tx_desc *f = NULL; 1884 u_int32_t frag, cur; 1885 struct ti_txmap_entry *entry; 1886 bus_dmamap_t txmap; 1887 int i = 0; 1888 1889 entry = SLIST_FIRST(&sc->ti_tx_map_listhead); 1890 if (entry == NULL) 1891 return (ENOBUFS); 1892 txmap = entry->dmamap; 1893 1894 cur = frag = *txidx; 1895 1896 /* 1897 * Start packing the mbufs in this chain into 1898 * the fragment pointers. Stop when we run out 1899 * of fragments or hit the end of the mbuf chain. 1900 */ 1901 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1902 BUS_DMA_NOWAIT)) 1903 return (ENOBUFS); 1904 1905 /* 1906 * Sanity check: avoid coming within 16 descriptors 1907 * of the end of the ring. 1908 */ 1909 if (txmap->dm_nsegs > (TI_TX_RING_CNT - sc->ti_txcnt - 16)) 1910 goto fail_unload; 1911 1912 for (i = 0; i < txmap->dm_nsegs; i++) { 1913 f = &sc->ti_rdata->ti_tx_ring[frag]; 1914 1915 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 1916 break; 1917 1918 TI_HOSTADDR(f->ti_addr) = txmap->dm_segs[i].ds_addr; 1919 f->ti_len = txmap->dm_segs[i].ds_len & 0xffff; 1920 f->ti_flags = 0; 1921 f->ti_vlan_tag = 0; 1922 1923#if NVLAN > 0 1924 if (m_head->m_flags & M_VLANTAG) { 1925 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 1926 f->ti_vlan_tag = m_head->m_pkthdr.ether_vtag; 1927 } 1928#endif 1929 1930 cur = frag; 1931 TI_INC(frag, TI_TX_RING_CNT); 1932 } 1933 1934 if (frag == sc->ti_tx_saved_considx) 1935 goto fail_unload; 1936 1937 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 1938 1939 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1940 BUS_DMASYNC_PREWRITE); 1941 1942 TI_RING_DMASYNC(sc, ti_tx_ring[cur], BUS_DMASYNC_POSTREAD); 1943 1944 sc->ti_cdata.ti_tx_chain[cur] = m_head; 1945 SLIST_REMOVE_HEAD(&sc->ti_tx_map_listhead, link); 1946 sc->ti_cdata.ti_tx_map[cur] = entry; 1947 sc->ti_txcnt += txmap->dm_nsegs; 1948 1949 *txidx = frag; 1950 1951 return (0); 1952 1953fail_unload: 1954 bus_dmamap_unload(sc->sc_dmatag, txmap); 1955 1956 return (ENOBUFS); 1957} 1958 1959/* 1960 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1961 * to the mbuf data regions directly in the transmit descriptors. 1962 */ 1963void 1964ti_start(struct ifnet *ifp) 1965{ 1966 struct ti_softc *sc; 1967 struct mbuf *m_head = NULL; 1968 u_int32_t prodidx; 1969 int pkts = 0, error; 1970 1971 sc = ifp->if_softc; 1972 1973 prodidx = sc->ti_tx_saved_prodidx; 1974 1975 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 1976 IFQ_POLL(&ifp->if_snd, m_head); 1977 if (m_head == NULL) 1978 break; 1979 1980 /* 1981 * Pack the data into the transmit ring. If we 1982 * don't have room, set the OACTIVE flag and wait 1983 * for the NIC to drain the ring. 1984 */ 1985 if (sc->ti_hwrev == TI_HWREV_TIGON) 1986 error = ti_encap_tigon1(sc, m_head, &prodidx); 1987 else 1988 error = ti_encap_tigon2(sc, m_head, &prodidx); 1989 1990 if (error) { 1991 ifp->if_flags |= IFF_OACTIVE; 1992 break; 1993 } 1994 1995 /* now we are committed to transmit the packet */ 1996 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1997 pkts++; 1998 1999 /* 2000 * If there's a BPF listener, bounce a copy of this frame 2001 * to him. 2002 */ 2003#if NBPFILTER > 0 2004 if (ifp->if_bpf) 2005 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 2006#endif 2007 } 2008 if (pkts == 0) 2009 return; 2010 2011 /* Transmit */ 2012 sc->ti_tx_saved_prodidx = prodidx; 2013 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2014 2015 /* 2016 * Set a timeout in case the chip goes out to lunch. 2017 */ 2018 ifp->if_timer = 5; 2019} 2020 2021void 2022ti_init(void *xsc) 2023{ 2024 struct ti_softc *sc = xsc; 2025 int s; 2026 2027 s = splnet(); 2028 2029 /* Cancel pending I/O and flush buffers. */ 2030 ti_stop(sc); 2031 2032 /* Init the gen info block, ring control blocks and firmware. */ 2033 if (ti_gibinit(sc)) { 2034 printf("%s: initialization failure\n", sc->sc_dv.dv_xname); 2035 splx(s); 2036 return; 2037 } 2038 2039 splx(s); 2040} 2041 2042void 2043ti_init2(struct ti_softc *sc) 2044{ 2045 struct ti_cmd_desc cmd; 2046 struct ifnet *ifp; 2047 u_int16_t *m; 2048 struct ifmedia *ifm; 2049 int tmp; 2050 2051 ifp = &sc->arpcom.ac_if; 2052 2053 /* Specify MTU and interface index. */ 2054 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dv.dv_unit); 2055 CSR_WRITE_4(sc, TI_GCR_IFMTU, 2056 TI_JUMBO_FRAMELEN + ETHER_VLAN_ENCAP_LEN); 2057 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2058 2059 /* Load our MAC address. */ 2060 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2061 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2062 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2063 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2064 2065 /* Program promiscuous mode and multicast filters. */ 2066 ti_iff(sc); 2067 2068 /* 2069 * If this is a Tigon 1, we should tell the 2070 * firmware to use software packet filtering. 2071 */ 2072 if (sc->ti_hwrev == TI_HWREV_TIGON) 2073 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2074 2075 /* Init RX ring. */ 2076 if (ti_init_rx_ring_std(sc) == ENOBUFS) 2077 panic("not enough mbufs for rx ring"); 2078 2079 /* Init jumbo RX ring. */ 2080 ti_init_rx_ring_jumbo(sc); 2081 2082 /* 2083 * If this is a Tigon 2, we can also configure the 2084 * mini ring. 2085 */ 2086 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2087 ti_init_rx_ring_mini(sc); 2088 2089 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2090 sc->ti_rx_saved_considx = 0; 2091 2092 /* Init TX ring. */ 2093 ti_init_tx_ring(sc); 2094 2095 /* Tell firmware we're alive. */ 2096 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2097 2098 /* Enable host interrupts. */ 2099 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2100 2101 ifp->if_flags |= IFF_RUNNING; 2102 ifp->if_flags &= ~IFF_OACTIVE; 2103 2104 /* 2105 * Make sure to set media properly. We have to do this 2106 * here since we have to issue commands in order to set 2107 * the link negotiation and we can't issue commands until 2108 * the firmware is running. 2109 */ 2110 ifm = &sc->ifmedia; 2111 tmp = ifm->ifm_media; 2112 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2113 ti_ifmedia_upd(ifp); 2114 ifm->ifm_media = tmp; 2115} 2116 2117/* 2118 * Set media options. 2119 */ 2120int 2121ti_ifmedia_upd(struct ifnet *ifp) 2122{ 2123 struct ti_softc *sc; 2124 struct ifmedia *ifm; 2125 struct ti_cmd_desc cmd; 2126 2127 sc = ifp->if_softc; 2128 ifm = &sc->ifmedia; 2129 2130 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2131 return(EINVAL); 2132 2133 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2134 case IFM_AUTO: 2135 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2136 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2137 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2138 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2139 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2140 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2141 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2142 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2143 break; 2144 case IFM_1000_SX: 2145 case IFM_1000_T: 2146 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2147 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2148 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2149 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2150 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2151 } 2152 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2153 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2154 break; 2155 case IFM_100_FX: 2156 case IFM_10_FL: 2157 case IFM_100_TX: 2158 case IFM_10_T: 2159 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2160 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2161 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2162 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2163 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2164 } else { 2165 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2166 } 2167 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2168 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2169 } else { 2170 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2171 } 2172 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2173 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2174 break; 2175 } 2176 2177 return (0); 2178} 2179 2180/* 2181 * Report current media status. 2182 */ 2183void 2184ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2185{ 2186 struct ti_softc *sc; 2187 u_int32_t media = 0; 2188 2189 sc = ifp->if_softc; 2190 2191 ifmr->ifm_status = IFM_AVALID; 2192 ifmr->ifm_active = IFM_ETHER; 2193 2194 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 2195 ifmr->ifm_active |= IFM_NONE; 2196 return; 2197 } 2198 2199 ifmr->ifm_status |= IFM_ACTIVE; 2200 2201 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2202 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2203 if (sc->ti_copper) 2204 ifmr->ifm_active |= IFM_1000_T; 2205 else 2206 ifmr->ifm_active |= IFM_1000_SX; 2207 if (media & TI_GLNK_FULL_DUPLEX) 2208 ifmr->ifm_active |= IFM_FDX; 2209 else 2210 ifmr->ifm_active |= IFM_HDX; 2211 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2212 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2213 if (sc->ti_copper) { 2214 if (media & TI_LNK_100MB) 2215 ifmr->ifm_active |= IFM_100_TX; 2216 if (media & TI_LNK_10MB) 2217 ifmr->ifm_active |= IFM_10_T; 2218 } else { 2219 if (media & TI_LNK_100MB) 2220 ifmr->ifm_active |= IFM_100_FX; 2221 if (media & TI_LNK_10MB) 2222 ifmr->ifm_active |= IFM_10_FL; 2223 } 2224 if (media & TI_LNK_FULL_DUPLEX) 2225 ifmr->ifm_active |= IFM_FDX; 2226 if (media & TI_LNK_HALF_DUPLEX) 2227 ifmr->ifm_active |= IFM_HDX; 2228 } 2229} 2230 2231int 2232ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2233{ 2234 struct ti_softc *sc = ifp->if_softc; 2235 struct ifaddr *ifa = (struct ifaddr *)data; 2236 struct ifreq *ifr = (struct ifreq *)data; 2237 int s, error = 0; 2238 2239 s = splnet(); 2240 2241 switch(command) { 2242 case SIOCSIFADDR: 2243 ifp->if_flags |= IFF_UP; 2244 if ((ifp->if_flags & IFF_RUNNING) == 0) 2245 ti_init(sc); 2246 if (ifa->ifa_addr->sa_family == AF_INET) 2247 arp_ifinit(&sc->arpcom, ifa); 2248 break; 2249 2250 case SIOCSIFFLAGS: 2251 if (ifp->if_flags & IFF_UP) { 2252 if (ifp->if_flags & IFF_RUNNING) 2253 error = ENETRESET; 2254 else 2255 ti_init(sc); 2256 } else { 2257 if (ifp->if_flags & IFF_RUNNING) 2258 ti_stop(sc); 2259 } 2260 break; 2261 2262 case SIOCSIFMEDIA: 2263 case SIOCGIFMEDIA: 2264 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2265 break; 2266 2267 default: 2268 error = ether_ioctl(ifp, &sc->arpcom, command, data); 2269 } 2270 2271 if (error == ENETRESET) { 2272 if (ifp->if_flags & IFF_RUNNING) 2273 ti_iff(sc); 2274 error = 0; 2275 } 2276 2277 splx(s); 2278 return (error); 2279} 2280 2281void 2282ti_watchdog(struct ifnet *ifp) 2283{ 2284 struct ti_softc *sc; 2285 2286 sc = ifp->if_softc; 2287 2288 printf("%s: watchdog timeout -- resetting\n", sc->sc_dv.dv_xname); 2289 ti_stop(sc); 2290 ti_init(sc); 2291 2292 ifp->if_oerrors++; 2293} 2294 2295/* 2296 * Stop the adapter and free any mbufs allocated to the 2297 * RX and TX lists. 2298 */ 2299void 2300ti_stop(struct ti_softc *sc) 2301{ 2302 struct ifnet *ifp; 2303 struct ti_cmd_desc cmd; 2304 2305 ifp = &sc->arpcom.ac_if; 2306 2307 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2308 2309 /* Disable host interrupts. */ 2310 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2311 /* 2312 * Tell firmware we're shutting down. 2313 */ 2314 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2315 2316 /* Halt and reinitialize. */ 2317 ti_chipinit(sc); 2318 ti_mem_set(sc, 0x2000, 0x100000 - 0x2000); 2319 ti_chipinit(sc); 2320 2321 /* Free the RX lists. */ 2322 ti_free_rx_ring_std(sc); 2323 2324 /* Free jumbo RX list. */ 2325 ti_free_rx_ring_jumbo(sc); 2326 2327 /* Free mini RX list. */ 2328 ti_free_rx_ring_mini(sc); 2329 2330 /* Free TX buffers. */ 2331 ti_free_tx_ring(sc); 2332 2333 sc->ti_ev_prodidx.ti_idx = 0; 2334 sc->ti_return_prodidx.ti_idx = 0; 2335 sc->ti_tx_considx.ti_idx = 0; 2336 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2337} 2338