smc93cx6.c revision 1.13 
1/*	$OpenBSD: smc93cx6.c,v 1.13 2002/06/30 19:36:58 smurph Exp $	*/
2/* $FreeBSD: sys/dev/aic7xxx/93cx6.c,v 1.5 2000/01/07 23:08:17 gibbs Exp $ */
3/*
4 * Interface for the 93C66/56/46/26/06 serial eeprom parts.
5 *
6 * Copyright (c) 1995, 1996 Daniel M. Eischen
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice immediately at the beginning of the file, without modification,
14 *    this list of conditions, and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 * 3. Absolutely no warranty of function or purpose is made by the author
19 *    Daniel M. Eischen.
20 * 4. Modifications may be freely made to this file if the above conditions
21 *    are met.
22 */
23
24/*
25 *   The instruction set of the 93C66/56/46/26/06 chips are as follows:
26 *
27 *               Start  OP	    *
28 *     Function   Bit  Code  Address**  Data     Description
29 *     -------------------------------------------------------------------
30 *     READ        1    10   A5 - A0             Reads data stored in memory,
31 *                                               starting at specified address
32 *     EWEN        1    00   11XXXX              Write enable must precede
33 *                                               all programming modes
34 *     ERASE       1    11   A5 - A0             Erase register A5A4A3A2A1A0
35 *     WRITE       1    01   A5 - A0   D15 - D0  Writes register
36 *     ERAL        1    00   10XXXX              Erase all registers
37 *     WRAL        1    00   01XXXX    D15 - D0  Writes to all registers
38 *     EWDS        1    00   00XXXX              Disables all programming
39 *                                               instructions
40 *     *Note: A value of X for address is a don't care condition.
41 *    **Note: There are 8 address bits for the 93C56/66 chips unlike
42 *	      the 93C46/26/06 chips which have 6 address bits.
43 *
44 *   The 93C46 has a four wire interface: clock, chip select, data in, and
45 *   data out.  In order to perform one of the above functions, you need
46 *   to enable the chip select for a clock period (typically a minimum of
47 *   1 usec, with the clock high and low a minimum of 750 and 250 nsec
48 *   respectively).  While the chip select remains high, you can clock in
49 *   the instructions (above) starting with the start bit, followed by the
50 *   OP code, Address, and Data (if needed).  For the READ instruction, the
51 *   requested 16-bit register contents is read from the data out line but
52 *   is preceded by an initial zero (leading 0, followed by 16-bits, MSB
53 *   first).  The clock cycling from low to high initiates the next data
54 *   bit to be sent from the chip.
55 *
56 */
57
58#include <sys/param.h>
59#include <sys/systm.h>
60#if !(defined(__NetBSD__) || defined(__OpenBSD__))
61#include <machine/bus_memio.h>
62#include <machine/bus_pio.h>
63#endif
64#include <machine/bus.h>
65#if defined(__OpenBSD__)
66#include <dev/ic/aic7xxx_openbsd.h>
67#endif
68#include <dev/ic/aic7xxx_inline.h>
69#if !(defined(__NetBSD__) || defined(__OpenBSD__))
70#include <dev/aic7xxx/93cx6.h>
71#else
72#include <dev/ic/smc93cx6var.h>
73#endif
74
75/*
76 * Right now, we only have to read the SEEPROM.  But we make it easier to
77 * add other 93Cx6 functions.
78 */
79static struct seeprom_cmd {
80  	unsigned char len;
81 	unsigned char bits[9];
82} seeprom_read = {3, {1, 1, 0}};
83
84static struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
85static struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
86static struct seeprom_cmd seeprom_write = {3, {1, 0, 1}};
87
88/*
89 * Wait for the SEERDY to go high; about 800 ns.
90 */
91#define CLOCK_PULSE(sd, rdy)				\
92	while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) {	\
93		;  /* Do nothing */			\
94	}						\
95	(void)SEEPROM_INB(sd);	/* Clear clock */
96
97/*
98 * Send a START condition and the given command
99 */
100static void
101send_seeprom_cmd(struct seeprom_descriptor *sd, struct seeprom_cmd *cmd)
102{
103	u_int8_t temp;
104	int i = 0;
105
106	/* Send chip select for one clock cycle. */
107	temp = sd->sd_MS ^ sd->sd_CS;
108	SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
109	CLOCK_PULSE(sd, sd->sd_RDY);
110
111	for (i = 0; i < cmd->len; i++) {
112		if (cmd->bits[i] != 0)
113			temp ^= sd->sd_DO;
114		SEEPROM_OUTB(sd, temp);
115		CLOCK_PULSE(sd, sd->sd_RDY);
116		SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
117		CLOCK_PULSE(sd, sd->sd_RDY);
118		if (cmd->bits[i] != 0)
119			temp ^= sd->sd_DO;
120	}
121}
122
123/*
124 * Clear CS put the chip in the reset state, where it can wait for new commands.
125 */
126static void
127reset_seeprom(struct seeprom_descriptor *sd)
128{
129	u_int8_t temp;
130
131	temp = sd->sd_MS;
132	SEEPROM_OUTB(sd, temp);
133	CLOCK_PULSE(sd, sd->sd_RDY);
134	SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
135	CLOCK_PULSE(sd, sd->sd_RDY);
136	SEEPROM_OUTB(sd, temp);
137	CLOCK_PULSE(sd, sd->sd_RDY);
138}
139
140/*
141 * Read the serial EEPROM and returns 1 if successful and 0 if
142 * not successful.
143 */
144int
145read_seeprom(sd, buf, start_addr, count)
146	struct seeprom_descriptor *sd;
147	u_int16_t *buf;
148	bus_size_t start_addr;
149	bus_size_t count;
150{
151	int i = 0;
152	u_int k = 0;
153	u_int16_t v;
154	u_int8_t temp;
155
156	/*
157	 * Read the requested registers of the seeprom.  The loop
158	 * will range from 0 to count-1.
159	 */
160	for (k = start_addr; k < count + start_addr; k++) {
161		/*
162		 * Now we're ready to send the read command followed by the
163		 * address of the 16-bit register we want to read.
164		 */
165		send_seeprom_cmd(sd, &seeprom_read);
166
167		/* Send the 6 or 8 bit address (MSB first, LSB last). */
168		temp = sd->sd_MS ^ sd->sd_CS;
169		for (i = (sd->sd_chip - 1); i >= 0; i--) {
170			if ((k & (1 << i)) != 0)
171				temp ^= sd->sd_DO;
172			SEEPROM_OUTB(sd, temp);
173			CLOCK_PULSE(sd, sd->sd_RDY);
174			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
175			CLOCK_PULSE(sd, sd->sd_RDY);
176			if ((k & (1 << i)) != 0)
177				temp ^= sd->sd_DO;
178		}
179
180		/*
181		 * Now read the 16 bit register.  An initial 0 precedes the
182		 * register contents which begins with bit 15 (MSB) and ends
183		 * with bit 0 (LSB).  The initial 0 will be shifted off the
184		 * top of our word as we let the loop run from 0 to 16.
185		 */
186		v = 0;
187		for (i = 16; i >= 0; i--) {
188			SEEPROM_OUTB(sd, temp);
189			CLOCK_PULSE(sd, sd->sd_RDY);
190			v <<= 1;
191			if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
192				v |= 1;
193			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
194			CLOCK_PULSE(sd, sd->sd_RDY);
195		}
196
197		buf[k - start_addr] = v;
198
199		/* Reset the chip select for the next command cycle. */
200		reset_seeprom(sd);
201	}
202#ifdef AHC_DUMP_EEPROM
203	printf("\nSerial EEPROM:\n\t");
204	for (k = 0; k < count; k = k + 1) {
205		if (((k % 8) == 0) && (k != 0)) {
206			printf ("\n\t");
207		}
208		printf (" 0x%x", buf[k]);
209	}
210	printf ("\n");
211#endif
212	return (1);
213}
214
215/*
216 * Write the serial EEPROM and return 1 if successful and 0 if
217 * not successful.
218 */
219int
220write_seeprom(sd, buf, start_addr, count)
221	struct seeprom_descriptor *sd;
222	u_int16_t *buf;
223	bus_size_t start_addr;
224	bus_size_t count;
225{
226	u_int16_t v;
227	u_int8_t temp;
228	int i, k;
229
230	/* Place the chip into write-enable mode */
231	send_seeprom_cmd(sd, &seeprom_ewen);
232	reset_seeprom(sd);
233
234	/* Write all requested data out to the seeprom. */
235	temp = sd->sd_MS ^ sd->sd_CS;
236	for (k = start_addr; k < count + start_addr; k++) {
237		/* Send the write command */
238		send_seeprom_cmd(sd, &seeprom_write);
239
240		/* Send the 6 or 8 bit address (MSB first). */
241		for (i = (sd->sd_chip - 1); i >= 0; i--) {
242			if ((k & (1 << i)) != 0)
243				temp ^= sd->sd_DO;
244			SEEPROM_OUTB(sd, temp);
245			CLOCK_PULSE(sd, sd->sd_RDY);
246			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
247			CLOCK_PULSE(sd, sd->sd_RDY);
248			if ((k & (1 << i)) != 0)
249				temp ^= sd->sd_DO;
250		}
251
252		/* Write the 16 bit value, MSB first */
253		v = buf[k - start_addr];
254		for (i = 15; i >= 0; i--) {
255			if ((v & (1 << i)) != 0)
256				temp ^= sd->sd_DO;
257			SEEPROM_OUTB(sd, temp);
258			CLOCK_PULSE(sd, sd->sd_RDY);
259			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
260			CLOCK_PULSE(sd, sd->sd_RDY);
261			if ((v & (1 << i)) != 0)
262				temp ^= sd->sd_DO;
263		}
264
265		/* Wait for the chip to complete the write */
266		temp = sd->sd_MS;
267		SEEPROM_OUTB(sd, temp);
268		CLOCK_PULSE(sd, sd->sd_RDY);
269		temp = sd->sd_MS ^ sd->sd_CS;
270		do {
271			SEEPROM_OUTB(sd, temp);
272			CLOCK_PULSE(sd, sd->sd_RDY);
273			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
274			CLOCK_PULSE(sd, sd->sd_RDY);
275		} while ((SEEPROM_DATA_INB(sd) & sd->sd_DI) == 0);
276
277		reset_seeprom(sd);
278	}
279
280	/* Put the chip back into write-protect mode */
281	send_seeprom_cmd(sd, &seeprom_ewds);
282	reset_seeprom(sd);
283
284	return (1);
285}
286
287int
288verify_cksum(struct seeprom_config *sc)
289{
290	int i;
291	int maxaddr;
292	u_int32_t checksum;
293	u_int16_t *scarray;
294
295	maxaddr = (sizeof(*sc)/2) - 1;
296	checksum = 0;
297	scarray = (uint16_t *)sc;
298
299	for (i = 0; i < maxaddr; i++)
300		checksum = checksum + scarray[i];
301	if (checksum == 0
302	 || (checksum & 0xFFFF) != sc->checksum) {
303		return (0);
304	} else {
305		return(1);
306	}
307}
308