silireg.h revision 1.6
1/* $OpenBSD: silireg.h,v 1.6 2007/03/26 00:33:38 dlg Exp $ */ 2 3/* 4 * Copyright (c) 2007 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19/* PCI Registers */ 20#define SILI_PCI_BAR_GLOBAL 0x10 /* Global Registers address */ 21#define SILI_PCI_BAR_PORT 0x18 /* Port Registers address */ 22#define SILI_PCI_BAR_INDIRECT 0x20 /* Indirect IO Registers address */ 23 24/* Global Registers */ 25#define SILI_REG_PORT0_STATUS 0x00 /* Port 0 Slot Status */ 26#define SILI_REG_PORT1_STATUS 0x04 /* Port 1 Slot Status */ 27#define SILI_REG_PORT2_STATUS 0x08 /* Port 2 Slot Status */ 28#define SILI_REG_PORT3_STATUS 0x0c /* Port 3 Slot Status */ 29#define SILI_REG_GC 0x40 /* Global Control */ 30#define SILI_REG_GIS 0x40 /* Global Interrupt Status */ 31#define SILI_REG_PHYCONF 0x48 /* PHY Configuration */ 32#define SILI_REG_BISTCTL 0x50 /* BIST Control */ 33#define SILI_REG_BISTPATTERN 0x54 /* BIST Pattern */ 34#define SILI_REG_BISTSTAT 0x58 /* BIST Status */ 35#define SILI_REG_FLASHADDR 0x70 /* Flash Address */ 36#define SILI_REG_FLASHDATA 0x74 /* Flash Memory Data / GPIO Control */ 37#define SILI_REG_GPIOCTL SILI_REG_FLASHDATA 38#define SILI_REG_IICADDR 0x78 /* I2C Address */ 39#define SILI_REG_IIC 0x7c /* I2C Data / Control */ 40 41/* Port Registers */ 42#define SILI_PREG_LRAM 0x0000 /* Port LRAM */ 43 /* XXX 31 slots and port multiplier stuff sits in here */ 44#define SILI_PREG_PCS 0x1000 /* Port Control Set / Status */ 45#define SILI_PREG_PCC 0x1004 /* Port Control Clear */ 46#define SILI_PREG_IS 0x1008 /* Interrupt Status */ 47#define SILI_PREG_IES 0x1008 /* Interrupt Enable Set */ 48#define SILI_PREG_IEC 0x1008 /* Interrupt Enable Clear */ 49#define SILI_PREG_AUA 0x101c /* Activation Upper Address */ 50#define SILI_PREG_FIFO 0x1020 /* Command Execution FIFO */ 51#define SILI_PREG_CE 0x1024 /* Command Error */ 52#define SILI_PREG_FC 0x1028 /* FIS Configuration */ 53#define SILI_PREG_RFT 0x102c /* Request FIFO Threshold */ 54#define SILI_PREG_DEC 0x1040 /* 8b/10b Decode Error Counter */ 55#define SILI_PREG_CEC 0x1044 /* CRC Error Counter */ 56#define SILI_PREG_HEC 0x1048 /* Handshake Error Counter */ 57#define SILI_PREG_PHYCONF 0x1050 /* Port PHY Configuration */ 58#define SILI_PREG_PSS 0x1800 /* Port Slot Status */ 59#define SILI_PREG_CAR 0x1c00 /* Command Activation Registers */ 60 /* XXX up to 0x1cf7 is more of these */ 61#define SILI_PREG_CONTEXT 0x1e0f /* Port Context Register */ 62#define SILI_PREG_SCTL 0x1f00 /* SControl */ 63#define SILI_PREG_SSTS 0x1f04 /* SStatus */ 64#define SILI_PREG_SERR 0x1f08 /* SError */ 65#define SILI_PREG_SACT 0x1f0c /* SActive */ 66 67